LH28F800BGR-BL12 - Sharp Electronics Corp.

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In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in catalogs, data books,

etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device.

LH28F800BG-L/BGH-L

(FOR TSOP, CSP)

8 M-bit (512 kB x 16) SmartVoltage

Flash Memories

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

DESCRIPTION

The LH28F800BG-L/BGH-L flash memories with

SmartVoltage technology are high-density, low-cost,

nonvolatile, read/write storage solution for a wide

range of applications. The LH28F800BG-L/BGH-L

can operate at VCC = 2.7 V and VPP = 2.7 V. Their

low voltage operation capability realizes longer

battery life and suits for cellular phone application.

Their boot, parameter and main-blocked

architecture, flexible voltage and enhanced cycling

capability provide for highly flexible component

suitable for portable terminals and personal

computers. Their enhanced suspend capabilities

provide for an ideal solution for code + data storage

applications. For secure code storage applications,

such as networking, where code is either directly

executed out of flash or downloaded to DRAM, the

LH28F800BG-L/BGH-L offer two levels of protection

: absolute protection with VPP at GND, selective

hardware boot block locking. These alternatives

give designers ultimate control of their code security

needs.

FEATURES

• SmartVoltage technology

– 2.7 V, 3.3 V or 5 V VCC

– 2.7 V, 3.3 V, 5 V or 12 V VPP

• High performance read access time

LH28F800BG-L85/BGH-L85

– 85 ns (5.0±0.25 V)/90 ns (5.0±0.5 V)/

100 ns (3.3±0.3 V)/120 ns (2.7 to 3.6 V)

LH28F800BG-L12/BGH-L12

– 120 ns (5.0±0.5 V)/130 ns (3.3±0.3 V)/

150 ns (2.7 to 3.6 V)

• Enhanced automated suspend options

– Word write suspend to read

– Block erase suspend to word write

– Block erase suspend to read

• Enhanced data protection features

– Absolute protection with VPP = GND

– Block erase/word write lockout during power

transitions

– Boot blocks protection with WP# = VIL

• SRAM-compatible write interface

• Optimized array blocking architecture

– Two 4 k-word boot blocks

– Six 4 k-word parameter blocks

– Fifteen 32 k-word main blocks

– Top or bottom boot location

• Enhanced cycling capability

– 100 000 block erase cycles

• Low power management

– Deep power-down mode

– Automatic power saving mode decreases ICC

in static mode

• Automated word write and block erase

– Command user interface

– Status register

• ETOXTM∗V nonvolatile flash technology

• Packages

– 48-pin TSOP Type I (TSOP048-P-1220)

Normal bend/Reverse bend

– 48-ball CSP (FBGA048-P-0808)

∗ETOX is a trademark of Intel Corporation.

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

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PIN CONNECTIONS

A3B

A1C

A0D

GND

CE#

OE#

DQ8

DQ0

A17

WP# WE#

DQ1

DQ2

DQ9

VPP

DQ10

DQ11

DQ3

RP#

DQ12

VCC

DQ4

DQ6

DQ5

DQ13

A11

A10

A12

DQ15

DQ14

DQ7

A14

A13

A15

A16

GND

RY/BY#

A18

(FBGA048-P-0808)

48-BALL CSP48-PIN TSOP (Type I)

(TSOP048-P-1220)

A15

A14

A13

A12

A11

A10

WE#

RP#

VPP

WP#

RY/BY#

A18

A17

A16

GND

DQ15

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

VCC

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

OE#

GND

CE#

VERSIONS OPERATING PACKAGE

DC CHARACTERISTICS

WRITE PROTECT FUNCTION

TEMPERATURE

deep power-down current (MAX.)

FOR BOOT BLOCKS

LH28F800BG-L 0 to +70°C 48-pin TSOP (I) 10 µA Controlled by

(FOR TSOP, CSP)

48-ball CSP WP# and RP# pins

LH28F800BGH-L –40 to +85°C 48-pin TSOP (I) 20 µA Controlled by

(FOR TSOP, CSP)

48-ball CSP WP# and RP# pins

LH28F800BG-L

∗10 to +70°C 44-pin SOP 10 µA Controlled by RP# pin

(FOR SOP)

COMPARISON TABLE

∗1 Refer to the datasheet of LH28F800BG-L (FOR SOP).

NOTE :

Reverse bend available on request.

TOP VIEW

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

BLOCK ORGANIZATION

This product features an asymmetrically-blocked

architecture providing system memory integration.

Each erase block can be erased independently of

the others up to 100 000 times. For the address

locations of the blocks, see the memory map in

Fig. 1.

Boot Blocks : The two boot blocks are intended to

replace a dedicated boot PROM in a micro-

processor or microcontroller-based system. The

boot blocks of 4 k words (4 096 words) feature

hardware controllable write-protection to protect the

crucial microprocessor boot code from accidental

modification. The protection of the boot blocks is

controlled using a combination of the VPP, RP# and

WP# pins.

Parameter Blocks : The boot block architecture

includes parameter blocks to facilitate storage of

frequently update small parameters that would

normally require an EEPROM. By using software

techniques, the byte-rewrite functionality of

EEPROMs can be emulated. Each boot block

component contains six parameter blocks of 4 k

words (4 096 words) each. The parameter blocks

are not write-protectable.

Main Blocks : The reminder is divided into main

blocks for data or code storage. Each 8 M-bit

device contains fifteen 32 k words (32 768 words)

blocks.

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INPUT

BUFFERBUFFER

OUTPUT

MULTIPLEXER

VCC

CE#

RP#

OE#

IDENTIFIER

COMMAND

USER

INTERFACE

WRITE

STATE

MACHINE

PROGRAM/ERASE

VOLTAGE SWITCH

I/O

LOGIC

STATUS

DATA

COMPARATOR

32 k-WORD

MAIN BLOCKS

DECODER

DECODER Y GATING RY/BY#

GND

A0-A18 INPUT

BUFFER

ADDRESS

LATCH

ADDRESS

COUNTER

BOOT BLOCK 0

BOOT BLOCK 1

PARAMETER BLOCK 0

PARAMETER BLOCK 1

PARAMETER BLOCK 2

PARAMETER BLOCK 3

PARAMETER BLOCK 4

PARAMETER BLOCK 5

MAIN BLOCK 0

MAIN BLOCK 1

MAIN BLOCK 13

MAIN BLOCK 14

WP#

WE#

OUTPUT

DQ0-DQ15

BLOCK DIAGRAM

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

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PIN DESCRIPTION

SYMBOL TYPE NAME AND FUNCTION

A0-A18 INPUT ADDRESS INPUTS : Inputs for addresses during read and write operations. Addresses

are internally latched during a write cycle.

DATA INPUT/OUTPUTS : Inputs data and commands during CUI write cycles; outputs

data during memory array, status register and identifier code read cycles. Data pins float

to high-impedance when the chip is deselected or outputs are disabled. Data is

internally latched during a write cycle.

CE# INPUT CHIP ENABLE : Activates the device’s control logic, input buffers, decoders and sense

amplifiers. CE#-high deselects the device and reduces power consumption to standby

levels.

RESET/DEEP POWER-DOWN : Puts the device in deep power-down mode and resets

internal automation. RP#-high enables normal operation. When driven low, RP# inhibits

write operations which provide data protection during power transitions. Exit from deep

power-down sets the device to read array mode. With RP# = V HH, block erase or word

write can operate to all blocks without WP# state. Block erase or word write with VIH <

RP# < VHH produce spurious results and should not be attempted.

OE# INPUT OUTPUT ENABLE : Gates the device’s outputs during a read cycle.

WE# INPUT WRITE ENABLE : Controls writes to the CUI and array blocks. Addresses and data are

latched on the rising edge of the WE# pulse.

WP# INPUT WRITE PROTECT : Master control for boot blocks locking. When VIL, locked boot

blocks cannot be erased and programmed.

READY/BUSY : Indicates the status of the internal WSM. When low, the WSM is

performing an internal operation (block erase or word write). RY/BY#-high indicates that

the WSM is ready for new commands, block erase is suspended, and word write is

inactive, word write is suspended, or the device is in deep power-down mode. RY/BY#

is always active and does not float when the chip is deselected or data outputs are

disabled.

VPP SUPPLY

BLOCK ERASE AND WORD WRITE POWER SUPPLY : For erasing array blocks or

writing words. With VPP ≤VPPLK, memory contents cannot be altered. Block erase and

word write with an invalid VPP (see Section 6.2.3 "DC CHARACTERISTICS") produce

spurious results and should not be attempted.

DEVICE POWER SUPPLY : Internal detection configures the device for 2.7 V, 3.3 V or

5 V operation. To switch from one voltage to another, ramp VCC down to GND and then

ramp VCC to the new voltage. Do not float any power pins. With VCC ≤VLKO, all write

attempts to the flash memory are inhibited. Device operations at invalid VCC voltage

(see Section 6.2.3 "DC CHARACTERISTICS") produce spurious results and should

not be attempted.

GND SUPPLY GROUND : Do not float any ground pins.

NC NO CONNECT : Lead is not inter nal connected; recommend to be floated.

DQ0-DQ15 INPUT/

OUTPUT

RP# INPUT/

RY/BY# OUTPUT

VCC SUPPLY

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

1 INTRODUCTION

This datasheet contains LH28F800BG-L/BGH-L

specifications. Section 1 provides a flash memory

overview. Sections 2, 3, 4 and 5 describe the

memory organization and functionality. Section 6

covers electrical specifications. LH28F800BG-L/

BGH-L flash memories documentation also includes

ordering information which is referenced in

Section 7.

1.1 New Features

Key enhancements of LH28F800BG-L/BGH-L

SmartVoltage flash memories are :

• SmartVoltage Technology

• Enhanced Suspend Capabilities

• Boot Block Architecture

Note following important differences :

•V

PPLK has been lowered to 1.5 V to support

2.7 V, 3.3 V and 5 V block erase and word

write operations. Designs that switch VPP off

during read operations should make sure that

the VPP voltage transitions to GND.

• To take advantage of SmartVoltage technology,

allow VPP connection to 2.7 V, 3.3 V or 5 V.

1.2 Product Overview

The LH28F800BG-L/BGH-L are high-performance

8 M-bit SmartVoltage flash memories organized as

512 k-word of 16 bits. The 512 k-word of data is

arranged in two 4 k-word boot blocks, six 4 k-word

parameter blocks and fifteen 32 k-word main blocks

which are individually erasable in-system. The

memory map is shown in Fig. 1.

SmartVoltage technology provides a choice of VCC

and VPP combinations, as shown in Table 1, to

meet system performance and power expectations.

2.7 V VCC consumes approximately one-fifth the

power of 5 V VCC and 3.3 V VCC consumes

approximately one-fourth the power of 5 V VCC.

But, 5 V VCC provides the highest read

performance. VPP at 2.7 V, 3.3 V and 5 V

eliminates the need for a separate 12 V converter,

while VPP = 12 V maximizes block erase and word

write performance. In addition to flexible erase and

program voltages, the dedicated VPP pin gives

complete data protection when VPP ≤VPPLK.

Table 1 VCC and VPP Voltage Combinations

Offered by SmartVoltage Technology

Internal VCC and VPP detection circuitry auto-

matically configures the device for optimized read

and write operations.

A Command User Interface (CUI) serves as the

interface between the system processor and

internal operation of the device. A valid command

sequence written to the CUI initiates device

automation. An internal Write State Machine (WSM)

automatically executes the algorithms and timings

necessary for block erase and word write

operations.

A block erase operation erases one of the device’s

32 k-word blocks typically within 0.39 second (5 V

VCC, 12 V VPP), 4 k-word blocks typically within

0.25 second (5 V VCC, 12 V VPP) independent of

other blocks. Each block can be independently

erased 100 000 times. Block erase suspend mode

allows system software to suspend block erase to

read data from, or write data to any other block.

Writing memory data is performed in word

increments of the device’s 32 k-word blocks

typically within 8.4 µs (5 V VCC, 12 V VPP), 4 k-

word blocks typically within 17 µs (5 V VCC, 12 V

VPP). Word write suspend mode enables the

VCC VOLTAGE VPP VOLTAGE

2.7 V 2.7 V, 3.3 V, 5 V, 12 V

3.3 V 3.3 V, 5 V, 12 V

5 V 5 V, 12 V

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LH28F800BG-L/BGH-L (FOR TSOP, CSP)

system to read data from, or write to any other

flash memory array location.

The boot block is located at either the top or the

bottom of the address map in order to

accommodate different micro-processor protect for

boot code location. The hardware-lockable boot

block provides complete code security for the

kernel code required for system initialization.

Locking and unlocking of the boot block is

controlled by WP# and/or RP# (see Section 4.9 for

details). Block erase or word write for boot block

must not be carried out by WP# to low and RP# to

VIH.

The status register indicates when the WSM’s block

erase or word write operation is finished.

The RY/BY# output gives an additional indicator of

WSM activity by providing both a hardware signal

of status (versus software polling) and status

masking (interrupt masking for background block

erase, for example). Status polling using RY/BY#

minimizes both CPU overhead and system power

consumption. When low, RY/BY# indicates that the

WSM is performing a block erase or word write.

RY/BY#-high indicates that the WSM is ready for a

new command, block erase is suspended (and

word write is inactive), word write is suspended, or

the device is in deep power-down mode.

The access time is 85 ns (tAVQV) at the VCC supply

voltage range of 4.75 to 5.25 V over the

temperature range, 0 to +70°C (LH28F800BG-L)/

– 40 to +85°C (LH28F800BGH-L). At 4.5 to 5.5 V

VCC, the access time is 90 ns or 120 ns. At lower

VCC voltage, the access time is 100 ns or 130 ns

(3.0 to 3.6 V) and 120 ns or 150 ns (2.7 to 3.6 V).

The Automatic Power Saving (APS) feature

substantially reduces active current when the

device is in static mode (addresses not switching).

In APS mode, the typical ICCR current is 1 mA at

5 V VCC and 3 mA at 2.7 V and 3.3 V VCC.

When CE# and RP# pins are at VCC, the ICC

CMOS standby mode is enabled. When the RP#

pin is at GND, deep power-down mode is enabled

which minimizes power consumption and provides

write protection during reset. A reset time (tPHQV) is

required from RP# switching high until outputs are

valid. Likewise, the device has a wake time (tPHEL)

from RP#-high until writes to the CUI are

recognized. With RP# at GND, the WSM is reset

and the status register is cleared.

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

- 7 -

32 k-Word Main Block

7FFFF

78000

77FFF

6FFFF

70000

68000

67FFF

60000

5FFFF

58000

57FFF

50000

4FFFF

48000

47FFF

40000

3FFFF

38000

37FFF

30000

2FFFF

28000

27FFF

20000

1FFFF

18000

17FFF

10000

0FFFF

08000

07FFF

07000

06FFF

06000

05FFF

05000

04FFF

04000

03FFF

03000

02FFF

02000

01FFF

01000

00FFF

00000

4 k-Word Parameter Block 5

4 k-Word Parameter Block 4

4 k-Word Parameter Block 3

4 k-Word Parameter Block 2

4 k-Word Parameter Block 1

4 k-Word Parameter Block 0

4 k-Word Boot Block 1

4 k-Word Boot Block 0

Bottom Boot

4 k-Word Boot Block

4 k-Word Parameter Block

32 k-Word Main Block

7FFFF

7F000

7EFFF

7DFFF

7E000

7D000

7CFFF

7C000

7BFFF

7B000

7AFFF

7A000

79FFF

79000

78FFF

78000

77FFF

70000

6FFFF

68000

67FFF

60000

5FFFF

58000

57FFF

50000

4FFFF

48000

47FFF

40000

3FFFF

38000

37FFF

30000

2FFFF

28000

27FFF

20000

1FFFF

18000

17FFF

10000

0FFFF

08000

07FFF

00000

32 k-Word Main Block 7

32 k-Word Main Block 8

32 k-Word Main Block 9

32 k-Word Main Block 10

32 k-Word Main Block 11

32 k-Word Main Block 12

32 k-Word Main Block 13

32 k-Word Main Block 14

Top Boot

Fig. 1 Memory Map

BLOCK CONFIGURATION VERSIONS

Top Boot LH28F800BG-TL

LH28F800BGH-TL

Bottom Boot LH28F800BG-BL

LH28F800BGH-BL

NOTES :

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

2 PRINCIPLES OF OPERATION

The LH28F800BG-L/BGH-L SmartVoltage flash

memories include an on-chip WSM to manage

block erase and word write functions. It allows for :

100% TTL-level control inputs, fixed power supplies

during block erasure and word write, and minimal

processor overhead with RAM-like interface timings.

After initial device power-up or return from deep

power-down mode (see Table 2 "Bus Operations"),

the device defaults to read array mode.

Manipulation of external memory control pins allow

array read, standby and output disable operations.

Status register and identifier codes can be

accessed through the CUI independent of the V PP

voltage. High voltage on VPP enables successful

block erasure and word writing. All functions

associated with altering memory contents—block

erase, word write, status and identifier codes—are

accessed via the CUI and verified through the

status register.

Commands are written using standard micro-

processor write timings. The CUI contents serve as

input to the WSM, which controls the block erase

and word write. The internal algorithms are

regulated by the WSM, including pulse repetition,

internal verification and margining of data.

Addresses and data are internally latched during

write cycles. Writing the appropriate command

outputs array data, accesses the identifier codes or

outputs status register data.

Interface software that initiates and polls progress

of block erase and word write can be stored in any

block. This code is copied to and executed from

system RAM during flash memory updates. After

successful completion, reads are again possible via

the Read Array command. Block erase suspend

allows system software to suspend a block erase to

read/write data from/to blocks other than that which

is suspended. Word write suspend allows system

software to suspend a word write to read data from

any other flash memory array location.

2.1 Data Protection

Depending on the application, the system designer

may choose to make the VPP power supply

switchable (available only when memory block

erases or word writes are required) or hardwired to

VPPH1/2/3. The device accommodates either design

practice and encourages optimization of the

processor-memory interface.

When VPP ≤VPPLK, memory contents cannot be

altered. The CUI, with two-step block erase or word

write command sequences, provides protection

from unwanted operations even when high voltage

is applied to VPP. All write functions are disabled

when VCC is below the write lockout voltage VLKO

or when RP# is at VIL. The device’s boot blocks

locking capability for WP# provides additional

protection from inadvertent code or data alteration

by block erase and word write operations.

3 BUS OPERATION

The local CPU reads and writes flash memory in-

system. All bus cycles to or from the flash memory

conform to standard microprocessor bus cycles.

3.1 Read

Information can be read from any block, identifier

codes or status register independent of the VPP

voltage. RP# can be at either VIH or VHH.

The first task is to write the appropriate read mode

command (Read Array, Read Identifier Codes or

Read Status Register) to the CUI. Upon initial

device power-up or after exit from deep power-

down mode, the device automatically resets to read

array mode. Five control pins dictate the data flow

in and out of the component : CE#, OE#, WE#,

RP# and WP#. CE# and OE# must be driven

active to obtain data at the outputs. CE# is the

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LH28F800BG-L/BGH-L (FOR TSOP, CSP)

device selection control, and when active enables

the selected memory device. OE# is the data

output (DQ0-DQ15) control and when active drives

the selected memory data onto the I/O bus. WE#

must be at VIH and RP# must be at VIH or VHH.

Fig. 11 illustrates read cycle.

3.2 Output Disable

With OE# at a logic-high level (VIH), the device

outputs are disabled. Output pins (DQ0-DQ15) are

placed in a high-impedance state.

3.3 Standby

CE# at a logic-high level (VIH) places the device in

standby mode which substantially reduces device

power consumption. DQ0-DQ15 outputs are placed

in a high-impedance state independent of OE#. If

deselected during block erase or word write, the

device continues functioning, and consuming active

power until the operation completes.

3.4 Deep Power-Down

RP# at VIL initiates the deep power-down mode.

In read modes, RP#-low deselects the memory,

places output drivers in a high-impedance state and

turns off all internal circuits. RP# must be held low

for a minimum of 100 ns. Time tPHQV is required

after return from power-down until initial memory

access outputs are valid. After this wake-up

interval, normal operation is restored. The CUI is

reset to read array mode and status register is set

to 80H.

During block erase or word write modes, RP#-low

will abort the operation. RY/BY# remains low until

the reset operation is complete. Memory contents

being altered are no longer valid; the data may be

partially erased or written. Time tPHWL is required

after RP# goes to logic-high (VIH) before another

command can be written.

As with any automated device, it is important to

assert RP# during system reset. When the system

comes out of reset, it expects to read from the flash

memory. Automated flash memories provide status

information when accessed during block erase or

word write modes. If a CPU reset occurs with no

flash memory reset, proper CPU initialization may

not occur because the flash memory may be

providing status information instead of array data.

SHARP’s flash memories allow proper CPU

initialization following a system reset through the

use of the RP# input. In this application, RP# is

controlled by the same RESET# signal that resets

the system CPU.

3.5 Read Identifier Codes Operation

The read identifier codes operation outputs the

manufacture code and device code (see Fig. 2).

Using the manufacture and device codes, the

system CPU can automatically match the device

with its proper algorithms.

Fig. 2 Device Identifier Code Memory Map

3.6 Write

Writing commands to the CUI enable reading of

device data and identifier codes. They also control

inspection and clearing of the status register. When

VCC = VCC1/2/3/4 and VPP = VPPH1/2/3, the CUI

additionally controls block erasure and word write.

The Block Erase command requires appropriate

command data and an address within the block to

be erased. The Word Write command requires the

command and address of the location to be written.

7FFFF

00002

00001

00000

Reserved for

Future Implementation

Device Code

Manufacture Code

- 10 -

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

The CUI does not occupy an addressable memory

location. It is written when WE# and CE# are

active. The address and data needed to execute a

command are latched on the rising edge of WE# or

CE# (whichever goes high first). Standard

microprocessor write timings are used. Fig. 12 and

Fig. 13 illustrate WE# and CE# controlled write

operations.

4 COMMAND DEFINITIONS

When the VPP voltage ≤VPPLK, read operations

from the status register, identifier codes, or blocks

are enabled. Placing VPPH1/2/3 on VPP enables

successful block erase and word write operations.

Device operations are selected by writing specific

commands into the CUI. Table 3 defines these

commands.

Table 2 Bus Operations

MODE NOTE RP# CE# OE# WE#

ADDRESS

VPP DQ0-15 RY/BY#

or V

VIL VIL VIH XXD

OUT X

Output Disable 3

or V

VIL VIH VIH X X High Z X

Standby 3

or V

VIH XXXXHigh Z X

Deep Power-Down 4 VIL XXXXXHigh Z VOH

Read Identifier Codes 8

or V

VIL VIL VIH

See Fig. 2

NOTE 5)

VOH

Write 3, 6, 7, 8

or V

VIL VIH VIL XXD

IN X

NOTES :

1. Refer to Section 6.2.3 "DC CHARACTERISTICS".

When VPP ≤VPPLK, memory contents can be read, but

not altered.

2. X can be VIL or VIH for control pins and addresses, and

VPPLK or VPPH1/2/3 for VPP. See Section 6.2.3 "DC

CHARACTERISTICS" for VPPLK and VPPH1/2/3 voltages.

3. RY/BY# is VOL when the WSM is executing internal

block erase or word write algorithms. It is VOH during

when the WSM is not busy, in block erase suspend

mode (with word write inactive), word write suspend

mode or deep power-down mode.

4. RP# at GND±0.2 V ensures the lowest deep power-

down current.

5. See Section 4.2 for read identifier code data.

6. Command writes involving block erase or word write are

reliably executed when VPP = VPPH1/2/3 and VCC =

VCC1/2/3/4. Block erase or word write with VIH < RP# <

VHH produce spurious results and should not be

attempted.

7. Refer to Table 3 for valid DIN during a write operation.

8. Don’t use the timing both OE# and WE# are VIL.

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

- 11 -

COMMAND BUS CYCLES NOTE FIRST BUS CYCLE SECOND BUS CYCLE

REQ’D.

Oper

(NOTE 1)

Addr

(NOTE 2)

Data

(NOTE 3)

Oper

(NOTE 1)

Addr

(NOTE 2)

Data

(NOTE 3)

Read Array/Reset 1 Write X FFH

Read Identifier Codes ≥2 4 Write X 90H Read IA ID

Read Status Register 2 Write X 70H Read X SRD

Clear Status Register 1 Write X 50H

Block Erase 2 5 Write BA 20H Write BA D0H

Word Write 2 5, 6 Write WA

40H or 10H

Write WA WD

Block Erase and 1 5 Write X B0H

Word Write Suspend

Block Erase and 1 5 Write X D0H

Word Write Resume

Table 3 Command Definitions (NOTE 7)

NOTES :

1. Bus operations are defined in Table 2.

2. X = Any valid address within the device.

IA = Identifier code address : see Fig. 2.

BA = Address within the block being erased.

WA = Address of memory location to be written.

3. SRD = Data read from status register. See Table 6 for a

description of the status register bits.

WD = Data to be written at location WA. Data is latched

on the rising edge of WE# or CE# (whichever

goes high first).

ID = Data read from identifier codes.

4. Following the Read Identifier Codes command, read

operations access manufacture and device codes. See

Section 4.2 for read identifier code data.

5. If the block is boot block, WP# must be at VIH or RP#

must be at VHH to enable block erase or word write

operations. Attempts to issue a block erase or word write

to a boot block while WP# is VIH or RP# is VIH.

6. Either 40H or 10H is recognized by the WSM as the

word write setup.

7. Commands other than those shown above are reserved

by SHARP for future device implementations and should

not be used.

- 12 -

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

4.1 Read Array Command

Upon initial device power-up and after exit from

deep power-down mode, the device defaults to

read array mode. This operation is also initiated by

writing the Read Array command. The device

remains enabled for reads until another command

is written. Once the internal WSM has started a

block erase or word write, the device will not

recognize the Read Array command until the WSM

completes its operation unless the WSM is

suspended via an Erase Suspend or Word Write

Suspend command. The Read Array command

functions independently of the VPP voltage and

RP# can be VIH or VHH.

4.2 Read Identifier Codes Command

The identifier code operation is initiated by writing

the Read Identifier Codes command. Following the

command write, read cycles from addresses shown

in Fig. 2 retrieve the manufacture and device codes

(see Table 4 for identifier code values). To

terminate the operation, write another valid

command. Like the Read Array command, the

Read Identifier Codes command functions

independently of the VPP voltage and RP# can be

VIH or VHH. Following the Read Identifier Codes

command, the following information can be read :

Table 4 Identifier Codes

4.3 Read Status Register Command

The status register may be read to determine when

a block erase or word write is complete and

whether the operation completed successfully. It

may be read at any time by writing the Read Status

subsequent read operations output data from the

status register until another valid command is

written. The status register contents are latched on

the falling edge of OE# or CE#, whichever occurs.

OE# or CE# must toggle to VIH before further reads

to update the status register latch. The Read Status

VPP voltage. RP# can be VIH or VHH.

4.4 Clear Status Register Command

Status register bits SR.5, SR.4, SR.3 or SR.1 are

set to "1"s by the WSM and can only be reset by

the Clear Status Register command. These bits

indicate various failure conditions (see Table 6 ). By

allowing system software to reset these bits,

several operations (such as cumulatively erasing

multiple blocks or writing several words in

sequence) may be performed. The status register

may be polled to determine if an error occurred

during the sequence.

To clear the status register, the Clear Status

independently of the applied VPP voltage. RP# can

be VIH or VHH. This command is not functional

during block erase or word write suspend modes.

4.5 Block Erase Command

Erase is executed one block at a time and initiated

by a two-cycle command. A block erase setup is

first written, followed by a block erase confirm.

This command sequence requires appropriate

sequencing and an address within the block to be

erased (erase changes all block data to FFFFH).

Block preconditioning, erase, and verify are handled

internally by the WSM (invisible to the system).

After the two-cycle block erase sequence is written,

the device automatically outputs status register data

when read (see Fig. 3). The CPU can detect block

erase completion by analyzing the output data of

the RY/BY# pin or status register bit SR.7.

When the block erase is complete, status register

bit SR.5 should be checked. If a block erase error

is detected, the status register should be cleared

before system software attempts corrective actions.

CODE ADDRESS DATA

Manufacture Code 00000H 00B0H

Device Code (Top Boot) 00001H 0060H

Device Code (Bottom Boot) 00001H 0062H

- 13 -

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

The CUI remains in read status register mode until

a new command is issued.

This two-step command sequence of set-up

followed by execution ensures that block contents

are not accidentally erased. An invalid Block Erase

command sequence will result in both status

reliable block erasure can only occur when VCC =

VCC1/2/3/4 and VPP = VPPH1/2/3. In the absence of

this high voltage, block contents are protected

against erasure. If block erase is attempted while

VPP ≤VPPLK, SR.3 and SR.5 will be set to "1".

Successful block erase for boot blocks requires that

the corresponding if set, that WP# = VIH or RP# =

VHH. If block erase is attempted to boot block when

the corresponding WP# = VIL or RP# = VIH, SR.1

and SR.5 will be set to "1". Block erase operations

with VIH < RP# < VHH produce spurious results and

should not be attempted.

4.6 Word Write Command

Word write is executed by a two-cycle command

sequence. Word write setup (standard 40H or

alternate 10H) is written, followed by a second write

that specifies the address and data (latched on the

rising edge of WE#). The WSM then takes over,

controlling the word write and write verify algorithms

internally. After the word write sequence is written,

the device automatically outputs status register data

when read (see Fig. 4). The CPU can detect the

completion of the word write event by analyzing the

RY/BY# pin or status register bit SR.7.

When word write is complete, status register bit

SR.4 should be checked. If word write error is

detected, the status register should be cleared. The

internal WSM verify only detects errors for "1"s that

do not successfully write to "0"s. The CUI remains

in read status register mode until it receives another

command.

Reliable word writes can only occur when VCC =

VCC1/2/3/4 and VPP = VPPH1/2/3. In the absence of

this high voltage, memory contents are protected

against word writes. If word write is attempted while

VPP ≤VPPLK, status register bits SR.3 and SR.4 will

be set to "1". Successful word write for boot blocks

requires that the corresponding if set, that WP# =

VIH or RP# = VHH. If word write is attempted to

boot block when the corresponding WP# = VIL or

RP# = VIH, SR.1 and SR.4 will be set to "1". Word

write operations with VIH < RP# < VHH produce

spurious results and should not be attempted.

4.7 Block Erase Suspend Command

The Block Erase Suspend command allows block

erase interruption to read or word write data in

another block of memory. Once the block erase

process starts, writing the Block Erase Suspend

command requests that the WSM suspend the

block erase sequence at a predetermined point in

the algorithm. The device outputs status register

data when read after the Block Erase Suspend

command is written. Polling status register bits

SR.7 and SR.6 can determine when the block

erase operation has been suspended (both will be

set to "1"). RY/BY# will also transition to VOH.

Specification tWHRH2 defines the block erase

suspend latency.

At this point, a Read Array command can be

written to read data from blocks other than that

which is suspended. A Word Write command

sequence can also be issued during erase suspend

to program data in other blocks. Using the Word

Write Suspend command (see Section 4.8), a

word write operation can also be suspended.

During a word write operation with block erase

suspended, status register bit SR.7 will return to "0"

and the RY/BY# output will transition to VOL.

However, SR.6 will remain "1" to indicate block

erase suspend status.

- 14 -

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

The only other valid commands while block erase is

suspended are Read Status Register and Block

Erase Resume. After a Block Erase Resume

command is written to the flash memory, the WSM

will continue the block erase process. Status

and RY/BY# will return to VOL. After the Erase

Resume command is written, the device

automatically outputs status register data when

read (see Fig. 5). VPP must remain at VPPH1/2/3

(the same VPP level used for block erase) while

block erase is suspended. RP# must also remain at

VIH or VHH (the same RP# level used for block

erase). WP# must also remain at VIL or VIH (the

same WP# level used for block erase). Block erase

cannot resume until word write operations initiated

during block erase suspend have completed.

4.8 Word Write Suspend Command

The Word Write Suspend command allows word

write interruption to read data in other flash memory

locations. Once the word write process starts,

writing the Word Write Suspend command requests

that the WSM suspend the word write sequence at

a predetermined point in the algorithm. The device

continues to output status register data when read

after the Word Write Suspend command is written.

Polling status register bits SR.7 and SR.2 can

determine when the word write operation has been

suspended (both will be set to "1"). RY/BY# will

also transition to VOH. Specification tWHRH1 defines

the word write suspend latency.

At this point, a Read Array command can be

written to read data from locations other than that

which is suspended. The only other valid

commands while word write is suspended are Read

Status Register and Word Write Resume. After

Word Write Resume command is written to the

flash memory, the WSM will continue the word

write process. Status register bits SR.2 and SR.7

will automatically clear and RY/BY# will return to

VOL. After the Word Write Resume command is

written, the device automatically outputs status

remain at VPPH1/2/3 (the same VPP level used for

word write) while in word write suspend mode. RP#

must also remain at VIH or VHH (the same RP#

level used for word write). WP# must also remain

at VIL or VIH (the same WP# level used for word

write).

4.9 Block Locking

This Boot Block flash memory architecture features

two hardware-lockable boot blocks so that the

kernel code for the system can be kept secure

while other blocks are programmed or erased as

necessary.

4.9.1 VPP = VIL FOR COMPLETE PROTECTION

The VPP programming voltage can be held low for

complete write protection of all blocks in the flash

device.

4.9.2 WP# = VIL FOR BLOCK LOCKING

The lockable blocks are locked when WP# = VIL;

any program or erase operation to a locked block

will result in an error, which will be reflected in the

status register. For top configuration, the top two

boot blocks are lockable. For the bottom

configuration, the bottom two boot blocks are

lockable. Unlocked blocks can be programmed or

erased normally (Unless VPP is below VPPLK).

4.9.3 BLOCK UNLOCKING

WP# = VIH or RP# = VHH unlocks all lockable

blocks.

These blocks can now be programmed or erased.

WP# or RP# controls all block locking and VPP

provides protection against spurious writes. Table 5

defines the write protection methods.

- 15 -

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

Table 6 Status Register Definition

WSMS ESS ES WWS VPPS WWSS DPS R

76543210

SR.7 = WRITE STATE MACHINE STATUS (WSMS)

1 = Ready

0 = Busy

SR.6 = ERASE SUSPEND STATUS (ESS)

1 = Block Erase Suspended

0 = Block Erase in Progress/Completed

SR.5 =

ERASE STATUS (ES)

1 = Error in Block Erase

0 = Successful Block Erase

SR.4 =

WORD WRITE STATUS (WWS)

1 = Error in Word Write

Successful Word Write

SR.3 = VPP STATUS (VPPS)

1=VPP Low Detect, Operation Abort

0=V

PP OK

SR.2 = WORD WRITE SUSPEND STATUS (WWSS)

1 = Word Write Suspended

0 = Word Write in Progress/Completed

SR.1 = DEVICE PROTECT STATUS (DPS)

1 = WP# or RP# Lock Detected, Operation Abort

0 = Unlock

SR.0 =

RESERVED FOR FUTURE ENHANCEMENTS (R)

NOTES :

Check RY/BY# or SR.7 to determine block erase or word

write completion. SR.6-0 are invalid while SR.7 = "0".

If both SR.5 and SR.4 are "1"s after a block erase attempt, an

improper command sequence was entered.

SR.3 does not provide a continuous indication of VPP level.

The WSM interrogates and indicates the VPP level only after

Block Erase or Word Write command sequences.

SR.3 is not guaranteed to reports accurate feedback only

when VPP ≠VPPH1/2/3.

The WSM interrogates the WP# and RP# only after Block

Erase or Word Write command sequences. It informs the

system, depending on the attempted operation, if the WP# is

not VIH, RP# is not VHH.

SR.0 is reserved for future use and should be masked out

when polling the status register.

OPERATION

VPP

RP# WP#

EFFECT

VIL X X All Blocks Locked.

Block Erase

VIL X All Blocks Locked.

or > V

PPLK

VHH X All Blocks Unlocked.

Word Write

VIH VIL

2 Boot Blocks Locked.

VIH All Blocks Unlocked.

Table 5 Write Protection Alternatives

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

- 16 -

Block Erase

Complete

Start

Write 20H,

Block Address

Write D0H,

Block Address

Read

Status Register

SR.7 =

Full Status

Check if Desired

Repeat for subsequent block erasures.

Full status check can be done after each block erase or after

a sequence of block erasures.

Write FFH after the last block erase operation to place device

in read array mode.

BUS

OPERATION

Write

Read

Standby

COMMAND

Erase Setup

COMMENTS

Data = 20H

Addr = Within Block to be Erased

Data = D0H

Addr = Within Block to be Erased

Status Register Data

Check SR.7

1 = WSM Ready

0 = WSM Busy

SR.3 =

FULL STATUS CHECK PROCEDURE

Read Status Register

Data (See Above)

VPP Range Error

SR.1 = Device Protect Error

BUS

OPERATION

COMMAND COMMENTS

Standby

Check SR.1

1 = Device Protect Detect

Check SR.5

1 = Block Erase Error

SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear

Status Register command in cases where multiple blocks

are erased before full status is checked.

If error is detected, clear the status register before attempting

retry or other error recovery.

Suspend

Block Erase Yes

Suspend Block

Erase Loop

Erase

Confirm

Block Erase

Successful

SR.4, 5 = Command Sequence

Error

SR.5 = Block Erase

Error

Standby Check SR.3

1 = VPP Error Detect

Standby Check SR.4, 5

Both 1 = Command Sequence Error

Fig. 3 Automated Block Erase Flowchart

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

- 17 -

Word Write

Complete

Start

Write 40H or 10H,

Address

Write Word

Data and Address

Read

Status Register

SR.7 =

Full Status

Check if Desired

Repeat for subsequent word writes.

SR full status check can be done after each word write or after

a sequence of word writes.

Write FFH after the last word write operation to place device

in read array mode.

BUS

OPERATION

Write

Read

Standby

COMMAND

Setup

Word Write

COMMENTS

Data = 40H or 10H

Addr = Location to be Written

Data = Data to be Written

Addr = Location to be Written

Status Register Data

Check SR.7

1 = WSM Ready

0 = WSM Busy

SR.3 =

FULL STATUS CHECK PROCEDURE

Read Status Register

Data (See Above)

VPP Range Error

SR.1 = Device Protect Error

BUS

OPERATION

COMMAND COMMENTS

Standby Check SR.1

1 = Device Protect Detect

SR.4, SR.3 and SR.1 are only cleared by the Clear Status

written before full status is checked.

If error is detected, clear the status register before attempting

retry or other error recovery.

Suspend

Word Write Yes

Suspend Word

Write Loop

Word Write

Successful

SR.4 = Word Write Error

Standby Check SR.3

1 = VPP Error Detect

Standby Check SR.4

1 = Data Write Error

Fig. 4 Automated Word Write Flowchart

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

- 18 -

Block Erase

Resumed

Start

Write B0H

Read

Status Register

SR.7 =

Word Write

BUS

OPERATION

Write

Read

Standby

COMMAND

Erase

Suspend

COMMENTS

Data = B0H

Addr = X

Status Register Data

Addr = X

Check SR.7

1 = WSM Ready

0 = WSM Busy

Check SR.6

1 = Block Erase Suspended

0 = Block Erase Completed

Erase

Resume

SR.6 =

Done?

Write D0H

Block Erase

Completed

Write FFH

Read

Array Data

Yes

Write Data = D0H

Addr = X

Read

or Word

Write?

Read

Read Array Data Word Write Loop

Fig. 5 Block Erase Suspend/Resume Flowchart

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

- 19 -

Word Write Resumed

Start

Write B0H

Read

Status Register

SR.7 =

Write FFH

BUS

OPERATION

Write

Read

Standby

COMMAND

Word Write

Suspend

COMMENTS

Data = B0H

Addr = X

Status Register Data

Addr = X

Check SR.7

1 = WSM Ready

0 = WSM Busy

Check SR.2

1 = Word Write Suspended

0 = Word Write Completed

Read Array

SR.2 =

Read

Array Data

Done

Reading

Write D0H

Word Write

Completed

Write FFH

Read

Array Data

Yes

Write

Read

Write Word Write

Resume

Data = FFH

Addr = X

Read array locations other

than that being written.

Data = D0H

Addr = X

Fig. 6 Word Write Suspend/Resume Flowchart

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

5 DESIGN CONSIDERATIONS

5.1 Three-Line Output Control

The device will often be used in large memory

arrays. SHARP provides three control inputs to

accommodate multiple memory connections. Three-

line control provides for :

a. Lowest possible memory power consumption.

b. Complete assurance that data bus contention

will not occur.

To use these control inputs efficiently, an address

decoder should enable CE# while OE# should be

connected to all memory devices and the system’s

READ# control line. This assures that only selected

memory devices have active outputs while

deselected memory devices are in standby mode.

RP# should be connected to the system

POWERGOOD signal to prevent unintended writes

during system power transitions. POWERGOOD

should also toggle during system reset.

5.2 RY/BY#, Block Erase and Word

Write Polling

RY/BY# is a full CMOS output that provides a

hardware method of detecting block erase and

word write completion. It transitions low after block

erase or word write commands and returns to VOH

when the WSM has finished executing the internal

algorithm.

RY/BY# can be connected to an interrupt input of

the system CPU or controller. It is active at all

times. RY/BY# is also VOH when the device is in

block erase suspend (with word write inactive),

word write suspend or deep power-down modes.

5.3 Power Supply Decoupling

Flash memory power switching characteristics

require careful device decoupling. System

designers are interested in three supply current

issues; standby current levels, active current levels

and transient peaks produced by falling and rising

edges of CE# and OE#. Transient current

magnitudes depend on the device outputs’

capacitive and inductive loading. Two-line control

and proper decoupling capacitor selection will

suppress transient voltage peaks. Each device

should have a 0.1 µF ceramic capacitor connected

between its VCC and GND and between its VPP

and GND. These high-frequency, low inductance

capacitors should be placed as close as possible to

package leads. Additionally, for every eight devices,

a 4.7 µF electrolytic capacitor should be placed at

the array’s power supply connection between VCC

and GND. The bulk capacitor will overcome voltage

slumps caused by PC board trace inductance.

5.4 VPP Trace on Printed Circuit Boards

Updating flash memories that reside in the target

system requires that the printed circuit board

designers pay attention to the VPP power supply

trace. The VPP pin supplies the memory cell current

for word writing and block erasing. Use similar trace

widths and layout considerations given to the VCC

power bus. Adequate VPP supply traces and

decoupling will decrease VPP voltage spikes and

overshoots.

5.5 VCC, VPP, RP# Transitions

Block erase and word write are not guaranteed if

VPP falls outside of a valid VPPH1/2/3 range, VCC falls

outside of a valid VCC1/2/3/4 range, or RP# ≠VIH or

VHH. If VPP error is detected, status register bit SR.3

is set to "1" along with SR.4 or SR.5, depending on

the attempted operation. If RP# transitions to VIL

during block erase or word write, RY/BY# will

remain low until the reset operation is complete.

Then, the operation will abort and the device will

enter deep power-down. The aborted operation may

leave data partially altered. Therefore, the command

sequence must be repeated after normal operation

is restored. Device power-off or RP# transitions to

VIL clear the status register.

- 20 -

- 21 -

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

The CUI latches commands issued by system

software and is not altered by VPP or CE#

transitions or WSM actions. Its state is read array

mode upon power-up, after exit from deep power-

down or after VCC transitions below VLKO.

After block erase or word write, even after VPP

transitions down to VPPLK, the CUI must be placed

in read array mode via the Read Array command if

subsequent access to the memory array is desired.

5.6 Power-Up/Down Protection

The device is designed to offer protection against

accidental block erasure or word writing during

power transitions. Upon power-up, the device is

indifferent as to which power supply (VPP or VCC)

powers-up first. Internal circuitry resets the CUI to

read array mode at power-up.

A system designer must guard against spurious

writes for VCC voltages above VLKO when VPP is

active. Since both WE# and CE# must be low for a

command write, driving either to VIH will inhibit

writes. The CUI’s two-step command sequence

architecture provides added level of protection

against data alteration.

WP# provides additional protection from inadvertent

code or data alteration. The device is disabled

while RP# = VIL regardless of its control inputs

state.

5.7 Power Consumption

When designing portable systems, designers must

consider battery power consumption not only during

device operation, but also for data retention during

system idle time. Flash memory’s nonvolatility

increases usable battery life because data is

retained when system power is removed.

In addition, deep power-down mode ensures

extremely low power consumption even when

system power is applied. For example, portable

computing products and other power sensitive

applications that use an array of devices for solid-

state storage can consume negligible power by

lowering RP# to VIL standby or sleep modes. If

access is again needed, the devices can be read

following the tPHQV and tPHWL wake-up cycles

required after RP# is first raised to VIH. See Section

6.2.4 through 6.2.6 "AC CHARACTERISTICS -

READ-ONLY and WRITE OPERATIONS" and

Fig. 11, Fig. 12 and Fig.13 for more information.

- 22 -

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

6 ELECTRICAL SPECIFICATIONS

6.1 Absolute Maximum Ratings∗

Operating Temperature

• LH28F800BG-L

During Read, Block Erase and

Word Write............................. 0 to +70°C

(NOTE 1)

Temperature under Bias............. –10 to +80°C

• LH28F800BGH-L

During Read, Block Erase and

Word Write ........................ –40 to +85°C

(NOTE 2)

Temperature under Bias............. –40 to +85°C

Storage Temperature........................ –65 to +125°C

Voltage On Any Pin

(except V

, V

, and RP#)

.... –2.0 to +7.0 V

(NOTE 3)

VCC Supply Voltage ................. –2.0 to +7.0 V

(NOTE 3)

VPP Update Voltage during

Block Erase and

Word Write.................. –2.0 to +14.0 V

(NOTE 3, 4)

RP# Voltage ........................ –2.0 to +14.0 V

(NOTE 3, 4)

Output Short Circuit Current ............... 100 mA

(NOTE 5)

∗

WARNING : Stressing the device beyond the

Absolute Maximum Ratings" may cause

permanent damage. These are stress ratings only.

Operation beyond the "Operating Conditions" is not

recommended and extended exposure beyond the

"Operating Conditions" may affect device reliability.

NOTES :

1. Operating temperature is for commercial product defined

by this specification.

2. Operating temperature is for extended temperature

product defined by this specification.

3. All specified voltages are with respect to GND. Minimum

DC voltage is –0.5 V on input/output pins and –0.2 V on

VCC and VPP pins. During transitions, this level may

undershoot to –2.0 V for periods < 20 ns. Maximum DC

voltage on input/output pins and VCC is VCC+0.5 V

which, during transitions, may overshoot to VCC+2.0 V

for periods < 20 ns.

4. Maximum DC voltage on VPP and RP# may overshoot

to +14.0 V for periods < 20 ns.

5. Output shorted for no more than one second. No more

than one output shorted at a time.

NOTICE : The specifications are subject to

change without notice. Verify with your local

SHARP sales office that you have the latest

datasheet before finalizing a design.

SYMBOL

PARAMETER NOTE MIN. MAX. UNIT VERSIONS

TAOperating Temperature 1

+70 ˚C LH28F800BG-L

–40 +85 ˚C LH28F800BGH-L

VCC1 VCC Supply Voltage (2.7 to 3.6 V) 2.7 3.6 V

VCC2 VCC Supply Voltage (3.3±0.3 V) 3.0 3.6 V

VCC3 VCC Supply Voltage (5.0±0.25 V) 4.75 5.25 V LH28F800BG-L85/BGH-L85

VCC4 VCC Supply Voltage (5.0±0.5 V) 4.50 5.50 V

6.2 Operating Conditions

NOTE :

1. Test condition : Ambient temperature

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

- 23 -

6.2.2 AC INPUT/OUTPUT TEST CONDITIONS

TEST POINTSINPUT OUTPUT

1.35 1.35

2.7

0.0

Fig. 7 Transient Input/Output Reference Waveform for VCC = 2.7 to 3.6 V

1.5 1.5

3.0

0.0

TEST POINTSINPUT OUTPUT

Fig. 8 Transient Input/Output Reference Waveform for VCC = 3.3±0.3 V and

VCC = 5.0±0.25 V (High Speed Testing Configuration)

AC test inputs are driven at 2.7 V for a Logic "1" and 0.0 V for a Logic "0". Input timing begins, and output

timing ends, at 1.35 V. Input rise and fall times (10% to 90%) < 10 ns.

AC test inputs are driven at 3.0 V for a Logic "1" and 0.0 V for a Logic "0". Input timing begins, and output

timing ends, at 1.5 V. Input rise and fall times (10% to 90%) < 10 ns.

2.0

0.8

2.0

0.8

2.4

0.45

TEST POINTSINPUT OUTPUT

Fig. 9 Transient Input/Output Reference Waveform for

VCC = 5.0±0.5 V (Standard Testing Configuration)

AC test inputs are driven at VOH (2.4 VTTL) for a Logic "1" and VOL (0.45 VTTL) for a Logic "0". Input timing

begins at VIH (2.0 VTTL) and VIL (0.8 VTTL). Output timing ends at VIH and VIL. Input rise and fall times (10% to

90%) < 10 ns.

NOTE :

1. Sampled, not 100% tested.

SYMBOL PARAMETER TYP. MAX. UNIT CONDITION

CIN Input Capacitance 7 10 pF VIN = 0.0 V

COUT Output Capacitance 9 12 pF VOUT = 0.0 V

6.2.1 CAPACITANCE (NOTE 1) TA= +25˚C, f = 1 MHz

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

- 24 -

DEVICE

UNDER

TEST

CL Includes Jig

Capacitance

RL = 3.3 kΩ

OUT

1.3 V

1N914

Fig. 10 Transient Equivalent Testing

Load Circuit

TEST CONFIGURATION CL(pF)

VCC = 3.3±0.3 V, 2.7 to 3.6 V 50

VCC = 5.0±0.25 V (NOTE 1) 30

VCC = 5.0±0.5 V 100

Test Configuration Capacitance Loading Value

NOTE :

1. Applied to high-speed products, LH28F800BG-L85 and

LH28F800BGH-L85.

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

- 25 -

6.2.3 DC CHARACTERISTICS

SYMBOL

PARAMETER NOTE

= 2.7 to 3.6 V

VCC = 5.0±0.5 V UNIT TEST

TYP. MAX. TYP. MAX. CONDITIONS

ILI Input Load Current 1 ±0.5 ±1 µA VCC = VCC Max.

VIN = VCC or GND

ILO Output Leakage Current 1 ±0.5 ±10 µA VCC = VCC Max.

VOUT = VCC or GND

CMOS Inputs

25 50 30 100 µA VCC = VCC Max.

ICCS VCC Standby Current 1, 3, 6 CE# = RP# = VCC±0.2 V

TTL Inputs

0.2 2 0.4 2 mA VCC = VCC Max.

CE# = RP# = VIH

ICCD

Deep Power-

LH28F800BG-L

1410 10

µA RP# = GND±0.2 V

Down Current

LH28F800BGH-L

420 20 IOUT (RY/BY#) = 0 mA

CMOS Inputs

VCC = VCC Max.

15 25 50 mA CE# = GND

f = 5 MHz (3.3 V, 2.7 V),

8 MHz (5 V)

ICCR VCC Read Current 1, 5, 6 IOUT = 0 mA

TTL Inputs

VCC = VCC Max.

30 65 mA CE# = GND

f = 5 MHz (3.3 V, 2.7 V),

8 MHz (5 V)

IOUT = 0 mA

517——mAVPP = 2.7 to 3.6 V

ICCW VCC Word Write Current 1, 7 5 17 35 mA VPP = 5.0±0.5 V

512 30mAVPP = 12.0±0.6 V

417——mAVPP = 2.7 to 3.6 V

ICCE VCC Block Erase Current 1, 7 4 17 30 mA VPP = 5.0±0.5 V

412 25mAVPP = 12.0±0.6 V

ICCWS VCC Word Write or Block 1, 2 1 6 1 10 mA CE# = VIH

ICCES Erase Suspend Current

IPPS

Standby or Read Current

1±2 ±15 ±2 ±15 µA VPP ≤VCC

IPPR 10 200 10 200 µA VPP > VCC

IPPD VPP Deep Power-Down 1 0.1 5 0.1 5 µA RP# = GND±0.2 V

Current 12 40 — — mA VPP = 2.7 to 3.6 V

IPPW VPP Word Write Current 1, 7 40 40 mA VPP = 5.0±0.5 V

30 30 mA VPP = 12.0±0.6 V

825——mAVPP = 2.7 to 3.6 V

IPPE VPP Block Erase Current 1, 7 25 25 mA VPP = 5.0±0.5 V

20 20 mA VPP = 12.0±0.6 V

IPPWS VPP Word Write or Block 1 10 200 10 200 µA VPP = VPPH1/2/3

IPPES Erase Suspend Current

- 26 -

SYMBOL

PARAMETER NOTE

= 2.7 to 3.6 V

VCC = 5.0±0.5 V UNIT TEST

MIN. MAX. MIN. MAX. CONDITIONS

VIL Input Low Voltage 7 –0.5 0.8 –0.5 0.8 V

VIH Input High Voltage 7 2.0 VCC 2.0 VCC V

+0.5 +0.5 VCC = VCC Min.

VOL Output Low Voltage 3, 7 0.4 0.45 V IOL = 5.8 mA (5 V)

= 2.0 mA (3.3 V, 2.7 V)

Output High Voltage VCC = VCC Min.

VOH1 (TTL) 3, 7 2.4 2.4 V IOH = –2.5 mA (5 V)

= –2.0 mA

(3.3 V, 2.7 V)

0.85 0.85 VVCC = VCC Min.

VOH2 Output High Voltage 3, 7 VCC VCC IOH = –2.5 mA

(CMOS) VCC VCC VVCC = VCC Min.

–0.4 –0.4 IOH = –100 µA

VPPLK VPP Lockout Voltage during 4, 7 1.5 1.5 V

Normal Operations

VPPH1

Voltage during Word Write

2.7 3.6 ——

or Block Erase Operations

VPPH2

Voltage during Word Write

4.5 5.5 4.5 5.5 V

or Block Erase Operations

VPPH3

Voltage during Word Write

11.4 12.6 11.4 12.6 V

or Block Erase Operations

VLKO VCC Lockout Voltage 2.0 2.0 V

VHH RP# Unlock Voltage 8, 9 11.4 12.6 11.4 12.6 V Unavailable WP#

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

6.2.3 DC CHARACTERISTICS (contd.)

NOTES :

1. All currents are in RMS unless otherwise noted. Typical

values at nominal VCC voltage and TA= +25˚C. These

currents are valid for all product versions (packages and

speeds).

2. ICCWS and ICCES are specified with the device de-

selected. If reading or word writing in erase suspend

mode, the device’s current draw is the sum of ICCWS or

ICCES and ICCR or ICCW, respectively.

3. Includes RY/BY#.

4. Block erases and word writes are inhibited when VPP ≤

VPPLK, and not guaranteed in the range between VPPLK

(max.) and VPPH1 (min.), between VPPH1 (max.) and

VPPH2 (min.), between VPPH2 (max.) and VPPH3 (min.),

and above VPPH3 (max.).

5. Automatic Power Saving (APS) reduces typical ICCR to

1 mA at 5 V VCC and 3 mA at 2.7 V and 3.3 V VCC in

static operation.

6. CMOS inputs are either VCC±0.2 V or GND±0.2 V. TTL

inputs are either VIL or VIH.

7. Sampled, not 100% tested.

8. Boot block erases and word writes are inhibited when

the corresponding RP# = VIH or WP# = VIL. Block erase

and word write operations are not guaranteed with VIH <

RP# < VHH and should not be attempted.

9. RP# connection to a VHH supply is allowed for a

maximum cumulative period of 80 hours.

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

- 27 -

6.2.4 AC CHARACTERISTICS - READ-ONLY OPERATIONS (NOTE 1)

•VCC = 2.7 to 3.6 V, TA= 0 to +70˚C or –40 to +85˚C

VERSIONS LH28F800BG-L85 LH28F800BG-L12

LH28F800BGH-L85 LH28F800BGH-L12 UNIT

SYMBOL

PARAMETER NOTE MIN. MAX. MIN. MAX.

tAVAV Read Cycle Time 120 150 ns

tAVQV Address to Output Delay 120 150 ns

tELQV CE# to Output Delay 2 120 150 ns

tPHQV RP# High to Output Delay 600 600 ns

tGLQV OE# to Output Delay 2 50 55 ns

tELQX CE# to Output in Low Z 3 0 0 ns

tEHQZ CE# High to Output in High Z 3 55 55 ns

tGLQX OE# to Output in Low Z 3 0 0 ns

tGHQZ OE# High to Output in High Z 3 20 25 ns

tOH Output Hold from Address, CE# or 30 0 ns

OE# Change, Whichever Occurs First

VERSIONS LH28F800BG-L85 LH28F800BG-L12

LH28F800BGH-L85 LH28F800BGH-L12 UNIT

SYMBOL

PARAMETER NOTE MIN. MAX. MIN. MAX.

tAVAV Read Cycle Time 100 130 ns

tAVQV Address to Output Delay 100 130 ns

tELQV CE# to Output Delay 2 100 130 ns

tPHQV RP# High to Output Delay 600 600 ns

tGLQV OE# to Output Delay 2 50 55 ns

tELQX CE# to Output in Low Z 3 0 0 ns

tEHQZ CE# High to Output in High Z 3 55 55 ns

tGLQX OE# to Output in Low Z 3 0 0 ns

tGHQZ OE# High to Output in High Z 3 20 25 ns

tOH Output Hold from Address, CE# or 30 0 ns

OE# Change, Whichever Occurs First

NOTES :

1. See AC Input/Output Reference Waveform (Fig. 7 through Fig. 9) for maximum allowable input slew rate.

2. OE# may be delayed up to tELQV-tGLQV after the falling edge of CE# without impact on tELQV.

3. Sampled, not 100% tested.

•VCC = 3.3±0.3 V, TA= 0 to +70˚C or –40 to +85˚C

- 28 -

SYMBOL

PARAMETER NOTE MIN. MAX. MIN. MAX. MIN. MAX.

tAVAV Read Cycle Time 85 90 120 ns

tAVQV Address to Output Delay 85 90 120 ns

tELQV CE# to Output Delay 2 85 90 120 ns

tPHQV RP# High to Output Delay 400 400 400 ns

tGLQV OE# to Output Delay 2 40 45 50 ns

tELQX CE# to Output in Low Z 3 0 0 0 ns

tEHQZ CE# High to Output in High Z 3 55 55 55 ns

tGLQX OE# to Output in Low Z 3 0 0 0 ns

tGHQZ OE# High to Output in High Z 3 10 10 15 ns

Output Hold from Address,

tOH CE# or OE# Change, 3 0 0 0 ns

Whichever Occurs First

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

NOTES :

1. See AC Input/Output Reference Waveform (Fig. 7

through Fig. 9) for maximum allowable input slew rate.

2. OE# may be delayed up to tELQV-tGLQV after the falling

edge of CE# without impact on tELQV.

3. Sampled, not 100% tested.

4. See Fig. 8 "Transient Input/Output Reference

Waveform" and Fig. 10 "Transient Equivalent Testing

Load Circuit" (High Speed Configuration) for testing

characteristics.

5. See Fig. 9 "Transient Input/Output Reference

Waveform" and Fig. 10 "Transient Equivalent Testing

Load Circuit" (Standard Configuration) for testing

characteristics.

VERSIONS

±0.25 V

VCC±0.5 V

(NOTE 4)

LH28F800BG-L85

LH28F800BGH-L85

(NOTE 5)

LH28F800BG-L12

LH28F800BGH-L12

(NOTE 5)

LH28F800BG-L85

LH28F800BGH-L85

UNIT

6.2.4 AC CHARACTERISTICS - READ-ONLY OPERATIONS (contd.) (NOTE 1)

•VCC = 5.0±0.25 V, 5.0±0.5 V, TA= 0 to +70˚C or –40 to +85˚C

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

- 29 -

ADDRESSES (A)

CE# (E)

OE# (G)

WE# (W)

DATA (D/Q)

(DQ0-DQ15)

RP# (P)

VCC

Standby Device

Address Selection Data Valid

Address Stable

tAVAV

tEHQZ

tGHQZ

High Z Valid Output

tGLQV

tELQV

tGLQX

tELQX

tAVQV

tPHQV

High Z

tOH

VIL

VOH

VOL

VIH

VIL

Fig. 11 AC Waveform for Read Operations

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

- 30 -

6.2.5 AC CHARACTERISTICS - WRITE OPERATIONS (NOTE 1)

•VCC = 2.7 to 3.6 V, TA= 0 to +70˚C or –40 to +85˚C

VERSIONS LH28F800BG-L85 LH28F800BG-L12

LH28F800BGH-L85 LH28F800BGH-L12 UNIT

SYMBOL

PARAMETER NOTE MIN. MAX. MIN. MAX.

tAVAV Write Cycle Time 120 150 ns

tPHWL RP# High Recovery to WE# Going Low 2 1 1 µs

tELWL CE# Setup to WE# Going Low 10 10 ns

tWLWH WE# Pulse Width 50 50 ns

tPHHWH RP# VHH Setup to WE# Going High 2 100 100 ns

tSHWH WP# VIH Setup to WE# Going High 2 100 100 ns

tVPWH VPP Setup to WE# Going High 2 100 100 ns

tAVWH Address Setup to WE# Going High 3 50 50 ns

tDVWH Data Setup to WE# Going High 3 50 50 ns

tWHDX Data Hold from WE# High 5 5 ns

tWHAX Address Hold from WE# High 5 5 ns

tWHEH CE# Hold from WE# High 10 10 ns

tWHWL WE# Pulse Width High 30 30 ns

tWHRL WE# High to RY/BY# Going Low 100 100 ns

tWHGL Write Recovery before Read 0 0 ns

tQVVL VPP Hold from Valid SRD, RY/BY# High 2, 4 0 0 ns

tQVPH RP# VHH Hold from Valid SRD, RY/BY# High 2, 4 0 0 ns

tQVSL WP# VIH Hold from Valid SRD, RY/BY# High 2, 4 0 0 ns

NOTES :

1. Read timing characteristics during block erase and word

write operations are the same as during read-only

operations. Refer to Section 6.2.4 "AC CHARAC-

TERISTICS" for read-only operations.

2. Sampled, not 100% tested.

3. Refer to Table 3 for valid AIN and DIN for block erase or

word write.

4. VPP should be held at VPPH1/2/3 (and if necessary RP#

should be held at VHH) until determination of block erase

or word write success (SR.1/3/4/5 = 0 : on Boot Blocks,

SR.3/4/5 = 0 : on Parameter Blocks and Main Blocks).

- 31 -

VERSIONS LH28F800BG-L85 LH28F800BG-L12

LH28F800BGH-L85 LH28F800BGH-L12 UNIT

SYMBOL

PARAMETER NOTE MIN. MAX. MIN. MAX.

tAVAV Write Cycle Time 100 130 ns

tPHWL RP# High Recovery to WE# Going Low 2 1 1 µs

tELWL CE# Setup to WE# Going Low 10 10 ns

tWLWH WE# Pulse Width 50 50 ns

tPHHWH RP# VHH Setup to WE# Going High 2 100 100 ns

tSHWH WP# VIH Setup to WE# Going High 2 100 100 ns

tVPWH VPP Setup to WE# Going High 2 100 100 ns

tAVWH Address Setup to WE# Going High 3 50 50 ns

tDVWH Data Setup to WE# Going High 3 50 50 ns

tWHDX Data Hold from WE# High 5 5 ns

tWHAX Address Hold from WE# High 5 5 ns

tWHEH CE# Hold from WE# High 10 10 ns

tWHWL WE# Pulse Width High 30 30 ns

tWHRL WE# High to RY/BY# Going Low 100 100 ns

tWHGL Write Recovery before Read 0 0 ns

tQVVL VPP Hold from Valid SRD, RY/BY# High 2, 4 0 0 ns

tQVPH RP# VHH Hold from Valid SRD, RY/BY# High 2, 4 0 0 ns

tQVSL WP# VIH Hold from Valid SRD, RY/BY# High 2, 4 0 0 ns

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

6.2.5 AC CHARACTERISTICS - WRITE OPERATIONS (contd.) (NOTE 1)

•VCC = 3.3±0.3 V, TA= 0 to +70˚C or –40 to +85˚C

NOTES :

1. Read timing characteristics during block erase and word

write operations are the same as during read-only

operations. Refer to Section 6.2.4 "AC CHARAC-

TERISTICS" for read-only operations.

2. Sampled, not 100% tested.

3. Refer to Table 3 for valid AIN and DIN for block erase or

word write.

4. VPP should be held at VPPH1/2/3 (and if necessary RP#

should be held at VHH) until determination of block erase

or word write success (SR.1/3/4/5 = 0 : on Boot Blocks,

SR.3/4/5 = 0 : on Parameter Blocks and Main Blocks).

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

- 32 -

NOTES :

1. Read timing characteristics during block erase and word

write operations are the same as during read-only

operations. Refer to Section 6.2.4 "AC CHARAC-

TERISTICS" for read-only operations.

2. Sampled, not 100% tested.

3. Refer to Table 3 for valid AIN and DIN for block erase or

word write.

4. VPP should be held at VPPH1/2/3 (and if necessary RP#

should be held at VHH) until determination of block erase

or word write success (SR.1/3/4/5 = 0 : on Boot Blocks,

SR.3/4/5 = 0 : on Parameter Blocks and Main Blocks).

5. See Fig. 8 "Transient Input/Output Reference

Waveform" and Fig. 10 "Transient Equivalent Testing

Load Circuit" (High Seed Configuration) for testing

characteristics.

6. See Fig. 9 "Transient Input/Output Reference

Waveform" and Fig. 10 "Transient Equivalent Testing

Load Circuit" (Standard Configuration) for testing

characteristics.

SYMBOL

PARAMETER NOTE MIN. MAX. MIN. MAX. MIN. MAX.

tAVAV Write Cycle Time 85 90 120 ns

tPHWL RP# High Recovery to WE# 2111µs

Going Low

tELWL CE# Setup to WE# Going Low 10 10 10 ns

tWLWH WE# Pulse Width 40 40 40 ns

tPHHWH

RP# V

Setup to WE# Going High

2 100 100 100 ns

tSHWH

WP# V

Setup to WE# Going High

2 100 100 100 ns

tVPWH VPP Setup to WE# Going High 2 100 100 100 ns

tAVWH

Address Setup to WE# Going High

3404040ns

tDVWH Data Setup to WE# Going High 3 40 40 40 ns

tWHDX Data Hold from WE# High 5 5 5 ns

tWHAX Address Hold from WE# High 5 5 5 ns

tWHEH CE# Hold from WE# High 10 10 10 ns

tWHWL WE# Pulse Width High 30 30 30 ns

tWHRL

WE# High to RY/BY# Going Low

90 90 90 ns

tWHGL Write Recovery before Read 0 0 0 ns

tQVVL VPP Hold from Valid SRD, 2, 4 0 0 0 ns

RY/BY# High

tQVPH RP# VHH Hold from Valid SRD, 2, 4 0 0 0 ns

RY/BY# High

tQVSL WP# VIH Hold from Valid SRD, 2, 4 0 0 0 ns

RY/BY# High

VERSIONS

±0.25 V

VCC±0.5 V

(NOTE 5)

LH28F800BG-L85

LH28F800BGH-L85

(NOTE 6)

LH28F800BG-L12

LH28F800BGH-L12

(NOTE 6)

LH28F800BG-L85

LH28F800BGH-L85

UNIT

6.2.5 AC CHARACTERISTICS - WRITE OPERATIONS (contd.) (NOTE 1)

•VCC = 5.0±0.25 V, 5.0±0.5 V, TA= 0 to +70˚C or –40 to +85˚C

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

- 33 -

(NOTE 1) (NOTE 2) (NOTE 3) (NOTE 4) (NOTE 5) (NOTE 6)

VIL

VIH

VOH

VIH

VIL

VOL

VIL

VIH

VHH

VIL

VPPLK

VPPH1/2/3

VIH

VIL

ADDRESSES (A)

CE# (E)

OE# (G)

WE# (W)

DATA (D/Q)

RP# (P)

VPP (V)

RY/BY# (R)

AIN AIN

tAVAV tAVWH

tELWL tWHEH tWHGL

tWHWL tWHQV1/2/3/4

tWLWH

tDVWH

tWHDX

Valid

SRD

tPHWL tWHRL

tVPWH tQVVL

DIN

High Z DIN

WP# (S) VIH

VIL

tPHHWH tQVPH

tSHWH tQVSL

tWHAX

NOTES :

1. VCC power-up and standby.

2. Write block erase or word write setup.

3. Write block erase confirm or valid address and data.

4. Automated erase or program delay.

5. Read status register data.

6. Write Read Array command.

Fig. 12 AC Waveform for WE#-Controlled Write Operations

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

- 34 -

6.2.6 ALTERNATIVE CE#-CONTROLLED WRITES (NOTE 1)

•VCC = 2.7 to 3.6 V, TA= 0 to +70˚C or –40 to +85˚C

VERSIONS LH28F800BG-L85 LH28F800BG-L12

LH28F800BGH-L85 LH28F800BGH-L12 UNIT

SYMBOL

PARAMETER NOTE MIN. MAX. MIN. MAX.

tAVAV Write Cycle Time 120 150 ns

tPHEL RP# High Recovery to CE# Going Low 2 1 1 µs

tWLEL WE# Setup to CE# Going Low 0 0 ns

tELEH CE# Pulse Width 70 70 ns

tPHHEH RP# VHH Setup to CE# Going High 2 100 100 ns

tSHEH WP# VIH Setup to CE# Going High 2 100 100 ns

tVPEH VPP Setup to CE# Going High 2 100 100 ns

tAVEH Address Setup to CE# Going High 3 50 50 ns

tDVEH Data Setup to CE# Going High 3 50 50 ns

tEHDX Data Hold from CE# High 5 5 ns

tEHAX Address Hold from CE# High 5 5 ns

tEHWH WE# Hold from CE# High 0 0 ns

tEHEL CE# Pulse Width High 25 25 ns

tEHRL CE# High to RY/BY# Going Low 100 100 ns

tEHGL Write Recovery before Read 0 0 ns

tQVVL VPP Hold from Valid SRD, RY/BY# High 2, 4 0 0 ns

tQVPH RP# VHH Hold from Valid SRD, RY/BY# High 2, 4 0 0 ns

tQVSL WP# VIH Hold from Valid SRD, RY/BY# High 2, 4 0 0 ns

NOTES :

1. In systems where CE# defines the write pulse width

(within a longer WE# timing waveform), all setup, hold,

and inactive WE# times should be measured relative to

the CE# waveform.

2. Sampled, not 100% tested.

3. Refer to Table 3 for valid AIN and DIN for block erase or

word write.

4. VPP should be held at VPPH1/2/3 (and if necessary RP#

should be held at VHH) until determination of block erase

or word write success (SR.1/3/4/5 = 0 : on Boot Blocks,

SR.3/4/5 = 0 : on Parameter Blocks and Main Blocks).

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

- 35 -

6.2.6 ALTERNATIVE CE#-CONTROLLED WRITES (contd.) (NOTE 1)

•VCC = 3.3±0.3 V, TA= 0 to +70˚C or –40 to +85˚C

VERSIONS LH28F800BG-L85 LH28F800BG-L12

LH28F800BGH-L85 LH28F800BGH-L12 UNIT

SYMBOL

PARAMETER NOTE MIN. MAX. MIN. MAX.

tAVAV Write Cycle Time 100 130 ns

tPHEL RP# High Recovery to CE# Going Low 2 1 1 µs

tWLEL WE# Setup to CE# Going Low 0 0 ns

tELEH CE# Pulse Width 70 70 ns

tPHHEH RP# VHH Setup to CE# Going High 2 100 100 ns

tSHEH WP# VIH Setup to CE# Going High 2 100 100 ns

tVPEH VPP Setup to CE# Going High 2 100 100 ns

tAVEH Address Setup to CE# Going High 3 50 50 ns

tDVEH Data Setup to CE# Going High 3 50 50 ns

tEHDX Data Hold from CE# High 5 5 ns

tEHAX Address Hold from CE# High 5 5 ns

tEHWH WE# Hold from CE# High 0 0 ns

tEHEL CE# Pulse Width High 25 25 ns

tEHRL CE# High to RY/BY# Going Low 100 100 ns

tEHGL Write Recovery before Read 0 0 ns

tQVVL VPP Hold from Valid SRD, RY/BY# High 2, 4 0 0 ns

tQVPH RP# VHH Hold from Valid SRD, RY/BY# High 2, 4 0 0 ns

tQVSL WP# VIH Hold from Valid SRD, RY/BY# High 2, 4 0 0 ns

NOTES :

1. In systems where CE# defines the write pulse width

(within a longer WE# timing waveform), all setup, hold,

and inactive WE# times should be measured relative to

the CE# waveform.

2. Sampled, not 100% tested.

3. Refer to Table 3 for valid AIN and DIN for block erase or

word write.

4. VPP should be held at VPPH1/2/3 (and if necessary RP#

should be held at VHH) until determination of block erase

or word write success (SR.1/3/4/5 = 0 : on Boot Blocks,

SR.3/4/5 = 0 : on Parameter Blocks and Main Blocks).

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

- 36 -

SYMBOL

PARAMETER NOTE MIN. MAX. MIN. MAX. MIN. MAX.

tAVAV Write Cycle Time 85 90 120 ns

tPHEL RP# High Recovery to CE# 2111µs

Going Low

tWLEL WE# Setup to CE# Going Low 0 0 0 ns

tELEH CE# Pulse Width 50 50 50 ns

tPHHEH

RP# V

Setup to CE# Going High

2 100 100 100 ns

tSHEH

WP# V

Setup to CE# Going High

2 100 100 100 ns

tVPEH VPP Setup to CE# Going High 2 100 100 100 ns

tAVEH

Address Setup to CE# Going High

3404040ns

tDVEH Data Setup to CE# Going High 3 40 40 40 ns

tEHDX Data Hold from CE# High 5 5 5 ns

tEHAX Address Hold from CE# High 5 5 5 ns

tEHWH WE# Hold from CE# High 0 0 0 ns

tEHEL CE# Pulse Width High 25 25 25 ns

tEHRL CE# High to RY/BY# Going Low 90 90 90 ns

tEHGL Write Recovery before Read 0 0 0 ns

tQVVL VPP Hold from Valid SRD, 2, 4 0 0 0 ns

RY/BY# High

tQVPH RP# VHH Hold from Valid SRD, 2, 4 0 0 0 ns

RY/BY# High

tQVSL WP# VIH Hold from Valid SRD, 2, 4 0 0 0 ns

RY/BY# High

VERSIONS

±0.25 V

VCC±0.5 V

(NOTE 5)

LH28F800BG-L85

LH28F800BGH-L85

(NOTE 6)

LH28F800BG-L12

LH28F800BGH-L12

(NOTE 6)

LH28F800BG-L85

LH28F800BGH-L85

UNIT

NOTES :

1. In systems where CE# defines the write pulse width

(within a longer WE# timing waveform), all setup, hold,

and inactive WE# times should be measured relative to

the CE# waveform.

2. Sampled, not 100% tested.

3. Refer to Table 3 for valid AIN and DIN for block erase or

word write.

4. VPP should be held at VPPH1/2/3 (and if necessary RP#

should be held at VHH) until determination of block erase

or word write success (SR.1/3/4/5 = 0 : on Boot Blocks,

SR.3/4/5 = 0 : on Parameter Blocks and Main Blocks).

5. See Fig. 8 "Transient Input/Output Reference

Waveform" and Fig. 10 "Transient Equivalent Testing

Load Circuit" (High Seed Configuration) for testing

characteristics.

6. See Fig. 9 "Transient Input/Output Reference

Waveform" and Fig. 10 "Transient Equivalent Testing

Load Circuit" (Standard Configuration) for testing

characteristics.

6.2.6 ALTERNATIVE CE#-CONTROLLED WRITES (contd.) (NOTE 1)

•VCC = 5.0±0.25 V, 5.0±0.5 V, TA= 0 to +70˚C or –40 to +85˚C

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

- 37 -

VIL

VIH

VIL

VOL

VOH

VIL

VIH

VHH

VIL

VPPLK

VPPH1/2/3

VIH

VIL

ADDRESSES (A)

WE# (W)

OE# (G)

CE# (E)

DATA (D/Q)

RP# (P)

VPP (V)

RY/BY# (R)

WP# (S) VIH

VIL

AIN AIN

tAVAV tAVEH

tWLEL tEHWH tEHGL

tEHEL tEHQV1/2/3/4

Valid

SRD

tPHEL tEHRL

tVPEH tQVVL

DIN

High Z DIN

tPHHEH tQVPH

tSHEH

tEHAX

tELEH

tDVEH

tEHDX

tQVSL

(NOTE 1) (NOTE 2) (NOTE 3) (NOTE 4) (NOTE 5) (NOTE 6)

NOTES :

1. VCC power-up and standby.

2. Write block erase or word write setup.

3. Write block erase confirm or valid address and data.

4. Automated erase or program delay.

5. Read status register data.

6. Write Read Array command.

Fig. 13 AC Waveform for CE#-Controlled Write Operations

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

- 38 -

6.2.7 RESET OPERATIONS

RP# (P)

VIL

VIH

VOH

VIH

VOH

VOL

VIL

VOL

RY/BY# (R)

RP# (P)

VIL (C) RP# Rising Timing

VIH

2.7 V/3.3 V/5 V

VIL

RP# (P)

VCC

(A) Reset During Read Array Mode

(B) Reset During Block Erase or Word Write

tPLPH

tPLRH

tPLPH

t235VPH

Fig. 14 AC Waveform for Reset Operation

Reset AC Specifications (NOTE 1)

NOTES :

1. These specifications are valid for all product versions

(packages and speeds).

2. If RP# is asserted while a block erase or word write

operation is not executing, the reset will complete within

100 ns.

3. A reset time, tPHQV, is required from the latter of RY/BY#

or RP# going high until outputs are valid.

4. When the device power-up, holding RP#-low minimum

100 ns is required after VCC has been in predefined

range and also has been in stable there.

VCC = 2.7 to 3.6 V VCC = 3.3±0.3 V VCC = 5.0±0.5 V

SYMBOL

PARAMETER NOTE MIN. MAX. MIN. MAX. MIN. MAX. UNIT

RP# Pulse Low Time

tPLPH (If RP# is tied to VCC, this 100 100 100 ns

specification is not applicable)

tPLRH RP# Low to Reset during 2, 3 22 20 12 µs

Block Erase or Word Write

VCC 2.7 V to RP# High

t235VPH VCC 3.0 V to RP# High 4 100 100 100 ns

VCC 4.5 V to RP# High

- 39 -

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

6.2.8 BLOCK ERASE AND WORD WRITE PERFORMANCE (NOTE 3, 4)

•VCC = 2.7 to 3.6 V, TA= 0 to +70˚C or –40 to +85˚C

VPP = 2.7 to 3.6 V VPP = 5.0±0.5 V VPP = 12.0±0.6 V

SYMBOL

PARAMETER NOTE MIN.

TYP.

(NOTE 1)

MAX. MIN.

TYP.

(NOTE 1)

MAX. MIN.

TYP.

(NOTE 1)

MAX. UNIT

32 k-Word

2 44.6 17.7 12.6 µs

tWHQV1 Word Write

Block

tEHQV1 Time 4 k-Word 2 45.9 26.1 24.5 µs

Block

32 k-Word

2 1.46 0.58 0.42 s

Block Write

Block

Time 4 k-Word 2 0.19 0.11 0.11 s

Block

32 k-Word

2 1.14 0.61 0.51 s

tWHQV2

Block Erase Block

tEHQV2

Time

4 k-Word 2 0.38 0.32 0.31 s

Block

tWHRH1 Word Write Suspend 78 68 67µs

tEHRH1 Latency Time to Read

tWHRH2

Erase Suspend Latency

18 22 11 14 11 14 µs

tEHRH2

Time to Read

•VCC = 3.3±0.3 V, TA= 0 to +70˚C or –40 to +85˚C

NOTES :

1. Typical values measured at TA= +25˚C and nominal

voltages. Subject to change based on device

characterization.

2. Excludes system-level overhead.

3. These performance numbers are valid for all speed

versions.

4. Sampled, not 100% tested.

VPP = 3.3±0.3 V VPP = 5.0±0.5 V VPP = 12.0±0.6 V

SYMBOL

PARAMETER NOTE MIN.

TYP.

(NOTE 1)

MAX. MIN.

TYP.

(NOTE 1)

MAX. MIN.

TYP.

(NOTE 1)

MAX. UNIT

32 k-Word

2 44 17.3 12.3 µs

tWHQV1 Word Write

Block

tEHQV1 Time 4 k-Word 2 45 25.6 24 µs

Block

32 k-Word

2 1.44 0.57 0.41 s

Block Write

Block

Time 4 k-Word 2 0.19 0.11 0.1 s

Block

32 k-Word

2 1.11 0.59 0.5 s

tWHQV2

Block Erase Block

tEHQV2

Time

4 k-Word 2 0.37 0.31 0.3 s

Block

tWHRH1 Word Write Suspend 67 57 56µs

tEHRH1 Latency Time to Read

tWHRH2

Erase Suspend Latency

16.2 20 9.6 12 9.6 12 µs

tEHRH2

Time to Read

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

- 40 -

NOTES :

1. Typical values measured at TA= +25˚C and nominal

voltages. Subject to change based on device

characterization.

2. Excludes system-level overhead.

3. These performance numbers are valid for all speed

versions.

4. Sampled, not 100% tested.

VPP = 5.0±0.5 V VPP = 12.0±0.6 V

SYMBOL

PARAMETER NOTE MIN.

TYP.

(NOTE 1)

MAX. MIN.

TYP.

(NOTE 1)

MAX. UNIT

tWHQV1 Word Write Time 32 k-Word Block 2 12.2 8.4 µs

tEHQV1 4 k-Word Block 2 18.3 17 µs

Block Write Time 32 k-Word Block 2 0.4 0.28 s

4 k-Word Block 2 0.08 0.07 s

tWHQV2 Block Erase Time 32 k-Word Block 2 0.46 0.39 s

tEHQV2 4 k-Word Block 2 0.26 0.25 s

tWHRH1 Word Write Suspend Latency Time to Read 5 6 4 5 µs

tEHRH1

tWHRH2 Erase Suspend Latency Time to Read 9.6 12 9.6 12 µs

tEHRH2

6.2.8 BLOCK ERASE AND WORD WRITE PERFORMANCE (contd.) (NOTE 3, 4)

•VCC = 5.0 V±0.25 V, 5.0±0.5 V, TA= 0 to +70˚C or –40 to +85˚C

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

- 41 -

7 ORDERING INFORMATION

LH28F800BG

(H)

ET-L85

Device Density

800 = 8 M-bit Access Speed (ns)

85 : 85 ns (5.0±0.25 V), 90 ns (5.0±0.5 V)

100 ns (3.3±0.3 V), 120 ns (2.7 to 3.6 V)

12 : 120 ns (5.0±0.5 V), 130 ns (3.3±0.3 V),

150 ns (2.7 to 3.6 V)

Package

E = 48-pin TSOP (I) (TSOP048-P-1220) Normal bend

R = 48-pin TSOP (I) (TSOP048-P-1220) Reverse bend

B = 48-ball CSP (FBGA048-P-0808)

Architecture

B = Boot Block

Power Supply Type

G = SmartVoltage Technology

Operating Temperature

Blank = 0 to +70°C

H = –40 to +85°C

Product line designator for all SHARP Flash products

Block Locate Option

T = Top Boot

B = Bottom Boot

VALID OPERATIONAL COMBINATIONS

VCC = 2.7 to 3.6 V VCC = 3.3±0.3 V VCC = 5.0±0.5 V VCC = 5.0±0.25 V

OPTION ORDER CODE 50 pF load, 50 pF load, 100 pF load, 30 pF load,

1.35 V I/O Levels 1.5 V I/O Levels TTL I/O Levels 1.5 V I/O Levels

LH28F800BGXX-XL85

120 ns 100 ns 90 ns 85 ns

LH28F800BGXX-XL12

150 ns 130 ns 120 ns

PACKAGING

1.2

0.1

±0.2

±0.05

±0.1

MAX.

±0.2

TYP.

12.0

48_0.2

0.5

0.1

0.10

±0.08

20.0

±0.3

18.4

0.125 M

0.125

19.0

±0.1

1.0

±0.1

Package base plane

48 TSOP (TSOP048-P-1220)

PACKAGING

0.30 AB

SCD

0.15

8.0

0.2

1.2

MAX.

0.35

±0.05

0.1 S

∗0.4

TYP.

0.45

±0.03

0.8

TYP.

0.4

TYP.

2.0

TYP.

0.8

TYP.

0.4

TYP.

1.2

TYP.

A18

∗Land hole diameter

for ball mounting

8.0

0.2

/ /

48 CSP (FBGA048-P-0808)