SG6901ASZ_F116 - Fairchild Semiconductor

February 2009

SG6901A • Rev. 1.0.2

SG6901A — CCM PFC / Flyback PWM Combination Controller

SG6901A

CCM PFC/Flyback PWM Comb ination Contro ller

Features

 Interleaved PFC/PWM Switching

 Low Startup and Operating Current

 Innovative Switching Charge Multiplier Divider

 Multi-vector Control for Improved PFC Output

Transient Response

 Average-Current-Mode Control for PFC

 Programmable Two-Level PFC Output Voltage

Protections

 PFC and PWM Feedback Open-Loop Protection

 Cycle-by-Cycle Current Limiting for PFC/PWM

 Slope Compensation for PWM

 H/L Line Over-Power Compensation for PWM

 Brownout Protection

 Over-Temperature Protection (OTP)

Applications

 Switching Power Supplies with Active PFC and

Standby Power

 High-Power Adaptors

Description

The highly integrated SG6901A is designed for power

supplies with boost PFC and flyback PWM. It requires

very few external components to achieve versatile

protections. It is available in a 20-pin SOP package.

A proprietary interleave-switching feature synchronizes

the PFC and PWM stages and reduces switching noise.

For PFC stage, the proprietary multi-vector control

scheme provides a fast transient response in a low-

bandwidth PFC loop, in which the overshoot and

undershoot of the PFC voltage are clamped. If the

feedback loop is broken, the SG6901A shuts off PFC to

prevent extra-high voltage on output.

For the flyback PWM, the synchronized slope

compensation ensures the stability of the current loop

under continuous-conduction-mode operation. Built-in

line-voltage compensation maintains constant output-

power limit. Hiccup operation during output overloading

is also guaranteed.

In addition, SG6901A provides protection functions,

such as brownout and RI pin open/short protection.

Ordering Information

Part Number Operating

Temperature Range Eco

Status Package Packing

Method

SG6901ASZ -30°C to +85°C RoHS

20-Lead, Small Outline Integrated

Circuit (SOIC), JEDEC

MS013, .300 inch, Wide Body

Tape & Reel

For Fairchild’s defini t i on of “green” Eco St atus, pleas e visit: http://www.fairchildsemi.com/company/green/rohs_green.html.

SG6901A • Rev. 1.0.2 2

SG6901A — CCM PFC / Flyback PWM Combination Controller

Application Circuit

Figure 1. Typical Application

SG6901A • Rev. 1.0.2 3

SG6901A — CCM PFC / Flyback PWM Combination Controller

Block Diagram

Figure 2. Block Diagram

SG6901A • Rev. 1.0.2 4

SG6901A — CCM PFC / Flyback PWM Combination Controller

Marking Informa ti on

Figure 3. Top Mark

Pin Configuration

Figure 4. Pin Configuration

T- S=SOP

P- Z=Lead Free

Null=regular package

XXXXXXXX- Wafer Lot

Y: Year; WW: Week

V: Assembly Location

SG6901A • Rev. 1.0.2 5

SG6901A — CCM PFC / Flyback PWM Combination Controller

Pin Definitions

Pin # Name Description

1 VRMS

Line voltage detection. The pin is used for PFC multiplier, RANGE control of PFC output

voltage, and brownout protection. For brownout protection, the controller is disabled after a

delay time when the VRMS voltage drops below a threshold.

2 RI

Reference setting. One resistor connected between RI and ground determines the switching

frequency. The switching frequency is equal to [1560 / RI] KHz, where RI is in KΩ. For example,

if RI is equal to 24KΩ, the switching frequency is 65KHz.

3 OTP

Over-temperature protection. A constant current is output from this pin. An external NTC

thermistor must be connected from this pin to ground. The impedance of the NTC thermistor

decreases whenever the temperature increases. Once the voltage of the OTP pin drops below

the OTP threshold, the SG6901A is disabled.

4 IEA

PFC current amplifier output. The signal from this pin is compared with an internal sawtooth

to determine the pulse width for PFC gate drive.

5 IPFC

The inverting input of the PFC current amplifier. Proper external compensation circuits result

in excellent input power factor via average-current-mode control.

6 IMP

The non-inverting input of the PFC current amplifier and the output of multiplier. Proper

external compensation circuits results in excellent input power factor via average-current-mode

control.

7 ISENSE

Current limit. A resistor from this pin to GND sets the current limit.

8 FBPWM

The control input for voltage-loop feedback of PWM stage. It is internally pulled high

through a 6.5kΩ resistance. Usually an external opto-coupler from secondary feedback circuit is

connected to this pin.

9 IPWM

The current-sense input for the flyback PWM. Via a current sense resistor, this pin provides

the control input for peak-current-mode control and cycle-by-cycle current limiting.

10 AGND

Signal ground.

11 SS

Soft start. During startup, the SS pin charges an external capacitor with a 50µA (RI=24KΩ)

constant current source. The voltage on FBPWM is clamped by SS during startup. In the event

of a protection condition occurring and/or PWM being disabled, the SS pin is quickly

discharged.

12 OPWM

The totem-pole output drive for the flyback PWM MOSFET. This pin is internally clamped under

17V to protect the MOSFET.

13 GND

Power ground.

14 OPFC

The totem-pole output drive for the PFC MOSFET. This pin is internally clamped under 17V

to protect the MOSFET.

15 VDD

The power supply pin.

16 RANGE

The RANGE pin has high impedance whenever the VRMS voltage is lower than a threshold.

The PFC output voltage at low line can be reduced to improve efficiency.

17 OVP

The PFC stage over-voltage input. The comparator disables the PFC output driver if the

voltage at this input exceeds a threshold. This pin can be connected to FBPFC or it can be

connected to the PFC boost output through a divider network.

18 FBPFC

The feedback input for PFC voltage loop. The inverting input of PFC error amplifier. This pin

is connected to the PFC output through a divider network.

19 VEA

The error amplifier output for PFC voltage feedback loop. A compensation network (usually

a capacitor) is connected between this pin and ground. A large capacitor value results in a

narrow bandwidth and improves the power factor.

20 IAC

This input is used to provide current reference for the multiplier.

SG6901A • Rev. 1.0.2 6

SG6901A — CCM PFC / Flyback PWM Combination Controller

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be

operable above the recommended operating conditions and stressing the parts to these levels is not recommended.

In addition, extended exposure to stresses above the recommended operating conditions may affect device

reliability. The absolute maximum ratings are stress ratings only.

Symbol Parameter Min. Max. Unit

VDD DC Supply Voltage 25 V

IAC Input AC Current 2 mA

VHIGH OPWM, OPFC, IAC -0.3 25.0 V

VLOW Others -0.3 7.0 V

PD Power Dissipation at TA< 50℃ 1.15 W

TJ Operating Junction Temperature -40 +125 °C

TSTG Storage Temperature Range -55 +150 °C

ӨJC Thermal Resistance (Junction-to-Case) +23.64 °C/W

TL Lead Temperature (Soldering) +260 °C

Human Body Model, JESD22-A114 4.5 KV

ESD Electrostatic Discharge Capability

Machine Model, JESD22-A115 250 V

Notes:

1. All voltage values, except differential voltage, are given with respect to GND pin.

2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended

operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not

recommend exceeding them or designing to Absolute Maximum Ratings.

Symbol Parameter Min. Max. Unit

TA Operating Ambient Temperature -30 +85 °C

SG6901A • Rev. 1.0.2 7

SG6901A — CCM PFC / Flyback PWM Combination Controller

Electrical Characteristics

VDD=15V and TA=25°C unless otherwise specified.

Symbol Parameter Conditions Min. Typ. Max. Units

VDD SECTION

VDD-OP Continuously Operating Voltage 20 V

IDD-ST Startup Current 0V < VDD < VDD-ON 10 25 µA

IDD-OP Operating Current VDD=15V; OPFC,

OPWM Open; RI=24KΩ 6 10 mA

VDD-ON Start Threshold Voltage 11 12 13 V

VDD-OFF Minimum Operating Voltage 9 10 11 V

VDD-OVP V

DD OVP Threshold 23.5 24.5 25.5 V

tD-VDDOVP Debounce Time of VDD OVP 8 25 µs

OSCILLATOR SECTION

fOSC PWM Frequency RI=24KΩ 62 65 68 KHz

RI RI Pin Resistance Range 15.6 47.0 KΩ

RI-OPEN RI Pin Open Protection If RI>RI-OPEN, SG6901A

Turns Off 200 KΩ

RI-SHORT RI Pin Short Protection If RI<RI-SHORT,

SG6901A Turns Off 2

KΩ

VRMS SECTION (for UVP and RANGE)

VRMS-UVP-1 RMS AC Voltage Under-Voltage

Protection Threshold (with tUVP delay) 0.75 0.80 0.85 V

VRMS-UVP-2 Recovery Level on VRMS

VRMS-UVP-

1 +

0.16V

VRMS-

UVP-1 +

0.18V

VRMS-

UVP-1 +

0.2V

V

tD-PWM When UVP Occurs, Interval from PFC

Off to PWM Off tUVP-

Min+9 tUVP-

Min+14 ms

tUVP Under-Voltage Protection Delay Time 150 195 240 ms

VRMS-H High VRMS Threshold for RANGE

Comparator

1.90 1.95 2.00 V

VRMS-L Low VRMS Threshold for RANGE

Comparator

1.55 1.60 1.65 V

tRANGE Range-Enable Delay Time 140 170 200 ms

VOL Output Low Voltage of RANGE Pin Io=1mA 0.5 V

IOH Output High Leakage Current of

RANGE Pin RANGE=5V 50 nA

Continued on the f ol l owing page…

SG6901A • Rev. 1.0.2 8

SG6901A — CCM PFC / Flyback PWM Combination Controller

Electrical Characteristics

VDD=15V and TA=25°C unless otherwise specified.

Symbol Parameter Conditions Min. Typ. Max. Units

PFC STAGE

Voltage Error Amplifier

VREF Reference Voltage 2.95 3.00 3.05 V

Av Open-Loop Gain 60 dB

Zo Output Impedance 110 KΩ

OVPPFC PFC Over-Voltage Protection (OVP Pin) 3.20 3.25 3.30 V

△OVPPFC PFC Feedback Voltage Protection

Hysteresis 60 90 120 mV

tOVP-PFC Debounce Time of PFC OVP 40 70 120 µs

VFBPFC-H Clamp-High Feedback Voltage 3.10 3.15 3.20 V

GFBPFC-H Clamp-High Gain 0.5 µA/mV

VFBPFC-L Clamp-Low Feedback Voltage 2.75 2.85 2.90 V

GFBPFC-L Clamp-Low Gain 6.5 mA/mV

IFBPFC-L Maximum Source Current 1.5 2.0 mA

IFBPFC-H Maximum Sink Current 70 110 µA

UVPFBPFC PFC Feedback Under-Voltage Protection 0.35 0.40 0.45 V

tUVP-FBPFC Debounce Time of PFC UVP 40 70 120 µs

CURRENT ERROR AMPLIFIER

VOFFSET Input Offset Voltage ((-) > (+)) 8 mV

AI Open-Loop Gain 60 dB

BW Unit Gain Bandwidth 1.5 MHz

CMRR Common Mode Rejection Ratio VCM=0 to +1.5V 70 dB

VOUT-HIGH Output High Voltage 3.2 V

VOUT-LOW Output Low Voltage 0.2 V

IMR1, IMR2 Reference Current Source RI=24KΩ

(IMR=20+IRI•0.8) 50 70 µA

IL Maximum Source Current 3 mA

IH Maximum Sink Current 0.25 mA

Continued on the f ol l owing page…

SG6901A • Rev. 1.0.2 9

SG6901A — CCM PFC / Flyback PWM Combination Controller

Electrical Characteristics

VDD=15V and TA=25°C unless otherwise specified.

Symbol Parameter Conditions Min. Typ. Max. Units

PEAK CURRENT LIMIT

IP Constant Current Output RI=24KΩ 90 100 110 µA

VRMS=1.05V 0.15 0.20 0.25 V

VPK

Peak Current Limit Threshold

Voltage Cycle-by-Cycle Limit (VSENSE

< VPK) VRMS=3V 0.35 0.40 0.45 V

tPD-PFC Propagation Delay 200 ns

tLEB-PFC Leading-Edge Blanking Time 270 350 450 ns

MULTIPLIER

IAC Input AC Current Multiplier Linear Range 0 360 µA

IMO–max Maximum Multiplier Current Output RI=24KΩ 250 µA

IMO-1 Multiplier Current Output (Low-line,

High-Power)

VRMS=1.05V; IAC=90µA;

VEA=7.5V; RI=24KΩ 200 250 280 µA

IMO–2 Multiplier Current Output (High-line,

High-Power)

VRMS=3V; IAC=264µA;

VEA=7.5V; RI=24KΩ 65 85 µA

VIMP Voltage of IMP Open 3.4 3.9 4.4 V

PFC OUTPUT DRIVER

VZ Output Voltage Maximum (Clamp) VDD=20V 16 18 V

VOL-PFC Output Voltage Low VDD=15V; IO=100mA 1.5 V

tPFC Interval OPFC Lags Behind OPWM

at Startup 9.0 11.5 14.0 ms

VOH-PFC Output Voltage High VDD=13V; IO=100mA 8 V

tR-PFC Rising Time VDD=15V; CL=5nF;

O/P=2V to 9V 40 70 120 ns

tF-PFC Falling Time VDD=15V; CL=5nF;

O/P=9V to 2V 40 60 110 ns

DCYMAX Maximum Duty Cycle 93 98 %

PWM STAGE

FBPWM

Av-PWM FB to Current Comparator

Attenuation 2.5 3.1 3.5 V/V

ZFB Input Impedance 4 5 7 KΩ

IFB Maximum Source Current 0.8 1.2 1.5 mA

FBOPEN-LOOP PWM Open-Loop Protection Voltage 4.2 4.5 4.8 V

tOPEN-PWM PWM Open-Loop Protection Delay

Time 45 56 70 ms

tOPEN-PWM-

Hiccup

Interval of PWM Open-Loop

Protection Reset 450 600 750 ms

Continued on the f ol l owing page…

SG6901A • Rev. 1.0.2 10

SG6901A — CCM PFC / Flyback PWM Combination Controller

Electrical Characteristics

VDD=15V and TA=25°C unless otherwise specified.

Symbol Parameter Conditions Min. Typ. Max. Units

PWM CURRENT SENSE

tPD-PWM Propagation Delay to

Output VDD=15V, OPWM<=9V 60 120 ns

VLIMIT-1 Peak Current Limit

Threshold Voltage1 RANGE=Open 0.65 0.70 0.75 V

VLIMIT-2 Peak Current Limit

Threshold Voltage2 RANGE=Ground 0.60 0.65 0.70 V

tLEB-PWM Leading-Edge Blanking

Time

270 350 450 ns

△VSLOPE Slope Compensation

△VS=△VSLOPE x (Ton/T)

△VS: Compensation

Voltage Added to Current

Sense

0.45 0.50 0.55 V

PWM OUTOUT DRIVER

VZ-PWM Output Voltage Maximum

(Clamp) VDD=20V 16 18 V

VOL-PWM Output Voltage Low VDD=15V; IO=100mA 1.5 V

VOH-PWM Output Voltage High VDD=13V; IO=100mA 8 V

tR-PWM Rising Time VDD=15V; CL=5nF;

O/P=2V to 9V 30 60 120 ns

tF-PWM Falling Time VDD=15V; CL=5nF;

O/P=9V to 2V 30 50 110 ns

DCYMAXPWM Maximum Duty Cycle 73 78 83 %

OTP SECTION

IOTP OTP Pin Output Current RI=24KΩ 90 100 110 µA

VOTP-ON Recovery Level on OTP 1.35 1.40 1.45 V

VOTP-OFF OTP Threshold Voltage 1.15 1.20 1.25 V

tOTP OTP Debounce Time 8 25 µs

SOFT START SECTION

ISS Constant Current Output

for Soft-Start RT=24KΩ 44 50 56 µA

RD Discharge RDSON 470 Ω

SG6901A • Rev. 1.0.2 11

SG6901A — CCM PFC / Flyback PWM Combination Controller

Typical Performance Characteristics

Startup Current (I

DD-ST

) vs. Temperature

0

5

10

15

20

25

-40 -25 -10 5 20 35 50 65 80 95 110 125

T emperature (°C)

IDD-ST (µA)

Minimum Operating Voltage (VDD-OFF) vs. Temperature

9.0

9.4

9.8

10.2

10.6

11.0

-40 -25 -10 5 20 35 50 65 80 95 110 125

T emperature (°C)

V

DD-OFF

(V)

Figure 5. Startup Current Figure 6. VDD Turn-Off Threshold Voltage

4.0

5.2

6.4

7.6

8.8

10.0

-40 -25 -10 5 20 35 50 65 80 95 110 125

Temperature (°C)

Operating Current (I

DD-OP

) vs. Temperature

I

DD-OP

(mA)

62

63

64

66

67

68

-40 -25 -10 5 20 35 50 65 80 95 110 125

Temperature (°C)

PWM Frequency (f

OSC

) vs. Temperature

f

OSC

(KHz)

Figure 7. Operating Current Figure 8. PWM Frequency

11.0

11.4

11.8

12.2

12.6

13.0

-40 -25 -10 5 20 35 50 65 80 95 110 125

Temperature (°C)

Start Threshold Voltage (V

DD-ON

) vs. Temperature

V

DD-ON

(V)

23.5

23.9

24.3

24.7

25.1

25.5

-40 -25 -10 5 20 35 50 65 80 95 110 125

V

DD

Over-Voltage Protection (V

DD-OVP

) vs. Temperature

V

DD-OVP

(V)

Temperature (°C)

Figure 9. VDD Turn-On Threshold Voltage Figure 10. VDD OVP Threshold Voltage

SG6901A • Rev. 1.0.2 12

SG6901A — CCM PFC / Flyback PWM Combination Controller

Typical Performance Characteristics

1.90

1.92

1.94

1.96

1.98

2.00

-40 - 25 -10 5 20 35 50 65 80 95 110 125

High VRMS Threshold for RANGE Comparator (V

RMS-H

) vs. Temperature

VRMS-H (V)

Temperature (°C)

2.95

2.97

2.99

3.01

3.03

3.05

-40 -25 -10 5 20 35 50 65 80 95 110 125

Reference Voltage (V

REF

) vs. Temperature

VREF (V)

Temperature (°C)

Figure 11. High VRMS Threshold for RANGE Comparator Figure 12. Reference Voltage

1.55

1.57

1.59

1.61

1.63

1.65

-40 -25 -10 5 20 35 50 65 80 95 110 125

Temperature (°C)

Low VRMS Threshold for RANGE Comparator (V

RMS-L



)

vs. Temperature

V

RMS-L

(V)

40

56

72

88

104

120

-40 -25 -10 5 20 35 50 65 80 95 110 125

t

R-PFC

(ns)

Rising Time (t

R-PFC

) vs. Temperature

Temperature (°C)

Figure 13. Low VRMS Threshold for RANGE Comparator Figure 14. OPFC Rising Time

3.20

3.22

3.24

3.26

3.28

3.30

-40 -25 -10 5 20 35 50 65 80 95 110 125

PFC Over-Voltage Protection (OVP

PFC

) vs. Temperature

OVP

PFC

(V)

Temperature (°C)

40

54

68

82

96

110

-40 -25 -10 5 20 35 50 65 80 95 110 125

Falling Time (t

F-PFC

) vs. Temperature (°C)

t

F-PFC

(ns)

Temperature (°C)

Figure 15. PFC OVP Threshold Voltage Figure 16. OPFC Falling Time

SG6901A • Rev. 1.0.2 13

SG6901A — CCM PFC / Flyback PWM Combination Controller

Typical Performance Characteristics

93

94

95

96

97

98

-40 -25 -10 5 20 35 50 65 80 95 110 125

Maximum Duty Cycle (DCY

MAX

) vs. Temperature

DCY

MAX

(%)

Temperature (°C)

0.65

0.67

0.69

0.71

0.73

0.75

-40 -25 -10 5 20 35 50 65 80 95 110 125

Peak Current Limit Threshold Voltage 1 (V

LIMIT-1

) vs. Temperature

V

LIMIT-1

(V)

Temperature (°C)

Figure 17. PFC Maximum Duty Cycle Figure 18. Peak Current Limit Threshold Voltage

4.20

4.32

4.44

4.56

4.68

4.80

-40 -25 -10 5 20 35 50 65 80 95 110 125

PWM Open-Loop Protection Voltage (FB

OPEN-LOOP

) vs. Temperature

FB

OPEN-LOOP

(V)

Temperature (°C)

0.60

0.62

0.64

0.66

0.68

0.70

-40 -25 -10 5 20 35 50 65 80 95 110 125

Peak Current Limit Threshold Voltage 2 (V

LIMIT-2

) vs. Temperature

V

LIMIT-2

(V)

Temperature (°C)

Figure 19. PWM Open-Loop Protection Voltage Figure 20. Peak Current Limit Threshold Voltage2

30

46

62

78

94

110

-40 -25 -10 5 20 35 50 65 80 95 110 125

Falling Time (t

F-PWM

) vs. Temperature

t

F-PWM

(ns)

Temperature (°C)

73

75

77

79

81

83

-40 -25 -10 5 20 35 50 65 80 95 110 125

PWM Maximum Duty Cycle (DCY

MAXPWM

) vs. Temperature (°C)

DCY

MAXPWM

(%)

Temperature (°C)

Figure 21. OPWM Falling Time Figure 22. PWM Maximum Duty Cycle

SG6901A • Rev. 1.0.2 14

SG6901A — CCM PFC / Flyback PWM Combination Controller

Typical Performance Characteristics

1.15

1.17

1.19

1.21

1.23

1.25

-40 -25 -10 5 20 35 50 65 80 95 110 125

OTP Threshold Voltage (V

OTP-OFF

) vs. Temperature

V

OTP-OFF

(V)

Temperature (°C)

Figure 23. VDD OTPurn Threshold Voltage

SG6901A • Rev. 1.0.2 15

SG6901A — CCM PFC / Flyback PWM Combination Controller

Functional Description

SG6901A is a highly integrated PFC/PWM combination

controller. Many functions and protections are built in to

provide a compact design. The following sections

describe the operation and function.

Switching Frequency and Current Sources

The switching frequency can be programmed by the

resistor RI connected between RI pin and GND. The

relationship is:

(kHz)

) (kΩ R

1560

f

I

OSC = (1)

For example, a 24KΩ resistor RI results in a 65KHz

switching frequency. Accordingly, a constant current, IT,

flows through RI:

(mA)

) (kΩ R

1.2V

I

T= (2)

IT is used to generate internal current reference.

Line Voltage Detection (VRMS)

Figure 24 shows a resistive divider with low-pass

filtering for line-voltage detection on the VRMS pin. The

VRMS voltage is used for the PFC multiplier, brownout

protection, and range control.

For brownout protection, SG6901A is disabled with a

195ms delay if the voltage VRMS drops below 0.8V.

For PFC multiplier and range control, refer to the PFC

Operation section below for details.

Figure 24. Line Voltage Detection Circuit

Interleave Switching

The SG6901A uses interleaved switching to

synchronize the PFC and flyback stages, which

reduces switching noise and spreads the EMI

emissions. Figure 25 shows off-time, tOFF, inserted

between the turn-off of the PFC gate drive and the turn-

on of the PWM.

For an universal input (90 ~ 264VAC) power supply

applying active boost PFC and flyback as a second

stage, the output voltage of PFC is usually designed

around 250V at low line and 390V at high line. This can

improve the efficiency at low-line input. The RANGE pin

(open-drain structure) is used for the two-level output

voltage setting.

Figure 25. Interleaved Switching Pattern

PFC Operation

The purpose of a boost active power factor corrector

(PFC) is to shape the input current of a power supply.

The input current waveform and phase follow that of the

input voltage. Average-current-mode control is utilized

for continuous-current-mode operation for the PFC

booster. With the innovative multi-vector control for

voltage loop and switching charge multiplier-divider for

current reference, excellent input power factor is

achieved with good noise immunity and transient

response. Figure 26 shows the total control loop for the

average-current-mode control circuit.

The current source output from the switching charge

multiplier-divider can be expressed as:

()

µA

VVI

KI RMS

EAAC

MO 2

×

×= (3)

As shown in Figure 26, the current output from the IMP

pin is the summation of IMO and IMR1. IMR1 and IMR2

are identical fixed-current sources used to pull high the

operating point of the IMP and IPFC pins since the

voltage across RS goes negative with respect to

ground. Constant current sources IMR1 and IMR2 are

typically 60µA.

Through the differential amplification of the signal

across RS, better noise immunity is achieved. The

output of IEA is compared with an internal sawtooth

and the pulse width for PFC is determined. Through the

average current-mode control loop, the input current IS

is proportional to IMO:

SS2MO RIRI

×

=

×

(4)

According to Equation 4, the minimum value of R2 and

maximum of RS can be determined since IMO should

not exceed the specified maximum value.

There are different concerns in determining the value of

the sense resistor RS. The value of RS should be small

enough to reduce power consumption, but large

enough to maintain the resolution. A current

transformer (CT) may be used to improve efficiency of

high-power converters.

SG6901A • Rev. 1.0.2 16

SG6901A — CCM PFC / Flyback PWM Combination Controller

To achieve good power factor, the voltage for VRMS and

VEA should be kept as constant as possible, according

to Equation 5. Good RC filtering for VRMS and narrow

bandwidth (lower than the line frequency) for voltage

loop are suggested for better input current shaping.

The transconductance error amplifier has output

impedance ZO and a capacitor CEA (1µF ~ 10µF)

should be connected to ground. This establishes a

dominant pole f1 for the voltage loop:

EAO

1CZ2

1

f

××

=

π

(5)

The average total input power can be expressed as:

AC

EA

2

RMS

EA

AC

RMS

2

RMS

EAAC

RMS

MORMS

(rms)

IN

(rms)

IN

R

V

2

V

R

Vin

V

VI

V

IV

IVPin

×=

×

×∝

×

×∝

×=

(6)

From Equation 6, VEA, the output of the voltage error

amplifier, controls the total input power and the power

delivered to the load.

Figure 26. Average-Current-Mode Control Loop

Multi-Vector Error Amplifier

Although the PFC stage has a low bandwidth voltage

loop for better input power factor, the innovative multi-

vector error amplifier provides a fast transient response

to clamp the overshoot and undershoot of the PFC

output voltage.

0 shows the block diagram of the multi-vector error

amplifier. When the variation of the feedback voltage

exceeds ±5% of the reference voltage, the

transconductance error amplifier adjusts its output

impedance to increase the loop response.

Figure 27. Multi-Vector Error Amplifier

PFC Over-Voltage Protect ion

Using a voltage divider from the output of PFC to the

OVP pin, the PFC output voltage can be safely

protected. Once the voltage on the OVP pin is over

OVPPFC, the OPFC is disabled. THE OPFC is not

enabled again until the OVP voltage falls below

OVPPFC.

Cycle-by-Cycle Current Limi t ing

SG6901A provides cycle-by-cycle current limiting for

both PFC and PWM stages. Figure 28 shows the peak

current limit for the PFC stage. The PFC gate drive is

terminated once the voltage on the ISENSE pin goes

below VPK.

The voltage of VRMS determines the voltage of VPK. The

relationship between VPK and VRMS is shown in Figure 28.

The amplitude of the constant current, Ip, is determined

by the internal current reference according to:

I

PR

1.2V

2 I ×= (8)

SG6901A • Rev. 1.0.2 17

SG6901A — CCM PFC / Flyback PWM Combination Controller

Figure 28. VRMS Controlled Current Limiting

The peak current of the ISENSE is given by

(VRMS<1.05V):

S

PP

SENSE_peak R

0.2V-)R(I

I ×

= (8)

Flyback PWM and Slope Compensation

As shown in Figure 29, peak-current-mode control is

utilized for flyback PWM. The SG6901A inserts a

synchronized 0.5V ramp at the beginning of each

switching cycle. This built-in slope compensation

ensures stable operation for continuous current-mode

operation.

When the IPWM voltage, across the sense resistor,

reaches the threshold voltage (0.9V), the OPWM is

turned off after a small propagation delay tPD-PWM.

To improve stability or prevent sub-harmonic

oscillation, a synchronized positive-going ramp is

inserted at every switching cycle.

Figure 29. Peak Current Control Loop

Limited Power Control

Every time the output of the power supply is shorted or

overloaded, the FBPWM voltage increases. If the

FBPWM voltage is higher than a designed threshold,

FBOPEN-LOOP (4.5V) for longer than tOPEN-PWM

(56ms), the OPWM is turned off.

As long as the voltage on the VDD pin is larger than

VDD-OFF (minimum operating voltage), the OPWM is not

enabled. This protection is reset every tOPEN-PWM-Hiccup

interval. A low-frequency hiccup mode protection

prevents the power supply from being overheated

under overload conditions.

Over-Temperature Protection

The OTP pin provides for over-temperature protection.

A constant current is output from this pin. If RI is equal

to 24KΩ, the magnitude of the constant current is

100µA. An external NTC thermistor must be connected

from this pin to ground, as shown as Figure 30. When

the OTP voltage drops below VOTP-OFF (1.2V), SG6901A

is disabled and does not recover until OTP voltage

exceeds VOTP-ON (1.4V).

Figure 30. OTP Function

Soft Star t

During startup of PWM stage, the SS pin charges an

external capacitor with a constant current source. The

voltage on FBPWM is clamped by the SS voltage

during startup. In the event of a protected condition

and/or PWM is disabled, the SS pin quickly discharges.

Gate Driver

SG6901A output stage is a fast totem-pole gate driver.

The output driver is clamped by an internal 18V Zener

diode to protect the external power MOSFET.

SG6901A • Rev. 1.0.2 18

SG6901A — CCM PFC / Flyback PWM Combination Controller

Physical Dimensions

0.10 C

C

A

SEE DETAIL A

NOTES: UNLESS OTHERWISE SPECIFIED

A) THIS PACKAGE CONFORMS TO JEDEC

MS-013, VARIATION AC, ISSUE E

B) ALL DIMENSIONS ARE IN MILLIMETERS.

C) DIMENSIONS DO NOT INCLUDE MOLD

FLASH OR BURRS.

E) LANDPATTERN STANDARD: SOIC127P1030X265-20L

PIN ONE

INDICATOR

0.25

110

BCA

M

20 11

B

X 45°

8°

0°

SEATING PLANE

GAGE PLANE

DETAIL A

SCALE: 2:1

SEATING PLANE

LAND PATTERN RECOMMENDATION

F) DRAWING FILENAME: MKT-M20BREV3

0.65

1.27

2.25

9.50

13.00

12.60

11.43

7.60

7.40

10.65

10.00

0.51

0.35 1.27

2.65 MAX

0.30

0.10

0.33

0.20

0.75

0.25

(R0.10)

1.27

0.40

(1.40)

0.25

D) CONFORMS TO ASME Y14.5M-1994

Figure 31. 20-Pin Small Outline Integrated Circuit (SOIC)

Pack age drawings are provided as a service to customers consideri ng Fai rchild components . Drawings may c hange i n any manner

without notice. P l ease note the revi sion and/or date on t he drawing and contac t a Fairchild S emiconductor represent ative to v er ify

or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically

the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’ s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/.

SG6901A • Rev. 1.0.2 19

SG6901A — CCM PFC / Flyback PWM Combination Controller