AR0134CSSC00SUEA0 - APTINA IMAGING

AR0134: 1/3-Inch 1.2Mp CMOS Digital Image Sensor

Features

Aptina Confidential and Proprietary

1/3-Inch 1.2Mp CMOS Digital Image Sensor with

Global Shutter

AR0134 Data Sheet, Rev. D

For the latest data sheet revision, refer to Aptina’s Web site:www.aptina.com

Features

• Aptina's 3rd Generation Global Shutter Technology

• Superior low-light performance

• HD video (720p60)

• Video/Single Frame mode

• Flexible row-skip modes

• On-chip AE and statistics engine

• Parallel and serial output

• Support for external LED or flash

• Auto black level calibration

•Context switching

Applications

• Scene processing

• Scanning and machine vision

• 720p60 video applications

General Description

Aptina's AR0134 is a 1/3-inch 1.2Mp CMOS digital

image sensor with an active-pixel array of 1280H x

960V. It is designed for low light performance and fea-

tures a global shutter for accurate capture of moving

scenes. It includes sophisticated camera functions

such as auto exposure control, windowing, scaling,

row skip mode, and both video and single frame

modes. It is programmable through a simple two-wire

serial interface. The AR0134 produces extraordinarily

clear, sharp digital pictures, and its ability to capture

both continuous video and single frames makes it the

perfect choice for a wide range of applications, includ-

ing scanning and industrial inspection.

Table 1: Key Parameters

Parameter Typical Value

Optical format 1/3-inch (6 mm)

Active pixels 1280H x 960V = 1.2 Mp

Pixel size 3.75m

Color filter array RGB Bayer or Monochrome

Shutter type Global shutter

Input clock range 6 – 50 MHz

Output pixel clock (maximum)74.25 MHz

Output Serial HiSPi

Parallel 12-bit

Ordering Information

Frame rate Full resolution 54 fps

720p 60 fps

Responsivity Monochrome 6.1 V/lux-sec

Color 5.3 V/lux-sec

SNRMAX 38.6 dB

Dynamic range 64 dB

Supply

voltage

I/O 1.8 or 2.8 V

Digital 1.8 V

Analog 2.8 V

HiSPi 0.4 V

Power consumption <400 mW

Operating temperature –30°C to +70°C (ambient)

–30°C to +80°C ( junction)

Package options 9 x 9 mm 64-pin iBGA

10x10 mm 48-pin iLCC

Bare die

Table 2: Available Part Numbers

Part Number Description

AR0134CSSM25SUEA0 Mono, iBGA, 25deg shift

AR0134CSSM00SUEA0 Mono, iBGA

AR0134CSSM00SUEAH Mono, iBGA, Head Board

AR0134CSSM00SUEAD Mono, iBGA, Demo Kit

AR0134CSSC00SUEA0 Color, iBGA

AR0134CSSC00SUEAH Color, iBGA, Head Board

AR0134CSSC00SUEAD Color, iBGA, Demo Kit

AR0134CSSM00SPCA0 Mono, iLCC (Parallel)

AR0134CSSM25SPCA0 Mono, iLCC (Parallel), 25deg shift

AR0134CSSC00SPCA0 Color, iLCC (Parallel)

AR0134CSSC00SPD20 Color, Bare die

AR0134CSSM00SPD20 Mono, Bare die

AR0134CSSM25SPD20 Mono, Bare die, 25deg shift

Table 1: Key Parameters (continued)

Parameter Typical Value

AR0134: 1/3-Inch 1.2Mp CMOS Digital Image Sensor

Table of Contents

Aptina Confidential and Proprietary

Table of Contents

Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Functional Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Features Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

Pixel Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Pixel Array Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Default Readout Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Configuration and Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Two-Wire Serial Register Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Start Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Stop Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Slave Address/Data Direction Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Message Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Acknowledge Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

No-Acknowledge Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Typical Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Single READ from Random Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Single READ from Current Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Sequential READ, Start from Random Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Sequential READ, Start from Current Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Single WRITE to Random Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Sequential WRITE, Start at Random Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Two-Wire Serial Register Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

I/O Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

HiSPi Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Power-On Reset and Standby Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Power-Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Power-Down Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Standby Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

AR0134: 1/3-Inch 1.2Mp CMOS Digital Image Sensor

List of Figures

Aptina Confidential and Proprietary

List of Figures

Figure 1: Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Figure 2: Pixel Array Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Figure 3: Pixel Color Pattern Detail (Top Right Corner) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Figure 4: Typical Configuration: Serial Four-Lane HiSPi Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Figure 5: Typical Configuration: Parallel Pixel Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Figure 6: 9x9mm 63-Ball iBGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Figure 7: 48 iLCC Package, Parallel Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Figure 8: Single READ from Random Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Figure 9: Single READ from Current Location. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Figure 10: Sequential READ, Start from Random Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Figure 11: Sequential READ, Start from Current Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Figure 12: Single WRITE to Random Location. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Figure 13: Sequential WRITE, Start at Random Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Figure 14: Two-Wire Serial Bus Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Figure 15: I/O Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Figure 16: Differential Output Voltage for Clock or Data Pairs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Figure 17: Eye Diagram for Clock and Data Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Figure 18: Skew Within the PHY and Output Channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Figure 19: Power Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Figure 20: Power Down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Figure 21: Enter Standby Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Figure 22: Exit Standby Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Figure 23: Quantum Efficiency – Monochrome Sensor (Typical) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Figure 24: Quantum Efficiency – Color Sensor (Typical) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Figure 25: 63-Ball iBGA Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Figure 26: 48-pin iLCC Package Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

AR0134: 1/3-Inch 1.2Mp CMOS Digital Image Sensor

List of Tables

Aptina Confidential and Proprietary

List of Tables

Table 1: Key Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Table 2: Available Part Numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Table 3: Pin Descriptions - 63-Ball iBGA Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Table 4: Pin Descriptions - 48 iLCC Package, Parallel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Table 5: Two-Wire Serial Bus Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Table 6: I/O Timing Characteristics, Parallel Output (1.8V Vdd_IO)1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Table 7: I/O Timing Characteristics, Parallel Output (2.8V Vdd_IO)1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Table 8: I/O Rise Slew Rate (2.8V Vdd_IO)1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Table 9: I/O Fall Slew Rate (2.8V Vdd_IO)1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Table 10: I/O Rise Slew Rate (1.8V Vdd_IO)1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Table 11: I/O Fall Slew Rate (1.8V Vdd_IO)1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Table 12: DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Table 13: Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Table 14: Operating Current Consumption for Parallel Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Table 15: Standby Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Table 16: Input Voltage and Current (HiSPi Power Supply 0.4 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Table 17: Rise and Fall Times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Table 18: Power-Up Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Table 19: Power-Down Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Table 20: Chief Ray Angle - 25deg Mono. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

AR0134: 1/3-Inch 1.2Mp CMOS Digital Image Sensor

General Description

Aptina Confidential and Proprietary

General Description

The Aptina™ AR0134 can be operated in its default mode or programmed for frame size,

exposure, gain, and other parameters. The default mode output is a full-resolution

image at 54 frames per second (fps). It outputs 12-bit raw data, using either the parallel

or serial (HiSPi) output ports. The device may be operated in video (master) mode or in

frame trigger mode.

FRAME_VALID and LINE_VALID signals are output on dedicated pins, along with a

synchronized pixel clock. A dedicated FLASH pin can be programmed to control

external LED or flash exposure illumination.

The AR0134 includes additional features to allow application-specific tuning:

windowing, adjustable auto-exposure control, auto black level correction, on-board

temperature sensor, and row skip and digital binning modes.

The sensor is designed to operate in a wide temperature range (–30°C to +70°C).

Functional Overview

The AR0134 is a progressive-scan sensor that generates a stream of pixel data at a

constant frame rate. It uses an on-chip, phase-locked loop (PLL) that can be optionally

enabled to generate all internal clocks from a single master input clock running between

6 and 50 MHz. The maximum output pixel rate is 74.25 Mp/s, corresponding to a clock

rate of 74.25 MHz. Figure 1 shows a block diagram of the sensor.

Figure 1: Block Diagram

User interaction with the sensor is through the two-wire serial bus, which communi-

cates with the array control, analog signal chain, and digital signal chain. The core of the

sensor is a 1.2 Mp Active- Pixel Sensor array. The AR0134 features global shutter tech-

nology for accurate capture of moving images. The exposure of the entire array is

controlled by programming the integration time by register setting. All rows simultane-

ously integrate light prior to readout. Once a row has been read, the data from the

columns is sequenced through an analog signal chain (providing offset correction and

gain), and then through an analog-to- digital converter (ADC). The output from the ADC

is a 12-bit value for each pixel in the array. The ADC output passes through a digital

Control Registers

Active Pixel Sensor

(APS)

Array

PLL

Memory

OTPM

Temperature

sensor

Timing and Control

(Sequencer)

Analog Processing and

A/D Conversion

Auto Exposure

and Stats Engine

Pixel Data Path

(Signal Processing)

External

Clock

Serial

Output

Flash

Parallel

Output

Two-Wire

Serial

Interface

Trigger

Power

AR0134: 1/3-Inch 1.2Mp CMOS Digital Image Sensor

Features Overview

Aptina Confidential and Proprietary

processing signal chain (which provides further data path corrections and applies digital

gain). The pixel data are output at a rate of up to 74.25 Mp/s, in parallel to frame and line

synchronization signals.

Features Overview

The AR0134 Global Sensor shutter has a wide array of features to enhance functionality

and to increase versatility. A summary of features follows. Please refer to the AR0134

Developer Guide for detailed feature descriptions, register settings, and tuning guide-

lines and recommendations.

•Operating Modes

The AR0134 works in master (video), trigger (single frame), or Auto Trigger modes. In

master mode, the sensor generates the integration and readout timing. In trigger

mode, it accepts an external trigger to start exposure, then generates the exposure and

readout timing. The exposure time is programmed through the two-wire serial inter-

face for both modes. Trigger mode is not compatible with the HiSPi interface.

•Window Control

Configurable window size and blanking times allow a wide range of resolutions and

frame rates. Digital binning and skipping modes are supported, as are vertical and

horizontal mirror operations.

•Context Switching

Context switching may be used to rapidly switch between two sets of register values.

Refer to the AR0134 Developer Guide for a complete set of context switchable regis-

ters.

•Gain

The AR0134 Global Shutter sensor can be configured for analog gain of up to 8x, and

digital gain of up to 8x.

•Automatic Exposure Control

The integrated automatic exposure control may be used to ensure optimal settings of

exposure and gain are computed and updated every other frame. Refer to the AR0134

Developer Guide for more details.

•HiSPi

The AR0134 Global Shutter image sensor supports two or three lanes of Streaming-SP

or Packetized-SP protocols of Aptina's High-Speed Serial Pixel Interface.

•PLL

An on chip PLL provides reference clock flexibility and supports spread spectrum

sources for improved EMI performance.

•Reset

The AR0134 may be reset by a register write, or by a dedicated input pin.

•Output Enable

The AR0134 output pins may be tri-stated using a dedicated output enable pin.

•Temperature Sensor

The temperature sensor is only guaranteed to be functional when the AR0134 is

initially powered-up or is reset at temperatures at or above 0°C.

• Black Level Correction

•Row Noise Correction

• Column Correction

• Test Patterns

Several test patterns may be enabled for debug purposes. These include a solid color,

color bar, fade to grey, and a walking 1s test pattern.

AR0134: 1/3-Inch 1.2Mp CMOS Digital Image Sensor

Pixel Data Format

Aptina Confidential and Proprietary

Pixel Data Format

Pixel Array Structure

The AR0134 pixel array is configured as 1412 columns by 1028 rows, (see Figure 2). The

dark pixels are optically black and are used internally to monitor black level. Of the right

108 columns, 64 are dark pixels used for row noise correction. Of the top 24 rows of

pixels, 12 of the dark rows are used for black level correction. There are 1296 columns by

976 rows of optically active pixels. While the sensor's format is 1280 x 960, the additional

active columns and active rows are included for use when horizontal or vertical mirrored

readout is enabled, to allow readout to start on the same pixel. The pixel adjustment is

always performed for monochrome or color versions. The active area is surrounded with

optically transparent dummy pixels to improve image uniformity within the active area.

Not all dummy pixels or barrier pixels can be read out.

Figure 2: Pixel Array Description

2 light dummy + 4 barrier + 24 dark + 4 barrier + 6 dark dummy

Dark pixel Barrier pixel Light dummy

pixel Active pixel

2 light dummy + 4 barrier + 6 dark dummy

1412

2 light dummy + 4 barrier

2 light dummy + 4 barrier + 100 dark + 4 barrier

1028

1296 x 976 (1288 x 968 active)

4.86 x 3.66 mm2 (4.83 x 3.63 mm2)

AR0134: 1/3-Inch 1.2Mp CMOS Digital Image Sensor

Pixel Data Format

Aptina Confidential and Proprietary

Figure 3: Pixel Color Pattern Detail (Top Right Corner)

Default Readout Order

By convention, the sensor core pixel array is shown with the first addressable (logical)

pixel (0,0) in the top right corner (see Figure 3). This reflects the actual layout of the array

on the die. Also, the physical location of the first pixel data read out of the sensor in

default condition is that of pixel (112, 44).

Active Pixel (0,0)

Array Pixel (110, 40)

Row

Reado

ut Direction

Column Readout Direction

AR0134: 1/3-Inch 1.2Mp CMOS Digital Image Sensor

Configuration and Pinout

Aptina Confidential and Proprietary

Configuration and Pinout

The figures and tables below show a typical configuration for the AR0134 image sensor

and show the package pinouts.

Figure 4: Typical Configuration: Serial Four-Lane HiSPi Interface

Notes: 1. All power supplies must be adequately decoupled.

2. Aptina recommends a resistor value of 1.5k, but it may be greater for slower two-wire speed.

3. This pull-up resistor is not required if the controller drives a valid logic level on SCLK at all times.

4. The parallel interface output pads can be left unconnected if the serial output interface is used.

5. Aptina recommends that 0.1μF and 10μF decoupling capacitors for each power supply are

mounted as close as possible to the pad. Actual values and results may vary depending on layout

and design considerations. Refer to the AR0134 demo headboard schematics for circuit recommen-

dations.

6. Aptina recommends that analog power planes be placed in a manner such that coupling with the

digital power planes is minimized.

7. Although 4 serial lanes are shown, the AR0134 supports only 2 or 3 lane HiSPi.

VDD_IO VDD_SLVS VDD_PLLVDD VAA

VDD VAA VAA_PIX

Master clock

(6–50 MHz)

SDATA

SCLK

RESET_BAR

TEST

EXTCLK

DGND AGND

Digital

ground

Analog

ground

Digital

Core

power1

HiSPi

power1

Analog

power1

controller

From

controller

VDD_IO VDD_PLL

PLL

power1

Digital

I/O

power1

1.5kΩ

2, 3

Analog

power1

VAA_PIX

SLVSC_N

SLVSC_P

SLVS0_P

SLVS0_N

SLVS1_P

SLVS1_N

SLVS2_P

SLVS2_N

SLVS3_P7

SLVS3_N7

FLASH

VDD_SLVS

OE_BAR

STANDBY

AR0134: 1/3-Inch 1.2Mp CMOS Digital Image Sensor

Configuration and Pinout

Aptina Confidential and Proprietary

Figure 5: Typical Configuration: Parallel Pixel Data Interface

Notes: 1. All power supplies must be adequately decoupled.

2. Aptina recommends a resistor value of 1.5k, but it may be greater for slower two-wire speed.

3. This pull-up resistor is not required if the controller drives a valid logic level on SCLK at all times.

4. The serial interface output pads can be left unconnected if the parallel output interface is used.

5. Aptina recommends that 0.1μF and 10μF decoupling capacitors for each power supply are

mounted as close as possible to the pad. Actual values and results may vary depending on layout

and design considerations. Refer to the AR0134 demo headboard schematics for circuit recommen-

dations.

6. Aptina recommends that analog power planes be placed in a manner such that coupling with the

digital power planes is minimized.

VDD

Master clock

(6–50 MHz)

SDATA

SCLK

TEST

FLASH

FRAME_VALID

DOUT [11:0]EXTCLK

DGND

Digital

ground

Analog

ground

Digital

core

power1

controller

From

Controller

LINE_VALID

PIXCLK

RESET_BAR

VDD_IO

Digital

I/O

power1

1.5kΩ

2, 3

VAA VAA_PIX

Analog

power1

VDD_PLL

PLL

power1

Analog

power1

VAA_PIX

VDD_IO VDD_PLLVDD VAA

TRIGGER

OE_BAR

STANDBY

AGND

AR0134: 1/3-Inch 1.2Mp CMOS Digital Image Sensor

Configuration and Pinout

Aptina Confidential and Proprietary

Figure 6: 9x9mm 63-Ball iBGA Package

Top View

(Ball Down)

SLVS0N SLVS0P SLVS1N SLVS1P VDD STANDBY

VDD_PLL SLVSCN SLVSCP SLVS2N SLVS2P VDD VAA VAA

EXTCLK VDD_

SLVS (SLVS3N) (SLVS3P) DGND VDD AGND AGND

SADDR SCLK SDATA DGND DGND VDD VAA_PIX VAA_PIX

LINE_

VALID

FRAME_

VALID PIXCLK FLASH DGND VDD_IO RESERVED

DOUT8DOUT9DOUT10 DOUT11 DGND TEST

DOUT4DOUT5DOUT6DOUT7DGND TRIGGER OE_BAR

DOUT0DOUT1DOUT2DOUT3DGND RESET

_BAR

12 3 567 84

VDD

VDD_IO

VDD_IO VDD_IO

RESERVED

AR0134: 1/3-Inch 1.2Mp CMOS Digital Image Sensor

Configuration and Pinout

Aptina Confidential and Proprietary

Table 3: Pin Descriptions - 63-Ball iBGA Package

Name iBGA Pin Type Description

SLVS0_N A2 Output HiSPi serial data, lane 0, differential N.

SLVS0_P A3 Output HiSPi serial data, lane 0, differential P.

SLVS1_N A4 Output HiSPi serial data, lane 1, differential N.

SLVS1_P A5 Output HiSPi serial data, lane 1, differential P.

STANDBY A8 Input Standby-mode enable pin (active HIGH).

VDD_PLL B1 Power PLL power.

SLVSC_N B2 Output HiSPi serial DDR clock differential N.

SLVSC_P B3 Output HiSPi serial DDR clock differential P.

SLVS2_N B4 Output HiSPi serial data, lane 2, differential N.

SLVS2_P B5 Output HiSPi serial data, lane 2, differential P.

VAA B7, B8 Power Analog power.

EXTCLK C1 Input External input clock.

VDD_SLVS C2 Power HiSPi power. (May leave unconnected if parallel interface is used)

SLVS3_N C3 Output (Unsupported) HiSPi serial data, lane 3, differential N.

SLVS3_P C4 Output (Unsupported) HiSPi serial data, lane 3, differential P.

DGND C5, D4, D5, E5, F5, G5, H5 Power Digital GND.

VDD A6, A7, B6, C6, D6 Power Digital power.

AGND C7, C8 Power Analog GND.

SADDR D1 Input Two-Wire Serial address select.

SCLK D2 Input Two-Wire Serial clock input.

SDATA D3 I/O Two-Wire Serial data I/O.

VAA_PIX D7, D8 Power Pixel power.

LINE_VALID E1 Output Asserted when DOUT line data is valid.

FRAME_VALID E2 Output Asserted when DOUT frame data is valid.

PIXCLK E3 Output Pixel clock out. DOUT is valid on rising edge of this clock.

FLASH E4 Output Control signal to drive external light sources.

VDD_IO E6, F6, G6, H6, H7 Power I/O supply power.

DOUT8 F1 Output Parallel pixel data output.

DOUT9 F2 Output Parallel pixel data output.

DOUT10 F3 Output Parallel pixel data output.

DOUT11 F4 Output Parallel pixel data output (MSB)

TEST F7 Input Manufacturing test enable pin (connect to DGND).

DOUT4 G1 Output Parallel pixel data output.

DOUT5 G2 Output Parallel pixel data output.

DOUT6 G3 Output Parallel pixel data output.

DOUT7 G4 Output Parallel pixel data output.

TRIGGER G7 Input Exposure synchronization input. (Connect to DGND if HiSPi interface is

used)

OE_BAR G8 Input Output enable (active LOW).

DOUT0 H1 Output Parallel pixel data output (LSB)

DOUT1 H2 Output Parallel pixel data output.

DOUT2 H3 Output Parallel pixel data output.

DOUT3 H4 Output Parallel pixel data output.

RESET_BAR H8 Input Asynchronous reset (active LOW). All settings are restored to factory

default.

Reserved E7, E8, F8 n/a Reserved (do not connect).

AR0134: 1/3-Inch 1.2Mp CMOS Digital Image Sensor

Configuration and Pinout

Aptina Confidential and Proprietary

Figure 7: 48 iLCC Package, Parallel Output

6 5 4 3 2 1 48 47 46 45 44 43

GND

EXTCLK

VDD_PLL

DOUT6

DGND

7DOUT7NC 42

8DOUT8NC 41

9DOUT9VAA 40

10 DOUT10 AGND 39

11 DOUT11 VAA_PIX 38

12 VDD_IO VAA_PIX 37

13 PIXCLK VAA 36

14 VDD AGND 35

15 SCLK VAA 34

16 SDATA Reserved 33

17 RESET_BAR Reserved 32

18 VDD_IO Reserved 31

VDD

STANDBY

SADDR

TEST

FLASH

TRIGGER

FRAME_VALID

LINE_VALID

GND

19 20 21 22 23 24 25 26 27 28 29 30

DOUT5

DOUT4

DOUT3

DOUT2

DOUT1

DOUT0

OE_BAR

AR0134: 1/3-Inch 1.2Mp CMOS Digital Image Sensor

Configuration and Pinout

Aptina Confidential and Proprietary

Table 4: Pin Descriptions - 48 iLCC Package, Parallel

Pin Number Name Type Description

OUT4 Output Parallel pixel data output.

2DOUT5 Output Parallel pixel data output.

OUT6 Output Parallel pixel data output.

DD_PLL Power PLL power.

5 EXTCLK Input External input clock.

GND Power Digital ground.

OUT7 Output Parallel pixel data output.

OUT8 Output Parallel pixel data output.

9DOUT9 Output Parallel pixel data output.

10 DOUT10 Output Parallel pixel data output.

11 DOUT11 Output Parallel pixel data output (MSB).

12 VDD_IO Power I/O supply power.

13 PIXCLK Output Pixel clock out. DOUT is valid on rising edge of this clock.

14 VDD Power Digital power.

15 SCLK Input Two-Wire Serial clock input.

16 SDATA I/O Two-Wire Serial data I/O.

17 RESET_BAR Input Asynchronous reset (active LOW). All settings are restored to factory default.

18 VDD_IO Power I/O supply power.

19 VDD Power Digital power.

20 NC No connection.

21 NC No connection.

22 STANDBY Input Standby-mode enable pin (active HIGH).

23 OE_BAR Input Output enable (active LOW).

24 SADDR Input Two-Wire Serial address select.

25 TEST Input Manufacturing test enable pin (connect to DGND).

26 FLASH Output Flash output control.

27 TRIGGER Input Exposure synchronization input.

28 FRAME_VALID Output Asserted when DOUT frame data is valid.

29 LINE_VALID Output Asserted when DOUT line data is valid.

30 DGND Power Digital ground

31 Reserved n/a Reserved (do not connect).

32 Reserved n/a Reserved (do not connect).

33 Reserved n/a Reserved (do not connect).

34 VAA Power Analog power.

35 AGND Power Analog ground.

36 VAA Power Analog power.

37 VAA_PIX Power Pixel power.

38 VAA_PIX Power Pixel power.

39 AGND Power Analog ground.

40 VAA Power Analog power.

41 NC No connection.

42 NC No connection.

43 NC No connection.

44 DGND Power Digital ground.

45 DOUT0 Output Parallel pixel data output (LSB)

46 DOUT1 Output Parallel pixel data output.

AR0134: 1/3-Inch 1.2Mp CMOS Digital Image Sensor

Configuration and Pinout

Aptina Confidential and Proprietary

47 DOUT2 Output Parallel pixel data output.

48 DOUT3 Output Parallel pixel data output.

Table 4: Pin Descriptions (continued)- 48 iLCC Package, Parallel

Pin Number Name Type Description

AR0134: 1/3-Inch 1.2Mp CMOS Digital Image Sensor

Two-Wire Serial Register Interface

Aptina Confidential and Proprietary

Two-Wire Serial Register Interface

The two-wire serial interface bus enables read/write access to control and status regis-

ters within the AR0134.The interface protocol uses a master/slave model in which a

master controls one or more slave devices. The sensor acts as a slave device. The master

generates a clock (SCLK) that is an input to the sensor and is used to synchronize trans-

fers. Data is transferred between the master and the slave on a bidirectional signal

(SDATA). SDATA is pulled up to VDD_IO off-chip by a 1.5k resistor. Either the slave or

master device can drive SDATA LOW—the interface protocol determines which device is

allowed to drive SDATA at any given time.

The protocols described in the two-wire serial interface specification allow the slave

device to drive SCLK LOW; the AR0134 uses SCLK as an input only and therefore never

drives it LOW.

Protocol

Data transfers on the two-wire serial interface bus are performed by a sequence of low-

level protocol elements:

1. a (repeated) start condition

2. a slave address/data direction byte

3. an (a no) acknowledge bit

4. a message byte

5. a stop condition

The bus is idle when both SCLK and SDATA are HIGH. Control of the bus is initiated with a

start condition, and the bus is released with a stop condition. Only the master can

generate the start and stop conditions.

Start Condition

A start condition is defined as a HIGH-to-LOW transition on SDATA while ScLK is HIGH.

At the end of a transfer, the master can generate a start condition without previously

generating a stop condition; this is known as a “repeated start” or “restart” condition.

Stop Condition

A stop condition is defined as a LOW-to-HIGH transition on SDATA while ScLK is HIGH.

Data Transfer

Data is transferred serially, 8 bits at a time, with the MSB transmitted first. Each byte of

data is followed by an acknowledge bit or a no-acknowledge bit. This data transfer

mechanism is used for the slave address/data direction byte and for message bytes.

One data bit is transferred during each SCLK clock period. SDATA can change when ScLK is

LOW and must be stable while ScLK is HIGH.

Slave Address/Data Direction Byte

Bits [7:1] of this byte represent the device slave address and bit [0] indicates the data

transfer direction. A “0” in bit [0] indicates a WRITE, and a “1” indicates a READ. The

default slave addresses used by the AR0134 are 0x20 (write address) and 0x21 (read

address) in accordance with the specification. Alternate slave addresses of 0x30 (write

address) and 0x31 (read address) can be selected by enabling and asserting the SADDR

input.

AR0134: 1/3-Inch 1.2Mp CMOS Digital Image Sensor

Two-Wire Serial Register Interface

Aptina Confidential and Proprietary

An alternate slave address can also be programmed through R0x31FC.

Message Byte

Message bytes are used for sending register addresses and register write data to the slave

device and for retrieving register read data.

Acknowledge Bit

Each 8-bit data transfer is followed by an acknowledge bit or a no-acknowledge bit in the

ScLK clock period following the data transfer. The transmitter (which is the master when

writing, or the slave when reading) releases SDATA. The receiver indicates an acknowl-

edge bit by driving SDATA LOW. As for data transfers, SDATA can change when ScLK is LOW

and must be stable while ScLK is HIGH.

No-Acknowledge Bit

The no-acknowledge bit is generated when the receiver does not drive SDATA LOW

during the ScLK clock period following a data transfer. A no-acknowledge bit is used to

terminate a read sequence.

Typical Sequence

A typical READ or WRITE sequence begins by the master generating a start condition on

the bus. After the start condition, the master sends the 8-bit slave address/data direction

byte. The last bit indicates whether the request is for a read or a write, where a “0” indi-

cates a write and a “1” indicates a read. If the address matches the address of the slave

device, the slave device acknowledges receipt of the address by generating an acknowl-

edge bit on the bus.

If the request was a WRITE, the master then transfers the 16-bit register address to which

the WRITE should take place. This transfer takes place as two 8-bit sequences and the

slave sends an acknowledge bit after each sequence to indicate that the byte has been

received. The master then transfers the data as an 8-bit sequence; the slave sends an

acknowledge bit at the end of the sequence. The master stops writing by generating a

(re)start or stop condition.

If the request was a READ, the master sends the 8-bit write slave address/data direction

byte and 16-bit register address, the same way as with a WRITE request. The master then

generates a (re)start condition and the 8-bit read slave address/data direction byte, and

clocks out the register data, eight bits at a time. The master generates an acknowledge

bit after each 8-bit transfer. The slave’s internal register address is automatically incre-

mented after every 8 bits are transferred. The data transfer is stopped when the master

sends a no-acknowledge bit.

AR0134: 1/3-Inch 1.2Mp CMOS Digital Image Sensor

Two-Wire Serial Register Interface

Aptina Confidential and Proprietary

Single READ from Random Location

This sequence (Figure 8 on page 18) starts with a dummy WRITE to the 16-bit address

that is to be used for the READ. The master terminates the WRITE by generating a restart

condition. The master then sends the 8-bit read slave address/data direction byte and

clocks out one byte of register data. The master terminates the READ by generating a no-

acknowledge bit followed by a stop condition. Figure 8 shows how the internal register

address maintained by the AR0134 is loaded and incremented as the sequence proceeds.

Figure 8: Single READ from Random Location

Single READ from Current Location

This sequence (Figure 9) performs a read using the current value of the AR0134 internal

followed by a stop condition. The figure shows two independent READ sequences.

Figure 9: Single READ from Current Location

S = start condition

P = stop condition

Sr = restart condition

A = acknowledge

A = no-acknowledge

slave to master

master to slave

Slave Address 0

S A Reg Address[15:8] A Reg Address[7:0] Slave Address AA 1Sr Read Data P

Previous Reg Address, N Reg Address, M M+1

Slave Address 1S A Read Data Slave Address A1SP Read Data P

Previous Reg Address, N Reg Address, N+1 N+2

AR0134: 1/3-Inch 1.2Mp CMOS Digital Image Sensor

Two-Wire Serial Register Interface

Aptina Confidential and Proprietary

Sequential READ, Start from Random Location

This sequence (Figure 10) starts in the same way as the single READ from random loca-

tion (Figure 8). Instead of generating a no-acknowledge bit after the first byte of data has

been transferred, the master generates an acknowledge bit and continues to perform

byte READs until “L” bytes have been read.

Figure 10: Sequential READ, Start from Random Location

Sequential READ, Start from Current Location

This sequence (Figure 11) starts in the same way as the single READ from current loca-

tion (Figure 9 on page 18). Instead of generating a no-acknowledge bit after the first byte

of data has been transferred, the master generates an acknowledge bit and continues to

perform byte READs until “L” bytes have been read.

Figure 11: Sequential READ, Start from Current Location

Single WRITE to Random Location

This sequence (Figure 12) begins with the master generating a start condition. The slave

address/data direction byte signals a WRITE and is followed by the HIGH then LOW

bytes of the register address that is to be written. The master follows this with the byte of

write data. The WRITE is terminated by the master generating a stop condition.

Figure 12: Single WRITE to Random Location

Slave Address 0

S Sr

AReg Address[15:8] AReg Address[7:0] ARead DataSlave Address

Previous Reg Address, N Reg Address, M

M+1 M+2

M+1

M+3

M+L-2 M+L-1 M+L

Read Data Read Data

Previous Reg Address, N N+1 N+2 N+L-1 N+L

Read DataSlave Address A1 Read Data A PS A A A

Slave Address 0

SAReg Address[15:8] AReg Address[7:0] AP

Previous Reg Address, N Reg Address, M M+

Write Data

AR0134: 1/3-Inch 1.2Mp CMOS Digital Image Sensor

Two-Wire Serial Register Interface

Aptina Confidential and Proprietary

Sequential WRITE, Start at Random Location

This sequence (Figure 13) starts in the same way as the single WRITE to random location

(Figure 12). Instead of generating a no-acknowledge bit after the first byte of data has

been transferred, the master generates an acknowledge bit and continues to perform

byte WRITEs until “L” bytes have been written. The WRITE is terminated by the master

generating a stop condition.

Figure 13: Sequential WRITE, Start at Random Location

Slave Address 0

SAReg Address[15:8]

AReg Address[7:0] A

Previous Reg Address, N Reg Address, M

M+1 M+2

M+1

M+3

M+L-2 M+L-1 M+L

Write Data

Write Data Write Data Write DataWrite Data

AR0134: 1/3-Inch 1.2Mp CMOS Digital Image Sensor

Electrical Specifications

Aptina Confidential and Proprietary

Electrical Specifications

Unless otherwise stated, the following specifications apply to the following conditions:

VDD = 1.8V – 0.10/+0.15; VDD_IO = VDD_PLL = VAA = VAA_PIX = 2.8V ± 0.3V;

VDD_SLVS = 0.4V – 0.1/+0.2; TA = -30°C to +70°C; output load = 10pF;

PIXCLK frequency = 74.25 MHz; HiSPi off.

Two-Wire Serial Register Interface

The electrical characteristics of the two-wire serial register interface (SCLK, SDATA) are

shown in Figure 14 and Table 5.

Figure 14: Two-Wire Serial Bus Timing Parameters

Note: Read sequence: For an 8-bit READ, read waveforms start after WRITE command and register

address are issued.

Table 5: Two-Wire Serial Bus Characteristics

fEXTCLK = 27 MHz; VDD = 1.8V; VDD_IO = 2.8V; VAA = 2.8V; VAA_PIX = 2.8V;

VDD_PLL = 2.8V; VDD_DAC = 2.8V; TA = 25°C

Parameter Symbol

Standard-Mode Fast-Mode

UnitMin Max Min Max

SCLK Clock Frequency fSCL 0 100 0 400 KHz

Hold time (repeated) START condition.

After this period, the first clock pulse is

generated

tHD;STA 4.0 - 0.6 - S

LOW period of the SCLK clock tLOW 4.7 - 1.3 - S

HIGH period of the SCLK clock tHIGH 4.0 - 0.6 - S

Set-up time for a repeated START

condition

tSU;STA 4.7 - 0.6 - S

Data hold time: tHD;DAT 043.455060.95S

Data set-up time tSU;DAT 250 - 1006-nS

Rise time of both SDATA and SCLK signals tr - 1000 20 + 0.1Cb7300 nS

Fall time of both SDATA and SCLK signals tf - 300 20 + 0.1Cb7300 nS

Set-up time for STOP condition tSU;STO 4.0 - 0.6 - S

SSr

tSU;STO

tSU;STA

tHD;STA tHIGH

tLOW tSU;DAT

tHD;DAT

DATA

CLK

tBUF

trtHD;STA

AR0134: 1/3-Inch 1.2Mp CMOS Digital Image Sensor

Electrical Specifications

Aptina Confidential and Proprietary

Notes: 1. This table is based on I2C standard (v2.1 January 2000). Philips Semiconductor.

2. Two-wire control is I2C-compatible.

3. All values referred to VIHmin = 0.9 VDD and VILmax = 0.1VDD levels. Sensor EXCLK = 27 MHz.

4. A device must internally provide a hold time of at least 300 ns for the SDATA signal to bridge the

undefined region of the falling edge of SCLK.

5. The maximum tHD;DAT has only to be met if the device does not stretch the LOW period (tLOW) of

the SCLK signal.

6. A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement

tSU;DAT 250 ns must then be met. This will automatically be the case if the device does not stretch

the LOW period of the SCLK signal. If such a device does stretch the LOW period of the SCLK signal, it

must output the next data bit to the SDATA line tr max + tSU;DAT = 1000 + 250 = 1250 ns (according

to the Standard-mode I2C-bus specification) before the SCLK line is released.

7. Cb = total capacitance of one bus line in pF.

Bus free time between a STOP and START

condition

tBUF 4.7 - 1.3 - S

Capacitive load for each bus line Cb - 400 - 400 pF

Serial interface input pin capacitance CIN_SI - 3.3 - 3.3 pF

SDATA max load capacitance CLOAD_SD - 30 - 30 pF

SDATA pull-up resistor RSD 1.5 4.7 1.5 4.7 K

Table 5: Two-Wire Serial Bus Characteristics

fEXTCLK = 27 MHz; VDD = 1.8V; VDD_IO = 2.8V; VAA = 2.8V; VAA_PIX = 2.8V;

VDD_PLL = 2.8V; VDD_DAC = 2.8V; TA = 25°C

Parameter Symbol

Standard-Mode Fast-Mode

UnitMin Max Min Max

AR0134: 1/3-Inch 1.2Mp CMOS Digital Image Sensor

Electrical Specifications

Aptina Confidential and Proprietary

I/O Timing

By default, the AR0134 launches pixel data, FV and LV with the falling edge of PIXCLK.

The expectation is that the user captures DOUT[11:0], FV and LV using the rising edge of

PIXCLK. The launch edge of PIXCLK can be configured in register R0x3028. See Figure 15

and Table 6 for I/O timing (AC) characteristics.

Figure 15: I/O Timing Diagram

Table 6: I/O Timing Characteristics, Parallel Output (1.8V VDD_IO)1

Sym bol Definition Condition Min Typ Max Unit

fEXTCLK Input clock frequency 6 50 MHz

tEXTCLK Input clock period 20 166 ns

tR Input clock rise time PLL enabled 3ns

tF Input clock fall time PLL enabled 3ns

tjJITTER Input clock jitter 600 ns

tcp EXTCLK to PIXCLK propagation

delay

Nominal voltages, PLL disabled,

PIXCLK slew rate = 4

5.7 14.3 ns

tRP PIXCLK rise time PCLK slew rate = 6 1.3 4.0 ns

tFP PIXCLK fall time PCLK slew rate = 6 1.3 3.9 ns

PIXCLK duty cycle 40 50 60 %

fPIXCLK PIXCLK frequency PIXCLK slew rate = 6,

Data slew rate = 7

6 74.25 MHz

tPD PIXCLK to data valid PIXCLK slew rate = 6,

Data slew rate = 7

-2.5 2 ns

tPFH PIXCLK to FV HIGH PIXCLK slew rate = 6,

Data slew rate = 7

-2.5 2 ns

tPLH PIXCLK to LV HIGH PIXCLK slew rate = 6,

Data slew rate = 7

-3 1.5 ns

tPFL PIXCLK to FV LOW PIXCLK slew rate = 6,

Data slew rate = 7

-2.5 2 ns

tPLL PIXCLK to LV LOW PIXCLK slew rate = 6,

Data slew rate = 7

-3 1.5 ns

CIN Input pin capacitance 2.5 pf

Data[11:0]

LINE_VALID/

PIXCLK

EXTCLK

tEXTCLK

FRAME_VALID leads LINE_VALID by 6 PIXCLKs. FRAME_VALID trails

LINE_VALID by 6 PIXCLKs.

tPLH

tPFH

tPFL

tPLL

tPD

Pxl_0 Pxl _1 Pxl _2 Pxl _n

90%

10%

tRP tFP

90%

10%

FRAME_VALID

AR0134: 1/3-Inch 1.2Mp CMOS Digital Image Sensor

Electrical Specifications

Aptina Confidential and Proprietary

Notes: 1. Minimum and maximum values are taken at 70°C, 1.7V and -30°C, 1.95V. All values are taken at the

50% transition point. The loading used is 10 pF.

2. Jitter from PIXCLK is already taken into account in the data for all of the output parameters.

Notes: 1. Minimum and maximum values are taken at 70°C, 1.7V and -30°C, 1.95V. All values are taken at the

50% transition point. The loading used is 10 pF.

2. Jitter from PIXCLK is already taken into account in the data for all of the output parameters.

Table 7: I/O Timing Characteristics, Parallel Output (2.8V VDD_IO)1

Sym bol Definition Condition Min Typ Max Unit

fEXTCLK Input clock frequency 6 50 MHz

tEXTCLK Input clock period 20 166 ns

tR Input clock rise time PLL enabled 3ns

tF Input clock fall time PLL enabled 3ns

tjJITTER Input clock jitter 600 ns

tcp EXTCLK to PIXCLK

propagation delay

Nominal voltages, PLL

disabled, PIXCLK slew

rate = 4

5.3 13.4 ns

tRP PIXCLK rise time PCLK slew rate = 6 1.3 4.0 ns

tFP PIXCLK fall time PCLK slew rate = 6 1.3 3.9 ns

PIXCLK duty cycle 40 50 60 %

fPIXCLK PIXCLK frequency PIXCLK slew rate = 6,

Data slew rate = 7

674.25MHz

tPD PIXCLK to data valid PIXCLK slew rate = 6,

Data slew rate = 7

-2.5 2 ns

tPFH PIXCLK to FV HIGH PIXCLK slew rate = 6,

Data slew rate = 7

-2.5 2 ns

tPLH PIXCLK to LV HIGH PIXCLK slew rate = 6,

Data slew rate = 7

-2.5 2 ns

tPFL PIXCLK to FV LOW PIXCLK slew rate = 6,

Data slew rate = 7

-2.5 2 ns

tPLL PIXCLK to LV LOW PIXCLK slew rate = 6,

Data slew rate = 7

-2.5 2 ns

CIN Input pin capacitance 2.5 pf

AR0134: 1/3-Inch 1.2Mp CMOS Digital Image Sensor

Electrical Specifications

Aptina Confidential and Proprietary

Note: 1. Minimum and maximum values are taken at 70°C, 2.5V and -30°C, 3.1V.

The loading used is 10 pF.

Note: 1. Minimum and maximum values are taken at 70°C, 2.5V and -30°C, 3.1V.

The loading used is 10 pF.

Table 8: I/O Rise Slew Rate (2.8V VDD_IO)1

Parallel Slew Rate

(R0x306E[15:13]) Conditions Min Typ Max Units

7 Default 1.50 2.50 3.90 V/ns

6 Default 0.98 1.62 2.52 V/ns

5 Default 0.71 1.12 1.79 V/ns

4 Default 0.52 0.82 1.26 V/ns

3 Default 0.37 0.58 0.88 V/ns

2 Default 0.26 0.40 0.61 V/ns

1 Default 0.17 0.27 0.40 V/ns

0 Default 0.10 0.16 0.23 V/ns

Table 9: I/O Fall Slew Rate (2.8V VDD_IO)1

Parallel Slew Rate

(R0x306E[15:13]) Conditions Min Typ Max Units

7 Default 1.40 2.30 3.50 V/ns

6 Default 0.97 1.61 2.48 V/ns

5 Default 0.73 1.21 1.86 V/ns

4 Default 0.54 0.88 1.36 V/ns

3 Default 0.39 0.63 0.88 V/ns

2 Default 0.27 0.43 0.66 V/ns

1 Default 0.18 0.29 0.44 V/ns

0 Default 0.11 0.17 0.25 V/ns

AR0134: 1/3-Inch 1.2Mp CMOS Digital Image Sensor

Electrical Specifications

Aptina Confidential and Proprietary

Note: 1. Minimum and maximum values are taken at 70°C, 1,7V and -30°C, 1.95V.

The loading used is 10 pF.

Notes: 1. Minimum and maximum values are taken at 70°C, 1.7V and -30°C, 1.95V.

The loading used is 10 pF.

Table 10: I/O Rise Slew Rate (1.8V VDD_IO)1

Parallel Slew Rate

(R0x306E[15:13]) Conditions Min Typ Max Units

7 Default 0.57 0.91 1.55 V/ns

6 Default 0.39 0.61 1.02 V/ns

5 Default 0.29 0.46 0.75 V/ns

4 Default 0.22 0.34 0.54 V/ns

3 Default 0.16 0.24 0.39 V/ns

2 Default 0.12 0.17 0.27 V/ns

1 Default 0.08 0.11 0.18 V/ns

0 Default 0.05 0.07 0.10 V/ns

Table 11: I/O Fall Slew Rate (1.8V VDD_IO)1

Parallel Slew Rate

(R0x306E[15:13]) Conditions Min Typ Max Units

7 Default 0.57 0.92 1.55 V/ns

6 Default 0.40 0.64 1.08 V/ns

5 Default 0.31 0.50 0.82 V/ns

4 Default 0.24 0.38 0.61 V/ns

3 Default 0.18 0.27 0.44 V/ns

2 Default 0.13 0.19 0.31 V/ns

1 Default 0.09 0.13 0.20 V/ns

0 Default 0.05 0.08 0.12 V/ns

AR0134: 1/3-Inch 1.2Mp CMOS Digital Image Sensor

Electrical Specifications

Aptina Confidential and Proprietary

DC Electrical Characteristics

The DC electrical characteristics are shown in Table 12, Table 13, Table 14, and Table 15.

Caution Stresses greater than those listed in Table 13 may cause permanent damage to the device.

This is a stress rating only, and functional operation of the device at these or any other con-

ditions above those indicated in the operational sections of this specification is not implied.

Note: 1. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Table 12: DC Electrical Characteristics

Symbol Definition Condition Min Typ Max Unit

VDD Core digital voltage 1.7 1.8 1.95 V

VDD_IO I/O digital voltage 1.7/2.5 1.8/2.8 1.9/3.1 V

VAA Analog voltage 2.5 2.8 3.1 V

VAA_PIX Pixel supply voltage 2.5 2.8 3.1 V

VDD_PLL PLL supply voltage 2.5 2.8 3.1 V

VDD_SLVS HiSPi supply voltage 0.3 0.4 0.6 V

VIH Input HIGH voltage VDD_IO * 0.7 – – V

VIL Input LOW voltage – – VDD_IO *

0.3

IIN Input leakage current No pull-up resistor; VIN = VDD_IO or

DGND

20 – – A

VOH Output HIGH voltage VDD_IO – 0.3 – – V

VOL Output LOW voltage VDD_IO = 2.8V – – 0.4 V

IOH Output HIGH current At specified VOH –22 – – mA

IOL Output LOW current At specified VOL ––22mA

Table 13: Absolute Maximum Ratings

Symbol Parameter Minimum Maximum Unit Symbol

VSUPPLY Power supply voltage (all supplies) –0.3 4.5 V VSUPPLY

ISUPPLY Total power supply current – 200 mA ISUPPLY

IGND Total ground current – 200 mA IGND

VIN DC input voltage –0.3 VDD_IO + 0.3 V VIN

VOUT DC output voltage –0.3 VDD_IO + 0.3 V VOUT

TSTG1Storage temperature –40 +85 °C TSTG1

Table 14: Operating Current Consumption for Parallel Output

VAA = VAA_PIX = VDD_IO = VDD_PLL = 2.8V; VDD= 1.8V; PLL Enabled and PIXCLK = 74.25 MHz; TA = 25°C; CLOAD = 10pF

Condition Symbol Min Typ Max Unit

Digital operating current Parallel, Streaming, Full resolution 54 fps IDD14660mA

I/O digital operating current Parallel, Streaming, Full resolution 54 fps IDD_IO 52 – mA

Analog operating current Parallel, Streaming, Full resolution 54 fps IAA 46 55 mA

Pixel supply current Parallel, Streaming, Full resolution 54 fps IAA_PIX 7 9 mA

PLL supply current Parallel, Streaming, Full resolution 54 fps IDD_PLL 8 10 mA

AR0134: 1/3-Inch 1.2Mp CMOS Digital Image Sensor

Electrical Specifications

Aptina Confidential and Proprietary

HiSPi Electrical Specifications

The Aptina AR0134 sensor supports SLVS mode only, and does not have a DLL for timing

adjustments. Refer to the High-Speed Serial Pixel (HiSPi) Interface Physical Layer Speci-

fication v2.00.00 for electrical definitions, specifications, and timing information. The

VDD_SLVS supply in this data sheet corresponds to VDD_TX in the HiSPi Physical Layer

Specification. Similarly, VDD is equivalent to VDD_HiSPi as referenced in the specifica-

tion. The HiSPi transmitter electrical specifications are listed at 700 MHz.

Table 15: Standby Current Consumption

Analog - VAA + VAA_PIX + VDD_PLL; Digital - VDD + VDD_IO; TA = 25°C

Definition Condition Min Typ Max Unit

Hard standby (clock off, driven low) Analog, 2.8V – 3 15 A

Digital, 1.8V – 25 80 A

Hard standby (clock on, EXTCLK = 20 MHz) Analog, 2.8V – 12 25 A

Digital, 1.8V – 1.1 1.7 mA

Soft standby (clock off, driven low) Analog, 2.8V – 3 15 A

Digital, 1.8V – 25 80 A

Soft standby (clock on, EXTCLK = 20 MHz) Analog, 2.8V – 12 25 A

Digital, 1.8V – 1.1 1.7 mA

Table 16: Input Voltage and Current (HiSPi Power Supply 0.4 V)

Measurement Conditions: Max Freq 700 MHz

Parameter Symbol Min Typ Max Unit

Supply current (PWRHiSPi)

(driving 100 load)

IDD_SLVS – 10 15 mA

HiSPi common mode voltage

(driving 100 load)

VCMD VDD_SLVS x 0.45 VDD_SLVS/2 VDD_SLVS x 0.55 V

HiSPi differential output voltage

(driving 100 load)

|VOD|VDD_SLVS x 0.36 VDD_SLVS/2 VDD_SLVS x 0.64 V

Change in VCM between logic 1 and 0 VCM 25 mV

Change in |VOD| between logic 1 and

|VOD|25mV

Vod noise margin NM – 30 %

Difference in VCM between any two

channels

|VCM|50mV

Difference in VOD between any two

channels

|VOD|100mV

Common-mode AC voltage (pk)

without VCM cap termination

VCM_ac 50 mV

Common-mode AC voltage (pk) with

VCM cap termination

VCM_ac 30 mV

Max overshoot peak |VOD|VOD_ac 1.3 x |VOD|V

Max overshoot Vdiff pk-pk Vdiff_pkpk 2.6 x |VOD|V

Eye Height Veye 1.4 x VOD

Single-ended output impedance Ro 35 50 70 

Output impedance mismatch Ro 20 %

AR0134: 1/3-Inch 1.2Mp CMOS Digital Image Sensor

Electrical Specifications

Aptina Confidential and Proprietary

Figure 16: Differential Output Voltage for Clock or Data Pairs

Notes: 1. One UI is defined as the normalized mean time between one edge and the following edge of the

clock.

2. Taken from 0V crossing point.

3. Also defined with a maximum loading capacitance of 10pF on any pin. The loading capacitance

may also need to be less for higher bitrates so the rise and fall times do not exceed the maximum

0.3UI.

4. The absolute mean skew between the Clock lane and any Data Lane in the same PHY between any

edges.

5. The absolute mean skew between any Clock in one PHY and any Data lane in any other PHY

between any edges.

6. Differential skew is defined as the skew between complementary outputs. It is measured as the

absolute time between the two complementary edges at mean VCM point.

Table 17: Rise and Fall Times

Measurement Conditions: HiSPi Power Supply 0.4V, Max Freq 700 MHz

Parameter Symbol Min Typ Max Unit

Data Rate 1/UI 280 – 700 Mb/s

Max setup time from transmitter TxPRE 0.3 – – UI1

Max hold time from transmitter TxPost 0.3 – – UI

Rise time (20% - 80%) RISE – 0.25UI –

Fall time (20% - 80%) FALL 150ps 0.25 UI –

Clock duty PLL_DUTY 45 50 55 %

Bitrate Period tpw 1.43 3.57 ns1

Eye Width teye 0.3 UI1, 2

Data Total jitter (pk pk)@1e-9 ttotaljit 0.2 UI1, 2

Clock Period Jitter (RMS) tckjit 50 ps2

Clock cycle to cycle jitter (RMS) tcyjit 100 ps2

Clock to Data Skew tchskew -0.1 0.1 UI1, 2

PHY-to-PHY Skew t|PHYskew| 2.1 UI1, 5

Mean differential skew tDIFFSKEW –100 100 ps6

0V Diff)

VDIFFmax

VDIFFmin

Output Signal is 'Cp - Cn' or 'Dp - Dn'

AR0134: 1/3-Inch 1.2Mp CMOS Digital Image Sensor

Electrical Specifications

Aptina Confidential and Proprietary

Figure 17: Eye Diagram for Clock and Data Signals

Figure 18: Skew Within the PHY and Output Channels

CLKJITTER

T ri gger/ R eference

VdiffMax

Vdiff

UI/ 2 UI/ 2

Vdiff

TxPre TxPost

CLOCK MASK

DATA MASK

RISE

FALL

20%

80%

tCMPSKEW

VCMD

tCHSKEW1PHY

AR0134: 1/3-Inch 1.2Mp CMOS Digital Image Sensor

Power-On Reset and Standby Timing

Aptina Confidential and Proprietary

Power-On Reset and Standby Timing

Power-Up Sequence

The recommended power-up sequence for the AR0134 is shown in Figure 19. The avail-

able power supplies (VDD_IO, VDD, VDD_SLVS, VDD_PLL, VAA, VAA_PIX) must have the

separation specified below.

1. Turn on VDD_PLL power supply.

2. After 0–10s, turn on VAA and VAA_PIX power supply.

3. After 0–10s, turn on VDD_IO power supply.

4. After the last power supply is stable, enable EXTCLK.

5. If RESET_BAR is in a LOW state, hold RESET_BAR LOW for at least 1ms.

If RESET_BAR is in a HIGH state, assert RESET_BAR for at least 1ms.

6. Wait 160000 EXTCLKs (for internal initialization into software standby).

7. Configure PLL, output, and image settings to desired values.

8. Wait 1ms for the PLL to lock.

9. Set streaming mode (R0x301a[2] = 1).

Figure 19: Power Up

Notes: 1. Xtal settling time is component-dependent, usually taking about 10 – 100 ms.

2. Hard reset time is the minimum time required after power rails are settled. In a circuit where hard

reset is held down by RC circuit, then the RC time must include the all power rail settle time and

Xtal settle time.

3. It is critical that VDD_PLL is not powered up after the other power supplies. It must be powered

before or at least at the same time as the others. If the case happens that VDD_PLL is powered after

Table 18: Power-Up Sequence

Definition Symbol Minimum Typical Maximum Unit

VDD_PLL to VAA/VAA_PIX t0 0 10 – s

VAA/VAA_PIX to VDD_IO t1 0 10 – s

VDD_IO to VDD t2 0 10 – s

VDD to VDD_SLVS t3 0 10 – s

Xtal settle time tx – 301–ms

Hard Reset t4 12–– ms

Internal Initialization t5 160000 – – EXTCLKs

PLL Lock Time t6 1 – – ms

VDD_PLL (2.8)

VAA_PIX

VAA (2.8)

VDD_IO (1.8/2.8)

VDD (1.8)

VDD_SLVS (0.4)

EXTCLK

RESET_BAR

t5 t6

Hard Reset Internal

Initialization

Software

Standby PLL Lock Streaming

AR0134: 1/3-Inch 1.2Mp CMOS Digital Image Sensor

Power-On Reset and Standby Timing

Aptina Confidential and Proprietary

other supplies then the sensor may have functionality issues and will experience high current draw

on this supply.

Power-Down Sequence

The recommended power-down sequence for the AR0134 is shown in Figure 20. The

available power supplies (VDD_IO, VDD, VDD_SLVS, VDD_PLL, VAA, VAA_PIX) must have

the separation specified below.

1. Disable streaming if output is active by setting standby R0x301a[2] = 0

2. The soft standby state is reached after the current row or frame, depending on config-

uration, has ended.

3. Turn off VDD_SLVS.

4. Turn off VDD.

5. Turn off VDD_IO

6. Turn off VAA/VAA_PIX.

7. Turn off VDD_PLL.

Figure 20: Power Down

Note: t4 is required between power down and next power up time; all decoupling caps

from regulators must be completely discharged.

Table 19: Power-Down Sequence

Definition Symbol Minimum Typical Maximum Unit

VDD_SLVS to VDD t0 0 – – S

VDD to VDD_IO t1 0 – – S

VDD_IO to VAA/VAA_PIX t2 0 – – S

VAA/VAA_PIX to VDD_PLL t3 0 – – S

PwrDn until Next PwrUp Time t4 100 – – mS

VDD_IO (1.8/2.8)

t 0

EXTCLK

VDD_SLVS (0.4)

VDD (1.8)

VAA_PIX

VAA (2.8)

VDD_PLL (2.8)

Power Down until next Power up cycle

AR0134: 1/3-Inch 1.2Mp CMOS Digital Image Sensor

Power-On Reset and Standby Timing

Aptina Confidential and Proprietary

Standby Sequence

Figures 21 and 22 show timing diagrams for entering and exiting standby. Delays are

shown indicating the last valid register write prior to entering standby as well as the first

valid write upon exiting standby. Also shown is timing if the EXTCLK is to be disabled

during standby.

Figure 21: Enter Standby Timing

Figure 22: Exit Standby Timing

EXTCLK

STANDBY

50 E XTC L Ks

R egister Writes Not ValidRegisterWrites Valid

SDATA

750 E XTC L Ks

EXTCLK

STANDBY

TRIGGER

10 E XTC L Ks

1ms

28 rows + C IT

R egister Writes Not Valid R egister Writes ValidSDATA

AR0134: 1/3-Inch 1.2Mp CMOS Digital Image Sensor

Power-On Reset and Standby Timing

Aptina Confidential and Proprietary

Figure 23: Quantum Efficiency – Monochrome Sensor (Typical)

AR0134: 1/3-Inch 1.2Mp CMOS Digital Image Sensor

Power-On Reset and Standby Timing

Aptina Confidential and Proprietary

Figure 24: Quantum Efficiency – Color Sensor (Typical)

AR0134: 1/3-Inch 1.2Mp CMOS Digital Image Sensor

Power-On Reset and Standby Timing

Aptina Confidential and Proprietary

Table 20: Chief Ray Angle - 25deg Mono

Image Height CRA

(%) (mm) (deg)

00 0

5 0.150 1.35

10 0.300 2.70

15 0.450 4.04

20 0.600 5.39

25 0.750 6.73

30 0.900 8.06

35 1.050 9.39

40 1.200 10.71

45 1.350 12.02

50 1.500 13.33

55 1.650 14.62

60 1.800 15.90

65 1.950 17.16

70 2.100 18.41

75 2.250 19.64

80 2.400 20.85

85 2.550 22.05

90 2.700 23.22

95 2.850 24.38

100 3000 25.51

0 102030405060708090100110

CRA (deg)

I H i ht (%)

AR0134: 1/3-Inch 1.2Mp CMOS Digital Image Sensor

Package Dimensions

Aptina Confidential and Proprietary

Package Dimensions

Figure 25: 63-Ball iBGA Package Outline Drawing

Notes: 1. Dimensions in mm. Dimensions in () are for reference only.

Encapsulant: Epoxy.

Substrate material: Plastic laminate 0.25 thickness.

Lid material: Borosilicate glass 0.4 ± 0.04 thickness.

Refractive index at 20C = 1.5255 @ 546nm and 1.5231 @ 588nm.

Double side AR Coating: 530-570nm R< 1%; 420-700nm R < 2%.

Image sensor die: 0.2mm thickness.

Solder ball material: SAC305 (95% Sn, 3% Ag, 0.5% Cu).

Dimensions apply to solder balls post reflow.

Pre-flow ball is0.5 on a Ø0.4 SMD ball pad.

Maximum rotation of optical area relative to package edges: 1°.

Maximum tilt of optical area relative to substrate plane : 25 m.

Maximum tilt of cover glass relative to optical area plane : 50 m.

AR0134: 1/3-Inch 1.2Mp CMOS Digital Image Sensor

Package Dimensions

Aptina Confidential and Proprietary

Figure 26: 48-pin iLCC Package Drawing

Notes: 1. Dimensions in mm. Dimensions in () are for reference only.

Encapsulant: Epoxy.

Substrate material: Plastic laminate 0.5 thickness.

Lid material: Borosilicate glass 0.4 ± 0.04 thickness.

Refractive index at 20C = 1.5255 @ 546nm and 1.5231 @ 588nm.

Double side AR Coating: 530-570nm R< 1%; 420-700nm R < 2%.

Lead finish: Gold plating, 0.5 microns minimum thickness.

Image sensor die: 0.2mm thickness.

Maximum rotation of optical area relative to package edges: 1°.

Maximum tilt of optical area relative to substrate plane : 25 m.

Maximum tilt of cover glass relative to optical area plane : 50 m.

AR0134: 1/3-Inch 1.2Mp CMOS Digital Image Sensor

Revision History

Aptina Confidential and Proprietary

Revision History

Rev. D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6/13/14

• Updated Table 1, “Key Parameters,” on page 1

• Updated Figure 4: “Typical Configuration: Serial Four-Lane HiSPi Interface,” on

page 9

• Updated Figure 6: “9x9mm 63-Ball iBGA Package,” on page 11

• Updated Table 5, “Two-Wire Serial Bus Characteristics,” on page 21

• Updated Table 6, “I/O Timing Characteristics, Parallel Output (1.8V VDD_IO)1,” on

page 23

• Updated Table 7, “I/O Timing Characteristics, Parallel Output (2.8V VDD_IO)1,” on

page 24

• Updated “Two-Wire Serial Register Interface” on page 16

• Split Table 6 and updated values in Table 8, “I/O Rise Slew Rate (2.8V VDD_IO)1,” on

page 25 and Table 9, “I/O Fall Slew Rate (2.8V VDD_IO)1,” on page 25

• Updated “Power-Up Sequence” on page 31

• Updated Figure 19: “Power Up,” on page 31

• Updated Figure 25: “63-Ball iBGA Package Outline Drawing,” on page 37

• Updated Figure 26: “48-pin iLCC Package Drawing,” on page 38

Rev. C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6/13/13

• Updated to Production

• Applied updated Aptina template

• Updated “General Description” on page 1

• Updated Table 1, “Key Parameters,” on page 1

• Updated Table 2, “Available Part Numbers,” on page 1

• Updated “Features Overview” on page 6

• Added “Pixel Data Format” on page 7

• Updated Table 6, “I/O Timing Characteristics, Parallel Output (1.8V VDD_IO)1,” on

page 23

• Updated Table 7, “I/O Rise Slew Rate (2.8V Vdd_IO)1,” on page 23

• Updated Table 8, “I/O Fall Slew Rate (2.8V Vdd_IO)1,” on page 23

• Updated Table 9, “I/O Rise Slew Rate (1.8V Vdd_IO)1,” on page 23

• Added “Two-Wire Serial Register Interface” on page 16

• Added “Standby Sequence” on page 33

• Added Table 20, “Chief Ray Angle - 25deg Mono,” on page 36

Rev. B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1/23/13

• Updated to Preliminary

• Updated “Features” on page 1

• Updated third paragraph of “General Description” on page 5

• Updated Figure 15: “I/O Timing Diagram,” on page 23

• Updated Table 6, “I/O Timing Characteristics, Parallel Output (1.8V VDD_IO)1,” on

page 23

• Added Figure 21: “Enter Standby Timing,” on page 33

• Added Figure 22: “Exit Standby Timing,” on page 33

• Added Table 7, “I/O Rise Slew Rate (2.8V Vdd_IO)1,” on page 23

• Added Table 8, “I/O Fall Slew Rate (2.8V Vdd_IO)1,” on page 23

• Added Table 9, “I/O Rise Slew Rate (1.8V Vdd_IO)1,” on page 23

180 Clemenceau Avenue, #05-02/04 Haw Par Centre, Singapore 239922 prodmktg@aptina.com www.aptina.com

Aptina, Aptina Imaging, and the Aptina logo are the property of Aptina Imaging Corporation

All other trademarks are the property of their respective owners.

This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered

final, these specifications are subject to change, as further product development and data characterization sometimes occur.

AR0134: 1/3-Inch 1.2Mp CMOS Digital Image Sensor

Revision History

Aptina Confidential and Proprietary

• Added Table 10, “I/O Fall Slew Rate (1.8V Vdd_IO)1,” on page 24

• Updated “Power-Up Sequence” on page 31

• Updated Table 18, “Power-Up Sequence,” on page 31

• Added Figure 21: “Enter Standby Timing,” on page 33

• Added Figure 22: “Exit Standby Timing,” on page 33

• Added Figure 23: “Quantum Efficiency – Monochrome Sensor (Typical),” on page 34

Rev. A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9/19/12

•Initial release

AR0134: Register Reference

Aptina Confidential and Proprietary

AR0134 Register Reference, Rev. D

For more information, refer to the data sheet on Aptina's Web site: www.aptina.com

AR0134 Register Reference

AR0134: Register Reference

Table of Contents

Aptina Confidential and Proprietary

Table of Contents

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

Conventions and Notations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

Register Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

Register Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

Register Aliases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

Bit Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Bit Field Aliases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Byte Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Address Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Bit Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Register Behavior. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

Double-Buffered Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

Bad Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

Register Summary Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Manufacturer-Specific Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Detailed Register Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Manufacturer-Specific Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

AR0134: Register Reference

List of Tables

Aptina Confidential and Proprietary

List of Tables

Table 1: Address Space Regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

Table 2: Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Table 3: Manufacturer-Specific Register List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Table 4: Manufacturer-Specific Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

AR0134: Register Reference

Introduction

Aptina Confidential and Proprietary

Introduction

This register reference is provided for engineers who are designing cameras that use the

AR0134.

Conventions and Notations

This document follows the conventions and notations described below.

• Hexadecimal numbers have a 0x prefix

• Binary numbers have 0b prefix

Example: 0b1010 = 0xA

The AR0134 provides a 16-bit register address space accessed through a serial interface.

Each register location is 8 or 16 bits in size.

The address space is divided into the five major regions shown in Table 1.

The underlying mechanism for reading and writing registers provides byte write capa-

bility. However, it is convenient to consider some registers as multiple adjacent bytes.

The AR0134uses 8-bit, 16-bit, and 32-bit registers, all implemented as 1 or more bytes at

naturally aligned, contiguous locations in the address space.

In this document, registers are described either by address or by name. When registers

are described by address, the size of the registers is explicit. For example, R0x3024 is an

8-bit register at address 0x3024, and R0x3000–1 is a 16-bit register at address 0x3000–

0x3001. When registers are described by name, the size of the register is implicit. It is

necessary to refer to the register table to determine that model_id is a 16-bit register.

A consequence of the internal architecture of the AR0134 is that some registers are

decoded at multiple addresses. Some registers in “configuration space” are also decoded

in “manufacturer-specific space.” To provide unique names for all registers, the name of

the register within manufacturer-specific register space has a trailing underscore. For

example, R0x0000–1 is model_id, and R0x3000–1 is model_id_. The effect of reading or

writing a register through any of its aliases is identical.

Table 1: Address Space Regions

Address Range Description

0x0000–0x0FFF Reserved

0x1000–0x1FFF Reserved

0x2000–0x2FFF Reserved

0x3000–0x3FFF Manufacturer-specific registers (read-only and read-write dynamic registers)

0x4000–0xFFFF Reserved (undefined)

AR0134: Register Reference

Introduction

Aptina Confidential and Proprietary

Bit Fields

Some registers provide control of several different pieces of related functionality, and

this makes it necessary to refer to bit fields within registers. As an example of the nota-

tion used for this, the least significant 4 bits of the model_id register are referred to as

model_id[3:0] or R0x0000–1[3:0].

Bit Field Aliases

In addition to the register aliases described above, some register fields are aliased in

multiple places. For example, R0x0100 (mode_select) only has one operational bit,

R0x0100[0]. This bit is aliased to R0x301A–B[2]. The effect of reading or writing a bit field

through any of its aliases is identical.

Byte Ordering

Registers that occupy more than 1 byte of address space are shown with the lowest

address in the highest-order byte lane to match the byte-ordering on the bus. For

example, the model_id register is R0x0000–1. In the register table the default value is

shown as 0x2600. This means that a READ from address 0x0000 would return 0x26, and a

READ from address 0x0001 would return 0x00. When reading this register as two 8-bit

transfers on the serial interface, the 0x26 will appear on the serial interface first, followed

by the 0x00.

Address Alignment

All register addresses are aligned naturally. Registers that occupy two bytes of address

space are aligned to even 16-bit addresses, and registers that occupy four bytes of

address space are aligned to 16-bit addresses that are an integer multiple of 4.

Bit Representation

For clarity, 32-bit hex numbers are shown with an underscore between the upper and

lower 16 bits. For example: 0x3000_01AB.

Data Format

Most registers represent an unsigned binary value or set of bit fields. For all other register

formats, the format is stated explicitly at the start of the register description. The nota-

tion for these formats is shown in Table 2.

Table 2: Data Formats

Name Description

FIX16 Signed fixed-point, 16-bit number: two’s complement number, 8 fractional bits.

Examples: 0x0100 = 1.0, 0x8000 = –128, 0xFFFF = –0.0039065

UFIX16 Unsigned fixed-point, 16-bit number: 8.8 format. Examples: 0x0100 = 1.0, 0x280 = 2.5

FLP32 Signed floating-point, 32-bit number: IEEE 754 format. Example: 0x4280_0000 = 64.0

AR0134: Register Reference

Aptina Confidential and Proprietary

Registers vary from “read-only,” “read/write,” and “read, write-1-to-clear.”

Double-Buffered Registers

Some sensor settings cannot be changed during frame readout. For example, changing

x_addr_start partway through frame readout would result in inconsistent row lengths

within a frame. To avoid this, the AR0134 double-buffers many registers by imple-

menting a “pending” and a “live” version. READs and WRITEs access the pending

The value in the pending register is transferred to a live register at a fixed point in the

frame timing, called frame start. Frame start is defined as the point at which the first

dark row is read out internally to the sensor. In the register tables the “Buffering” column

shows which registers or register fields are single- or double-buffered

Bad Frames

A bad frame is a frame where all rows do not have the same integration time or where

offsets to the pixel values have changed during the frame.

Many changes to the sensor register settings can cause a bad frame. For example, when

line_length_pck is changed, the new register value does not affect sensor behavior until

the next frame start. However, the frame that would be read out at that frame start will

have been integrated using the old row width, so reading it out using the new row width

would result in a frame with an incorrect integration time.

By default, bad frames are not masked. If the masked bad frame option is enabled, both

LV and FV are inhibited for these frames so that the vertical blanking time between

frames is extended by the frame time.

In the register tables, the “Bad Frame” column shows where changing a register or

N—No. Changing the register value will not produce a bad frame.

Y—Yes. Changing the register value might produce a bad frame.

YM—Yes; but the bad frame will be masked out when mask_corrupted_frames

(R0x301A[9]) is set to “1.”

AR0134: Register Reference

Aptina Confidential and Proprietary

Note: Green1 corresponds to greenR; green2 corresponds to greenB.

Caution Writing and changing the value of a reserved register (word or bit) puts the device in an

unknown state and may damage the device.

Manufacturer-Specific Registers

Table 3: Manufacturer-Specific Register List

1 = read-only, always 1; 0 = read-only, always 0; d = programmable; ? = read-only, dynamic

Dec(Hex) Name Data Format

(Binary) Default Value

Dec(Hex)

R12288

(R0x3000)

chip_version_reg dddd dddd dddd dddd 9222

(0x2406)

R12290

(R0x3002)

y_addr_start 0000 00dd dddd dddd 0

(0x0000)

R12292

(R0x3004)

x_addr_start 0000 0ddd dddd dddd 0

(0x0000)

R12294

(R0x3006)

y_addr_end 0000 00dd dddd dddd 959

(0x03BF)

R12296

(R0x3008)

x_addr_end 0000 0ddd dddd dddd 1279

(0x04FF)

R12298

(R0x300A)

frame_length_lines dddd dddd dddd dddd 990

(0x03DE)

R12300

(R0x300C)

line_length_pck dddd dddd dddd ddd0 1388

(0x056C)

R12302

(R0x300E)

revision_number dddd dddd 19

(0x13)

R12306

(R0x3012)

coarse_integration_time dddd dddd dddd dddd 100

(0x0064)

R12308

(R0x3014)

fine_integration_time dddd dddd dddd dddd 0

(0x0000)

R12310

(R0x3016)

coarse_integration_time_cb dddd dddd dddd dddd 16

(0x0010)

R12312

(R0x3018)

fine_integration_time_cb dddd dddd dddd dddd 0

(0x0000)

R12314

(R0x301A)

reset_register d00d dddd dddd dddd 4312

(0x10D8)

R12318

(R0x301E)

data_pedestal 0000 dddd dddd dddd 300

(0x012C)

R12326

(R0x3026)

gpi_status 0000 0000 0000 ???? 0

(0x0000)

R12328

(R0x3028)

row_speed 0000 0000 0ddd 0000 16

(0x0010)

R12330

(R0x302A)

vt_pix_clk_div 0000 0000 dddd dddd 8

(0x0008)

R12332

(R0x302C)

vt_sys_clk_div 0000 0000 000d dddd 1

(0x0001)

AR0134: Register Reference

Aptina Confidential and Proprietary

R12334

(R0x302E)

pre_pll_clk_div 0000 0000 00dd dddd 2

(0x0002)

R12336

(R0x3030)

pll_multiplier 0000 0000 dddd dddd 44

(0x002C)

R12338

(R0x3032)

digital_binning 0000 0000 00dd 00dd 0

(0x0000)

R12346

(R0x303A)

frame_count dddd dddd dddd dddd 0

(0x0000)

R12348

(R0x303C)

frame_status 0000 0000 0000 00?? 0

(0x0000)

R12352

(R0x3040)

read_mode dd00 0000 0000 0000 0

(0x0000)

R12356

(R0x3044)

dark_control 000d ddd0 d000 dd00 1028

(0x0404)

R12358

(R0x3046)

flash ??00 000d d000 0000 0

(0x0000)

R12374

(R0x3056)

green1_gain 0000 0000 dddd dddd 32

(0x0020)

R12376

(R0x3058)

blue_gain 0000 0000 dddd dddd 32

(0x0020)

R12378

(R0x305A)

red_gain 0000 0000 dddd dddd 32

(0x0020)

R12380

(R0x305C)

green2_gain 0000 0000 dddd dddd 32

(0x0020)

R12382

(R0x305E)

global_gain 0000 0000 dddd dddd 32

(0x0020)

R12388

(R0x3064)

embedded_data_ctrl 000d dddd d0d0 dddd 6530

(0x1982)

R12398

(R0x306E)

datapath_select dddd dd0d 000d 00dd 36864

(0x9000)

R12400

(R0x3070)

test_pattern_mode 0000 000d 0000 0ddd 0

(0x0000)

R12402

(R0x3072)

test_data_red 0000 dddd dddd dddd 0

(0x0000)

R12404

(R0x3074)

test_data_greenr 0000 dddd dddd dddd 0

(0x0000)

R12406

(R0x3076)

test_data_blue 0000 dddd dddd dddd 0

(0x0000)

R12408

(R0x3078)

test_data_greenb 0000 dddd dddd dddd 0

(0x0000)

R12410

(R0x307A)

test_raw_mode 0000 0000 0000 00dd 0

(0x0000)

R12422

(R0x3086)

seq_data_port dddd dddd dddd dddd 0

(0x0000)

R12424

(R0x3088)

seq_ctrl_port ?d00 000d dddd dddd 49152

(0xC000)

R12426

(R0x308A)

x_addr_start_cb 0000 0ddd dddd dddd 2

(0x0002)

Table 3: Manufacturer-Specific Register List (continued)

1 = read-only, always 1; 0 = read-only, always 0; d = programmable; ? = read-only, dynamic

Dec(Hex) Name Data Format

(Binary) Default Value

Dec(Hex)

AR0134: Register Reference

Aptina Confidential and Proprietary

R12428

(R0x308C)

y_addr_start_cb 0000 00dd dddd dddd 4

(0x0004)

R12430

(R0x308E)

x_addr_end_cb 0000 0ddd dddd dddd 1281

(0x0501)

R12432

(R0x3090)

y_addr_end_cb 0000 00dd dddd dddd 963

(0x03C3)

R12448

(R0x30A0)

x_even_inc 0000 0000 0000 000? 1

(0x0001)

R12450

(R0x30A2)

x_odd_inc 0000 0000 0000 000d 1

(0x0001)

R12452

(R0x30A4)

y_even_inc 0000 0000 0000 000? 1

(0x0001)

R12454

(R0x30A6)

y_odd_inc 0000 0000 0ddd dddd 1

(0x0001)

R12456

(R0x30A8)

y_odd_inc_cb 0000 0000 0ddd dddd 63

(0x003F)

R12458

(R0x30AA)

frame_length_lines_cb dddd dddd dddd dddd 90

(0x005A)

R12460

(R0x30AC)

frame_exposure ???? ???? ???? ???? 16

(0x0010)

R12464

(R0x30B0)

digital_test dddd dddd dddd 0000 128

(0x0080)

R12466

(R0x30B2)

tempsens_data 0000 00dd dddd dddd 0

(0x0000)

R12468

(R0x30B4)

tempsens_ctrl 0000 0000 00dd dddd 0

(0x0000)

R12476

(R0x30BC)

green1_gain_cb 0000 0000 dddd dddd 32

(0x0020)

R12478

(R0x30BE)

blue_gain_cb 0000 0000 dddd dddd 32

(0x0020)

R12480

(R0x30C0)

red_gain_cb 0000 0000 dddd dddd 32

(0x0020)

R12482

(R0x30C2)

green2_gain_cb 0000 0000 dddd dddd 32

(0x0020)

R12484

(R0x30C4)

global_gain_cb 0000 0000 dddd dddd 32

(0x0020)

R12486

(R0x30C6)

tempsens_calib1 dddd dddd dddd dddd 0

(0x0000)

R12488

(R0x30C8)

tempsens_calib2 dddd dddd dddd dddd 0

(0x0000)

R12490

(R0x30CA)

tempsens_calib3 dddd dddd dddd dddd 0

(0x0000)

R12492

(R0x30CC)

tempsens_calib4 dddd dddd dddd dddd 0

(0x0000)

R12500

(R0x30D4)

column_correction ddd0 0000 0000 dddd 57351

(0xE007)

R12544

(R0x3100)

ae_ctrl_reg 0000 0000 0ddd dddd 0

(0x0000)

Table 3: Manufacturer-Specific Register List (continued)

1 = read-only, always 1; 0 = read-only, always 0; d = programmable; ? = read-only, dynamic

Dec(Hex) Name Data Format

(Binary) Default Value

Dec(Hex)

AR0134: Register Reference

Aptina Confidential and Proprietary

R12546

(R0x3102)

ae_luma_target_reg dddd dddd dddd dddd 1280

(0x0500)

R12552

(R0x3108)

ae_min_ev_step_reg dddd dddd dddd dddd 112

(0x0070)

R12554

(R0x310A)

ae_max_ev_step_reg dddd dddd dddd dddd 8

(0x0008)

R12556

(R0x310C)

ae_damp_offset_reg dddd dddd dddd dddd 512

(0x0200)

R12558

(R0x310E)

ae_damp_gain_reg dddd dddd dddd dddd 8192

(0x2000)

R12560

(R0x3110)

ae_damp_max_reg dddd dddd dddd dddd 320

(0x0140)

R12572

(R0x311C)

ae_max_exposure_reg dddd dddd dddd dddd 672

(0x02A0)

R12574

(R0x311E)

ae_min_exposure_reg dddd dddd dddd dddd 1

(0x0001)

R12580

(R0x3124)

ae_dark_cur_thresh_reg dddd dddd dddd dddd 32767

(0x7FFF)

R12586

(R0x312A)

ae_current_gains 0000 00?? ???? ???? 32

(0x0020)

R12608

(R0x3140)

ae_roi_x_start_offset 0000 0ddd dddd ddd0 0

(0x0000)

R12610

(R0x3142)

ae_roi_y_start_offset 0000 00dd dddd ddd0 0

(0x0000)

R12612

(R0x3144)

ae_roi_x_size 0000 0ddd dddd ddd0 1280

(0x0500)

R12614

(R0x3146)

ae_roi_y_size 0000 00dd dddd ddd0 960

(0x03C0)

R12626

(R0x3152)

ae_mean_l ???? ???? ???? ???? 0

(0x0000)

R12644

(R0x3164)

ae_coarse_integration_time ???? ???? ???? ???? 0

(0x0000)

R12646

(R0x3166)

ae_ag_exposure_hi dddd dddd dddd dddd 986

(0x03DA)

R12648

(R0x3168)

ae_ag_exposure_lo dddd dddd dddd dddd 419

(0x01A3)

R12680

(R0x3188)

delta_dk_level ???? ???? ???? ???? 0

(0x0000)

R12736

(R0x31C0)

hispi_timing 0ddd dddd dddd dddd 0

(0x0000)

R12742

(R0x31C6)

hispi_control_status ??00 00dd dddd dd00 32768

(0x8000)

R12744

(R0x31C8)

hispi_crc_0 ???? ???? ???? ???? 65535

(0xFFFF)

R12746

(R0x31CA)

hispi_crc_1 ???? ???? ???? ???? 65535

(0xFFFF)

R12748

(R0x31CC)

hispi_crc_2 ???? ???? ???? ???? 65535

(0xFFFF)

Table 3: Manufacturer-Specific Register List (continued)

1 = read-only, always 1; 0 = read-only, always 0; d = programmable; ? = read-only, dynamic

Dec(Hex) Name Data Format

(Binary) Default Value

Dec(Hex)

AR0134: Register Reference

Aptina Confidential and Proprietary

R12750

(R0x31CE)

hispi_crc_3 ???? ???? ???? ???? 65535

(0xFFFF)

R12754

(R0x31D2)

stat_frame_id dddd dddd dddd dddd 0

(0x0000)

R12758

(R0x31D6)

i2c_wrt_checksum dddd dddd dddd dddd 65535

(0xFFFF)

R12776

(R0x31E8)

horizontal_cursor_position 0000 00dd dddd dddd 0

(0x0000)

R12778

(R0x31EA)

vertical_cursor_position 0000 0ddd dddd dddd 0

(0x0000)

R12780

(R0x31EC)

horizontal_cursor_width 0000 00dd dddd dddd 0

(0x0000)

R12782

(R0x31EE)

vertical_cursor_width 0000 0ddd dddd dddd 0

(0x0000)

R12796

(R0x31FC)

i2c_ids dddd dddd dddd dddd 12320

(0x3020)

Table 3: Manufacturer-Specific Register List (continued)

1 = read-only, always 1; 0 = read-only, always 0; d = programmable; ? = read-only, dynamic

Dec(Hex) Name Data Format

(Binary) Default Value

Dec(Hex)

AR0134: Register Reference

Detailed Register Descriptions

Aptina Confidential and Proprietary

Detailed Register Descriptions

Manufacturer-Specific Registers

Table 4: Manufacturer-Specific Register Descriptions

R/W (Read or Write) bit; RO (Read Only) bit; Y (Yes); N (No); YM (Yes, Masked); S (Single Buffered); D (Double Buffered)

Dec(Hex) Bits Default Name Frame

Sync'd Bad

Frame Buffering

12288

R0x3000

15:0 0x2406 chip_version_reg (R/W) N N

Model ID. Read-only. Can be made read/write by clearing R0x301A[3].

12290

R0x3002

15:0 0x0000 y_addr_start (R/W) Y YM D

The first row of visible pixels to be read out (not counting any dark rows that may be read). To move the image

window, set this register to the starting Y value.

12292

R0x3004

15:0 0x0000 x_addr_start (R/W) Y N D

The first column of visible pixels to be read out (not counting any dark columns that may be read). To move the image

window, set this register to the starting X value.

12294

R0x3006

15:0 0x03BF y_addr_end (R/W) Y YM D

The last row of visible pixels to be read out.

12296

R0x3008

15:0 0x04FF x_addr_end (R/W) Y N D

The last column of visible pixels to be read out.

12298

R0x300A

15:0 0x03DE frame_length_lines (R/W) Y YM D

The number of complete lines (rows) in the output frame. This includes visible lines and vertical blanking lines.

12300

R0x300C

15:0 0x056C line_length_pck (R/W) Y YM S

The number of pixel clock periods in one line (row) time. This includes visible pixels and horizontal blanking time.

The minimum supported value is 0x056C.

12302

R0x300E

7:0

0x13

revision_number (R/W)

The upper four bits represent silicon revision, the lower four bits

indicate OTPM version.

12306

R0x3012

15:0 0x0064 coarse_integration_time (R/W) Y N S

Integration time specified in multiples of line_length_pck_.

12308

R0x3014

15:0 0x0000 fine_integration_time (R/W) Y N D

The fine integration time increases the integration time.

The resolution is 1 pixel clock time.

12310

R0x3016

15:0 0x0010 coarse_integration_time_cb (R/W) N N S

Coarse integration time in context B.

12312

R0x3018

15:0 0x0000 fine_integration_time_cb (R/W) N N D

Fine integration time in context B.

AR0134: Register Reference

Detailed Register Descriptions

Aptina Confidential and Proprietary

12314

R0x301A

15:0 0x10D8 reset_register (R/W) N Y

0x0000

grouped_parameter_hold

0: Register updates are synchronized to next frame start.

1: Register changes will remain pending until this bit is returned

to 0, after which the register updates will take effect at the next

frame start.

14:13 X Reserved

12 0x0001 smia_serialiser_dis

This bit disables the serial (HiSPi) interface NN

11 0x0000 forced_pll_on

When set, forces the PLL on, no matter sensor state. NN

0x0000

restart_bad

1: A restart is forced any time a bad frame is detected. This can

shorten the delay when waiting for a good frame, since the

delay for masking out a bad frame will be the integration time

rather than the full-frame time.

0x0000

mask_bad

0: The sensor will produce bad (corrupted) frames as a result of

some register changes.

1: Bad (corrupted) frames are masked within the sensor by

extending the vertical blanking time for the duration of the bad

frame.

0x0000

gpi_en

0: The primary input buffers associated with the

OUTPUT_ENABLE_N, TRIGGER and STANDBY inputs are powered

down and cannot be used.

1: The input buffers are enabled and can be read through

R0x3026.

0x0001

parallel_en

0: The parallel data interface (DOUT[9:0], LINE_VALID,

FRAME_VALID, and PIXCLK) is disabled and the outputs are

placed in a high-impedance state.

1: The parallel data interface is enabled. The output signals can

be switched between a driven and a high-impedance state

using output-enable control.

0x0001

drive_pins

0: The parallel data interface (DOUT[9:0], LINE_VALID,

FRAME_VALID, and PIXCLK) may enter a high-impedance state

(depending upon the configuration of R0x3026).

1: The parallel data interface is driven.

This bit is “do not care” unless bit[7]=1.

5XReserved

0x0001

stdby_eof

0: Transition to standby is synchronized to the end of a sensor

row readout (held-off until LINE_VALID has fallen).

1: Transition to standby is synchronized to the end of a frame.

0x0001

lock_reg

Many parameter limitation registers that are specified as read-

only are actually implemented as read/write registers. Clearing

this bit allows such registers to be written.

Table 4: Manufacturer-Specific Register Descriptions (continued)

R/W (Read or Write) bit; RO (Read Only) bit; Y (Yes); N (No); YM (Yes, Masked); S (Single Buffered); D (Double Buffered)

Dec(Hex) Bits Default Name Frame

Sync'd Bad

Frame Buffering

AR0134: Register Reference

Detailed Register Descriptions

Aptina Confidential and Proprietary

0x0000

stream

Setting this bit places the sensor in streaming mode. Clearing

this bit places the sensor in a low power mode. The result of

clearing this bit depends upon the operating mode of the

sensor.

Entry and exit from streaming mode can also be controlled from

the signal interface.

0x0000

restart

This bit always reads as 0. Setting this bit has two effects: first,

the current frame is read out and the sensor enters standby.

Second, any writes to frame-synchronized registers and the

shutter width registers take effect immediately, and a new

frame starts. The current frame completes before the new

frame is started, so the time between issuing the Restart and

the beginning of the next frame is a maximum of tFRAME

0x0000

reset

This bit always reads as 0. Setting this bit initiates a reset

sequence: the frame being generated will be truncated.

Controls the operation of the sensor. For details see the bit field descriptions.

12318

R0x301E

15:0 0x012C data_pedestal (R/W) N Y

Constant offset that is added to pixel values at the end of datapath (after all corrections).

12326

R0x3026

15:0 0x0000 gpi_status (RO) N N

15:4 X Reserved

standby

Read-only. Return the current state of the STANDBY input pin.

Invalid if R0x301A[8]=0.

trigger

Read-only. Return the current state of the TRIGGER input pin.

Invalid if R0x301A[8]=0.

oe_n

Read-only. Return the current state of the OUTPUT_ENABLE_N

input pin. Invalid if R0x301A[8]=0.

saddr

Read-only. Return the current state of the pin SADDR input pin.

Invalid if R0x301A[8]=0.

Reflects the status of the input pins:

STANDBY(3), TRIGGER(2), OUTPUT_ENABLE_N(1).

Bit 0 is not used.

12328

R0x3028

15:0 0x0010 row_speed (R/W) N N

Bits [6:4] of this register define the phase of the output pixclk.

2 sets of values are valid:

a) 000, 010, 100, 110 => 0 delay (rising edge of PIXCLK coincides DOUT change).

b) 001, 011, 101, 111 => 1/2 clk delay (falling edge of pixclk coincides DOUT change).

12330

R0x302A

15:0 0x0008 vt_pix_clk_div (R/W) N N

Sets the ratio of the serial output clock and sensor operation clock (P2 clock divider in PLL).

12332

R0x302C

15:0 0x0001 vt_sys_clk_div (R/W) N N

Sets the ratio of the VCO clk and the serial output clock (P1 divider in PLL).

12334

R0x302E

15:0 0x0002 pre_pll_clk_div (R/W) N N

Referring to the PLL documentation: shows the n value.

Table 4: Manufacturer-Specific Register Descriptions (continued)

R/W (Read or Write) bit; RO (Read Only) bit; Y (Yes); N (No); YM (Yes, Masked); S (Single Buffered); D (Double Buffered)

Dec(Hex) Bits Default Name Frame

Sync'd Bad

Frame Buffering

AR0134: Register Reference

Detailed Register Descriptions

Aptina Confidential and Proprietary

12336

R0x3030

15:0 0x002C pll_multiplier (R/W) N N

PLL_MULTIPLIER: shows m value.

12338

R0x3032

15:0 0x0000 digital_binning (R/W) N N

15:6 X Reserved

5:4

0x0000

digital_binning_cb

DIGITAL_BINNING for context B

00: No binning

01: Horizontal only binning

10: Horizontal and Vertical binning

3:2 X Reserved

1:0

0x0000

digital_binning_ca

DIGITAL_BINNING for context A

00: No binning

01: Horizontal only binning

10: Horizontal and Vertical binning

12346

R0x303A

15:0 0x0000 frame_count (R/W) N N

Counts the number of output frames. At the startup is initialized to 0xffff.

12348

R0x303C

15:0 0x0000 frame_status (RO) N N

15:2 X Reserved

standby_status

This bit indicates whether the sensor is in standby state. Can be

polled after standby is entered to see when the real low-power

state is entered; which can happen at the end of row or frame

depending on bit R0x301A[4].

framesync

Set on register write and reset on frame synchronization. Acts as

debug flag to verify that register writes completed before last

frame synchronization.

12352

R0x3040

15:0 0x0000 read_mode (R/W) Y YM

0x0000

vert_flip

0: Normal readout

1: Readout is flipped (mirrored) vertically so that the row

specified by y_addr_end_ is read out of the sensor first.

Setting this bit will change the Bayer pixel order.

YYM D

0x0000

horiz_mirror

0: Normal readout

1: Readout is mirrored horizontally so that the column specified

by x_addr_end_ is read out of the sensor first.

Setting this bit will change the Bayer pixel order.

YYM D

13:0 X Reserved

Table 4: Manufacturer-Specific Register Descriptions (continued)

R/W (Read or Write) bit; RO (Read Only) bit; Y (Yes); N (No); YM (Yes, Masked); S (Single Buffered); D (Double Buffered)

Dec(Hex) Bits Default Name Frame

Sync'd Bad

Frame Buffering

AR0134: Register Reference

Detailed Register Descriptions

Aptina Confidential and Proprietary

12356

R0x3044

15:0 0x0404 dark_control (R/W) N N

15:13 X Reserved

0x0000

show_colcorr_rows

When set, the column correction and delta dark rows are

included in the frame valid and are output from the chip.

The order of lines in frame valid will be:

col_corr, delta dark, embedded data, image data,..

No correction will be applied to the data.

0x0000

show_dark_extra_rows

When set, the delta dark rows (including the guard/extra rows)

will be included in frame valid and output. The order of rows will

be:

delta dark rows, embedded data, image data, ..

No correction will be applied to the dark row data.

0x0001

row_noise_correction_en

0: Row-noise cancellation algorithm is disabled

1: Row-noise cancellation algorithm is enabled.

0x0000

show_dark_cols

When set, the row noise correction columns (tied pixels) will be

added to line valid and output.

No correction will be applied to the dark row data.

8:0 X Reserved

12358

R0x3046

15:0 0x0000 flash (R/W) Y Y

15 RO strobe

Reflects the current state of the FLASH output signal. Read-only. NN

triggered

Indicates that the FLASH output signal was asserted for the

current frame. Read-only.

13:9 X Reserved

0x0000

en_flash

Enables LED flash.

The flash is asserted with the start integration.

The flash is de-asserted when the integration is complete.

YY S

0x0000

invert_flash

Invert flash output signal. When set, the FLASH output signal

will be active low.

6:0 X Reserved

12374

R0x3056

15:0 0x0020 green1_gain (R/W) Y N D

Digital gain for green1 (Gr) pixels, in format of xxx.yyyyy.

12376

R0x3058

15:0 0x0020 blue_gain (R/W) Y N D

Digital gain for Blue pixels,, in format of xxx.yyyyy.

12378

R0x305A

15:0 0x0020 red_gain (R/W) Y N D

Digital gain for Red pixels, in format of xxx.yyyyy.

12380

R0x305C

15:0 0x0020 green2_gain (R/W) Y N D

Digital gain for green2 (Gb) pixels in format of xxx.yyyyy.

12382

R0x305E

15:0 0x0020 global_gain (R/W) Y N D

Writing a gain to this register is equivalent to writing that code to each of the 4 color-specific gain registers. Reading

from this register returns the value most recently written to the green1_gain register.

Table 4: Manufacturer-Specific Register Descriptions (continued)

R/W (Read or Write) bit; RO (Read Only) bit; Y (Yes); N (No); YM (Yes, Masked); S (Single Buffered); D (Double Buffered)

Dec(Hex) Bits Default Name Frame

Sync'd Bad

Frame Buffering

AR0134: Register Reference

Detailed Register Descriptions

Aptina Confidential and Proprietary

12388

R0x3064

15:0 0x1982 embedded_data_ctrl (R/W) N N

15:13 X Reserved

12 X Reserved

11:10 X Reserved

9XReserved

0x0001

embedded_data

0: Frames out of the sensor exclude the embedded data.

1: Frames out of the sensor include 2 rows of embedded data.

This register field should only be changed while the sensor is in

software standby.

0x0001

embedded_stats_en

Enables two rows of statistical data (used by external auto-

exposure), after the transmission image data. Cannot be

enabled unless EMBEDDED_DATA_EN is enabled.

6:4 X Reserved

3:0 X Reserved

12398

R0x306E

15:0 0x9000 datapath_select (R/W) N N

15:13

0x0004

slew_rate_ctrl_parallel

Selects the slew (edge) rate for the DOUT[9:0], FRAME_VALID,

LINE_VALID and FLASH outputs. Only affects FLASH outputs

when parallel data output is disabled. The value 7 results in the

fastest edge rates on these signals. Slowing down the edge rate

can reduce ringing and electromagnetic emissions.

12:10

0x0004

slew_rate_ctrl_pixclk

Selects the slew (edge) rate for the PIXCLK output. Has no effect

when parallel data output is disabled. The value 7 results in the

fastest edge rates on this signal. Slowing down the edge rate

can reduce ringing and electromagnetic emissions.

9XReserved

0x0000

postscaler_data_sel

0: Statistics data are generated from pixel data before scaler.

1: Statistics data are generated from pixel data after scaler.

7:5 X Reserved

40x0000 true_bayer

Enables true Bayer scaling mode. NN

3:2 X Reserved

1:0

0x0000

special_line_valid

00: Normal behavior of LINE_VALID

01: LINE_VALID is driven continuously (continue generating

LINE_VALID during vertical blanking)

10: LINE_VALID is driven continuously as LINE_VALID XOR

FRAME_VALID

12400

R0x3070

15:0 0x0000 test_pattern_mode (R/W) N Y

0: Normal operation: Generate output data from pixel array

1: Solid color test pattern.

2: 100% color bar test pattern

3: Fade to gray color bar test pattern

256 : Walking 1s test pattern (12 bit)

Other: Reserved.

Table 4: Manufacturer-Specific Register Descriptions (continued)

R/W (Read or Write) bit; RO (Read Only) bit; Y (Yes); N (No); YM (Yes, Masked); S (Single Buffered); D (Double Buffered)

Dec(Hex) Bits Default Name Frame

Sync'd Bad

Frame Buffering

AR0134: Register Reference

Detailed Register Descriptions

Aptina Confidential and Proprietary

12402

R0x3072

15:0 0x0000 test_data_red (R/W) N Y

The value for red pixels in the Bayer data used for the solid color test pattern and the test cursors.

12404

R0x3074

15:0 0x0000 test_data_greenr (R/W) N Y

The value for green pixels in red/green rows of the Bayer data used for the solid color test pattern and the test

cursors.

12406

R0x3076

15:0 0x0000 test_data_blue (R/W) N Y

The value for blue pixels in the Bayer data used for the solid color test pattern and the test cursors.

12408

R0x3078

15:0 0x0000 test_data_greenb (R/W) N Y

The value for green pixels in blue/green rows of the Bayer data used for the solid color test pattern and the test

cursors.

12422

R0x3086

15:0 0x0000 seq_data_port (R/W) N N

12424

R0x3088

15:0 0xC000 seq_ctrl_port (R/W) N N

sequencer_stopped

Showing that sequencer is stopped (STANDBY mode) and the

RAM is available for read or write.

0x0001

auto_inc_on_read

1: The access_address is incremented (by 1) after each read

operation from seq_data_port (which returns only1 byte)

13:9 X Reserved

8:0

0x0000

access_address

When in STANDBY (not streaming) mode: address pointer to the

sequencer RAM.

12426

R0x308A

15:0 0x0002 x_addr_start_cb (R/W) N N D

x_address_start context B

12428

R0x308C

15:0 0x0004 y_addr_start_cb (R/W) N N D

y_addr_start for context B

12430

R0x308E

15:0 0x0501 x_addr_end_cb (R/W) N N D

x_addr_end for context B

12432

R0x3090

15:0 0x03C3 y_addr_end_cb (R/W) N N D

Y_ADDR_END for context B

12448

R0x30A0

15:0 0x0001 x_even_inc (RO) N N

Read-only.

12450

R0x30A2

15:0 0x0001 x_odd_inc (R/W) Y YM

Not supported.

12452

R0x30A4

15:0 0x0001 y_even_inc (RO) N N

Read-only.

12454

R0x30A6

15:0 0x0001 y_odd_inc (R/W) Y YM D

Row skip factor:

1: No Skip

3: Skip Factor 2

7: Skip Factor 4

15: Skip Factor 8

31: Skip Factor 16

63: Skip Factor 32

127: Skip Factor 64

Table 4: Manufacturer-Specific Register Descriptions (continued)

R/W (Read or Write) bit; RO (Read Only) bit; Y (Yes); N (No); YM (Yes, Masked); S (Single Buffered); D (Double Buffered)

Dec(Hex) Bits Default Name Frame

Sync'd Bad

Frame Buffering

AR0134: Register Reference

Detailed Register Descriptions

Aptina Confidential and Proprietary

12456

R0x30A8

15:0 0x003F y_odd_inc_cb (R/W) N N D

y_odd_inc for context B

12458

R0x30AA

15:0 0x005A frame_length_lines_cb (R/W) N N D

frame_length_lines for context B.

12460

R0x30AC

15:0 0x0010 frame_exposure (LK) N N

Shows the current frame exposure time in rows.

12464

R0x30B0

15:0 0x0080 digital_test (R/W) N Y

15 X Reserved

0x0000

pll_complete_bypass

When set, the EXTCLK will be used and PLL will be completely

bypassed. Note that the serial interface would not function.

0x0000

context_b

0: Use context A

1: Use Context B

12:11 X Reserved

0x0000

enable_short_llpck

This bit allows the line length to be reduced to 1388 and must

be set to 1 for correct line timing for non-skipping modes. It

must be set to 0 for skip modes. Triggered mode does not

support short line lengths - so it must be set to 0 for trigger

mode.

9:8

0x0000

col_gain_cb

Column gain for Context B

00: 1

01: 2

10: 4

11: 8

NN D

0x0001

mono_chrome

When set the CFA is monochrome and not color. Some features

like skipping and corrections are affected.

6XReserved

5:4

0x0000

col_gain

Column gain:

00: 1

01: 2

10: 4

11: 8

NN D

3:0 X Reserved

12466

R0x30B2

15:0 0x0000 tempsens_data (R/W) N N

Data from temperature sensor

Table 4: Manufacturer-Specific Register Descriptions (continued)

R/W (Read or Write) bit; RO (Read Only) bit; Y (Yes); N (No); YM (Yes, Masked); S (Single Buffered); D (Double Buffered)

Dec(Hex) Bits Default Name Frame

Sync'd Bad

Frame Buffering

AR0134: Register Reference

Detailed Register Descriptions

Aptina Confidential and Proprietary

12468

R0x30B4

15:0 0x0000 tempsens_ctrl (R/W) N N

15:6 X Reserved

5 0x0000 temp_clear_value N N

4 0x0000 temp_start_conversion N N

3:1 0x0000 tempsens_test_ctrl N N

0 0x0000 tempsens_power_on N N

Control register for temp sensor:

Bit[0]: Tempsens power on when set.

Bits [3:1]: Tempsens test ctrl

Bit [4]: Tempsens starts conversion when set

Bit [5]: Tempsens clears value when set.

12476

R0x30BC

15:0 0x0020 green1_gain_cb (R/W) N N D

Digital gain green1 context B

12478

R0x30BE

15:0 0x0020 blue_gain_cb (R/W) N N D

digital gain blue context B

12480

R0x30C0

15:0 0x0020 red_gain_cb (R/W) N N D

digital gain red context B

12482

R0x30C2

15:0 0x0020 green2_gain_cb (R/W) N N D

digital gain green 2 context B

12484

R0x30C4

15:0 0x0020 global_gain_cb (R/W) N N D

global digital gain context B

12486

R0x30C6

15:0 0x0000 tempsens_calib1 (R/W)

This register will read out sensor-specific calibration data. NN

12488

R0x30C8

15:0 0x0000 tempsens_calib2 (R/W)

This register will read out sensor-specific calibration data. NN

12490

R0x30CA

15:0 0x0000 tempsens_calib3 (R/W)

This register is not used. NN

12492

R0x30CC

15:0 0x0000 tempsens_calib4 (R/W)

This register is not used.

12500

R0x30D4

15:0 0xE007 column_correction (R/W) N N

15 0x0001 enable

Enable column correction. NN

0x0001

double_range

Doubles the range of the correction value but halves the

precision.

0x0001

double_samples

Makes the column correction use 128 rows instead of 64. Adds

64 to the minimum frame blanking.

12:4 X Reserved

3:0 0x0007 colcorr_rows

Value showing the number of column correction rows - 1. NN

Table 4: Manufacturer-Specific Register Descriptions (continued)

R/W (Read or Write) bit; RO (Read Only) bit; Y (Yes); N (No); YM (Yes, Masked); S (Single Buffered); D (Double Buffered)

Dec(Hex) Bits Default Name Frame

Sync'd Bad

Frame Buffering

AR0134: Register Reference

Detailed Register Descriptions

Aptina Confidential and Proprietary

12544

R0x3100

15:0 0x0000 ae_ctrl_reg (R/W)

15:7 X Reserved

6:5

0x0000

min_ana_gain

Minimum analog gain to be used by AE.

00:1x (default)

01: 2x

10: 4x

11: 8x

40x0000 auto_dg_en

Automatic control of digital gain by AE is enabled. NN

3:2 X Reserved

10x0000 auto_ag_en

When set, enables the automatic AE control of analog gain. NN

0x0000

ae_enable

1: Enables the on-chip AE algorithm. Auto Exposure also

requires embedded_data_en R0x3064[8] and

embedded_stats_en R0x3064[7] to be set to 1 for proper

operation.

12546

R0x3102

15:0 0x0500 ae_luma_target_reg (R/W) N N

Average luma target value to be reached by the auto exposure

12552

R0x3108

15:0 0x0070 ae_min_ev_step_reg (R/W) N N

Minimum exposure value step size

[15:8]: Reserved

[7:0] : Min_EV_stepsize = (min step size)*256.

Since Min_EV_step sizes are small and they are typically less than 1 e.g. 1/16, 7/16 etc... these are multiplied by 256

and then the value is written to this register.

12554

R0x310A

15:0 0x0008 ae_max_ev_step_reg (R/W) N N

Maximum exposure value step size.

Note that since this value is always greater than 1 there is no need to multiply by 256 as in the case of

min_EV_stepsize.

12556

R0x310C

15:0 0x0200 ae_damp_offset_reg (R/W) N N

Adjusts step size and settling speed.

12558

R0x310E

15:0 0x2000 ae_damp_gain_reg (R/W) N N

Adjusts step size and settling speed.

12560

R0x3110

15:0 0x0140 ae_damp_max_reg (R/W)

Max value allowed for recursiveDamp (multiplied by 256 since internal value is typical <1). For most applications, the

value of recursiveDamp should be <1, otherwise AE will overshoot the target. For applications with fast settling

required, it may be desirable to allow recursiveDamp >1. Default value: 0.875 * 256 = 0x00E0

12572

R0x311C

15:0 0x02A0 ae_max_exposure_reg (R/W) N N

Maximum integration (exposure) time in rows to be used by AE.

12574

R0x311E

15:0 0x0001 ae_min_exposure_reg (R/W)

Minimum integration (exposure) time in rows to be used by AE.

12580

R0x3124

15:0 0x7FFF ae_dark_cur_thresh_reg (R/W)

The dark current level that stops AE from increasing integration time.

Note that increased integration time would increase dark current as well and signal level (SNR) would drop because

photo diode well capacity is limited.

Table 4: Manufacturer-Specific Register Descriptions (continued)

R/W (Read or Write) bit; RO (Read Only) bit; Y (Yes); N (No); YM (Yes, Masked); S (Single Buffered); D (Double Buffered)

Dec(Hex) Bits Default Name Frame

Sync'd Bad

Frame Buffering

AR0134: Register Reference

Detailed Register Descriptions

Aptina Confidential and Proprietary

12586

R0x312A

15:0 0x0020 ae_current_gains (RO)

15:10 X Reserved

9:8

ae_ana_gain

The gain decided by AE, when it is enabled and can control the

analog gain.

7:0

ae_dig_gain

The gain decided by AE, when it is enabled and can control the

digital gain.

Shows the gain settings decided by AE.

12608

R0x3140

15:0 0x0000 ae_roi_x_start_offset (R/W)

Number of pixels into each row before the ROI starts

NOTE: if statistics are being gathered from a scaled image then the 'number of pixels' value must be the number of

scaled pixels

12610

R0x3142

15:0 0x0000 ae_roi_y_start_offset (R/W)

Number of rows into each frame before the ROI starts

12612

R0x3144

15:0 0x0500 ae_roi_x_size (R/W)

Number of columns in the ROI

12614

R0x3146

15:0 0x03C0 ae_roi_y_size (R/W)

Number of rows in the ROI

12626

R0x3152

15:0 0x0000 ae_mean_l (RO)

The true mean of all Gr pixels in the ROI (16 least significant bits)

12644

R0x3164

15:0 0x0000 ae_coarse_integration_time (RO)

The integration time decided by AE.

12646

R0x3166

15:0 0x03DA ae_ag_exposure_hi (R/W)

At this integration time, the analog gain is increased (when AE is enabled to control also the analog gain).

12648

R0x3168

15:0 0x01A3 ae_ag_exposure_lo (R/W) N N

At this integration time, the AE is reduced (when AE is enabled to control the analog gain also),

12680

R0x3188

15:0 0x0000 delta_dk_level (RO) N N

Measured dark current.

12736

R0x31C0

15:0 0x0000 hispi_timing (R/W) N N

Bits [2:0]: DLL delay setting for data lane 0

Bits [5:3]: DLL delay setting for data lane 1

Bits [8:6]: DLL delay setting for data lane 2

Bits [11:9]: DLL delay setting for data lane 3

Bits [14:12]: DLL delay setting for clock lane

The delay setting selects a tap along a delay element. Each stage is 1/8 of a symbol period. When the delay is set to

zero, the delay element is powered down.

Table 4: Manufacturer-Specific Register Descriptions (continued)

R/W (Read or Write) bit; RO (Read Only) bit; Y (Yes); N (No); YM (Yes, Masked); S (Single Buffered); D (Double Buffered)

Dec(Hex) Bits Default Name Frame

Sync'd Bad

Frame Buffering

AR0134: Register Reference

Detailed Register Descriptions

Aptina Confidential and Proprietary

12742

R0x31C6

15:0 0x8000 hispi_control_status (R/W) N N

15:14 RO hispi_status N N

13:10 X Reserved

9:2

0x0000

hispi_control

Bit[2]: Stream mode enable.

Bit[3]: Enable 3 lanes for compressed data

Bit[6:4]: Test mode:

//////////////////////////////////

000: Transmit constant 0 on all enabled data lanes.

001: Transmit constant 1 on all enabled data lanes.

010: Transmit square wave at the half the potential serial data

rate on all the enabled lanes.

011: Transmit square wave at the pixel data rate on all the

enabled lanes.

100: Transmit a continuous, repeated, sequence of pseudo

random data, with no SAV code, copied on all enabled data

lanes.

101: Replace pixel data with a known sequence (PN9), copied

on all the enabled data lanes.

//////////////////////////////////////////

Bit[7]: Test mode enable

Bit[8]: IO test enable

Bit[9]: Frame wide checksum test enable

1:0 X Reserved

12744

R0x31C8

15:0 0xFFFF hispi_crc_0 (RO) NN

12746

R0x31CA

15:0 0xFFFF hispi_crc_1 (RO)

12748

R0x31CC

15:0 0xFFFF hispi_crc_2 (RO) NN

12750

R0x31CE

15:0 0xFFFF hispi_crc_3 (RO)

12754

R0x31D2

15:0 0x0000 stat_frame_id (R/W) NN

12758

R0x31D6

15:0 0xFFFF i2c_wrt_checksum (R/W) N N

Checksum of I2C write operations.

12776

R0x31E8

15:0 0x0000 horizontal_cursor_position (R/W) N N

Specifies the start row for the test cursor.

12778

R0x31EA

15:0 0x0000 vertical_cursor_position (R/W) N N

Specifies the start column for the test cursor.

12780

R0x31EC

15:0 0x0000 horizontal_cursor_width (R/W) N N

Specifies the width, in rows, of the horizontal test cursor. A width of 0 disables the cursor.

12782

R0x31EE

15:0 0x0000 vertical_cursor_width (R/W)

Specifies the width, in columns, of the vertical test cursor. A width of 0 disables the cursor.

12796

R0x31FC

15:0 0x3020 i2c_ids (R/W) N N

I2C addresses.

Table 4: Manufacturer-Specific Register Descriptions (continued)

R/W (Read or Write) bit; RO (Read Only) bit; Y (Yes); N (No); YM (Yes, Masked); S (Single Buffered); D (Double Buffered)

Dec(Hex) Bits Default Name Frame

Sync'd Bad

Frame Buffering

AR0134: Register Reference

Revision History

Aptina Confidential and Proprietary

Revision History

Rev. D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6/12/14

• Updated corporate address on last page

• Deleted lock_control from Table 3, “Manufacturer-Specific Register List,” on page 7

and Table 4, “Manufacturer-Specific Register Descriptions,” on page 12

• Updated descriptions of register field “restart” and “enable_short_llpck” in Table 3,

“Manufacturer-Specific Register List,” on page 7 and Table 4, “Manufacturer-Specific

• Updated description of register field “col_gain_cb” in Table 4.

Rev. C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4/25/13

• Updated to Production

• Updated default values of:

– frame_length_lines

– digital_test

–enable_short_llpck

– revision_number

• Updated description of ae_enable

Rev. B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1/23/13

• Updated to Preliminary

• Updated the default values for:

– revision_number

– reset_register

– digital_test

– tempsens_calib1

– tempsens_calib2

– tempsens_calib3

– tempsens_calib4

• Updated the descriptions for:

– frame_length_lines

–line_length_pck

– show_dark_extra_rows

– show_dark_cols

–enable_short_llpck

– tempsens_calib1

– tempsens_calib2

– tempsens_calib3

– tempsens_calib4

– grouped_parameter_hold

• Added description for bit 10 of R0x30B0

• Updated “Bad Frames” on page 6

180 Clemenceau Avenue, #05-02/04 Haw Par Centre, Singapore 239922 prodmktg@aptina.com www.aptina.com

Aptina, Aptina Imaging, and the Aptina logo are the property of Aptina Imaging Corporation

All other trademarks are the property of their respective owners.

This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered

final, these specifications are subject to change, as further product development and data characterization sometimes occur.

AR0134: Register Reference

Revision History

Aptina Confidential and Proprietary

Revision A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11/2/12

•Initial release

AR0134: Developer Guide

Aptina Confidential and Proprietary

1/3-Inch CMOS Digital Image Sensor

AR0134 Developer Guide, Rev. C

For the latest data sheet, refer to Aptina’s Web site: www.aptina.com

AR0134 Developer Guide

AR0134: Developer Guide

Table of Contents

Aptina Confidential and Proprietary

Table of Contents

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

Optimal Setting Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

Resolution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

Frame Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

Blanking Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

Pixel Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Pixel Array Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Default Readout Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Output Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Readout Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Parallel Output Data Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

LV and FV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

LV Format Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

High Speed Serial Pixel Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

HiSPi Physical Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

DLL Timing Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Frame Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Exposure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Row-Time Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Exposure Indicator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Real-Time Context Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Operational Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Master Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Trigger Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Hard Reset of Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Soft Reset of Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Output Enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

PLL-Generated Master Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Spread-Spectrum Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Stream/Standby Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Soft Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Hard Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Window Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Blanking Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Readout Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Digital Binning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Skipping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Mirror . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Column Mirror Image. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Row Mirror Image . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Maintaining a Constant Frame Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Synchronizing Register Writes to Frame Boundaries. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Restart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Auto Exposure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Auto Exposure Implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

AE Embedded Statistics and Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

AE Target Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

AR0134: Developer Guide

Table of Contents

Aptina Confidential and Proprietary

Exposure Control System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

Auto Exposure Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

AE Frame Synchronization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

Digital Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

Column Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

Black Level Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

Row-wise Noise Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

Column Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Column Correction Triggering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Column Triggering on Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Column Correction Retriggering Due to Mode Change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Test Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

Color Field. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

Vertical Color Bars. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

Walking 1s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

Two-Wire Serial Interface CRC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

Two-Wire Serial Interface Sequential Writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

Reading the Sensor CRA and Chromaticity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

AR0134: Developer Guide

List of Figures

Aptina Confidential and Proprietary

List of Figures

Figure 1: Pixel Array Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Figure 2: Pixel Color Pattern Detail (Top Right Corner) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Figure 3: Imaging a Scene . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Figure 4: Spatial Illustration of Image Readout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Figure 5: Default Pixel Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Figure 6: LV Format Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Figure 7: HiSPi Transmitter and Receiver Interface Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Figure 8: Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Figure 9: Block Diagram of DLL Timing Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Figure 10: Delaying the Clock with Respect to Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Figure 11: Delaying Data with Respect to the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Figure 12: Line Timing and FRAME_VALID/LINE_VALID Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Figure 13: Master Mode Synchronization Waveform #1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Figure 14: Master Mode Synchronization Waveform #2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Figure 15: Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Figure 16: Pulsed Trigger Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Figure 17: Automatic Trigger Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Figure 18: PLL Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Figure 19: Pixel Readout (no skipping) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Figure 20: Pixel Readout (Row Skip 2X Bayer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Figure 21: Pixel Readout (Row Skip 2X Monochrome) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Figure 22: Six Rows in Normal and Row Mirror Readout Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Figure 23: Latency For Single Buffered Registers - Coarse Integration Time Example. . . . . . . . . . . . . . . . . . . . . .35

Figure 24: Latency For Double Buffered Registers - Column Gain Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Figure 25: Latency For Double Buffered Registers - Fine Integration Time Example. . . . . . . . . . . . . . . . . . . . . . .36

Figure 26: Calculating Temperature Sensor Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Figure 27: AE Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Figure 28: AE Stats Calculation Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Figure 29: Frame Format with Embedded Data Lines Enabled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

Figure 30: Embedded Statistics Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

Figure 31: Exposure Control System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

Figure 32: Selecting the ROI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

Figure 33: Automatic Gain Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Figure 34: AE Frame Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

Figure 35: Solid Color . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

Figure 36: Vertical Color Bars . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

Figure 37: Walking 1s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

Figure 38: Checksum Generation Flow Within the Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

Figure 39: Definition of 16-bit CRC Shift Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

AR0134: Developer Guide

List of Tables

Aptina Confidential and Proprietary

List of Tables

Table 1: AR0134 HiSPi Protocol Configuration Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Table 2: Frame Time (Example Based on 1280 x 960, 54 Frames Per Second) . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Table 3: Frame Time: Long Integration Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Table 4: Real-Time Context-Switchable Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Table 5: Exposure Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Table 6: Snapshot Mode Register Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Table 7: Example 1 (With Default Setting for Full Resolution) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Table 8: Example 2 (With Default Settings for 720p) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Table 9: PLL Parameters for the Parallel Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Table 10: Example PLL Configuration for the Parallel Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Table 11: PLL Parameters for the Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Table 12: Example PLL Configurations for the Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Table 13: Skip Mode Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Table 14: Six Pixels in Normal and Column Mirror Readout Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Table 15: Exposure Control Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Table 16: AE Enable Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Table 17: Auto Exposure Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

Table 18: Test Pattern Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

Table 19: CRA Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

AR0134: Developer Guide

Introduction

Aptina Confidential and Proprietary

Introduction

This Developer Guide provides detailed descriptions and usage guidelines for various

features of the AR0134 Global Shutter Sensor. Also provided are guidelines for optimal

settings for various use cases. For detailed electrical and timing specifications or register

descriptions, refer to the AR0134 Data Sheet and the AR0134 Register Reference docu-

ments, respectively.

Optimal Setting Guidelines

The AR0134 Global Shutter Sensor has many built-in features and is capable of many

resolutions and frame rates. Guidelines for setting resolution and frame rate are

provided in this section. Detailed settings for the many features are provided throughout

the remainder of this Developer Guide. Window registers are also provided to enable

context switching. See the section on Real-Time Context Switching and the register

reference guide for more details.

Resolution

Aptina's AR0134 sensor is capable of a maximum resolution of 1280 x 960 at up to 54 fps,

or it may be configured to run 720p at 60fps. Registers y_addr_start, x_addr_start, y_ad-

dr_end, and x_addr_end are used to specify the image window. The minimum value for

x_addr_start is 0 and the maximum value for x_addr_end is 1279. The minimum y_ad-

dr_start and maximum y_addr_end are 0 and 975, respectively.

Frame Rate

Achieving the desired frame rate at the proper resolution is a balancing act between row

timing and the number of rows in the image. Integration time and the pixel clock

frequency are additional factors. The minimum line length is 1388 pixel clocks which

enables a frame rate of 54 fps. When using trigger mode, the minimum line length is

1650 pixel clocks.

Blanking Control

Horizontal blanking and vertical blanking times are controlled by the Line_length_Pck

and Frame_Length_Lines registers, respectively.

• Horizontal blanking is specified in terms of pixel clocks. It is calculated by subtracting

the X window size from the Line_Length_Pck register. The minimum horizontal

blanking time is 108 pixel clocks when the X window is set to 1280. If the X window

size is configured to less than 1280, the sum of the X window size and the horizontal

blanking must be equal to or greater than 1388.

• Vertical blanking is specified in terms of numbers of lines. It is calculated by

subtracting the Y window size from the Frame_Length_Lines register. The minimum

value for vertical blanking is 23 lines.

The actual imager timing is described in the Frame Time section of this Developer

Guide.

AR0134: Developer Guide

Pixel Data Format

Aptina Confidential and Proprietary

Pixel Data Format

Pixel Array Structure

The AR0134 pixel array is configured as 1412 columns by 1028 rows, (see Figure 1). The