8-
/
4-Channel, 24-Bit, Simultaneous Sampling
ADCs with Power Scaling, 110.8 kHz BW
Data Sheet AD7768/AD7768-4
Rev. B Document Feedback
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FEATURES
Precision ac and dc performance
8-/4-channel simultaneous sampling
256 kSPS maximum ADC ODR per channel
108 dB dynamic range
110.8 kHz maximum input bandwidth (−3 dB BW)
−120 dB THD, typical
±2 ppm of full-scale range (FSR) integral nonlinearity
(INL), ±50 μV offset error, ±30 ppm gain error
Optimized power dissipation vs. noise vs. input bandwidth
Selectable power, speed, and input bandwidth
Fast (highest speed): 110.8 kHz BW, 51.5 mW per channel
Median (half speed): 55.4 kHz BW, 27.5 mW per channel
Low power (lowest power): 13.8 kHz BW, 9.375 mW per
channel
Input BW range: dc to 110.8 kHz
Programmable input bandwidth/sampling rates
CRC error checking on data interface
Daisy-chaining
Linear phase digital filter
Low latency sinc5 filter
Wideband brick wall filter: ±0.005 dB ripple to 102.4 kHz
Analog input precharge buffers
Power supply
AVDD1 = 5.0 V, AVDD2 = 2.25 V to 5.0 V
IOVDD = 2.5 V to 3.3 V or IOVDD = 1.8 V
64-lead LQFP package, no exposed pad
Temperature range: −40°C to +105°C
APPLICATIONS
Data acquisition systems: USB/PXI/Ethernet
Instrumentation and industrial control loops
Audio testing and measurement
Vibration and asset condition monitoring
3-phase power quality analysis
Sonar
High precision medical electroencephalogram (EEG)/
electromyography (EMG)/electrocardiogram (ECG)
FUNCTIONAL BLOCK DIAGRAM
ADC
OUTPUT
DATA
SERIAL
INTERFACE
DIGITAL
FILTER
ENGINE
WIDEBAND
LOW RIPPLE
FILTER
SINC5
LOW LATENCY
FILTER
SPI
CONTROL
INTERFACE
1.8V
LDO
SYNC_IN
1.8V
LDO
BUFFERED
VCM
VCM
AIN1+
CH 1
AIN1–
AIN2+
CH 2
AIN2–
AIN3+
CH 3
AIN3–
AIN4+
CH 4*
AIN4–
AIN5+
CH 5*
AIN5–
AIN6+
CH 6*
AIN6–
AIN7+
CH 7*
AIN7–
AIN0+
CH 0
AIN0–
VCM ×8
PRECHARGE
REFERENCE
BUFFERS
SYNC_OUT
START
RESET
FORMAT1*
FORMAT0
DRDY
DCLK
ST0/CS
PIN/SPI
ST1*/SCLK
DEC0/SDO
DEC1/SDI
AVSS XTAL2/MCLK XTAL1 MODE3/GPIO3
TO
MODE0/GPIO0
FILTER/GPIO4
Σ-∆
ADC
Σ-∆
ADC
Σ-∆
ADC
Σ-∆
ADC
Σ-∆
ADC
Σ-∆
ADC
Σ-∆
ADC
Σ-∆
ADC
DOUT7*
AVDD1A,
AVDD1B DGND
AD7768/AD7768-4
IOVDD DREGCAP
REGCAPA,
REGCAPB
A
VDD2A,
AVDD2B
REFx+ REFx–
OFFSET,
GAIN PHASE
CORRECTION
OFFSET,
GAIN PHASE
CORRECTION
OFFSET,
GAIN PHASE
CORRECTION
OFFSET,
GAIN PHASE
CORRECTION
OFFSET,
GAIN PHASE
CORRECTION
OFFSET,
GAIN PHASE
CORRECTION
OFFSET,
GAIN PHASE
CORRECTION
OFFSET,
GAIN PHASE
CORRECTION
DOUT1
14001-001
DOUT0
DOUT2
DOUT3
DOUT4*
DOUT5*
DOUT6*, DIN
*THESE CHANNELS/PINS EXIST ONLY ON THE AD7768.
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
×16 ANALOG INPUT
PRECHARGE BUFFERS (P)
Figure 1.
AD7768/AD7768-4 Data Sheet
Rev. B | Page 2 of 105
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 3
General Description ......................................................................... 5
Specifications ..................................................................................... 6
1.8 V IOVDD Specifications ..................................................... 13
Timing Specifications ................................................................ 17
1.8 V IOVDD Timing Specifications ....................................... 18
Absolute Maximum Ratings .......................................................... 22
Thermal Resistance .................................................................... 22
ESD Caution ................................................................................ 22
Pin Configurations and Function Descriptions ......................... 23
Typical Performance Characteristics ........................................... 31
Terminology .................................................................................... 41
Theory of Operation ...................................................................... 42
Clocking, Sampling Tree, and Power Scaling ............................. 42
Noise Performance and Resolution .......................................... 43
Applications Information .............................................................. 45
Power Supplies ............................................................................ 46
Device Configuration ................................................................ 47
Pin Control .................................................................................. 47
SPI Control .................................................................................. 50
SPI Control Functionality ......................................................... 51
SPI Control Mode Extra Diagnostic Features ........................ 54
Circuit Information ........................................................................ 55
Core Signal Chain ....................................................................... 55
Analog Inputs .............................................................................. 56
VCM ............................................................................................. 58
Reference Input ........................................................................... 58
Clock Selection ........................................................................... 58
Digital Filtering ........................................................................... 58
Decimation Rate Control .......................................................... 62
Antialiasing ................................................................................. 62
Calibration ................................................................................... 64
Data Interface .................................................................................. 66
Setting the Format of Data Output .......................................... 66
ADC Conversion Output: Header and Data .......................... 67
Functionality ................................................................................... 77
GPIO Functionality .................................................................... 77
AD7768 Register Map Details (SPI Control) .............................. 78
AD7768 Register Map................................................................ 78
Channel Standby Register ......................................................... 80
Channel Mode A Register ......................................................... 80
Channel Mode B Register ......................................................... 81
Channel Mode Select Register .................................................. 81
Power Mode Select Register ...................................................... 82
General Device Configuration Register .................................. 83
Data Control: Soft Reset, Sync, and Single-Shot Control
Register ........................................................................................ 83
Interface Configuration Register .............................................. 84
Digital Filter RAM Built In Self Test (BIST) Register............ 85
Status Register ............................................................................. 85
Revision Identification Register ............................................... 85
GPIO Control Register .............................................................. 86
GPIO Write Data Register ......................................................... 86
GPIO Read Data Register .......................................................... 87
Analog Input Precharge Buffer Enable Register Channel 0 to
Channel 3 .................................................................................... 87
Analog Input Precharge Buffer Enable Register Channel 4 to
Channel 7 .................................................................................... 87
Positive Reference Precharge Buffer Enable Register ............ 88
Negative Reference Precharge Buffer Enable Register .......... 88
Offset Registers ........................................................................... 89
Gain Registers ............................................................................. 89
Sync Phase Offset Registers ...................................................... 90
ADC Diagnostic Receive Select Register ................................ 90
ADC Diagnostic Control Register ........................................... 91
Modulator Delay Control Register ........................................... 91
Chopping Control Register ....................................................... 91
AD7768-4 Register Map Details (SPI Control) .......................... 92
AD7768-4 Register Map ............................................................ 92
Channel Standby Register ......................................................... 94
Channel Mode A Register ......................................................... 94
Channel Mode B Register ......................................................... 95
Channel Mode Select Register .................................................. 95
Power Mode Select Register ...................................................... 95
General Device Configuration Register .................................. 96
Data Control: Soft Reset, Sync, and Single-Shot Control
Register ........................................................................................ 97
Interface Configuration Register .............................................. 97
Data Sheet AD7768/AD7768-4
Rev. B | Page 3 of 105
Digital Filter RAM Built In Self Test (BIST) Register ............ 98
Status Register .............................................................................. 98
Revision Identification Register ................................................ 99
GPIO Control Register ............................................................... 99
GPIO Write Data Register ...................................................... 100
GPIO Read Data Register ....................................................... 100
Analog Input Precharge Buffer Enable Register Channel 0
and Channel 1 ........................................................................... 100
Analog Input Precharge Buffer Enable Register Channel 2
and Channel 3 ........................................................................... 101
Positive Reference Precharge Buffer Enable Register .......... 101
Negative Reference Precharge Buffer Enable Register ......... 101
Offset Registers .......................................................................... 102
Gain Registers ............................................................................ 102
Sync Phase Offset Registers ..................................................... 102
ADC Diagnostic Receive Select Register ............................... 102
ADC Diagnostic Control Register .......................................... 103
Modulator Delay Control Register ......................................... 104
Chopping Control Register ...................................................... 104
Outline Dimensions ...................................................................... 105
Ordering Guide ......................................................................... 105
REVISION HISTORY
7/2018—Rev. A to Rev. B
Changed Eco Mode to Low Power Mode .................. Throughout
Changes to General Description Section ....................................... 5
Changes to Table 1 ............................................................................ 6
Changes to Table 9 .......................................................................... 24
Changes to Table 10 ........................................................................ 28
Changes to Figure 73 ...................................................................... 45
Changes to MCLK Source Selection Section ............................... 53
Changes to Analog Inputs Section ................................................ 56
Added Figure 87 and Table 28; Renumbered Sequentially ........ 57
Changes to Table 27 ........................................................................ 57
Added Figure 88 .............................................................................. 58
Added Filter Settling Time Section ............................................... 59
Moved Table 29 ................................................................................ 60
Moved Table 30 ................................................................................ 61
Changes to Modulator Saturation Point Section ........................ 64
Added Figure 94 .............................................................................. 64
Changes to Data Interface: Standard Conversion Operation
Section .............................................................................................. 68
Added Figure 102 ............................................................................ 69
Added Figure 106 ............................................................................ 71
Changes to Daisy-Chaining Section and Synchronization
Section .............................................................................................. 73
Changes to CRC Check on Data Interface Section ..................... 74
Added Table 38 ................................................................................ 74
Changes to Table 43 ........................................................................ 81
Change to Analog Input Precharge Buffer Enable Register
Channel 0 to Channel 3 Section and Analog Input Precharge
Buffer Enable Register Channel 4 to Channel 7 Section................. 85
Change to Analog Input Precharge Buffer Enable Register
Channel 0 and Channel 1 Section ................................................. 98
Change to Analog Input Precharge Buffer Enable Register
Channel 2 and Channel 3 ............................................................... 99
3/2016—Rev. 0 to Rev. A
Added AD7768-4 ............................................................... Universal
Changed Precharge Analog Input Reference to Analog Input
Precharge ........................................................................ Throughout
Changes to General Description Section ....................................... 5
Changes to Table 1 ............................................................................ 6
Changes to Table 2 .......................................................................... 12
Changes to Table 3 and t30 Parameter, Table 4 ............................. 16
Changes to Table 5 .......................................................................... 17
Changes to t30 Parameter, Table 6 and Figure 2 ........................... 18
Changes to Figure 4 and Figure 7 ................................................. 19
Changes to Figure 8 and Figure 9 ................................................. 20
Changes to Figure 10 and Table 9 ................................................. 22
Added Figure 11 and Table 10; Renumbered Sequentially ........ 26
Changes to Typical Performance Characteristics Section ......... 30
Changes to Theory of Operation Section and Clocking,
Sampling Tree, and Power Scaling Section .................................. 41
Changes to Table 11 ........................................................................ 42
Added Example of Power vs. Noise Performance Optimization
Section and Clocking Out the ADC Conversion Results
(DCLK) Section ............................................................................... 42
Changes to Applications Information Section and Figure 73 ... 44
Changes to Table 14 and Power Supplies Section ....................... 45
Moved 1.8 V IOVDD Operation Section .................................... 46
Changes to Figure 75, Analog Supply Internal Connectivity
Section, and Pin Control Section .................................................. 46
Added Figure 76 .............................................................................. 47
Changes to Channel Standby Section and Accessing the ADC
Register Map Section ...................................................................... 49
Added Table 22 ................................................................................ 49
Changes to Channel Configuration Section ................................ 50
Changes to Channel Modes Section, Reset over SPI Control
Interface Section, Sleep Mode Section, and Channel Standby
Section .............................................................................................. 51
Changes to MCLK Source Selection Section, Interface
Configuration Section, and ADC Synchronization over SPI
Section .............................................................................................. 52
Added Figure 81 .............................................................................. 52
Changes to RAM Built In Self Test Section ................................. 53
Changes to Analog Inputs Section and Figure 85 ....................... 55
Added Figure 86 .............................................................................. 55
Added Table 27 ................................................................................ 56
AD7768/AD7768-4 Data Sheet
Rev. B | Page 4 of 105
Changes to VCM Section, Reference Input Section, and Digital
Filtering Section .............................................................................. 56
Changes to Figure 87, Figure 88, and Figure 89 ......................... 57
Changes to Antialiasing Section and Modulator Sampling
Frequency Section .......................................................................... 58
Changes to Modulator Chopping Frequency Section and
Table 29, and Modulator Saturation Point Section, ................... 59
Changes to Sync Phase Offset Adjustment Section ................... 60
Changes to Setting the Format of Data Output Section ............ 61
Added Table 32 and Figure 93 ...................................................... 61
Changes to Figure 94 Caption and ADC Conversion Output:
Header and Data Section ............................................................... 62
Changes to Data Interface: Standard Conversion Operation
Section .............................................................................................. 63
Changes to Figure 99 ...................................................................... 64
Added Figure 100 ........................................................................... 64
Added Figure 101 ........................................................................... 65
Changes to Daisy-Chaining Section and Figure 104 ................. 66
Added Figure 105 ........................................................................... 67
Changes to CRC Check on Data Interface Section .................... 68
Changes to Table 35 ........................................................................ 69
Changes to Table 36 ........................................................................ 70
Changes to GPIO Functionality Section and Figure 108 .......... 71
Added Figure 109 ........................................................................... 71
Changes to AD7768 Register Map Details (SPI Control) Section
and Table 37 .................................................................................... 72
Changes to Channel Standby Register Section ........................... 74
Changes to Table 42 and Table 43 ................................................ 76
Changes to Table 44 ....................................................................... 77
Changes to Table 45 and Table 46 ................................................ 78
Changes to Table 49 ....................................................................... 79
Changes to Table 61 ....................................................................... 85
Added AD7768-4 Register Map Details (SPI Control) Section and
Table 63 ...................................................................................................... 86
Added Table 64 and Table 65 ................................................................. 88
Added Table 66, Table 67, and Table 68 ............................................... 89
Added Table 69 ......................................................................................... 90
Added Table 70 and Table 71 ................................................................. 91
Added Table 72 and Table 73 ................................................................. 92
Added Table 74 and Table 75 ................................................................. 93
Added Table 76, Table 77, and Table 78 ............................................... 94
Added Table 79, Table 80, and Table 81 ............................................... 95
Added Table 82, Table 83, Table 84, and Table 85 .............................. 96
Added Table 86 and Table 87 ................................................................. 97
Added Table 88 ......................................................................................... 98
Changes to Ordering Guide ................................................................... 99
1/2016—Revision 0: Initial Version
Data Sheet AD7768/AD7768-4
Rev. B | Page 5 of 105
GENERAL DESCRIPTION
The AD7768/AD7768-4 are 8-channel and 4-channel,
simultaneous sampling sigma-delta (Σ-) analog-to-digital
converters (ADCs), respectively, with a Σ- modulator and digital
filter per channel, enabling synchronized sampling of ac and dc
signals.
The AD7768/AD7768-4 achieve 108 dB dynamic range at a
maximum input bandwidth of 110.8 kHz, combined with typical
performance of ±2 ppm integral nonlinearity (INL), ±50 µV
offset error, and ±30 ppm gain error.
The AD7768/AD7768-4 user can trade off input bandwidth,
output data rate, and power dissipation, and select one of three
power modes to optimize for noise targets and power consum-
ption. The flexibility of the AD7768/AD7768-4 allows them to
become reusable platforms for low power dc and high
performance ac measurement modules.
The AD7768/AD7768-4 have three modes: fast mode (256 kSPS
maximum, 110.8 kHz input bandwidth, 51.5 mW per channel),
median mode (128 kSPS maximum, 55.4 kHz input bandwidth,
27.5 mW per channel) and low power mode (32 kSPS maximum,
13.8 kHz input bandwidth, 9.375 mW per channel).
The AD7768/AD7768-4 offer extensive digital filtering
capabilities, such as a wideband, low ±0.005 dB pass-band
ripple, antialiasing low-pass filter with sharp roll-off, and
105 dB attenuation at the Nyquist frequency.
Frequency domain measurements can use the wideband linear
phase filter. This filter has a flat pass band (±0.005 dB ripple)
from dc to 102.4 kHz at 256 kSPS, from dc to 51.2 kHz at
128 kSPS, or from dc to 12.8 kHz at 32 kSPS.
The AD7768/AD7768-4 also offer sinc response via a sinc5
filter, a low latency path for low bandwidth, and low noise
measurements. The wideband and sinc5 filters can be selected
and run on a per channel basis.
Within these filter options, the user can improve the dynamic
range by selecting from decimation rates of ×32, ×64, ×128,
×256, ×512, and ×1024. The ability to vary the decimation
filtering optimizes noise performance to the required input
bandwidth.
Embedded analog functionality on each ADC channel makes
design easier, such as a precharge buffer on each analog input
that reduces analog input current and a precharge reference
buffer per channel reduces input current and glitches on the
reference input terminals.
The device operates with a 5 V AVDD1A and AVDD1B supply,
a 2.25 V to 5.0 V AVDD2A and AVDD2B supply, and a 2.5 V to
3.3 V or 1.8 V IOVDD supply (see the 1.8 V IOVDD Operation
section for specific requirements for operating at 1.8 V IOVDD).
The device requires an external reference; the absolute input
reference voltage range is 1 V to AVDD1 − AVSS.
For the purposes of clarity in this data sheet, the AVDD1A and
AVDD1B supplies are referred to as AVDD1 and the AVDD2A and
AVDD2B supplies are referred to as AVDD2. For the negative
supplies, AVSS refers to the AVSS1A, AVSS1B, AVSS2A,
AVSS2B, and AVSS pins.
The specified operating temperature range is −40°C to +105°C.
The device is housed in a 10 mm × 10 mm 64-lead LQFP package
with a 12 mm × 12 mm printed circuit board (PCB) footprint.
Throughout this data sheet, multifunction pins, such as
XTAL2/MCLK, are referred to either by the entire pin name or
by a single function of the pin, for example MCLK, when only
that function is relevant.
AD7768/AD7768-4 Data Sheet
Rev. B | Page 6 of 105
SPECIFICATIONS
AVDD1A = AVDD1B = 4.5 V to 5.5 V, AVDD2A = AVDD2B = 2.0 V to 5.5 V, IOVDD = 2.25 V to 3.6 V, AVSS = DGND = 0 V, REFx+ =
4.096 V and REFx− = 0 V, MCLK = 32.768 MHz, analog input precharge buffers on, reference precharge buffers off, wideband filter, fCHOP =
fMOD/32, TA = −40°C to +105°C, unless otherwise noted. See Table 2 for specifications at 1.8 V IOVDD.
Table 1.
Parameter Test Conditions/Comments Min Typ Max Unit
ADC SPEED AND PERFORMANCE
Output Data Rate (ODR), per
Channel1
Fast mode 8 256 kSPS
Median mode 4 128 kSPS
Low power mode 1 32 kSPS
−3 dB Bandwidth (BW) Fast mode, wideband filter 110.8 kHz
Median mode, wideband filter 55.4 kHz
Low power mode, wideband filter 13.8 kHz
Data Output Coding Twos complement, MSB first
No Missing Codes2 24 Bits
DYNAMIC PERFORMANCE
Fast Mode Decimation by 32, 256 kSPS ODR
Dynamic Range Shorted input, wideband filter 106.2 108 dB
Signal-to-Noise Ratio (SNR) 1 kHz, −0.5 dBFS, sine wave input
Sinc5 filter 109 111 dB
Wideband filter 106 107.8 dB
Signal-to-Noise-and-
Distortion Ratio (SINAD)
1 kHz, −0.5 dBFS, sine wave input 104.7 107.5 dB
Total Harmonic Distortion
(THD)
1 kHz, −0.5 dBFS, sine wave input −120 −107 dB
Spurious-Free Dynamic
Range (SFDR)
128 dBc
Median Mode Decimation by 32, 128 kHz ODR
Dynamic Range Shorted input, wideband filter 106.2 108 dB
SNR Sinc5 filter, 1 kHz, −0.5 dBFS, sine wave
input
109 111 dB
Wideband filter, 1 kHz, −0.5 dBFS, sine
wave input
106 107.8 dB
SINAD 1 kHz, −0.5 dBFS, sine wave input 105.8 107.5 dB
THD 1 kHz, −0.5 dBFS, sine wave input −120 −113 dB
SFDR 128 dBc
Low Power Mode Decimation by 32, 32 kHz ODR
Dynamic Range Shorted input, wideband filter 106.2 108 dB
SNR Sinc5 filter, 1 kHz, −0.5 dBFS, sine wave
input
109 111 dB
Wideband filter, 1 kHz, −0.5 dBFS, sine
wave input
106 107.8 dB
SINAD 1 kHz, −0.5 dBFS, sine wave input 105.8 107.5 dB
THD 1 kHz, −0.5 dBFS, sine wave input −120 −113 dB
SFDR 128 dBc
INTERMODULATON DISTORTION
(IMD)3
fINA = 9.7 kHz, fINB = 10.3 kHz
Second order −125 dB
Third order −125 dB
Data Sheet AD7768/AD7768-4
Rev. B | Page 7 of 105
Parameter Test Conditions/Comments Min Typ Max Unit
ACCURACY
INL Endpoint method ±2 ±7 ppm of FSR
Offset Error4 DCLK frequency ≤ 24 MHz ±50 ±115 µV
24 MHz to 32.768 MHz DCLK frequency2 ±75 ±150 µV
Offset Error Drift DCLK frequency ≤ 24 MHz ±250 nV/°C
24 MHz to 32.768 MHz DCLK frequency ±750 nV/°C
Gain Error4 T
A = 25°C ±30 ±70 ppm of FSR
Gain Drift vs. Temperature2 ±0.5 ±1 ppm/°C
VCM PIN
Output With respect to AVSS (AVDD1 −
AVSS)/2
V
Load Regulation VOUT/IL 400 µV/mA
Voltage Regulation Applies to the following VCM output
options only: VCM = VOUT/(AVDD1 −
AVSS)/2; VCM = 1.65 V; and VCM = 2.5 V
5 µV/V
Short-Circuit Current 30 mA
ANALOG INPUTS See the Analog Inputs section
Differential Input Voltage Range VREF = (REFx+) − (REFx−) −VREF +VREF V
Input Common-Mode Range2 AVSS AVDD1 V
Absolute Analog Input
Voltage Limits2
AVSS AVDD1 V
Analog Input Current
Unbuffered Differential component ±48 µA/V
Common-mode component ±17 µA/V
Precharge Buffer On5 −20 µA
Input Current Drift
Unbuffered ±5 nA/V/°C
Precharge Buffer On ±31 nA/°C
EXTERNAL REFERENCE
Reference Voltage VREF = (REFx+) − (REFx−) 1 AVDD1 − AVSS V
Absolute Reference Voltage
Limits2
Precharge reference buffers off AVSS − 0.05 AVDD1 + 0.05 V
Precharge reference buffer on AVSS AVDD1 V
Average Reference Current Fast mode; see Figure 63
Precharge reference buffers off ±72 µA/V/channel
Precharge reference buffers on ±16 µA/V/channel
Average Reference Current Drift Fast mode; see Figure 63
Precharge reference buffers off ±1.7 nA/V/°C
Precharge reference buffers on ±49 nA/V/°C
Common-Mode Rejection 95 dB
DIGITAL FILTER RESPONSE
Low Ripple Wideband Filter FILTER = 0
Decimation Rate Up to six selectable decimation rates 32 1024
Group Delay Latency 34/ODR sec
Settling Time Complete settling 68/ODR sec
Pass-Band Ripple2 From dc to 102.4 kHz at 256 kSPS ±0.005 dB
Pass Band ±0.005 dB bandwidth 0.4 × ODR Hz
−0.1 dB bandwidth 0.409 × ODR Hz
−3 dB bandwidth 0.433 × ODR Hz
Stop Band Frequency Attenuation > 105 dB 0.499 × ODR Hz
Stop Band Attenuation 105 dB
AD7768/AD7768-4 Data Sheet
Rev. B | Page 8 of 105
Parameter Test Conditions/Comments Min Typ Max Unit
Sinc5 Filter FILTER = 1
Decimation Rate Up to six selectable decimation rates 32 1024
Group Delay Latency 3/ODR sec
Settling Time Complete settling 7/ODR sec
Pass Band −3 dB bandwidth 0.204 × ODR Hz
REJECTION
AC Power Supply Rejection
Ratio (PSRR)
VIN = 0.1 V, AVDD1 = 5 V, AVDD2 = 5 V,
IOVDD = 2.5 V
AVDD1 90 dB
AVDD2 100 dB
IOVDD 75 dB
DC PSRR VIN = 1 V
AVDD1 100 dB
AVDD2 118 dB
IOVDD 90 dB
Analog Input Common-Mode
Rejection Ratio (CMRR)
DC VIN = 0.1 V 95 dB
AC Up to 10 kHz 95 dB
Crosstalk −0.5 dBFS input on adjacent channels −120 dB
CLOCK See the Clocking Selections section for
performance functionality
Crystal Frequency 8 32.768 34 MHz
External Clock (MCLK) 32.768 MHz
Duty Cycle 50:50 %
MCLK Pulse Width2
Logic Low 12.2 ns
Logic High 12.2 ns
CMOS Clock Input Voltage See the Logic Inputs parameter
High, VINH
Low, VINL
LVDS Clock2 R
L = 100 Ω
Differential Input Voltage 100 650 mV
Common-Mode Input
Voltage
800 1575 mV
Absolute Input Voltage 1.88 V
ADC RESET2
ADC Start-Up Time After Reset6 Time to first DRDY, fast mode, decimation
by 32
1.58 1.66 ms
Minimum RESET Low Pulse
Width
tMCLK = 1/MCLK 2 × tMCLK
LOGIC INPUTS
Input Voltage2
High, VINH 0.65 ×
IOVDD
V
Low, VINL 0.7 V
Hysteresis2 0.04 0.09 V
Leakage Current −10 +0.03 +10 µA
RESET pin7 −10 +10 µA
Data Sheet AD7768/AD7768-4
Rev. B | Page 9 of 105
Parameter Test Conditions/Comments Min Typ Max Unit
LOGIC OUTPUTS See Table 2 for 1.8 V operation
Output Voltage2
High, VOH I
SOURCE = 200 A 0.8 × IOVDD V
Low, VOL I
SINK = 400 µA 0.4 V
Leakage Current Floating state −10 +10 µA
Output Capacitance Floating state 10 pF
SYSTEM CALIBRATION2
Full-Scale Calibration Limit 1.05 × VREF V
Zero-Scale Calibration Limit −1.05 × VREF V
Input Span 0.4 × VREF 2.1 × VREF V
POWER REQUIREMENTS
Power Supply Voltage
AVDD1 − AVSS 4.5 5.0 5.5 V
AVDD2 − AVSS 2.0 2.25 to 5.0 5.5 V
AVSS − DGND −2.75 0 V
IOVDD − DGND See Table 2 for 1.8 V operation 2.25 2.5 to 3.3 3.6 V
POWER SUPPLY CURRENTS Maximum output data rate, CMOS MCLK,
eight DOUTx signals, all supplies at
maximum voltages, all channels in
Channel Mode A
AD7768 Eight channels active
Fast Mode
AVDD1 Current Precharge reference buffers off/on 36/57.5 40/64 mA
AVDD2 Current 37.5 40 mA
IOVDD Current Wideband filter 63 67 mA
Sinc5 filter 27 29 mA
Median Mode
AVDD1 Current Precharge reference buffers off/on 18.5/29 20.5/32.5 mA
AVDD2 Current 21.3 23 mA
IOVDD Current Wideband filter 34 37 mA
Sinc5 filter 16 18 mA
Low Power Mode
AVDD1 Current Precharge reference buffers off/on 5.1/8 5.8/9 mA
AVDD2 Current 9.3 10.1 mA
IOVDD Current Wideband filter 12.5 13.7 mA
Sinc5 filter 8 9 mA
AD7768-4 Four channels active
Fast Mode
AVDD1 Current Precharge reference buffers off/on 18.2/28.8 20.3/32.5 mA
AVDD2 Current 18.8 20.3 mA
IOVDD Current Wideband filter2 43.5 46.8 mA
Wideband filter, SPI mode only;
Channel Mode A set to sinc5 filter8
37 40 mA
Sinc5 filter2 17 18.6 mA
Median Mode
AVDD1 Current Reference precharge buffers off/on 9.3/14.7 10.5/16.6 mA
AVDD2 Current 10.7 11.7 mA
IOVDD Current Wideband filter2 24.4 26.4 mA
Wideband filter, SPI mode only;
Channel Mode A set to sinc5 filter8
21 23 mA
Sinc5 filter2 11 12.3 mA
AD7768/AD7768-4 Data Sheet
Rev. B | Page 10 of 105
Parameter Test Conditions/Comments Min Typ Max Unit
Low Power Mode
AVDD1 Current Precharge reference buffers off/on 2.7/4.1 3.1/4.7 mA
AVDD2 Current 4.7 5.3 mA
IOVDD Current Wideband filter2 10 11.1 mA
Wideband filter, SPI mode only;
Channel Mode A set to sinc5 filter8
9 10 mA
Sinc5 filter2 6.5 7.6 mA
AD7768 and AD7768-4—Two
Channels Active2
Serial peripheral interface (SPI) control
mode only; see the Channel Standby
section for details on disabling channels
Fast Mode
AVDD1 Current Precharge reference buffers off/on 9.3/14.7 10.5/16.6 mA
AVDD2 Current 9.5 10.5 mA
IOVDD Current Wideband filter 33.7 36.3 mA
Wideband filter; disabled channels in
Channel Mode A, and set to sinc5 filter
mode8
23.4 25.5 mA
Sinc5 filter 11.9 13.3 mA
Median Mode
AVDD1 Current Precharge reference buffers off/on 4.8/7.5 5.5/8.6 mA
AVDD2 Current 5.5 6.2 mA
IOVDD Current Wideband filter 19.4 21.1 mA
Wideband filter; disabled channels in
Channel Mode A, and set to sinc5 filter
mode8
14.1 15.5 mA
Sinc5 filter 8.5 9.6 mA
Low Power Mode
AVDD1 Current Precharge reference buffers off/on 1.52/2.2 1.77/2.6 mA
AVDD2 Current 2.4 3 mA
IOVDD Current Wideband filter 8.6 9.7 mA
Wideband filter; disabled channels in
Channel Mode A, and set to sinc5 filter
mode8
7.2 8 mA
Sinc5 filter 5.8 6.7 mA
Standby Mode All channels disabled (sinc5 filter enabled) 6.5 8 mA
Sleep Mode2 Full power-down (SPI control mode only) 0.73 1.2 mA
Crystal Excitation Current Extra current in IOVDD when using an
external crystal compared to using the
CMOS MCLK
540 µA
POWER DISSIPATION External CMOS MCLK, all channels
active, MCLK = 32.768 MHz, all channels
in Channel Mode A except where
otherwise specified
Full Operating Mode Analog precharge buffers on
AD7768
Wideband Filter
Fast Mode AVDD1 = 5 V, AVDD2 = IOVDD = 2.5 V,
precharge reference buffers off2
412 446 mW
AVDD1 = 5 V, AVDD2 = IOVDD = 3.3 V,
precharge reference buffers on2
600 645 mW
AVDD1 = 5.5 V, AVDD2 = 5.5 V, IOVDD =
3.6 V, precharge reference buffers off
631 681 mW
Data Sheet AD7768/AD7768-4
Rev. B | Page 11 of 105
Parameter Test Conditions/Comments Min Typ Max Unit
Median Mode AVDD1 = 5 V, AVDD2 = IOVDD = 2.5 V,
precharge reference buffers off2
220 240 mW
AVDD1 = 5 V, AVDD2 = IOVDD = 3.3 V,
precharge reference buffers on2
320 345 mW
AVDD1 = 5.5 V, AVDD2 = 5.5 V, IOVDD =
3.6 V, precharge reference buffers off
341 372 mW
Low Power Mode AVDD1 = 5 V, AVDD2 = IOVDD = 2.5 V,
precharge reference buffers off2
75 85 mW
AVDD1 = 5 V, AVDD2 = IOVDD = 3.3 V,
precharge reference buffers on2
107 118 mW
AVDD1 = 5.5 V, AVDD2 = 5.5 V, IOVDD =
3.6 V, precharge reference buffers off
124 137 mW
Sinc5 Filter
Fast Mode AVDD1 = 5 V, AVDD2 = IOVDD = 2.5 V,
precharge reference buffers off2
325 355 mW
AVDD1 = 5 V, AVDD2 = IOVDD = 3.3 V,
precharge reference buffers on2
475 525 mW
AVDD1 = 5.5 V, AVDD2 = 5.5 V, IOVDD =
3.6 V, precharge reference buffers off
501 545 mW
Median Mode AVDD1 = 5 V, AVDD2 = IOVDD = 2.5 V,
precharge reference buffers off2
175 195 mW
AVDD1 = 5 V, AVDD2 = IOVDD = 3.3 V,
precharge reference buffers on2
260 285 mW
AVDD1 = 5.5 V, AVDD2 = 5.5 V, IOVDD =
3.6 V, precharge reference buffers off
277 304 mW
Low Power Mode AVDD1 = 5 V, AVDD2 = IOVDD = 2.5 V,
precharge reference buffers off2
65 72 mW
AVDD1 = 5 V, AVDD2 = IOVDD = 3.3 V,
precharge reference buffers on2
95 105 mW
AVDD1 = 5.5 V, AVDD2 = 5.5 V, IOVDD =
3.6 V, precharge reference buffers off
108 120 mW
AD7768-4
Wideband Filter
Fast Mode AVDD1 = 5 V, AVDD2 = IOVDD = 2.5 V,
precharge reference buffers off
235 mW
AVDD1 = 5 V, AVDD2 = IOVDD = 3.3 V,
precharge reference buffers on
336 mW
AVDD1 = 5.5 V, AVDD2 = 5.5 V, IOVDD =
3.6 V, precharge reference buffers off2
360 392 mW
SPI mode only; AVDD1 = 5.5 V, AVDD2 =
5.5 V, IOVDD = 3.6 V, precharge reference
buffers off, Channel Mode A set to sinc5
filter8
337 368 mW
Median Mode AVDD1 = 5 V, AVDD2 = IOVDD = 2.5 V,
precharge reference buffers off
127 mW
AVDD1 = 5 V, AVDD2 = IOVDD = 3.3 V,
precharge reference buffers on
181 mW
AVDD1 = 5.5 V, AVDD2 = 5.5 V, IOVDD =
3.6 V, precharge reference buffers off2
198 218 mW
SPI mode only; AVDD1 = 5.5 V, AVDD2 =
5.5 V, IOVDD = 3.6 V, precharge reference
buffers off, Channel Mode A set to sinc5
filter8
186 205 mW
AD7768/AD7768-4 Data Sheet
Rev. B | Page 12 of 105
Parameter Test Conditions/Comments Min Typ Max Unit
Low Power Mode AVDD1 = 5 V, AVDD2 = IOVDD = 2.5 V,
precharge reference buffers off
49 mW
AVDD1 = 5 V, AVDD2 = IOVDD = 3.3 V,
precharge reference buffers on
66 mW
AVDD1 = 5.5 V, AVDD2 = 5.5 V, IOVDD =
3.6 V, precharge reference buffers off2
77 87 mW
SPI mode only; AVDD1 = 5.5 V, AVDD2 =
5.5 V, IOVDD = 3.6 V, precharge reference
buffers off, Channel Mode A set to sinc5
filter8
73 83 mW
Sinc5 Filter
Fast Mode AVDD1 = 5 V, AVDD2 = IOVDD = 2.5 V,
precharge reference buffers off
168 mW
AVDD1 = 5 V, AVDD2 = IOVDD = 3.3 V,
precharge reference buffers on
248 mW
AVDD1 = 5.5 V, AVDD2 = 5.5 V, IOVDD =
3.6 V, precharge reference buffers off
265 291 mW
Median Mode AVDD1 = 5 V, AVDD2 = IOVDD = 2.5 V,
precharge reference buffers off
94 mW
AVDD1 = 5 V, AVDD2 = IOVDD = 3.3 V,
precharge reference buffers on
137 mW
AVDD1 = 5.5 V, AVDD2 = 5.5 V, IOVDD =
3.6 V, precharge reference buffers off
150 167 mW
Low Power Mode AVDD1 = 5 V, AVDD2 = IOVDD = 2.5 V,
precharge reference buffers off
40 mW
AVDD1 = 5 V, AVDD2 = IOVDD = 3.3 V,
precharge reference buffers on
55 mW
AVDD1 = 5.5 V, AVDD2 = 5.5 V, IOVDD =
3.6 V, precharge reference buffers off
64 74 mW
Standby Mode All channels disabled (sinc5 filter enabled),
AVDD1 = 5 V, AVDD2 = IOVDD = 2.5 V2
18 mW
AVDD1 = 5 V, AVDD2 = IOVDD = 3.3 V2 26 mW
AVDD1 = AVDD2 = 5.5 V, IOVDD = 3.6 V 29 mW
Sleep Mode2 Full power-down (SPI control mode),
AVDD1 = 5 V, AVDD2 = IOVDD = 2.5 V
1.8 4 mW
AVDD1 = 5 V, AVDD2 = IOVDD = 3.3 V 2.5 5 mW
AVDD1 = AVDD2 = 5.5 V, IOVDD = 3.6 V 2.7 6.5 mW
1 The output data rate ranges refer to the programmable decimation rates available on the AD7768/AD7668-4 for a fixed MCLK rate of 32.768 MHz. Varying MCLK rates
allow users a wider variation of ODR.
2 These specifications are not production tested but are supported by characterization data at initial product release.
3 See the Terminology section for more information about the fa and fb input frequencies.
4 Following a system zero-scale calibration, the offset error is in the order of the noise for the programmed output data rate selected. A system full-scale calibration
reduces the gain error to the order of the noise for the programmed output data rate.
5 −25 µA is measured when the analog input is close to either the AVDD1 or AVSS rail. The input current reduces as the common-mode voltage approaches (AVDD1 −
AVSS)/2. The analog input current scales with the MCLK frequency and device power mode. See Figure 85 and Figure 86 for more details on how the analog input
current scales with input voltage.
6 For lower MCLK rates or higher decimation rates, use Table 28 and Table 29 to calculate any additional delay before the first DRDYE pulse.
7 The RESETE pin has an internal pull-up device to IOVDD.
8 Configuring Channel Mode A to the sinc5 filter and/or assigning disabled channels to Channel Mode A allows a lower power consumption to be achieved. To do this,
the user must be operating in SPI control mode because it requires assigning channels to different channel modes (only possible in SPI control mode). If using pin
control mode, all channels, whether active or in standby, are assigned to the same channel group and use the same filter type. This means that, in pin control mode, a
higher current consumption is seen from disabled channels than can be achieved in SPI mode. See the Channel Modes section for more details.
Data Sheet AD7768/AD7768-4
Rev. B | Page 13 of 105
1.8 V IOVDD SPECIFICATIONS
AVDD1A = AVDD1B = 4.5 V to 5.5 V, AVDD2A = AVDD2B = 2.0 V to 5.5 V, IOVDD = 1.72 V to 1.88 V, AVSS = DGND = 0 V, REFx+ =
4.096 V and REFx− = 0 V, MCLK = 32.76 8 MHz, analog precharge buffers on, reference precharge buffers off, wideband filter, fCHOP =
fMOD/32, TA = −40°C to +105°C, unless otherwise noted.
Table 2.
Parameter Test Conditions/Comments Min Typ Max Unit
DYNAMIC PERFORMANCE For dynamic range and SNR across all decimation
rates, see Table 12 and Table 13
Fast Mode Decimation by 32, 256 kSPS ODR
Dynamic Range Shorted input, wideband filter 106.2 108 dB
SNR Sinc5 filter, 1 kHz, −0.5 dBFS, sine wave input 109 111 dB
Wideband filter, 1 kHz, −0.5 dBFS, sine wave input 106 107.8 dB
SINAD1 1 kHz, −0.5 dBFS, sine wave input 103.8 107.5 dB
THD 1 kHz, −0.5 dBFS, sine wave input −120 −107 dB
SFDR 128 dBc
Median Mode Decimation by 32, 128 kHz ODR
Dynamic Range Shorted input, wideband filter 106.2 108 dB
SNR 1 kHz, −0.5 dBFS, sine wave input
Sinc5 filter 109 111 dB
Wideband filter 106 107.8 dB
SINAD 1 kHz, −0.5 dBFS, sine wave input 105.8 107.5 dB
THD 1 kHz, −0.5 dBFS, sine wave input −120 −113 dB
SFDR 128 dBc
Low Power Mode Decimation by 32, 32 kHz ODR
Dynamic Range Shorted input, wideband filter 106.2 108 dB
SNR Sinc5 filter, 1 kHz, −0.5 dBFS, sine wave input 109 111 dB
Wideband filter, 1 kHz, −0.5 dBFS, sine wave input 106 107.8 dB
SINAD 1 kHz, −0.5 dBFS, sine wave input 105.8 107.5 dB
THD 1 kHz, −0.5 dBFS, sine wave input −120 −113 dB
SFDR 128 dBc
ACCURACY1
INL Endpoint method ±2 ±7 ppm of
FSR
Offset Error2 DCLK frequency ≤ 24 MHz ±50 ±115 µV
24 MHz to 32.768 MHz DCLK frequency ±75 ±170 µV
Offset Error Drift DCLK frequency ≤ 24 MHz ±250 nV/°C
24 MHz to 32.768 MHz DCLK frequency ±750 nV/°C
Gain Error2 T
A = 25°C ±60 ±120 ppm/FSR
Gain Drift vs. Temperature ±0.5 ±2 ppm/°C
LOGIC INPUTS
Input Voltage1
High, VINH 0.65 × IOVDD V
Low, VINL 0.4 V
Hysteresis1 0.04 0.2 V
Leakage Current −10 +0.03 +10 µA
RESETE pin −10 +10 µA
LOGIC OUTPUTS
Output Voltage1
High, VOH I
SOURCE = 200 µA 0.8 × IOVDD V
Low, VOL I
SINK = 400 µA 0.4 V
Leakage Current Floating state −10 +10 µA
Output Capacitance Floating state 10 pF
AD7768/AD7768-4 Data Sheet
Rev. B | Page 14 of 105
Parameter Test Conditions/Comments Min Typ Max Unit
POWER REQUIREMENTS
Power Supply Voltage
AVDD1 − AVSS 4.5 5.0 5.5 V
AVDD2 − AVSS 2.0 2.25 to 5.0 5.5 V
AVSS − DGND −2.75 0 V
IOVDD − DGND DREGCAP shorted to IOVDD 1.72 1.8 1.88 V
POWER SUPPLY CURRENTS1 Maximum output data rate, CMOS MCLK, eight DOUTx
signals, all supplies at maximum voltages, all channels in
Channel Mode A except where otherwise specified
AD7768 Eight channels active
Fast Mode
AVDD1 Current Reference precharge buffers off/on 36/57.5 40/64 mA
AVDD2 Current 37.5 40 mA
IOVDD Current Wideband filter 63 69 mA
Sinc5 filter 26 28.4 mA
Median Mode
AVDD1 Current Reference precharge buffers off/on 18.5/29 20.5/32.5 mA
AVDD2 Current 21.3 23 mA
IOVDD Current Wideband filter 34 36.8 mA
Sinc5 filter 15 16.8 mA
Low Power Mode
AVDD1 Current Reference precharge buffers off/on 5.1/8 5.8/9 mA
AVDD2 Current 9.3 10.1 mA
IOVDD Current Wideband filter 11.6 12.9 mA
Sinc5 filter 7 8.1 mA
AD7768-4 Four channels active
Fast Mode
AVDD1 Current Reference precharge buffers off/on 18.2/28.8 20.3/32.5 mA
AVDD2 Current 18.8 20.3 mA
IOVDD Current Wideband filter 43.9 47.7 mA
Wideband filter, SPI mode only; Channel Mode A set
to sinc5 filter3
36.8 41 mA
Sinc5 filter 16 17.7 mA
Median Mode
AVDD1 Current Reference precharge buffers off/on 9.3/14.7 10.5/16.6 mA
AVDD2 Current 10.7 11.7 mA
IOVDD Current Wideband filter 24 26.1 mA
Wideband filter, SPI mode only; Channel Mode A set
to sinc5 filter3
20.4 22.7 mA
Sinc5 filter 10 11.3 mA
Low Power Mode
AVDD1 Current Reference precharge buffers off/on 2.7/4.1 3.1/4.7 mA
AVDD2 Current 4.7 5.3 mA
IOVDD Current Wideband filter 9 10.2 mA
Wideband filter, SPI mode only; Channel Mode A set
to sinc5 filter3
8.1 9.2 mA
Sinc5 filter 5.5 6.5 mA
Data Sheet AD7768/AD7768-4
Rev. B | Page 15 of 105
Parameter Test Conditions/Comments Min Typ Max Unit
AD7768 and AD7768-4—
Two Channels Active
SPI control mode only; see the Channel Standby section
for details on disabling channels
Fast Mode
AVDD1 Current Reference precharge buffers off/on 9.3/14.7 10.5/16.6 mA
AVDD2 Current 9.5 10.5 mA
IOVDD Current Wideband filter 33.8 36.7 mA
Wideband filter, SPI mode only; disabled channels in
Channel Mode A, and set to sinc5 filter3
23.1 25.6 mA
Sinc5 filter 11 12.3 mA
Median Mode
AVDD1 Current Reference precharge buffers off/on 4.8/7.5 5.5/8.6 mA
AVDD2 Current 5.5 6.2 mA
IOVDD Current Wideband filter 18.9 20.6 mA
Wideband filter, SPI mode only; disabled channels in
Channel Mode A, and set to sinc5 filter3
13.4 15.1 mA
Sinc5 filter 7.4 8.6 mA
Low Power Mode
AVDD1 Current Precharge reference buffers off/on 1.52/2.2 1.77/2.6 mA
AVDD2 Current 2.4 3 mA
IOVDD Current Wideband filter 7.6 8.8 mA
Wideband filter, SPI mode only; disabled channels in
Channel Mode A, and set to sinc5 filter3
6.3 7.2 mA
Sinc5 filter 4.8 5.8 mA
Standby Mode All channels disabled (sinc5 filter enabled) 6.5 8 mA
Sleep Mode Full power-down (SPI control mode) 0.73 1.2 mA
Crystal Excitation Current Extra current in IOVDD when using an external crystal
compared to using the CMOS MCLK
540 µA
POWER DISSIPATION1 External CMOS MCLK, all channels active, AVDD1 =
AVDD2 = 5.5 V, IOVDD = 1.88 V, MCLK = 32.768 MHz, all
channels in Channel Mode A except where otherwise
noted
Full Operating Mode Analog precharge buffers on
AD7768 Eight channels active
Wideband Filter
Fast Mode Reference precharge buffers off 524 571 mW
Reference precharge buffers on 638 704 mW
Median Mode Reference precharge buffers off 284 309 mW
Reference precharge buffers on 342 375 mW
Low Power Mode Reference precharge buffers off 98.5 109 mW
Reference precharge buffers on 118 130 mW
Sinc5 Filter
Fast Mode Reference precharge buffers off 455 495 mW
Median Mode Reference precharge buffers off 248 271 mW
Low Power Mode Reference precharge buffers off 94 105 mW
AD7768/AD7768-4 Data Sheet
Rev. B | Page 16 of 105
Parameter Test Conditions/Comments Min Typ Max Unit
AD7768-4 Four channels active
Wideband Filter
Fast Mode Reference precharge buffers off 287 314 mW
Reference precharge buffers on 345 381 mW
Median Mode Reference precharge buffers off 156 172 mW
Reference precharge buffers on 185 206 mW
Low Power Mode Reference precharge buffers off 58 66 mW
Reference precharge buffers on 66 75 mW
Sinc5 Filter
Fast Mode Reference precharge buffers off 234 257 mW
Median Mode Reference precharge buffers off 129 144 mW
Low Power Mode Reference precharge buffers off 51 59 mW
Standby Mode All channels disabled (sinc5 filter enabled) 17 mW
Sleep Mode Full power-down (SPI control mode) 1.5 4.5 mW
1 These specifications are not production tested but are supported by characterization data at initial product release.
2 Following a system zero-scale calibration, the offset error is in the order of the noise for the programmed output data rate selected. A system full-scale calibration
reduces the gain error to the order of the noise for the programmed output data rate.
3 This configuration of setting Channel Mode A to the sinc5 filter and/or assigning disabled channels to Channel Mode A allows a lower power consumption to be
achieved due to the disabling of internal clocks on the disabled only and sinc5 only channel modes. This configuration requires assigning sinc5 and wideband filters to
different channels, or channel modes, and is only available in SPI control mode. In pin control mode, all channels, whether active or in standby, effectively use the
same channel mode. See the Channel Modes section for more details.
Data Sheet AD7768/AD7768-4
Rev. B | Page 17 of 105
TIMING SPECIFICATIONS
AVDD1A = AVDD1B = 5 V, AVDD2A = AVDD2B = 5 V, IOVDD = 2.25 V to 3.6 V, Input Logic 0 = DGND, Input Logic 1 = IOVDD;
CLOAD = 10 pF on the DCLK pin, CLOAD = 20 pF on the other digital outputs; REFx+ = 4.096 V, TA = −40°C to +105°C. See Table 5 and
Table 6 for timing specifications at 1.8 V IOVDD.
Table 3. Data Interface Timing1
Parameter Description Test Conditions/Comments Min Typ Max Unit
MCLK Master clock 1.15 34 MHz
fMOD Modulator frequency Fast mode MCLK/4 Hz
Median mode MCLK/8 Hz
Low power mode MCLK/32 Hz
t1 DRDY high time tDCLK = t8 + t9 t
DCLK − 10% 28 ns
t2 DCLK rising edge to DRDY rising edge 2 ns
t3 DCLK rising to DRDY falling −3.5 0 ns
t4 DCLK rise to DOUTx valid 1.5 ns
t5 DCLK rise to DOUTx invalid −3 ns
t6 DOUTx valid to DCLK falling 9.5 tDCLK/2 ns
t7 DCLK falling edge to DOUTx invalid 9.5 tDCLK/2 ns
t8 DCLK high time, DCLK = MCLK/1 50:50 CMOS clock tDCLK/2 tDCLK/2 (tDCLK/2) + 5 ns
t
8a = DCLK = MCLK/2 tMCLK = 1/MCLK tMCLK ns
t
8b = DCLK = MCLK/4 2 × tMCLK ns
t
8c = DCLK = MCLK/8 4 × tMCLK ns
t9 DCLK low time DCLK = MCLK/1 50:50 CMOS clock (tDCLK/2) − 5 tMCLK/2 tDCLK/2 ns
t
9a = DCLK = MCLK/2 tMCLK ns
t
9b = DCLK = MCLK/4 2 × tMCLK ns
t
9c = DCLK = MCLK/8 4 × tMCLK ns
t10 MCLK rising to DCLK rising CMOS clock 30 ns
t11 Setup time (daisy-chain inputs) DOUT6 and DOUT7 on the AD7768,
DIN on the AD7768-4
14 ns
t12 Hold time (daisy-chain inputs) DOUT6 and DOUT7 on the AD7768,
DIN on the AD7768-4
0 ns
t13 START low time 1 × tMCLK ns
t14 MCLK to SYNC_OUT valid CMOS clock
SYNC_OUT RETIME_EN bit disabled;
measured from falling edge of MCLK
4.5 22 ns
SYNC_OUT RETIME_EN bit enabled;
measured from rising edge of MCLK
9.5 27.5 ns
t15 SYNC_IN setup time CMOS clock 0 ns
t16 SYNC_IN hold time CMOS clock 10 ns
1 These specifications are not production tested but are supported by characterization data at initial product release.
Table 4. SPI Control Interface Timing1
Parameter Description Test Conditions/Comments Min Typ Max Unit
t17 SCLK period 100 ns
t18 CS falling edge to SCLK rising edge 26.5 ns
t19 SCLK falling edge to CS rising edge 27 ns
t20 CS falling edge to data output enable 22.5 40.5 ns
t21 SCLK high time 20 50 ns
t22 SCLK low time 20 50 ns
t23 SCLK falling edge to SDO valid 15 ns
t24 SDO hold time after SCLK falling 7 ns
t25 SDI setup time 0 ns
t26 SDI hold time 6 ns
t27 SCLK enable time 0 ns
AD7768/AD7768-4 Data Sheet
Rev. B | Page 18 of 105
Parameter Description Test Conditions/Comments Min Typ Max Unit
t28 SCLK disable time 0 ns
t29 CS high time 10 ns
t30 CS low time fMOD = MCLK/4 1.1 × tMCLK ns
f
MOD = MCLK/8 2.2 × tMCLK ns
f
MOD = MCLK/32 8.8 × tMCLK ns
1 These specifications are not production tested but are supported by characterization data at initial product release.
1.8 V IOVDD TIMING SPECIFICATIONS
AVDD1A = AVDD1B = 5 V, AVDD2A = AVDD2B = 5 V, IOVDD = 1.72 V to 1.88 V (DREGCAP tied to IOVDD), Input Logic 0 =
DGND, Input Logic 1 = IOVDD, CLOAD = 10 pF on DCLK pin, CLOAD = 20 pF on other digital outputs, TA = −40°C to +105°C.
Table 5. Data Interface Timing1
Parameter Description Test Conditions/Comments Min Typ Max Unit
MCLK Master clock 1.15 34 MHz
fMOD Modulator frequency Fast mode MCLK/4 Hz
Median mode MCLK/8 Hz
Low power mode MCLK/32 Hz
t1 DRDY high time t
DCLK − 10% 28 ns
t2 DCLK rising edge to DRDY rising edge 2 ns
t3 DCLK rising to DRDY falling −4.5 0 ns
t4 DCLK rise to DOUTx valid 2.0 ns
t5 DCLK rise to DOUTx invalid −4 ns
t6 DOUTx valid to DCLK falling 8.5 tDCLK/2 ns
t7 DCLK falling edge to DOUTx invalid 8.5 tDCLK/2 ns
t8 DCLK high time, DCLK = MCLK/1 50:50 CMOS clock tDCLK/2 tDCLK/2 (tDCLK/2) + 5 ns
t
8a = DCLK = MCLK/2 tMCLK ns
t
8b = DCLK = MCLK/4 2 × tMCLK ns
t
8c = DCLK = MCLK/8 4 × tMCLK ns
t9 DCLK low time DCLK=MCLK/1 50:50 CMOS clock (tDCLK/2) − 5 tMCLK/2 (tDCLK/2 ns
t
9a = DCLK = MCLK/2 tMCLK ns
t
9b = DCLK = MCLK/4 2 × tMCLK ns
t
9c = DCLK = MCLK/8 4 × tMCLK ns
t10 MCLK rising to DCLK rising CMOS clock 37 ns
t11 Setup time (daisy-chain inputs) DOUT6 and DOUT7 on the
AD7768, DIN on the AD7768-4
14 ns
t12 Hold time (daisy-chain inputs) DOUT6 and DOUT7 on the
AD7768, DIN on the AD7768-4
0 ns
t13 START low time 1 × tMCLK ns
t14 MCLK to SYNC_OUT valid CMOS clock
SYNC_OUT RETIME_EN bit
disabled; measured from falling
edge of MCLK
10 31 ns
SYNC_OUT RETIME_EN bit
enabled; measured from rising
edge of MCLK
15 37 ns
t15 SYNC_IN setup time CMOS clock 0 ns
t16 SYNC_IN hold time CMOS clock 11 ns
1 These specifications are not production tested but are supported by characterization data at initial product release.
Data Sheet AD7768/AD7768-4
Rev. B | Page 19 of 105
Table 6. SPI Control Interface Timing1
Parameter Description Test Conditions/Comments Min Typ Max Unit
t17 SCLK period 100 ns
t18 CS falling edge to SCLK rising edge 31.5 ns
t19 SCLK falling edge to CS rising edge 30 ns
t20 CS falling edge to data output enable 29 54 ns
t21 SCLK high time 20 50 ns
t22 SCLK low time 20 50 ns
t23 SCLK falling edge to SDO valid 16 ns
t24 SDO hold time after SCLK falling 7 ns
t25 SDI setup time 0 ns
t26 SDI hold time 10 ns
t27 SCLK enable time 0 ns
t28 SCLK disable time 0 ns
t29 CS high time 10 ns
t30 CS low time fMOD = MCLK/4 1.1 × tMCLK ns
f
MOD = MCLK/8 2.2 × tMCLK ns
f
MOD = MCLK/32 8.8 × tMCLK ns
1 These specifications are not production tested but are supported by characterization data at initial product release.
Timing Diagrams
DRDY
DCLK
LSB LSBMSBDOUTx
t
1
t
ODR
t
7
t
6
t
5
t
4
t
3
t
2
t
8
t
9
14001-002
Figure 2. Data Interface Timing Diagram
t
8a
t
8b
t
9a
MCLK
DCLK = MCLK/2
DCLK = MCLK/4
DCLK = MCLK/8
t
10
t
9b
t
8c
t
9c
14001-003
Figure 3. MCLK to DCLK Divider Timing Diagram
AD7768/AD7768-4 Data Sheet
Rev. B | Page 20 of 105
t
11
t
ODR
t
12
DRDY
DCLK
DOUT6
AND
DOUT7
14001-004
Figure 4. Daisy-Chain Setup and Hold Timing Diagram
t
13
t
14
MCLK
START
S
YNC_OUT
14001-005
Figure 5. Asynchronous START and SYNC_OUT Timing Diagram
t
16
t
15
MCLK
SYNC_IN
t
15
14001-006
Figure 6. Synchronous SYNC_IN
E
Pulse Timing Diagram
CS
S
CL
K
SDO MSB
t
18
t
17
t
21
t
30
t
22
t
23
t
24
t
20
t
19
14001-007
Figure 7. SPI Serial Read Timing Diagram
Data Sheet AD7768/AD7768-4
Rev. B | Page 21 of 105
CS
SCLK
SDI MSB LSB
t
18
t
25
t
26
14001-008
t
30
Figure 8. SPI Serial Write Timing Diagram
CS
S
CL
K
t28
t29
t27
14001-009
Figure 9. SCLK Enable and Disable Timing Diagram
AD7768/AD7768-4 Data Sheet
Rev. B | Page 22 of 105
ABSOLUTE MAXIMUM RATINGS
Table 7.
Parameter Rating
AVDD1, AVDD2 to AVSS1 −0.3 V to +6.5 V
AVDD1 to DGND −0.3 V to +6.5 V
IOVDD to DGND −0.3 V to +6.5 V
IOVDD, DREGCAP to DGND (IOVDD Tied
to DREGCAP for 1.8 V Operation)
−0.3 V to +2.25 V
IOVDD to AVSS −0.3 V to +7.5 V
AVSS to DGND −3.25 V to +0.3 V
Analog Input Voltage to AVSS −0.3 V to AVDD1 + 0.3 V
Reference Input Voltage to AVSS −0.3 V to AVDD1 + 0.3 V
Digital Input Voltage to DGND −0.3 V to IOVDD + 0.3 V
Digital Output Voltage to DGND −0.3 V to IOVDD + 0.3 V
Operating Temperature Range −40°C to +105°C
Storage Temperature Range −65°C to +150°C
Pb-Free Temperature, Soldering
Reflow (10 sec to 30 sec)
260°C
Maximum Junction Temperature 150°C
Maximum Package Classification
Temperature
260°C
1 Transient currents of up to 100 mA do not cause silicon controlled rectifier
(SCR) latch-up.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
Thermal performance is directly linked to PCB design and
operating environment. Careful attention to PCB thermal
design is required.
Table 8. Thermal Resistance
Package Type θJA θ
JC Unit JEDEC Board Layers
ST-64-2 38 9.2 °C/W 2P2S1
1 2P2S is a JEDEC standard PCB configuration per JEDEC Standard JESD51-7.
ESD CAUTION