24-bit Capacitance to Digital Converter with Temperature Sensor AD7745/AD7746 Preliminary Technical Data FEATURES GENERAL DESCRIPTION Capacitance to Digital Converter (CDC) Standard One Chip Solution Interfaces to Single or Differential Floating Sensors Resolution: 20 aF (i.e. 19-bit) at 16.6 Hz Accuracy: 2 fF Linearity: 0.01% Input Range: 4 pF Offset / Common Capacitance Removal: up to 17 pF Update rate: 5 Hz to 90 Hz Simultaneous 50 Hz and 60 Hz rejection at 16.6 Hz Tolerant of ground capacitance and ground leakage current Temperature sensor on chip Resolution: 0.1C, accuracy: 2C Voltage input channel Internal clock oscillator 2-Wire Serial Interface (I2C(R)-Compatible) Power 2.7 V to 5.25 V Single-Supply Operation 1 mA Current Consumption Operating temperature: -40C to +125C Package: 16-lead TSSOP The AD7745/AD7746 is a high-resolution - capacitance to digital converter (CDC). The capacitance to be measured is connected directly to the device inputs. The architecture features inherent high resolution (24-bit no missing codes, 19-bit effective resolution at 16.6 Hz data rate), high linearity (0.01%) and high accuracy (2 fF factory calibrated). The AD7745/AD7746 capacitance input range is 4 pF (changing), while it can accept up to 17 pF absolute capacitance (not changing), which is compensated by an on-chip digital to capacitance converter (CAPDAC). The AD7745 has one capacitance input channel, while the AD7746 has two channels. Each channel can be configured as single ended or differential. The AD7745/AD7746 is designed for floating capacitive sensors. For capacitive sensors with one plate connected to ground, the AD7747 is recommended. The parts have an on-chip temperature sensor with resolution of 0.1C and accuracy of 2C. The on-chip voltage reference and the on-chip clock generator eliminate the need for any external components in most capacitive sensor applications. The parts have a standard voltage input, which together with the differential reference input allows easy interface to an external temperature sensor, such as an RTD, thermistor or diode. APPLICATIONS Automotive, Industrial and Medical Systems for: Pressure Measurement Position Sensors Level Sensors Flowmeters Humidity Sensors Impurity Detection The AD7745/AD7746 has a 2-wire, I2C compatible serial interface. Both parts operate from a single 3 V or 5 V power supply. They are specified over the automotive temperature range of -40C to +125C and are housed in a 16-lead TSSOP package. FUNCTIONAL BLOCK DIAGRAMS VDD TEMP SENSOR CLOCK GENERATOR VDD VIN(+) VIN(-) MUX CIN1(+) CIN1(-) 24-BIT - MODULATOR TEMP SENSOR AD7745 DIGITAL FILTER I2C SERIAL INTERFACE SDA VIN(+) VIN(-) SCL CIN1(+) CIN1(-) CLOCK GENERATOR MUX 24-BIT - MODULATOR AD7746 DIGITAL FILTER I2C SERIAL INTERFACE SDA SCL CIN2(+) CIN2(-) CONTROL LOGIC CALIBRATION CAP DAC RDY CAP DAC CAP DAC EXCA CONTROL LOGIC CALIBRATION CAP DAC VOLTAGE REFERENCE EXCITATION EXC1 VOLTAGE REFERENCE EXCITATION EXC2 EXCB REFIN(+) REFIN(-) GND Figure 1. REFIN(+) REFIN(-) GND Figure 2. Rev. PrF, 3. March 2005 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2005 Analog Devices, Inc. All rights reserved. RDY Preliminary Technical Data AD7745/AD7746 TABLE OF CONTENTS AD7745/AD7746--PRELIMINARY SPECIFICATIONS........... 3 Timing Specifications....................................................................... 5 Absolute Maximum Ratings............................................................ 5 Output Noise and Resolution SpecificationS................................ 6 Pin Configuration and Function Descriptions............................. 7 SERIAL INTERFACE....................................................................... 8 Write Operation............................................................................ 8 Read Operation............................................................................. 8 General Call................................................................................... 9 AD7745/AD7746 Reset ............................................................... 9 REGISTER DESCRIPTIONS........................................................ 10 Status Register............................................................................. 11 Cap Data Register....................................................................... 11 VT Data Register ........................................................................ 11 Cap Setup Register ..................................................................... 12 VT Setup Register....................................................................... 12 Exc Setup Register ...................................................................... 13 Configuration Register .............................................................. 14 Cap DAC A Register................................................................... 15 Cap DAC B Register................................................................... 15 Cap Offset Register..................................................................... 15 Cap Gain Register....................................................................... 15 Volt Gain Register....................................................................... 15 Typical Application Diagram ........................................................ 16 Outline Dimensions ....................................................................... 17 ESD Caution................................................................................ 17 Rev. PrF | Page 2 of 17 Preliminary Technical Data AD7745/AD7746 AD7745/AD7746--PRELIMINARY SPECIFICATIONS Table 1. (VDD = 2.7 V to 3.3 V, or 4.75V to 5.25V, GND = 0 V, -40C to +125C, unless otherwise noted.) Parameter CAPACITIVE INPUT (INPUTS) Conversion Input Range Integral Nonlinearity (INL) 1 No-missing Codes 1 Resolution p-p Resolution effective Output Noise rms Absolute Error 2 Offset Error Offset Drift vs. Temperature Gain Error Gain Drift vs. Temperature 1 Allowed Capacitance to GND 1 Power Supply Rejection Conversion Time CAPDAC Full Range Resolution 3 Drift vs. Temperature 1 EXCITATION Frequency Voltage across Capacitance Min Max 4.096 0.01 24 16.5 19 5 2 -29 32 -1 0.02 -27 -25 60 500 11.0 17 Average DC Voltage across Capac. Allowed Capacitance to GND 1 TEMPERATURE SENSOR 4 Resolution Error 1 VOLTAGE INPUT 4 Differential VIN Voltage Range Absolute VIN Voltage Integral Nonlinearity (INL) 1 No-missing Codes 1 Resolution p-p Output Noise Offset Error Offset Drift vs. Temperature Full-Scale Error 5 Full-Scale Drift vs. Temperature Average VIN Input Current Analog VIN Input Current Drift Power Supply Rejection Power Supply Rejection Common-Mode Rejection Conversion Time Typ 217.3 Test Conditions/Comments pF % of FSR bit bit bit aF/Hz fF Factory calibrated aF aF/C % of FS ppm of FS/C pF aF/V ms 21 164 +27 pF fF ppm of FS/C 32 VDD /8 VDD /4 VDD x 3/8 VDD /2 < 50 100 kHz V V V V mV pF 2 4 C C C 0.1 0.5 2 VREF GND -0.03 VDD +0.03 15 5 24 16 3 3 15 TBD 0.5 400 50 90 80 90 20.1 Unit 122.1 Rev. PrF | Page 3 of 17 V V ppm of FSR Bit bits V rms V nV/C V ppm of FSR/C nA/V pA/V/C dB dB dB ms 62ms conversion time 62ms conversion time 62ms conversion time 62ms conversion time 25C, after offset calibration 62ms conversion time After system offset calibration Configurable via digital interface 7-bit CAPDAC Exc. setup register bit CLKCTRL = 0 Configurable via digital interface Internal temperature sensor External sensing diode 62ms conversion time 62ms conversion time 62ms conversion time External reference External reference Internal reference Configurable via Digital Interface Preliminary Technical Data AD7745/AD7746 Parameter INTERNAL VOLTAGE REFERENCE Voltage Drift vs. Temperature EXTERNAL VOLTAGE REFERENCE INPUT Differential REFIN Voltage 1 Absolute REFIN Voltage Average REFIN Input Current Average REFIN Input Current Drift Min Typ Max Unit Test Conditions/Comments 1.168 1.17 10 1.172 V ppm/C At VDD = 4V, TA = 25C 0.1 GND -0.03 2.5 VDD VDD +0.03 V V nA/V pA/V/C 400 50 SERIAL INTERFACE LOGIC INPUTS (SCL, SDA) VIH Input High Voltage VIL Input Low Voltage Hysteresis OPEN-DRAIN OUTPUT (SDA) VOL Output Low Voltage 2.1 IDD Current IDD Current Power Down Mode V V mV 0.4 V 1 A ISINK = -6.0 mA VOUT = VDD 0.4 V V V V ISINK = 1.6 mA, VDD = 5 V ISOURCE = 200 A, VDD = 5 V ISINK = 100 A, VDD = 3 V ISOURCE = 100 A, VDD = 3 V V V mA A VDD = 5 V nominal VDD = 3 V nominal Digital inputs equal to VDD or GND Digital inputs equal to VDD or GND 150 IOH Output High Leakage Current LOGIC OUTPUT (RDY) VOL Output Low Voltage VOH Output High Voltage VOL Output Low Voltage VOH Output High Voltage POWER REQUIREMENTS VDD to GND Voltage 0.8 0.1 4.0 0.4 DVDD - 0.6 4.75 2.7 5.25 3.3 1 1 1 Specification is not production tested, but is supported by characterization data at initial product release. Factory calibrated The absolute error includes factory gain calibration error, integral nonlinearity error, and offset error after system offset calibration, all at 25C. At different temperatures, compensation for gain drift over temperature is required. 3 The CAPDAC resolution is 7-bit in the actual CAPDAC full range. Using the on-chip offset calibration or adjusting the capacitive offset calibration register can further reduce the CIN offset or the non-changing CIN component. 4 The VTCHOP bit in the VT SETUP register must be set to 1 for the specified temperature sensor and voltage input performance. 5 Full-scale error applies to both positive and negative full-scale. 2 Rev. PrF | Page 4 of 17 Preliminary Technical Data AD7745/AD7746 TIMING SPECIFICATIONS Table 2. (VDD = 2.7 V to 3.3 V, or 4.75V to 5.25V, GND = 0 V; Input Logic 0 = 0 V; Input Logic 1 = VDD; -40C to +125C, unless otherwise noted.) Parameter SERIAL INTERFACE1, 2 SCL Frequency SCL High Pulse Width, tHIGH SCL Low Pulse Width, tLOW SCL, SDA Rise Time, tR SCL, SDA Fall Time, tF Hold Time (Start Condition), tHD;STA Setup Time (Start Condition), tSU;STA Data Setup Time, tSU;DAT Setup Time (Stop Condition), tSU;STO Data Hold Time, tHD;DAT (Master) Bus Free Time (Between Stop and Start Condition, tBUF 1 2 Min 0 0.6 1.3 Typ Max Unit 400 kHz s s s s s s s s s s 0.3 0.3 0.6 0.6 0.1 0.6 0 1.3 Test Conditions/Comments See Figure 3 After this period, the first clock is generated Relevant for repeated start condition Sample tested during initial release to ensure compliance. All input signals are specified with input rise/fall times = 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs. Output load = 10 pF. tLOW tR tF tHD:STA SCL tHIGH tHD:DAT tSU:STA tSU:DAT tSU:STO SDA tBUF P S S P 04918-0-002 tHD:STA Figure 3.Serial Interface Timing Diagram ABSOLUTE MAXIMUM RATINGS Table 3. (TA = 25C, unless otherwise noted.) Parameter Positive Supply Voltage VDD to GND Rating -0.3 V to +6.5 V Voltage on any input or output pin to GND ESD Rating (ESD Association Human Body Model, S5.1) Operating Temperature Range Storage Temperature Range Junction Temperature -0.3 V to VDD + 0.3 V TBD V -40C to +125C -65C to +150C 150C 128 C/W TSSOP Package JA Thermal Impedance to Air TSSOP Package JC Thermal Impedance to Case Lead Temperature, Soldering Vapor Phase (60 sec) Infrared (15 sec) 14 C/W 215C 220C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. PrF | Page 5 of 17 Preliminary Technical Data AD7745/AD7746 OUTPUT NOISE AND RESOLUTION SPECIFICATIONS The AD7745/46 resolution is limited by noise. The noise performance varies with the selected conversion time. The Table 4 and Table 5 show typical noise performance and resolution for the capacitive channel. These numbers were generated from 1000 data samples acquired in continuous conversion mode, VDD = 5.0V, all CIN and EXC pins open circuit. RMS noise represents standard deviation, p-p noise represents difference between minimum and maximum result in the data. Effective resolution is calculated from RMS noise, p-p resolution is calculated from p-p noise. Table 4. Typical Capacitive Input Noise and Resolution versus Conversion Time, CAP CHOP = 0 Conversion Time (ms) Output Data Rate (Hz) RMS Noise (aF) P-P Noise (aF) Effective Resolution (Bits) P-P Resolution (Bits) 11.0 11.9 20.0 38.0 62.0 77.0 92.0 109.6 90.9 83.8 50.0 26.3 16.1 13.0 10.9 9.1 40.0 27.3 12.2 7.3 5.4 4.9 4.4 4.4 212.4 137.7 82.5 50.3 33.7 28.3 27.8 27.3 17.6 18.2 19.4 20.1 20.5 20.7 20.8 20.8 15.2 15.9 16.6 17.3 17.9 18.1 18.2 18.2 Table 5. Typical Capacitive Input Noise and Resolution versus Conversion Time, CAP CHOP = 1 Conversion Time (ms) Output Data Rate (Hz) RMS Noise (aF) P-P Noise (aF) Effective Resolution (Bits) P-P Resolution (Bits) 20.1 22.0 38.1 74.1 122.1 152.1 182.1 217.3 49.8 45.6 26.3 13.5 8.2 6.6 5.5 4.6 31.7 24.9 9.8 4.9 3.9 3.4 2.9 2.9 159.2 118.2 63.0 31.7 26.4 21.5 18.6 18.6 18.0 18.3 19.7 20.7 21.0 21.2 21.4 21.4 15.7 16.1 17.0 18.0 18.2 18.5 18.8 18.8 Rev. PrF | Page 6 of 17 Preliminary Technical Data AD7745/AD7746 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SCL 1 16 SDA SCL 1 16 SDA RDY 2 15 NC RDY 2 15 NC EXCA 3 14 VDD EXCA 3 14 VDD EXCB 4 AD7745 13 GND EXCB 4 AD7746 13 GND REFIN(+) 5 TOP VIEW (Not to Scale) 12 VIN(-) REFIN(+) 5 TOP VIEW (Not to Scale) 12 VIN(-) REFIN(-) 6 11 VIN(+) REFIN(-) 6 11 VIN(+) CIN1(-) 7 10 NC CIN1(-) 7 10 CIN2(-) CIN1(+) 8 9 NC CIN1(+) 8 9 CIN2(+) Figure 4. AD7745 Pin Configuration (16-Lead TSSOP) Figure 5. AD7746 Pin Configuration (16-Lead TSSOP) Table 6. Pin Function Descriptions Pin No. 1 Mnemonic SCL 2 RDY 3, 4 EXCA, EXCB 5, 6 REFIN(+), REFIN(-) 7 CIN1(-) 8 CIN1(+) 9 CIN2(+) 10 CIN2(-) 11, 12 VIN(+), VIN(-) 13 14 GND VDD 15 16 NC SDA Description Serial interface clock input. Connects to the master's clock line. (Requires pull-up resistor if not already provided in the system.) Logic output. A falling edge on this output indicates that a conversion on enabled channel(s) has been finished and the new data are available. Alternatively, the status register can be read via the 2-wire serial interface and the relevant bit(s) decoded to query finished conversion. If not used, this pin should be left open circuit. CDC excitation outputs. The measured capacitance is connected between one of the EXC pins and one of the CIN pins. If not used, these pins should be left open circuit. Differential voltage reference input for the voltage channel (ADC). Alternatively, the onchip internal reference can be used for the voltage channel. These reference input pins are not used for conversion on capacitive channel(s) (CDC). If not used, these pins can be left open circuit or connected to GND. CDC negative capacitive input in differential mode. This pin is internally disconnected in single ended CDC configuration. If not used, this pin can be left open circuit or connected to GND. CDC capacitive input (in single ended mode) or positive capacitive input (in differential mode). The measured capacitance is connected between one of the EXC pins and one of the CIN pins. If not used, this pin can be left open circuit or connected to GND. AD7746 only. CDC second capacitive input (in single ended mode) or positive capacitive input (in differential mode). If not used, this pin can be left open circuit or connected to GND. AD7746 only. CDC negative capacitive input in differential mode. This pin is internally disconnected in single ended CDC configuration. If not used, this pin can be left open circuit or connected to GND. Differential voltage input for the voltage channel (ADC). These pins are also used to connect an external temp sensing diode. If not used, these pins can be left open circuit or connected to GND. Ground pin. Power supply voltage. This pin should be decoupled to GND, using a low impedance capacitor, for example combination of 10uF tantalum and 0.1uF multilayer ceramic. Not connected. This pin should be left open circuit. Serial interface bidirectional data. Connects to the master's data line. Requires pull-up resistor if not provided elsewhere in the system. Rev. PrF | Page 7 of 17 Preliminary Technical Data AD7745/AD7746 SERIAL INTERFACE The AD7745/AD7746 supports an I2C compatible two wire serial interface. The two wires on the I2C Bus are called SCL, (clock) and SDA, (data). These two wires carry all addressing, control and data information one bit at a time over the bus to all connected peripheral devices. The SDA wire carries the data, while the SCL wire synchronizes the sender and receiver during the data transfer. I2C devices are classified as either a MASTER or SLAVE devices. A device that initiates a data transfer message is called a master, while a device that responds to this message is called a slave. To control the AD7745/AD7746 device on the bus the following protocol must be followed. First, the master initiates a data transfer by establishing a START CONDITION, defined by a high-to-low transition on SDA while SCL remains high. This indicates that the START BYTE will follow next. This 8 bit, start byte is made up of a 7 bit address plus an R/W bit indicator. All peripherals connected to the bus respond to the start condition and shift in the next eight bits (7-bit address + R/W bit). The bits arrive MSB first. The peripheral that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse. This is known as the ACKNOWLEDGE bit. All other devices withdraw from the bus at this point and maintain an IDLE CONDITION. An exception to this is the GENERAL CALL address which is described later in this document. The idle condition is where the device monitors the SDA and SCL lines waiting for the start condition and the correct address byte. The R/W bit determines the direction of the data transfer. A logic `0' LSB in the start byte means that the master will write information to the addressed peripheral. In this case the AD7745/AD7746 becomes a slave receiver. A logic `1' LSB in the start byte means that the master will read information from the addressed peripheral. In this case the AD7745/AD7746 becomes a slave transmitter. In all instances, the AD7745/AD7746 acts as a standard slave device on the I2C bus. If a data byte is transmitted after the register address pointer byte, the AD7745/AD7746 will load this byte into the register that is currently addressed by the address pointer register, send an acknowledge and the address pointer auto-incrementer will automatically increment the address pointer register to the next internal register address. Thus subsequent transmitted data bytes will be loaded into sequentially incremented addresses. If a repeated start condition is encountered after the address pointer byte, all peripherals connected to the bus respond exactly as outlined above for a start condition, i.e. a repeated start condition is treated the same as a start condition. (When a master device issues a stop condition, it relinquishes control of the bus, allowing another master device to take control of the bus. Hence, a master wanting to retain control of the bus will issue successive start conditions known as repeated start conditions). READ OPERATION When a READ is selected in the start byte, the register that is currently addressed by the address pointer is transmitted on to the SDA line by the AD7745/AD7746. This is then clocked out by the master device and the AD7745/AD7746 will await an acknowledge from the master. If an acknowledge is received from the master, the address autoincrementer will automatically increment the address pointer register and output the next addressed registers contents on to the SDA line for transmission to the master. If no acknowledge is received the AD7745/AD7746 returns to its idle state and the address pointer is not incremented. The address pointers' auto-incrementer allows block data to be written or read from the starting address and subsequent incremental addresses. The user can also access any unique register (address) on a one-to-one basis without having to update all the registers. The address pointer register contents cannot be read. The start byte address for the AD7745/AD7746 is 0x90 for a Write and 0x91 for a Read. If an incorrect address pointer location is accessed or, if the user allows the auto incrementer to exceed the required register address, the following applies: WRITE OPERATION 1. When a WRITE is selected, the byte following the start byte is always the register ADDRESS POINTER (sub-address) byte, which points to of one of the internal registers on the AD7745/AD7746. The address pointer byte is automatically loaded into the address pointer register and acknowledged by the AD7745/AD7746. After the address pointer byte acknowledge, a STOP CONDITION, REPEATED START CONDITION, or another data byte can follow from the master. In Read Mode, the AD7745/AD7746 will continue to output various internal register contents until the master device issues a not-acknowledge, start or stop condition. The address pointers' auto-incrementer's contents will reset to point to the STATUS REGISTER at address 0x00 when a stop condition is received at the end of a read operation. This allows the status register to be read (polled) continually without having to constantly write to address pointer. 2. In Write Mode, the data for the invalid address will not be loaded into the AD7745/AD7746 registers but an acknowledge will be issued by the AD7745/AD7746. A stop condition is defined by a low-to-high transition on SDA while SCL remains high. If a stop condition is ever encountered by the AD7745/AD7746, it will return to its idle condition and the address pointer is reset to address 0x00. Rev. PrF | Page 8 of 17 Preliminary Technical Data AD7745/AD7746 GENERAL CALL AD7745/AD7746 RESET When a master issues a slave address consisting of seven zeros with the eighth bit (R/W bit) set to zero, this is known as the general call address. The general call address is for addressing every device connected to the I2C bus. The AD7745/AD7746 will acknowledge this address and read in the following data byte. In order that the AD7745/AD7746 can be reset without having to reset the entire I2C bus, an explicit reset command is provided. This uses a particular address pointer word as a command word to reset the part and upload all default settings. The reset command address word is 0xBF. If the second byte is 0x06, the AD7745/AD7746 will reset completely uploading all default values. The AD7745/AD7746 will not acknowledge any other general call commands. SCLOCK S 1-7 8 9 1 -7 8 9 START ADDR R/W ACK SUBADDRESS ACK 1-7 DATA 8 9 P ACK STOP 02980-A-034 SDATA Figure 6. Bus Data Transfer S SLAVE ADDR A(S) SUB ADDR S SLAVE ADDR A(S) S = START BIT P = STOP BIT DATA A(S) DATA A(S) P LSB = 1 LSB = 0 READ SEQUENCE A(S) SUB ADDR A(S) S SLAVE ADDR A(S) = ACKNOWLEDGE BY SLAVE A(M) = ACKNOWLEDGE BY MASTER A(S) DATA A(M) A(S) = NO-ACKNOWLEDGE BY SLAVE A(M) = NO-ACKNOWLEDGE BY MASTER Figure 7. Write and Read Sequences Rev. PrF | Page 9 of 17 DATA A(M) P 02980-A-035 WRITE SEQUENCE Preliminary Technical Data AD7745/AD7746 REGISTER DESCRIPTIONS After the part has been accessed over the bus and a read/write operation is selected, the address pointer register is set up. The address pointer register determines to/from which register the operation takes place. A read/write operation is performed from to the target address, which then increments to the next address until a stop command on the bus is performed. The master can write to or read from all of the AD7745/AD7746 registers except the address pointer register, which is a write-only register. The address pointer register determines which register the next read or write operation accesses. All communications with the part through the bus start with an access to the address pointer register. Table 7. Register Summary Register Address Pointer (dec) (hex) Dir Bit 7 Bit 6 Bit 5 0 0 Bit 4 Bit 3 (Default Value) EXCERR 0 0 Bit 2 Bit 1 Bit 0 RDY 1 RDYVT 1 RDYCAP 1 0 VTSHORT 0 EXCLVL1 CAPCHOP 0 VTCHOP 0 EXCLVL0 1 MD1 0 1 MD0 0 Status 0 0x00 R 0 Cap Data H 1 0x01 R Capacitive channel data - High byte 0x00 Cap Data M 2 0x02 R Capacitive channel data - Middle byte 0x00 Cap Data L 3 0x03 R Capacitive channel data - Low byte 0x00 VT Data H 4 0x04 R Voltage / Temperature channel data - High byte 0x00 VT Data M 5 0x05 R Voltage / Temperature channel data - Middle byte 0x00 VT Data L 6 0x06 R Voltage / Temperature channel data - Low byte 0x00 Cap Setup 7 0x07 R/W VT Setup 8 0x08 R/W Exc Setup 9 0x09 R/W Configuration 10 0x0A R/W Cap DAC A 11 0x0B R/W Cap DAC B 12 0x0C R/W Cap Offset H 13 0x0D R/W Capacitive offset calibration - High byte 0x80 Cap Offset L 14 0x0E R/W Capacitive offset calibration - Low byte 0x00 Cap Gain H 15 0x0F R/W Capacitive gain calibration - High byte Factory calibrated Cap Gain L 16 0x10 R/W Capacitive gain calibration - Low byte Factory calibrated Volt Gain H 17 0x11 R/W Voltage gain calibration - High byte Factory calibrated Volt Gain L 18 0x12 R/W Voltage gain calibration - Low byte Factory calibrated 1 CAPEN 0 VTEN 0 CLKCTRL CIN21 0 VTMD1 0 EXCON CAPDIFF 0 VTMD0 0 EXCB 0 EXTREF 0 EXCB 0 VTFS1 1 DACAENA 0 DACBENB 0 0 VTFS0 0 0 CAPFS2 1 0 0 0 CAPFS1 CAPFS0 MD2 0 0 0 DACA - 7-Bit Value 0x00 DACB - 7-Bit Value 0x00 The CIN2 bit is relevant only for AD7746. The CIN2 bit should be always 0 on AD7745. Rev. PrF | Page 10 of 17 0 0 EXCA 0 0 EXCA Preliminary Technical Data AD7745/AD7746 STATUS REGISTER Address pointer 0x00, read only, default value 0x07 Indicates status of the converter. Status register can be read via the 2-wire serial interface to query a finished conversion. Bit 6 0 Bit 5 0 The RDY pin reflects status of the RDY bit. Therefore, the RDY pin high to low transition can be used as an alternative indication of the finished conversion. Bit Mnemonic Default Bit 7 0 Bit 4 0 Bit 3 EXCERR 0 Bit 2 RDY 1 Bit 1 RDYVT 1 Bit 0 RDYCAP 1 Bit 7-4 Mnemonic - 3 EXCERR 2 RDY 1 RDYVT 0 RDYCAP Description Not used, always read 0 EXCERR = 1 indicates that the excitation output cannot be driven properly. The possible reason can be short or too high capacitance between the excitation pin and ground. RDY = 0 indicates that conversion on the enabled channel(s) has been finished and new unread data are available. If both capacitive and voltage / temperature channels are enabled, thy RDY bit will be changed to 0 after conversion on both channels is finished. The RDY bit will return to 1 either when data are read or prior finishing the next conversion. If only one channel is enabled, for example capacitive, then the RDY bit will reflect the RDYCAP bit. RDYVT = 0 indicates that a conversion on the voltage / temperature channel has been finished and new unread data are available. RDYCAP = 0 indicates that a conversion on the capacitive channel has been finished and new unread data are available. CAP DATA REGISTER VT DATA REGISTER 24 bits, address pointer 0x01, 0x02, 0x03, read only, default value 0x000000 24 bits, address pointer 0x04, 0x05, 0x06, read only, default value 0x000000 Capacitive channel output data. The register is updated after finished conversion on the capacitive channel, with one exception: When the serial interface read operation from the CAP DATA register is in progress, the data register is not updated and the new capacitance conversion result is lost. Voltage / Temperature channel output data. The register is updated after finished conversion on the voltage channel or temperature channel, with one exception: When the serial interface read operation from the VT DATA register is in progress, the data register is not updated and the new voltage / temperature conversion result is lost. Stop condition on the serial interface is considered as the end of the read operation. Therefore, to prevent data corruption, all 3 bytes of the data register should be read subsequently using the register address pointer auto-increment feature of the serial interface. To prevent losing some of the results, the CAP DATA register should be read before the next conversion on the capacitive channel is finished. Code 0x000000 represents negative full-scale (-4.096 pF), code 0x800000 represents zero scale (0 pF) and the code 0xFFFFFF represents positive full scale (+4.096 pF). Stop condition on the serial interface is considered as the end of the read operation. Therefore, to prevent data corruption, all 3 bytes of the data register should be read subsequently using the register address pointer auto-increment feature of the serial interface. For voltage input, code 0 represents negative full scale (-VREF), code 0x800000 represents zero scale (0 V) and the code 0xFFFFFF represents positive full scale (+VREF). To prevent losing some of the results, the VT DATA register should be read before the next conversion on the voltage /temperature channel is finished. For temperature sensor, the temperature can be calculated from code using equation: Temperature (C) = (Code / 2048) - 4096 Rev. PrF | Page 11 of 17 Preliminary Technical Data AD7745/AD7746 CAP SETUP REGISTER Address pointer 0x07, default value 0x00 Capacitive channel setup. Bit Mnemonic Default Bit 7 CAPEN 0 Bit 7 6 5 4-1 0 Description CAPEN = 1 enables capacitive channel for single conversion, continuous conversion or calibration. CIN2 = 1 switches the internal multiplexer to the second capacitive input on the AD7746. DIFF = 1 sets differential mode on the selected capacitive input. These bits must be 0 for proper operation. CAPCHOP = 1 enables chopping on the capacitive channel. Mnemonic CAPEN CIN2 DIFF CAPCHOP Bit 6 CIN2 0 Bit 5 DIFF 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 CAPCHOP 0 VT SETUP REGISTER Address pointer 0x08, default value 0x00 Voltage / Temperature channel setup. Bit Mnemonic Default Bit 7 VTEN 0 Bit 7 Description VTEN = 1 enables voltage / temperature channel for single conversion, continuous conversion or calibration. Voltage / temperature channel input configuration: 6 5 Mnemonic VTEN VTMD1 VTMD0 4 EXTREF 3-2 1 VTSHORT 0 VTCHOP = 1 Bit 6 VTMD1 0 Bit 5 VTMD0 0 Bit 4 EXTREF 0 Bit 3 0 Bit 2 0 Bit 1 VTSHORT 0 Bit 0 VTCHOP 0 VTMD1 VTMD0 Channel Input 0 0 Internal Temperature Sensor 0 1 External Temperature Sensor Diode 1 0 VDD Monitor 1 1 External Voltage Input (VIN) EXTREF = 1 selects an external reference voltage connected to REFIN(+), REFIN(-) for the voltage input or the VDD Monitor. EXTREF = 0 selects the on-chip internal reference. The internal reference must be used with the internal temperature sensor for proper operation. These bits must be 0 for proper operation. VTSHORT = 1 internally shorts the voltage / temperature channel input for test purposes. VTCHOP = 1 sets internal chopping on the voltage / temperature channel. The VTCHOP bit must be set to 1 for the specified voltage / temperature channel performance. Rev. PrF | Page 12 of 17 Preliminary Technical Data AD7745/AD7746 EXC SETUP REGISTER Address pointer 0x09, default value 0x03 Capacitive channel excitation setup. Bit Mnemonic Default Bit 7 CLKCTRL 0 Bit 6 EXCON 0 Bit 5 EXCB 0 Bit 4 EXCB 0 Bit 3 EXCA 0 Bit 2 EXCA 0 Bit 1 EXCLVL1 0 Bit Mnemonic 7 CLKCTRL 6 EXCON 5 EXCB 4 EXCB 3 EXCA 2 EXCA Description CLKCTRL = 1 decreases the excitation signal frequency and the modulator clock frequency by factor of 2. This also increases the conversion time on all channels (capacitive, voltage and temperature) by factor of 2. When EXCON = 0, the excitation signal is present on the output only during capacitance channel conversion When EXCON = 1, the excitation signal is present on the output during both capacitance and voltage / temperature conversion EXCB = 1 enables EXCB pin as the excitation output EXCB = 1 enables EXCB pin as the inverted excitation output Only one of the EXCB or the EXCB bits should be set for proper operation. EXCA = 1 enables EXCA pin as the excitation output EXCA = 1 enables EXCA pin as the inverted excitation output Only one of the EXCA or the EXCA bits should be set for proper operation. Excitation Voltage Level: 1 0 EXCLVL1, EXCLVL0 EXCLVL1 EXCLVL0 0 0 0 1 1 0 1 1 Voltage on Cap. VDD/8 VDD/4 VDD x 3/8 VDD/2 EXC pin Low Level VDD x 3/8 VDD x 1/4 VDD x 1/8 0 Rev. PrF | Page 13 of 17 EXC pin High Level VDD x 5/8 VDD x 3/4 VDD x 7/8 VDD Bit 0 EXCLVL0 0 Preliminary Technical Data AD7745/AD7746 CONFIGURATION REGISTER Address pointer 0x0A, default value 0xA0 Converter update rate and mode of operation setup. Bit Mnemonic Default Bit 7 VTF1 0 Bit Description Mnemonic Bit 6 VTF0 0 Bit 5 CAPF2 0 Bit 4 CAPF1 0 Bit 3 CAPF0 0 Bit 2 MD2 0 Bit 1 MD1 0 Bit 0 MD0 0 Voltage / temperature channel digital filter setup - conversion time / update rate setup. The conversion times in this table are valid for the CLKCTRL = 0 in the EXC SETUP register. The conversion times are longer by factor of two for the CLKCTRL = 1. 7 6 VTF1 VTF0 VTF1 VTF0 0 0 1 1 0 1 0 1 VTCHOP = 1 Conversion Update Rate Time (ms) (Hz) 20.1 49.8 32.1 31.2 62.1 16.1 122.1 8.2 Capacitive channel digital filter setup - conversion time / update rate setup. The conversion times in this table are valid for the CLKCTRL = 0 in the EXC SETUP register. The conversion times are longer by factor of two for the CLKCTRL = 1. 5 4 3 CAPF2 CAPF1 CAPF0 CAPF2 CAPF1 CAPF0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 CAP CHOP = 1 Conversion Update Rate Time (ms) (Hz) 20.1 49.8 22.0 45.6 38.1 26.3 74.1 13.5 122.1 8.2 152.1 6.6 182.1 5.5 217.3 4.6 CAP CHOP = 0 Conversion Update Rate Time (ms) (Hz) 11.0 90.9 11.9 83.8 20.0 50.0 38.0 26.3 62.0 16.1 77.0 13.0 92.0 10.9 109.6 9.1 Converter mode of operation setup 2 1 0 MD2 MD1 MD0 MD2 0 0 0 0 1 1 1 1 MD1 0 0 1 1 0 0 1 1 MD0 0 1 0 1 0 1 0 1 Mode Idle Continuous Conversion Single Conversion Power-Down Capacitance Offset Calibration Capacitance or Voltage Gain Calibration Rev. PrF | Page 14 of 17 Preliminary Technical Data AD7745/AD7746 CAP DAC A REGISTER Address pointer 0x0B, default value 0x00 Capacitive DAC setup. Bit Mnemonic Default Bit 7 DACAENA 0 Bit 7 6-1 Description DACAENA = 1 connects capacitive DAC A to the positive capacitance input. Mnemonic DACAENA DACA Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 DACA - 7-Bit Value 0x00 Bit 1 Bit 0 Bit 1 Bit 0 DAC A value, code 0x00 0pF, code 0x7F Full Range CAP DAC B REGISTER Address pointer 0x0C, default value 0x00 Capacitive DAC setup. Bit Mnemonic Default Bit 7 DACBENB 0 Bit 7 6-1 Description DACBENB = 1 connects capacitive DAC B to the positive capacitance input. Mnemonic DACBENB DACB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 DACB - 7-Bit Value 0x00 DAC B value, code 0x00 0pF, code 0x7F Full Range CAP OFFSET REGISTER 16 bits, address pointer 0x0D, 0x0E default value 0x8000 Capacitive offset calibration register. The register holds capacitive channel zero-scale calibration coefficient. The value in this register is used to digitally remove the capacitive channel offset. The value in this register is updated automatically following the execution of a capacitance offset calibration. The capacitive offset calibration resolution (cap offset register LSB) is less than 32 aF, the full range is 1 pF. On the AD7746, the register is shared by the two capacitive channels. CAP GAIN REGISTER 16 bits, address pointer 0x0F, 0x10, default value 0xXXXX Capacitive gain calibration register. The register holds capacitive channel full scale factory calibration coefficient. VOLT GAIN REGISTER 16 bits, address pointer 0x11,0x12, default value 0xXXXX Voltage gain calibration register. The register holds voltage channel full scale factory calibration coefficient. Rev. PrF | Page 15 of 17 Preliminary Technical Data AD7745/AD7746 TYPICAL APPLICATION DIAGRAM 0.1uF + 10uF +3V / +5V POWER SUPPLY VDD TEMP SENSOR CLOCK GENERATOR HOST SYSTEM AD7745 VIN(+) SDA VIN(-) MUX 24-BIT - MODULATOR CIN1(+) I2C SERIAL INTERFACE DIGITAL FILTER SCL CIN1(-) RDY CONTROL LOGIC CALIBRATION CAP DAC CAP DAC VOLTAGE REFERENCE EXC1 EXCITATION EXC2 REFIN(+) GND REFIN(-) Figure 8. Basic Application Diagram for a Differential Capacitive Sensor 0.1uF + 10uF +3V / +5V POWER SUPPLY VDD TEMP SENSOR CLOCK GENERATOR HOST SYSTEM AD7745 VIN(+) RTD SDA VIN(-) MUX 24-BIT - MODULATOR DIGITAL FILTER CIN1(+) I2C SERIAL INTERFACE SCL CIN1(-) CAPACITIVE SENSOR CONTROL LOGIC CALIBRATION CAP DAC RDY CAP DAC VOLTAGE REFERENCE EXC1 EXCITATION EXC2 REFIN(-) REFIN(+) GND RREF Figure 9. Application Diagram for a Single Capacitive Sensor and an External RTD or PTC Sensor Rev. PrF | Page 16 of 17 Preliminary Technical Data AD7745/AD7746 OUTLINE DIMENSIONS 5.10 5.00 4.90 16 9 4.50 4.40 4.30 6.40 BSC 1 8 PIN 1 1.20 MAX 0.15 0.05 0.20 0.09 0.30 0.19 0.65 BSC COPLANARITY 0.10 SEATING PLANE 8 0 0.75 0.60 0.45 COMPLIANT TO JEDEC STANDARDS MO-153AB Figure 10. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. (c) 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective companies. PR05468-0-3/05(PrF)