Datasheet 3.5 V to 40 V Input, 1 A Single 2.2 MHz Buck DC/DC Converter For Automotive BD9P1x5EFV-C Series General Description Key Specifications Input Voltage Range: 3.5 V to 40 V (Initial startup is 4.0 V or more) Output Voltage Range BD9P105EFV-C: 0.8 V to 8.5 V BD9P135EFV-C: 3.3 V (Typ) BD9P155EFV-C: 5.0 V (Typ) Output Current: OCP_SEL = L 0.5 A (Max) 1.0 A (Max) OCP_SEL = H Switching Frequency: 2.2 MHz (Typ) Output Voltage Accuracy: 1.75 % (-40 C to +125 C) Shutdown Current: 2.1 A (Typ) Operating Temperature Range: -40 C to +125 C BD9P1x5EFV-C Series are current mode synchronous buck DC/DC converter integrating POWER MOSFETs. Features TM Nano Pulse Control (Note 1) AEC-Q100 Qualified Minimum ON Pulse 50 ns (Max) Synchronous Buck DC/DC Converter Integrating POWER MOSFETs Soft Start Function Current Mode Control Reset Function Quiescent Current 10 A (Typ) with 12 V Input to 5.0 V Output Light Load Mode (LLM) Forced Pulse Wide Modulation (PWM) Mode Phase Compensation Included Selectable Spread Spectrum Switching External Synchronization Function Selectable Over Current Protection (OCP) Input Under Voltage Lockout (UVLO) Protection Thermal Shut Down (TSD) Protection Output Over Voltage Protection (OVP) Short Circuit Protection (SCP) Package HTSSOP-B20 W (Typ) x D (Typ) x H (Max) 6.5 mm x 6.4 mm x 1.0 mm (Note 1) Grade 1 Applications Automotive Powered Supplies Consumer Powered Supplies HTSSOP-B20 Typical Application Circuit CBST VIN VIN BST PVIN CIN VOUT L1 SW VCC_EX EN VOUT_DIS PGND VOUT_SNS COUT RRST RESET VREG CREG OCP_SEL GND MODE VMODE SSCG VSSCG Figure 1. Application Circuit with Discharge Function (BD9P135EFV-C, BD9P155EFV-C) Nano Pulse Control TM is a trademark of ROHM Co., Ltd. Product structure : Silicon integrated circuit .www.rohm.com (c) 2019 ROHM Co., Ltd. All rights reserved. TSZ22111 * 14 * 001 This product has no designed protection against radioactive rays 1/57 TSZ02201-0J1J0AL01480-1-2 08.Apr.2020 Rev.002 BD9P1x5EFV-C Series Typical Application Circuit - continued CBST VIN VIN BST CIN VOUT L1 SW PVIN VCC_EX EN VOUT_DIS PGND VOUT_SNS VREG RESET CREG OCP_SEL GND COUT RRST MODE VMODE SSCG VSSCG Figure 2. Application Circuit without Discharge Function (BD9P135EFV-C, BD9P155EFV-C) CBST VIN VIN BST CIN VOUT L1 SW PVIN VCC_EX VOUT_DIS FB EN PGND VOUT_SNS VREG RESET CREG OCP_SEL GND RFB1 COUT RRST MODE VMODE SSCG VSSCG RFB2 Figure 3. Application Circuit with Discharge Function (BD9P105EFV-C) CBST VIN VIN BST PVIN CIN VOUT L1 SW VCC_EX VOUT_DIS FB EN PGND VOUT_SNS RFB1 COUT RRST RESET VREG CREG OCP_SEL GND MODE VMODE SSCG VSSCG RFB2 Figure 4. Application Circuit without Discharge Function (BD9P105EFV-C) www.rohm.com (c) 2019 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 2/57 TSZ02201-0J1J0AL01480-1-2 08.Apr.2020 Rev.002 BD9P1x5EFV-C Series Pin Configuration EN 20 VREG VIN 2 19 VCC_EX PVIN 3 18 N.C. PVIN 4 17 VOUT_SNS N.C. 5 16 VOUT_DIS EXP-PAD PGND 6 15 GND PGND 7 14 RESET SW 8 13 SSCG SW 9 12 MODE BST 10 11 OCP_SEL (TOP VIEW) Figure 5. Pin Configuration (BD9P135EFV-C, BD9P155EFV-C) EN 1 20 VREG VIN 2 19 VCC_EX PVIN 3 18 FB PVIN 4 17 VOUT_SNS N.C. 5 16 VOUT_DIS PGND 6 15 GND PGND 7 14 RESET SW 8 13 SSCG SW 9 12 MODE BST 10 11 OCP_SEL EXP-PAD (TOP VIEW) Figure 6. Pin Configuration (BD9P105EFV-C) www.rohm.com (c) 2019 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 3/57 TSZ02201-0J1J0AL01480-1-2 08.Apr.2020 Rev.002 BD9P1x5EFV-C Series Pin Description Pin No. Pin Name 1 EN 2 VIN 3, 4 PVIN 5 N.C. 6, 7 PGND 8, 9 SW 10 BST 11 OCP_SEL 12 MODE 13 SSCG 14 RESET 15 GND 16 VOUT_DIS 17 (BD9P105EFV-C) 17 (BD9P135EFV-C, BD9P155EFV-C) VOUT_SNS 18 (BD9P105EFV-C) FB 18 (BD9P135EFV-C, BD9P155EFV-C) N.C. 19 VCC_EX 20 VREG - EXP-PAD www.rohm.com (c) 2019 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 Function Enable pin. Apply low level (0.8 V or lower) to disable device and apply high level (2.0 V or higher) to enable device. This pin must not be left open. If this pin is connected to other devices, it is recommended to insert a current limiting resistor to avoid damages caused by a short between pins. Power supply input pins for the internal circuit. Connect this pin to the PVIN pins. Power supply input pins that are used for the output stage of the switching regulator. Connect input ceramic capacitors referring Page 33 between the PGND pins and these pins. This pin is not connected to the chip. Use this as open. If this pin is used other than open and adjacent pins are expected to be shorted, please confirm if there is any problem with the actual application. Ground pins for the output stage of the switching regulator. Switching node pins. These pins are connected to the source of the internal High Side FET and the drain of the internal Low Side FET. Connect the power inductor and the bootstrap capacitor. Connect a bootstrap capacitor of 0.1 F (Typ) between this pin and the SW pins. The voltage of this capacitor is the gate drive of the High Side FET. This is OCP threshold selective pin. OCP threshold is set to 1.250 A (Typ) at high, and 0.625 A (Typ) at low. These values mean the average inductor current. Connect this pin to VREG (High) or GND (Low). Pin to select FPWM (Forced PWM) mode, AUTO (Automatically switched between PWM mode and LLM) mode, or SYNC (Activate synchronization) mode. In case of using FPWM mode, set high. In case of using AUTO mode, set low or open. In case of using SYNC mode, apply a clock to this pin. Pin to select Spread Spectrum function. Set high to enable Spread Spectrum and set low to disable Spread Spectrum. Connect this pin to VREG (High) or GND (Low). Output reset pin with open drain. Connect a pull-up resistor to the VREG pin or the power supply within the absolute maximum voltage ratings of the RESET pin. Using a 5 k to 100 k resistance is recommended. Ground pin. This pin discharges the VOUT node. Connect this pin to the VOUT when discharge function is required. Otherwise, connect this pin to GND. Pin to define the clamp voltage of GmAmp2 output and phase compensation. Connect this pin to the output voltage. Inverting input node of the GmAmp1. This pin is used for OVP, SCP and RESET detection. And, this pin is used for defining the clamp voltage of GmAmp2 output and phase compensation. Connect this pin to the output voltage. Inverting input node of the GmAmp1. This pin is used for OVP, SCP and RESET detection. Connect output voltage divider to this pin to set the output voltage. This pin is not connected to the chip. Use this as open. If this pin is used other than open and adjacent pins are expected to be shorted, please confirm if there is any problem with the actual application. This pin is power supply input for internal circuit. VREG voltage is supplied from VCC_EX when voltage between 3.2 V (VTEXH, Max) and 5.65 V (VEXOVPL, Min) is connected to this pin. Connecting this pin to VOUT improves efficiency. In case of not use this function, connect this pin to GND. Pin to output 3.3 V (Typ) for internal circuit. Connect a ceramic capacitor of 1.0 F (Typ). Do not connect to any external loads except the OCP_SEL pin, the MODE pin, the SSCG pin and a pull-up resistor to the RESET pin. Exposed pad. The EXP-PAD is connected to the P substrate of the IC. Connect this pad to the internal PCB ground plane using multiple via holes to obtain excellent heat dissipation characteristics. 4/57 TSZ02201-0J1J0AL01480-1-2 08.Apr.2020 Rev.002 BD9P1x5EFV-C Series Block Diagram VCC_EX VREG VIN VREF Pre Reg VREG tsdout TSD GND VREF VIN porout UVLO REG POR VREF uvloout EN OSC SSCG clk MODE MODE mode Discharge OCP_SEL OCP_SEL VOUT_DIS vout_det vout_dis VREF VOUT_SNS scpout VOUT_SNS porout SCP uvloout HOCP Comp scpout VREG ovpout FB mode GmAmp1 OCP_SEL BST VREG Clamper1 PVIN GmAmp2 PWM Comp VREF Vc Soft Start VOUT_SNS Control Logic Clamper2 Driver SW EN clk Sleep Comp Ramp Vr ZX Comp sleep VREF VREF Current Sense Reset PGND VREF VOUT_SNS EN porout uvloout tsdout OVP VCC_EX RESET ovpout Figure 7. Block Diagram (BD9P105EFV-C) www.rohm.com (c) 2019 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 5/57 TSZ02201-0J1J0AL01480-1-2 08.Apr.2020 Rev.002 BD9P1x5EFV-C Series Block Diagram - continued VCC_EX VREG VIN VREF Pre Reg VREG tsdout TSD VREF VIN porout UVLO REG POR VREF GND uvloout EN OSC SSCG clk MODE MODE mode Discharge OCP_SEL VOUT_DIS vout_det vout_dis OCP_SEL VREF scpout porout SCP VOUT_SNS uvloout HOCP Comp scpout VREG ovpout mode FB GmAmp1 OCP_SEL BST VREG Clamper1 GmAmp2 PWM Comp VREF PVIN vout_dis Vc Soft Start VOUT_SNS EN clk Sleep Comp Control Logic Clamper2 Ramp Vr Driver SW ZX Comp sleep VREF Current Sense VREF Reset PGND VREF EN porout uvloout tsdout OVP VCC_EX RESET ovpout Figure 8. Block Diagram (BD9P135EFV-C, BD9P155EFV-C) www.rohm.com (c) 2019 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 6/57 TSZ02201-0J1J0AL01480-1-2 08.Apr.2020 Rev.002 BD9P1x5EFV-C Series Description of Blocks - PreReg This block is the internal power supply for TSD and VREF circuits. - VREG This block is the internal power supply circuit. It outputs 3.3 V (Typ) and is the power supply to the control circuit and Driver. - TSD This is the thermal shutdown circuit. It will shut down the device when the junction temperature (Tj) reaches to 175 C (Typ) or more. When the Tj falls below the TSD threshold with hysteresis of 25 C (Typ), the circuits are automatically restored to normal operation. - VREF The VREF block generates the internal reference voltage. - POR The POR block is power on reset for internal logic circuit. The IC releases power on reset and starts operation with soft start when the VIN rises to 3.8 V (Typ) or more. - UVLO REG The UVLO block is for under voltage lockout protection. It will shut down the device when the VREG falls to 2.85 V (Typ) or less. This protection is released when VREG voltage increase to 2.95 V (Typ) or more. - MODE This block detects the MODE pin signal and controls switching mode. When the MODE pin is logic high level or is applied external clock, switching operation becomes forced PWM mode regardless load current. When the MODE pin is open or logic low level, switching operation changes between PWM and light load operation depending on load current. - OSC This block generates the clock frequency. When the clock is applied to the MODE pin, it synchronizes to external clock. Connect the SSCG pin to GND to disable Spread Spectrum function and connect the SSCG pin to the VREG pin to enable it. - OVP This is the output over voltage protection (OVP) circuit. When the output voltage +7.3 % (Typ) or more of the normal regulation voltage, VOUT is reduced by forced PWM switching. After output voltage falls +4.7 % (Typ) or less, the operation recovers into normal condition. - SCP This is the short circuit protection circuit. After soft start is completed, the switching is disabled if the output voltage falls SCP Threshold voltage or less for 0.9 ms (Typ). This short circuit protection is maintained for 30 ms (Typ) and then automatically released. - Soft Start This function starts up the output voltage taking 3 ms (Typ) to prevent the overshoot. - GmAmp1 This block is an error amplifier and its inputs are the reference voltage 0.8 V (Typ) and the FB voltage. - GmAmp2 This block sends the signal Vc which is composed of the GmAmp1 output and the current sense signal to PWM Comp. - Clamper1 This block clamps GmAmp1 output voltage and inductor current. It works as the over current protection and LLM control current. - Clamper2 This block clamps GmAmp2 output voltage. - Current Sense This block detects the amount of change in inductor current through the Low Side FET and sends a current sense signal to GmAmp2. www.rohm.com (c) 2019 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 7/57 TSZ02201-0J1J0AL01480-1-2 08.Apr.2020 Rev.002 BD9P1x5EFV-C Series Description of Blocks - continued - PWM Comp This block compares the output voltage of the GmAmp2 (Vc) and the saw tooth waveform (Vr) to control the switching duty. - Ramp This block generates the saw tooth waveform (Vr) from the clock signal generated by OSC. - Control Logic This block controls switching operation and protection functions. - Driver This circuit drives the gates of the output FETs. - Sleep Comp If output/feedback voltage becomes 101.3 % (Typ) or more, this block puts the device into SLEEP state. This state is released when output/feedback voltage becomes 101.0 % (Typ) or less. - ZX Comp This block stops the switching by detecting reverse current of the SW current at LLM control. - HOCP Comp This block detects the current flowing through the High Side FET and limits the current of 2.2 A (Min) or more. This function works in abnormal situation such as the SW pin shorted to GND condition in order to prevent the High Side FET from destruction. - Reset When the output voltage reaches -4.7 % (Typ) or more of the normal regulation voltage, the open drain MOSFET connected to the RESET pin turns off in 3.6 ms (Typ) and the output of the RESET pin becomes high by its external pull-up resistor. When the output voltage reaches -7.2 % (Typ) or less, the RESET pin open drain MOSFET turns on and the RESET pin is pulled down with an impedance of 190 (Typ). - Discharge This block discharges the output voltage during EN is low and before VOUT start up. The VOUT_DIS pin is pulled down with an impedance of 75 (Typ). www.rohm.com (c) 2019 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 8/57 TSZ02201-0J1J0AL01480-1-2 08.Apr.2020 Rev.002 BD9P1x5EFV-C Series Absolute Maximum Ratings Parameter Input Voltage EN Voltage Symbol Rating Unit VVIN, VPVIN -0.3 to +42 V VEN -0.3 to +42 V VBST -0.3 to +49 V VSW -0.3 to VSW +7 V -0.3 to +7 V VOUT_DIS Voltage VBST VFB, VRESET, VMODE, VSSCG VOCP_SEL VVOUT_DIS -0.3 to +10 V VOUT_SNS Voltage VVOUT_SNS -0.3 to +10 V BST Voltage Voltage from SW to BST FB, RESET, MODE, SSCG, OCP_SEL Voltage VVCC_EX -0.3 to +7 V VREG Voltage VREG -0.3 to +7 V Storage Temperature Range Tstg -55 to +150 C Tjmax 150 C VESD_HBM 2 kV VCC_EX Voltage Maximum Junction Temperature Human Body Model (HBM) (Note 1) Caution 1: Operating the IC over the absolute maximum ratings may damage the IC. The damage can either be a short circuit between pins or an open circuit between pins and the internal circuitry. Therefore, it is important to consider circuit protection measures, such as adding a fuse, in case the IC is operated over the absolute maximum ratings. Caution 2: Should by any chance the maximum junction temperature rating be exceeded the rise in temperature of the chip may result in deterioration of the properties of the chip. In case of exceeding this absolute maximum rating, design a PCB with thermal resistance taken into consideration by increasing board size and copper area so as not to exceed the maximum junction temperature rating. (Note 1) These voltages are guaranteed by design. Not tested. Thermal Resistance (Note 2) Parameter Symbol Thermal Resistance (Typ) 1s (Note 4) (Note 5) 2s2p Unit HTSSOP-B20 Junction to Ambient Junction to Top Characterization Parameter (Note 3) JA 143.0 26.8 C/W JT 8 4 C/W (Note 2) Based on JESD51-2A(Still-Air). (Note 3) The thermal characterization parameter to report the difference between junction temperature and the temperature at the top center of the outside surface of the component package. (Note 4) Using a PCB board based on JESD51-3. (Note 5) Using a PCB board based on JESD51-5, 7. Layer Number of Measurement Board Single Material Board Size FR-4 114.3 mm x 76.2 mm x 1.57 mmt Top Copper Pattern Thickness Footprints and Traces 70 m Layer Number of Measurement Board 4 Layers (Note 6) Material Board Size FR-4 114.3 mm x 76.2 mm x 1.6 mmt Top 2 Internal Layers Thermal Via Pitch Diameter 1.20 mm 0.30 mm Bottom Copper Pattern Thickness Copper Pattern Thickness Copper Pattern Thickness Footprints and Traces 70 m 74.2 mm x 74.2 mm 35 m 74.2 mm x 74.2 mm 70 m (Note 6) This thermal via connects with the copper pattern of all layers. www.rohm.com (c) 2019 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 9/57 TSZ02201-0J1J0AL01480-1-2 08.Apr.2020 Rev.002 BD9P1x5EFV-C Series Recommended Operating Conditions Parameter Input Voltage Operating Temperature Output Voltage for BD9P105EFV-C (Note 1) Output Voltage for BD9P135EFV-C Symbol Min Typ Max Unit VVIN, VPVIN 3.5 - 40 V Ta -40 - +125 C VOUT 0.8 - 8.5 V VOUT - 3.3 - V VOUT - 5.0 - V SW Minimum ON Time tONMIN - - 50 ns SW Minimum OFF Time (VREG = 3.3 V) tOFFMIN - - 130 ns SW Minimum OFF Time (VREG = 5.0 V) tOFFMIN - - 100 ns IOUT - - 1 A CIN 2.3 - - F CREG 0.6 1.0 2.0 F CBST 0.05 0.1 0.2 F Output Voltage for BD9P155EFV-C (Note 2) Output Current Input Capacitor (Note 3) (VIN Continuous Condition) (Note 3) VREG Capacitor BST Capacitor (Note 3) (Note 1) Although the output voltage is configurable at 0.8 V and higher, it may be limited by the SW min ON pulse width. For the same reason, although the output voltage is configurable at 8.5 V and more, it may be limited by the SW minimum OFF pulse width. For the configurable range, please refer to the Output Voltage Setting in Selection of Components Externally Connected (page 30). (Note 2) This parameter is for 0.5 A output. Not tested. (Note 3) Ceramic capacitor is recommended. The capacitor value including temperature change, DC bias change, and aging change must be considered. If a bulk capacitor is used with Input ceramic capacitors, please select capacitors referring page 33. Electrical Characteristics (Unless otherwise specified Ta = -40 C to +125 C, VIN = 12 V) Parameter Symbol Min Typ Max Unit Conditions ISDWN - 2.1 10.0 A IQ_VIN1 - 2.1 6.0 A IQ_VIN2 - 15 30 A IQ_VIN3 - 33 66 A IQ_VIN4 - 1200 2400 A IQ_VCC_EX1 - 16 60 A IQ_VCC_EX2 - 1500 3000 A VPOR_R 3.6 3.8 4.0 V VEN = 0 V, Ta = -40 C to +105 C VMODE = 0 V, VVCC_EX = 5 V VFB = VFB1 x 1.04 (SLEEP) VMODE = 0 V, VVCC_EX = 0 V VFB = VFB1 x 1.04 (SLEEP) VMODE = 5 V, VVCC_EX = 5 V VFB =VFB1 x 1.04 (No SLEEP) VMODE = 5 V, VVCC_EX = 0 V VFB = VFB1 x 1.04 (No SLEEP) VMODE = 0 V VFB = VFB1 x 1.04 (SLEEP) VMODE = 5 V VFB = VFB1 x 1.04 (No SLEEP) VIN Sweep Up VREG Under Voltage Lockout Falling VUVLO_F 2.70 2.85 3.00 V VREG Sweep Down VREG Under Voltage Lockout Rising VUVLO_R 2.75 2.95 3.15 V VREG Sweep Up EN Input Voltage High VENH 2.0 - 40 V EN Input Voltage Low VENL 0 - 0.8 V EN Hysteresis Voltage VENHYS 0.10 0.25 0.50 V IEN - 0 1 A MODE Input Voltage High VMODEH 2.0 - 5.5 V MODE Input Voltage Low General Shutdown Current Quiescent Current from VIN Quiescent Current from VCC_EX VIN Power On Reset Rising EN/MODE/OCP_SEL/SSCG EN Input Current VMODEL - - 0.8 V MODE Input Current IMODE - 6 10 A OCP_SEL Input Voltage High VSELH 2.0 - 5.5 V OCP_SEL Input Voltage Low VSELL - - 0.8 V OCP_SEL Input Current ISEL - 0 1 A SSCG Input Voltage High VSSCGH 2.0 - 5.5 V SSCG Input Voltage Low VSSCGL - - 0.8 V ISSCG - 0 1 A SSCG Input Current www.rohm.com (c) 2019 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 10/57 VEN = 5 V VMODE = 5 V VOCP_SEL = 5 V VSSCG = 5 V TSZ02201-0J1J0AL01480-1-2 08.Apr.2020 Rev.002 BD9P1x5EFV-C Series Electrical Characteristics - continued (Unless otherwise specified Ta = -40 C to +125 C, VIN = 12 V) Parameter Symbol Min Typ Max Unit Conditions VREG Voltage VREG 3.0 3.3 3.6 V VCC_EX Switch ON Resistance RONEX - 6 12 Voltage Follower VVCC_EX = 0 V VVCC_EX = 5 V VCC_EX Threshold Voltage High VTEXH 2.90 3.05 3.20 V VVCC_EX Sweep Up VCC_EX Threshold Voltage Low VTEXL 2.70 2.90 3.10 V VVCC_EX Sweep Down VCC_EX OVP Threshold Voltage High VEXOVPH 5.85 6.20 6.55 V VCC_EX OVP Threshold Voltage Low VEXOVPL 5.65 6.00 6.35 V VOUT_DIS Discharge ON Resistance RDIS - 75 150 VOUT Discharge Deactivate Voltage VDISL 100 200 300 mV fSW 2.0 2.2 2.4 MHz fSW_EX 1.8 - 2.4 MHz External Clock Input MHz VSSCG = 5 V VREG VEN = 0 V, VOUT_DIS = 0.3 V VOUT_DIS Sweep Down Oscillator Switching Frequency Synchronization Frequency Range Switching Frequency (Spread Spectrum) Spread Spectrum Modulation Rate fSWSSR 1.90 - 2.52 fSSCG - 4.5 - % VSSCG = 5 V Spread Spectrum Modulation Cycle tSSCG_CYCLE - 466 - s VSSCG = 5 V VFB1 0.788 0.802 0.816 V VFB2 0.794 0.812 0.830 V VFB3 0.792 0.810 0.828 V VOUT_SNS1 3.250 3.308 3.366 V VOUT_SNS2 3.275 3.349 3.424 V VOUT_SNS3 3.266 3.341 3.416 V VOUT_SNS1 4.925 5.013 5.100 V VOUT_SNS2 4.963 5.076 5.188 V VOUT_SNS3 4.949 5.063 5.176 V VREF/GmAmp Feedback Reference Voltage (BD9P105EFV-C) Enter SLEEP State Voltage (BD9P105EFV-C) Exit SLEEP State Voltage (BD9P105EFV-C) Output Voltage (BD9P135EFV-C) Enter SLEEP State Voltage (BD9P135EFV-C) Exit SLEEP State Voltage (BD9P135EFV-C) Output Voltage (BD9P155EFV-C) Enter SLEEP State Voltage (BD9P155EFV-C) Exit SLEEP State Voltage (BD9P155EFV-C) FB Input Current for BD9P105EFV-C IFB - 0 1 A VFB Voltage, PWM Mode VFB Rising, Light Load Mode VFB Falling, Light Load Mode VOUT_SNS Voltage, PWM Mode VOUT_SNS Rising, Light Load Mode VOUT_SNS Falling, Light Load Mode VOUT_SNS Voltage, PWM Mode VOUT_SNS Rising, Light Load Mode VOUT_SNS Falling, Light Load Mode VFB = 5 V IVOUT_SNS - 0.5 2.0 A VOUT_SNS = 5 V Start Delay Time tDLY - 400 800 s Soft Start Time tSS 2.5 3.0 3.9 ms VFB1 x 0.1 to VFB1 x 0.9 High Side FET ON Resistance RONH - 210 440 m VBST-VSW = 3.3 V Low Side FET ON Resistance RONL - 140 290 m High Side FET Leakage Current ILKH -10 0 - A Low Side FET Leakage Current ILKL - 0 10 A IOCP10 1.000 1.250 1.500 A VVCC_EX = 3.3 V VIN = 40 V, VEN = 0 V, Ta = 25 C, VSW = 0 V VIN = 40 V, VEN = 0 V, Ta = 25 C, VSW = 40 V VOCP_SEL = 5 V IOCP05 0.500 0.625 0.750 A VOCP_SEL = 0 V VOUT_SNS Input Current Driver Over Current Protection Threshold www.rohm.com (c) 2019 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 11/57 TSZ02201-0J1J0AL01480-1-2 08.Apr.2020 Rev.002 BD9P1x5EFV-C Series Electrical Characteristics - continued (Unless otherwise specified Ta = -40 C to +125 C, VIN = 12 V) Parameter Reset Reset Threshold Voltage Low (BD9P105EFV-C) Reset Threshold Voltage Low (BD9P135EFV-C) Reset Threshold Voltage Low (BD9P155EFV-C) Reset Threshold Voltage High (BD9P105EFV-C) Reset Threshold Voltage High (BD9P135EFV-C) Reset Threshold Voltage High (BD9P155EFV-C) Symbol VRTL Min Typ Max Unit 0.718 0.744 0.770 V 3.000 3.065 3.130 V 4.550 4.650 4.750 V 0.738 0.764 0.790 V 3.08 3.16 3.24 V 4.66 4.78 4.90 V Conditions VFB Sweep Down VOUT_SNS Sweep Down VRTH VFB Sweep Up VOUT_SNS Sweep Up VRESET = 5.0 V, VFB = 0.8 V VIN = 2 V, VEN = 0 V IRESET = 1 mA Reset Leakage Current IRSTLK - 0 1 A Reset ON Resistance RRST - 190 400 Reset Active Time tRSTNACT 2.0 3.6 5.0 ms Reset Filtering Time tRSTNFILT 1 5 10 s VOVPH 0.825 0.860 0.895 V VFB Sweep Up VOVPL 0.805 0.840 0.875 V VFB Sweep Down 9.0 9.5 10.0 V 3.402 3.541 3.693 V 5.156 5.379 5.595 V 8.5 9.0 9.5 V 3.321 3.455 3.609 V 5.033 5.249 5.467 V 0.68 0.72 0.76 V 2.81 2.97 3.14 V 4.25 4.50 4.75 V 0.60 0.64 0.68 V 2.48 2.64 2.81 V 3.75 4.00 4.25 V 1.20 1.33 1.45 V/V OVP/SCP FB OVP Threshold Voltage High (BD9P105EFV-C) FB OVP Threshold Voltage Low (BD9P105EFV-C) VOUT_SNS OVP Threshold Voltage High (BD9P105EFV-C) VOUT_SNS OVP Threshold Voltage High (BD9P135EFV-C) VOUT_SNS OVP Threshold Voltage High (BD9P155EFV-C) VOUT_SNS OVP Threshold Voltage Low (BD9P105EFV-C) VOUT_SNS OVP Threshold Voltage Low (BD9P135EFV-C) VOUT_SNS OVP Threshold Voltage Low (BD9P155EFV-C) SCP Threshold Voltage High (BD9P105EFV-C) SCP Threshold Voltage High (BD9P135EFV-C) SCP Threshold Voltage High (BD9P155EFV-C) SCP Threshold Voltage Low (BD9P105EFV-C) SCP Threshold Voltage Low (BD9P135EFV-C) SCP Threshold Voltage Low (BD9P155EFV-C) SCP Deactivate Rate of VIN/VOUT_SNS www.rohm.com (c) 2019 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 VSNSOVPH VSNSOVPL VSCPH VOUT_SNS Sweep Up VOUT_SNS Sweep Down VFB Sweep Up VOUT_SNS Sweep Up VSCPL VFB Sweep Down VOUT_SNS Sweep Down VSCP_DACT 12/57 SCP function is deactivated this value or less TSZ02201-0J1J0AL01480-1-2 08.Apr.2020 Rev.002 BD9P1x5EFV-C Series 10 0.816 9 0.812 Feedback Reference Voltage : VFB1[V] Shutdown Current : I SDWN [A] Typical Performance Curves 8 7 Ta = +125 C 6 5 Ta = +25 C 4 3 2 Ta = -40 C 1 0.808 0.804 0.800 0.796 0.792 0.788 0.784 0 0 5 10 15 20 25 30 Input Voltage : VIN[V] 35 -50 40 Figure 9. Shutdown Current vs Input Voltage -25 0 25 50 75 Temperature : Ta[C] 100 125 Figure 10. Feedback Reference Voltage vs Temperature (BD9P105EFV-C) 5.100 3.345 5.075 Output Voltage : VOUT_SNS1[V] Output Voltage : VOUT_SNS1[V] 3.360 3.330 3.315 3.300 3.285 3.270 3.255 5.050 5.025 5.000 4.975 4.950 4.925 3.240 4.900 -50 -25 0 25 50 75 Temperature : Ta[C] 100 125 -50 Figure 11. Output Voltage vs Temperature (BD9P135EFV-C) www.rohm.com (c) 2019 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 -25 0 25 50 75 Temperature : Ta[C] 100 125 Figure 12. Output Voltage vs Temperature (BD9P155EFV-C) 13/57 TSZ02201-0J1J0AL01480-1-2 08.Apr.2020 Rev.002 BD9P1x5EFV-C Series Typical Performance Curves - continued 3.15 VREG Under Voltage Lockout : VUVLO [V] VIN Power On Reset Rising : V POR_R [V] 4.0 3.9 3.8 3.7 3.05 Rising 3.00 2.95 2.90 2.85 2.80 Falling 2.75 2.70 3.6 -50 -25 0 25 50 75 Temperature : Ta[C] 100 -50 125 -25 0 25 50 75 Temperature : Ta[C] 100 125 Figure 14. VREG Under Voltage Lockout vs Temperature Figure 13. VIN Power On Reset Rising vs Temperature 2.0 1.00 0.80 1.8 High 0.60 EN Input Current : I EN[A] EN Input Voltage : VEN[V] 3.10 1.6 1.4 1.2 Low 1.0 Ta = -40 C, +25 C, +125 C 0.40 0.20 0.00 -0.20 -0.40 -0.60 -0.80 0.8 -50 -25 0 25 50 75 Temperature : Ta[C] 100 -1.00 125 0 10 15 20 25 30 EN Voltage : VEN[V] 35 40 Figure 16. EN Input Current vs EN Voltage Figure 15. EN Input Voltage vs Temperature www.rohm.com (c) 2019 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 5 14/57 TSZ02201-0J1J0AL01480-1-2 08.Apr.2020 Rev.002 BD9P1x5EFV-C Series Typical Performance Curves - continued 10 1.8 MODE, OCP_SEL, SSCG Input Current : I MODE,ISEL,ISSCG[A] MODE, OCP_SEL, SSCG Input Voltage : VMODE,VSEL,VSSCG[V] 2.0 High 1.6 1.4 Low 1.2 1.0 0.8 MODE Ta = +125 C Ta = +25 C Ta = -40 C 8 7 6 5 4 3 2 OCP_SEL, SSCG Ta = -40 C, +25 C, +125 C 1 0 -1 -50 -25 0 25 50 75 100 125 Temperature : Ta[C] 0 Figure 17. MODE, OCP_SEL, SSCG Input Voltage vs Temperature 1 2 3 4 5 MODE, OCP_SEL, SSCG Voltage : VMODE,VOCP_SEL,VSSCG[V] 6 Figure 18. MODE, OCP_SEL, SSCG Input Current vs MODE, OCP_SEL, SSCG Voltage 2.40 Over Current Protection Threshold : I OCP[A] 1.5 2.35 Switching Frequency : fSW[MHz] 9 2.30 2.25 2.20 2.15 2.10 2.05 2.00 1.4 IOCP10 (OCP_SEL = High) 1.3 1.2 1.1 1.0 0.9 0.8 IOCP05 (OCP_SEL = Low) 0.7 0.6 0.5 -50 -25 0 25 50 75 Temperature : Ta[C] 100 Figure 19. Switching Frequency vs Temperature www.rohm.com (c) 2019 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 125 -50 -25 0 25 50 75 Temperature : Ta[C] 100 125 Figure 20. Over Current Protection Threshold vs Temperature 15/57 TSZ02201-0J1J0AL01480-1-2 08.Apr.2020 Rev.002 BD9P1x5EFV-C Series Typical Performance Curves - continued 290 Low Side FET ON Resistance : R ONL[m] High Side FET ON Resistance : R ONH [m] 440 350 VBST-VSW = 3.3 V 260 170 VBST-VSW = 5.0 V VVCC_EX = 3.3 V 170 110 VVCC_EX = 5.0 V 50 80 -50 -25 0 25 50 75 Temperature : Ta[C] 100 -50 125 Figure 21. High Side FET ON Resistance vs Temperature -25 0 25 50 75 Temperature : Ta[C] 100 125 Figure 22. Low Side FET ON Resistance vs Temperature 0.780 3.240 3.200 Reset Threshold Voltage : VRT[V] Reset Threshold Voltage : VRT[V] 230 High 0.767 High 3.160 0.754 3.120 3.080 0.741 3.040 Low Low 0.728 3.000 -50 -25 0 25 50 75 Temperature : Ta[C] 100 125 -50 Figure 23. Reset Threshold Voltage vs Temperature (BD9P105EFV-C) www.rohm.com (c) 2019 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 -25 0 25 50 75 Temperature : Ta[C] 100 125 Figure 24. Reset Threshold Voltage vs Temperature (BD9P135EFV-C) 16/57 TSZ02201-0J1J0AL01480-1-2 08.Apr.2020 Rev.002 BD9P1x5EFV-C Series Typical Performance Curves - continued 0.880 Reset Threshold Voltage : VRT[V] 4.850 FB OVP Threshold Voltage : VOVP[V] 4.900 High 4.800 4.750 4.700 4.650 4.600 0.860 0.850 0.840 0.830 Low Low 0.820 4.550 -50 -25 0 25 50 75 Temperature : Ta[C] 100 -50 125 Figure 25. Reset Threshold Voltage vs Temperature (BD9P155EFV-C) VOUT_SNS OVP Threshold Voltage : VSNSOVP[V] High 9.75 9.50 9.25 9.00 Low 8.75 -25 0 25 50 75 Temperature : Ta[C] 100 125 Figure 26. FB OVP Threshold Voltage vs Temperature (BD9P105EFV-C) 10.00 VOUT_SNS OVP Threshold Voltage : VSNSOVP[V] High 0.870 8.50 5.50 5.24 BD9P155EFV-C High Low 4.97 4.71 4.44 4.18 BD9P135EFV-C High Low 3.91 3.65 3.38 -50 -25 0 25 50 75 Temperature : Ta[C] 100 125 -50 Figure 27. VOUT_SNS OVP Threshold Voltage vs Temperature (BD9P105EFV-C) www.rohm.com (c) 2019 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 -25 0 25 50 75 Temperature : Ta[C] 100 125 Figure 28. VOUT_SNS OVP Threshold Voltage vs Temperature (BD9P135EFV-C/BD9P155EFV-C) 17/57 TSZ02201-0J1J0AL01480-1-2 08.Apr.2020 Rev.002 BD9P1x5EFV-C Series Function Explanation 1. TM Nano Pulse Control TM Nano Pulse Control is an original technology developed by ROHM Co., Ltd. It enables to control voltage stably, which is difficult in the conventional technology, even in a short SW ON time such as less than 50 ns at typical condition. Narrow SW ON Pulse enables direct convert of high output voltage to low output voltage. The output voltage VOUT 3.3 V can be output directly from the supply voltage VIN 24 V at 2.2 MHz. VSW (5 V/div) fSW = 2.2 MHz VIN = 24 V VOUT = 3.3 V (5 V/div) Time (100 ns/div) Figure 29. Switching Waveform (VIN = 24 V, VOUT = 3.3 V, IOUT = 0.5 A, fSW = 2.2 MHz 2. Light Load Mode Control and Forced PWM Mode Control BD9P1x5EFV-C is a synchronous DC/DC converter with integrated POWER MOSFETs and realizes high transient response by using current mode Pulse Width Modulation (PWM) mode control architecture. Under a heavy load, the switching operation is performed with the PWM mode control at a fixed frequency. When the load is lighter, the operation is changed over to the Light Load Mode (LLM) control to improve the efficiency. Efficiency [%] Light Load Mode PWM Mode Output Current IOUT [A] Figure 30. Efficiency (Light Load Mode, PWM Mode) www.rohm.com (c) 2019 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 18/57 TSZ02201-0J1J0AL01480-1-2 08.Apr.2020 Rev.002 BD9P1x5EFV-C Series 2. Light Load Mode control and Forced PWM Mode control - continued If the output load decreases below 200 mA (Typ) (OCP_SEL = H), the output voltage rises and power state is changed to SLEEP state when the output voltage exceeds to VFB2 (101.3 % of its setting voltage VFB1). During SLEEP state, switching operation is stopped and the circuit current is reduced by stopping the circuit operation except for the monitor circuit of output voltage monitor. Then, the switching operation restarts when the output voltage decreases less than VFB3 (101.0 % of its setting voltage VFB1) by the load current. If the light load mode operation is not required, the IC operates in forced PWM mode by applying high voltage or an external clock to the MODE pin. In forced PWM mode, the IC operates with fixed frequency regardless of the output load and the ripple voltage of output can be reduced. Also, during soft start time, the IC operates in forced PWM mode regardless of the condition of the MODE pin. After detecting RESET high, the IC operates according to the MODE pin condition. If OCP_SEL set low level, then the threshold current of switched between PWM mode and LLM is changed to 100 mA (Typ). In addition, good EMI performance in AM band may not be provided by a load condition in LLM. To avoid this, use Forced PWM mode. VEN VFB2 = VFB1 x 101.3 % (Typ) VFB3 = VFB1 x 101.0 % (Typ) VFB1 VOUT 200 mA IL 200 mA IOUT VRESET Figure 31. Timing Chart in Light Load Mode (OCP_SEL = H) VEN VFB2 = VFB1 x 101.3 % (Typ) VFB3 = VFB1 x 101.0 % (Typ) VFB1 VOUT 200 mA IL 200 mA IOUT VRESET Figure 32. Timing Chart in Light Load Mode after Detecting RESET High (OCP_SEL = H) www.rohm.com (c) 2019 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 19/57 TSZ02201-0J1J0AL01480-1-2 08.Apr.2020 Rev.002 BD9P1x5EFV-C Series Function Explanation - continued 3. Enable Control The device shutdown can be controlled by the EN pin. When VEN reaches VENH (2.0 V) or higher, the internal circuit is activated. When the VOUT_DIS pin is connected to output voltage and the EN pin is low, the VOUT_DIS pin is pulled down by the resistance of RDIS (75 , Typ) and discharges the output voltage. This discharge function is deactivated when VOUT_DIS voltage falls below VDISL (200 mV, Typ) at once or 30 ms (Typ) pass after the EN pin becomes high. After being deactivated, the VOUT starts up with soft start operation. The delay time tDLY (400 s, Typ) is implemented from the EN pin becoming high to VOUT starting up regardless of VOUT_DIS voltage. The soft start time (VOUT x 0.1 to VOUT x 0.9) is set to tSS (3.0 ms, Typ). When an EN voltage becomes VENL (0.8 V) or less, the device is shut down. When discharge function is not required, connect the VOUT_DIS pin to GND. VENH 2.0 V VEN VENL 0.8 V 90 % tDLY 400 s (Typ) ON Discharge VDISL 200 mV (Typ) VDISL 200 mV (Typ) 10 % VOUT tSS 3.0 ms (Typ) tSS x 1.25 OFF tDLY 400 s (Typ) 30 ms (Typ) Figure 33. Enable ON/OFF Timing Chart 4. Reset Function For BD9P105EFV-C, the reset function monitors the FB pin voltage. When the output voltage reaches VRTH (95.3 %, Typ) or more of the normal regulation voltage, the open drain MOSFET on the RESET pin is turned off in tRSTNACT (3.6 ms, Typ) and the output of the RESET pin becomes high by its pull-up resistor. In addition, when the FB voltage reaches VRTL (92.8 %, Typ) or less, the open drain MOSFET on the RESET pin is turned on and the RESET pin is pulled down with an impedance of RRST (190 , Typ). To reject noise, the filtering time tRSTNFILT (5 s, Typ) is implemented after FB voltage decreases below its threshold voltage (VRTL). The reset function also works when output over voltage is detected. When the output voltage reaches VOVPH (107.3 %, Typ) or more, the open drain MOSFET on the RESET pin is turned on. Then, when the FB voltage goes below VOVPL (104.7 %, Typ) or less, the open drain MOSFET on the RESET pin is turned off. The reset active time and filtering time are activated when over voltage conditions are detected. For BD9P135EFV-C and BD9P155EFV-C, this function monitors the VOUT_SNS pin voltage. The RESET output voltage low level (VRESET_LOW(Max)) when the open drain MOSFET is turned on is calculated by the following equation. It is recommended to use resistance of 5 k to 100 k and pull it up to the VREG pin or the power supply in the absolute maximum voltage ratings of the RESET pin. During shutdown condition, the RESET pin is pulled down regardless the output voltage as far as VIN is 2 V or higher. VOVPH = VFB1 x 107.3 % (Typ) VOVPL = VFB1 x 104.7 % (Typ) VFB1 VRTH = VFB1 x 95.3 % (Typ) VRTL = VFB1 x 92.8 % (Typ) VOUT VRESET tRSTNACT Under tRSTNFILT 3.6 ms (Typ) Under 5 s (Typ) tRSTNFILT tRSTNACT Under tRSTNFILT tRSTNFILT tRSTNACT 5 s (Typ) 3.6 ms (Typ) Under 5 s (Typ) 5 s (Typ) 3.6 ms (Typ) Figure 34. Reset Timing Chart (BD9P105EFV-C) _() = - x () () +- [V] Where: _() - () - www.rohm.com (c) 2019 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 is the RESET Low voltage level (Max) [V] is the Voltage of pull-up power source [V] is the RESET ON Resistance (Max) [] is the value of pull-up resistor to VPULL_UP [] 20/57 TSZ02201-0J1J0AL01480-1-2 08.Apr.2020 Rev.002 BD9P1x5EFV-C Series Function Explanation - continued 5. External Synchronization Function By applying clock signal to the MODE pin, the switching frequency can be synchronized to the external clock signal. When clock signal is applied with the synchronization frequency range between 1.8 MHz and 2.4 MHz and the duty range between 25 % and 75 %, the Synchronous mode is started after 4 rising edges of the clock signal. In addition, this function is enabled after VRESET becomes high. If the duration between each rising edge exceeds 0.9 s (Typ) or more, the Synchronous mode is deactivated and switching operation by internal clock is activated (the Non-Synchronous mode). The Spread Spectrum function cannot be activated during the Synchronous mode. VIN VEN VRTH VOUT VSW VRESET tDLY 400 s (Typ) tRSTNACT 3.6 ms (Typ) VMODE 0.9 s (Typ) Non-Synchronous Synchronous Non-Synchronous Synchronous Figure 35. External Synchronization Function www.rohm.com (c) 2019 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 21/57 TSZ02201-0J1J0AL01480-1-2 08.Apr.2020 Rev.002 BD9P1x5EFV-C Series Function Explanation - continued 6. Frequency Division Function This device drives the High Side FET with a bootstrap and requires the ON time of the Low Side FET to charge the BST pin. Therefore, the minimum OFF time of the SW pin is specified, and the output voltage is limited by the minimum OFF time under the condition in which the voltage between input and output are close. To prevent this situation, OFF pulses are skipped when the voltage between input and output are small to keep the High Side FET turned on and increase the ON duty of the SW pin. The OFF pulse skip is done for 7 consecutive switching cycles in maximum (The switching frequency becomes a one eighth of nominal frequency). In this case, the output voltage can be calculated with the following equation. = x ( - x ) - x = (1 - x ) x ( - x ) - x [V] 8 Where: is the SW pin Maximum ON Duty Cycle [%] is the Input Voltage [V] is the High Side FET ON Resistance [] (Refer to page 11) is the Output Current [A] is the DCR of Inductor [] is the SW pin Minimum OFF Time [s] (Refer to page 10) is the Switching Frequency [Hz] (Refer to page 11) VIN VOUT VSW Figure 36. Frequency Division Function www.rohm.com (c) 2019 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 22/57 TSZ02201-0J1J0AL01480-1-2 08.Apr.2020 Rev.002 BD9P1x5EFV-C Series Function Explanation - continued 7. Spread Spectrum Function Connecting the SSCG pin with the VREG pin activates the Spread Spectrum function, reducing the EMI noise level. When the Spread Spectrum function is activated, the switching frequency is varied with triangular wave of fSSCG (4.5 %, Typ) amplitude centered on typical frequency f SW (2.2 MHz, Typ). The period of the triangular wave is tSSCG_CYCLE (466 s, Typ). However, this function is masked when the RESET output is low. Connecting the SSCG pin with GND deactivates this function. VIN VEN VRTH tSSCG_CYCLE 466 s (Typ) VOUT fSW VRESET fSW 2.2 MHz (Typ) fSSCG = +4.5 % (Typ) fSSCG = -4.5 % (Typ) tRSTNACT 3.6 ms (Typ) tDLY 400 s (Typ) VSSCG SSCG OFF SSCG ON Figure 37. Spread Spectrum Function www.rohm.com (c) 2019 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 23/57 TSZ02201-0J1J0AL01480-1-2 08.Apr.2020 Rev.002 BD9P1x5EFV-C Series Function Explanation - continued 8. VCC_EX Function This IC has the function that supplies power from VOUT to internal supply VREG to improve the efficiency. When VVCC_EX goes above VTEXH (3.05 V, Typ) or more, VREG is supplied from the VCC_EX pin. In case of the VCC_EX pin connected with VOUT, the output voltage is used as a power supply for the internal circuitry and driver block. To protect the internal circuit, VOUT is reduced with PWM switching when VCC_EX voltage exceeds VEXOVPH (6.0 V, Typ). Therefore, the VCC_EX pin connection can be used when the output voltage is in the range of between VTEXH (3.2 V, Max) and VEXOVPL (5.65 V, Min). Connect the VCC_EX pin with GND when VCC_EX function is not required. The bias current IBIAS using VCC_EX function can be calculated using the following formula. 1 = _1 + __1 x x _ [A] Where: _1 __1 _ is total current from VIN [A] is quiescent current from VIN (without current from VCC_EX) [A] (Refer to page 10) is quiescent current from VCC_EX [A] (Refer to page 10) is efficiency of Buck Converter is the VCC_EX voltage [V] is the input voltage [V] VIN VREG VCC_EX VREG (LDO) + ON/OFF ON/OFF VTEXH = 3.05 V (Typ) / V TEXL = 2.90 V (Typ) Figure 38. VCC_EX Block Diagram VIN VEN Vout Setting Level VTEXH 3.05 V (Typ) VTEXL 2.90 V (Typ) VOUT = VVCC_EX (Short) VSW VREG 3.3 V (Typ) Vout Setting Level VREG VCC_EX State VCC_EX OFF VCC_EX ON VCC_EX OFF Figure 39. VCC_EX Timing Chart www.rohm.com (c) 2019 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 24/57 TSZ02201-0J1J0AL01480-1-2 08.Apr.2020 Rev.002 BD9P1x5EFV-C Series Protect Function 1. Over Current Protection (OCP) The Over Current Protection (OCP) monitors the average inductor current. The OCP detection level can be selected by the OCP_SEL pin. When the OCP_SEL voltage is high, it is IOCP10 (1.250 A, Typ) and when the OCP_SEL voltage is low, it is IOCP05 (0.625 A, Typ). When the average inductor current exceeds to its setting value, the duty cycle of the switching is limited and the output voltage decreases. This protection circuit is effective in preventing damage due to sudden and unexpected incidents. However, the IC should never be used in applications where the protection circuit operates continuously (e.g. when a load that significantly exceeds the output current capability of the chip is connected). IOCP IL IOUT VOUT Figure 40. Over Current Protection 2. Short Circuit Protection (SCP) For BD9P105EFV-C, the Short Circuit Protection (SCP) block compares the FB pin voltage with the internal reference voltage VREF. When the FB pin voltage has decreased to VSCPL (0.64 V, Typ) or less and remained there for 0.9 ms (Typ), SCP stops the operation for 30 ms (Typ) and subsequently initiates a restart. If the FB pin voltage decreases to VSCPL (0.64 V, Typ) or less and increases to VSCPH (0.72 V, Typ) or more within 0.9 ms afterwards, SCP protection is released and output voltage recovers to normal operation. For BD9P135EFV-C and BD9P155EFV-C, the SCP block monitors the VOUT_SNS pin for the protection. SCP detection voltage VSCPL is 80 % (Typ) of normal output voltage. On the other hand, SCP release voltage VSCPH is 90 % (Typ) of normal output voltage. The SCP function is deactivated during 7 ms (Typ) from VOUT starting up. In addition, when VIN decreases and VOUT also decreases, the SCP function is deactivated not to detect short circuit protection. The SCP function is likewise deactivated when VIN voltage is lower than VSCP_DACT (133 %, Typ) of the VOUT_SNS pin voltage, and then is activated after 7 ms (Typ) from VIN voltage exceeds VSCP_DACT (133 %, Typ) of the VOUT_SNS pin voltage. Therefore, in the case of short circuit from VIN close to VOUT condition, SCP stops the switching operation after 7.9 ms (Typ) from short circuit. However, the device should never be used in applications characterized by continuous operation of the protection circuit (e.g. when a load that significantly exceeds the output current capability of the chip is connected). Output Load Condition Normal Over Load Normal VIN VOUT x 133 % 33 % VOUT VOUT x 133 % 33 % 100 % 100 % VFB VSCPH:0.72 V (Typ) VSCPL:0.64 V (Typ) 0.9 ms (Typ) VSW Inductor Current (Internal) SCP Mask Delay Signal 0.9 ms (Typ) 0.9 ms (Typ) HiZ HiZ OCP Threshold OCP Threshold 7 ms (Typ) 7 ms (Typ) 7 ms (Typ) 7.9 ms (Typ) (Internal) HICCUP Delay Signal 30 ms (Typ) 30 ms (Typ) SCP Reset SCP Reset Figure 41. Short Circuit Protection (SCP) Timing Chart (BD9P105EFV-C) www.rohm.com (c) 2019 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 25/57 TSZ02201-0J1J0AL01480-1-2 08.Apr.2020 Rev.002 BD9P1x5EFV-C Series Protect Function - continued 3. Power On Reset (POR)/Under Voltage Lockout Protection (UVLO) The UVLO and POR are integrated to prevent the malfunction when the power supply voltage is decreased. The POR monitors the VIN pin voltage. On the other hand, UVLO monitors the VREG pin voltage. In the sequence of VIN rising, the VREG pin voltage also rises up to 3.3 V (Typ) following VIN voltage. First, UVLO is released when VREG voltage increase above VUVLO_R (2.95 V, Typ). Next, POR is released when VIN voltage increase above VPOR_R (3.8 V, Typ). When both POR and UVLO are released, the IC starts up with soft start. In the sequence of VIN falling, VREG voltage also falls. When VREG voltage decreases below VUVLO_F (2.85 V, Typ), UVLO is detected and puts the IC goes into standby state. At the same time, POR is detected. When the VCC_EX pin is connected to VOUT, VREG voltage supplied from VCC_EX. In this case, drop voltage between VIN and VREG becomes larger than the case of VCC_EX connected to GND because VOUT voltage is restricted by maximum duty at low VIN condition. Therefore, UVLO is detected at higher VIN condition than the case when the VCC_EX pin is connected to GND. VPOR_R 3.8 V (Typ) 3.3 V (Typ) VUVLO_R 2.95 V (Typ) VUVLO_F 2.85 V (Typ) VIN VREG POR UVLO VOUT Figure 42. POR/UVLO Timing Chart www.rohm.com (c) 2019 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 26/57 TSZ02201-0J1J0AL01480-1-2 08.Apr.2020 Rev.002 BD9P1x5EFV-C Series Protect Function - continued 4. Thermal Shutdown (TSD) This IC has a built-in thermal shutdown circuit that prevents heat damage to the IC. If junction temperature (Tj) exceeds TSD detection temperature (175 C, Typ), the POWER MOSFETs are turned off. When the Tj falls below the TSD temperature (150 C, Typ), the IC restarts up with soft start. Where the input voltage required for the restart is the same as that for the initial startup (Input voltage 4.0 V or more). Note that the TSD circuit operates in a situation that exceeds the absolute maximum ratings and therefore, under no circumstances, should the TSD circuit be used in a set design or for any purpose other than protecting the IC from heat damage. VIN VEN TSD Detect 175 C (Typ) TSD Release 150 C (Typ) Tj VREG VUVLO_R 2.95 V (Typ) VRTH VOUT tDLY 400 s (Typ) VRESET tRSTNACT 3.6 ms (Typ) Figure 43. TSD Timing Chart www.rohm.com (c) 2019 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 27/57 TSZ02201-0J1J0AL01480-1-2 08.Apr.2020 Rev.002 BD9P1x5EFV-C Series 5. Over Voltage Protection (OVP) This IC has Over Voltage Protection (OVP) monitoring FB to prevent the increase of output voltage in case of external injected current to VOUT. When FB voltage exceeds VOVPH (107.3 % of its setting voltage VFB1), the switching regulator sinks current from VOUT by changing state to PWM. The sink current during OVP is restricted to INCP (0.625 A, Typ) (OCP_SEL = L). In addition, the RESET pin is pulled down to GND during OVP detection. To prevent the malfunction by noise, the internal delay tRSTNFILT of 5 s (Typ) is implemented after OVP detection. When FB voltage falls below VOVPL (104.7 % of its setting voltage VFB1), OVP function is released. The RESET pin is kept low and PWM switching is also kept during tRSTNACT (3.6 ms, Typ) after OVP function is released. When OCP_SEL is set high level, then INCP value is changed to INCP (1.250 A, Typ). If the FB pin is open, this IC cannot regulate VOUT correctly. In this case, if VOUT voltage exceeds VSNSOVPH or VCC_EX voltage exceed VEXOVPH, the VOUT is pulled down by PWM switching to protect internal devices same as the situation that the FB pin over voltage is detected. VOUT VOVPH VOVPL VFB IL INCP VSW tRSTNACT VRESET tRSTNFILT Figure 44. FB OVP Timing Chart VEXOVPH/VSNSOVPH VEXOVPL/VSNSOVPL VOUT VFB IOCP IL INCP VSW VRESET < tRSTNACT tRSTNFILT Figure 45. VCC_EX/VOUT_SNS OVP Timing Chart www.rohm.com (c) 2019 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 28/57 TSZ02201-0J1J0AL01480-1-2 08.Apr.2020 Rev.002 BD9P1x5EFV-C Series 5. Over Voltage Protection (OVP) - continued If VOUT is shorted to the Battery Line as following figure, the DC/DC converter (BD9P1x5EFV-C) sinks current from VOUT to the Low Side FET. If a Reverse Polarity Protection Diode is on the Battery Line, the VIN voltage results in being boosted up and might exceed the absolute maximum ratings. Battery Line Battery Line Reverse Polarity Protection Diode D VIN SW DC/DC Converter L1 VOUT Figure 46. VOUT shorted to Battery Line www.rohm.com (c) 2019 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 29/57 TSZ02201-0J1J0AL01480-1-2 08.Apr.2020 Rev.002 BD9P1x5EFV-C Series Selection of Components Externally Connected Contact us if not use the recommended constant in the application circuit. Necessary parameters in designing the power supply are as follows: Table 1. Application Sample Specification Parameter Symbol Input Voltage Specification Case VIN 3.5 V to 40 V Output Voltage VOUT 5.0 V Output Ripple Voltage VP-P 20 mVp-p Output Current IOUT Typ 0.5 A/Max 1.0 A Switching Frequency fSW 2.2 MHz Operating Temperature Range Ta -40 C to +125 C CBST VIN VIN BST VCC_EX VOUT_DIS FB VOUT_SNS EN CBLK CIN PGND VOUT RFB1 COUT RRST RESET VREG CREG L1 SW PVIN OCP_SEL GND MODE VMODE SSCG VSSCG RFB2 Figure 47. Application Sample Circuit www.rohm.com (c) 2019 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 30/57 TSZ02201-0J1J0AL01480-1-2 08.Apr.2020 Rev.002 BD9P1x5EFV-C Series Selection of Components Externally Connected - continued 1. Selection of the inductor L1 value The inductor in the switching regulator supplies a continuous current to the load and functions as a filter to smooth the output voltage. When a large inductor is selected, the Inductor ripple current IL and the output voltage ripple VP-P are reduced. It is the trade-off between the size and the cost of the inductor. The inductance of the inductor is shown by the following equation: = (() - )x [H] () x x Where: () is the input voltage (Max) [V] is the output voltage [V] is the switching frequency [Hz] is the peak to peak inductor current [A] In current mode control, the sub-harmonic oscillation may happen. The slope compensation is integrated into the IC to prevent the sub-harmonic oscillation. The sub-harmonic oscillation depends on the rate of increase of output switch current. If the inductor value is too small, the sub-harmonic oscillation may happen because the inductor ripple current IL is increased. If the inductor value is too large, the feedback loop may not achieve stability because the inductor ripple current IL is decreased. Therefore, the recommended inductor value range for each output current is shown below. Table 2. Inductor range of each output current Output Voltage OCP_SEL Maximum Output Current 1.1 V to 8.5 V 0.8 V to 1.1 V Inductor Range H 1.0 A 4.7 H to 15 H L 0.5 A 4.7 H to 15 H H 1.0 A 10 H to 15 H L 0.5 A 10 H to 15 H If the IL becomes small, the Inductor core loss (iron loss), the loss due to ESR of the output capacitor and the V P-P (Output peak-to-peak ripple voltage) are also reduced. VP-P is shown in the following equation. - = x + 8x x [V] (a) Where: is the equivalent series resistance of the output capacitor [] is the output capacitance [F] is the peak to peak inductor current [A] is the switching frequency [Hz] Even if IL is large, the VP-P target is usually satisfied by using a ceramic capacitor because it has a low ESR. The advantage of this is that the inductance value can be set smaller. It also contributes to the miniaturization of the application board because when the inductance value is small, the inductor that has large rated current and is small can be selected. The disadvantages are increase of core losses in the inductor. The shielded type (closed magnetic circuit type) is the recommended type of inductor to be used. It is important not to magnetic saturate the core in any situation, so please make sure that the definition of rated current is different according to the manufactures. Please check the rated current at maximum ambient temperature of application to inductor manufacturer. www.rohm.com (c) 2019 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 31/57 TSZ02201-0J1J0AL01480-1-2 08.Apr.2020 Rev.002 BD9P1x5EFV-C Series Selection of Components Externally Connected - continued 2. Selection of Output Capacitor COUT The output capacitor is selected based on the ESR that is required from the previous page equation (a). VP-P can be reduced by using a capacitor with a small ESR. The ceramic capacitor is the best option that meets this requirement. It is because not only it has a small ESR but the ceramic capacitor also contributes to the size reduction of the application circuit. Please confirm the frequency characteristics of ESR from the datasheet of the capacitor manufacturer, and consider a low ESR value for the switching frequency being used. It is necessary to consider that the capacitance of the ceramic capacitor changes obviously according to DC biasing characteristic. For the voltage rating of the ceramic capacitor, twice or more the maximum output voltage is usually required. By selecting a high voltage rating, it is possible to reduce the influence of DC bias characteristics. Moreover, in order to maintain good temperature characteristics, the one with the characteristics of X7R or better is recommended. Because the voltage rating of a large ceramic capacitor is low, the selection becomes difficult for an application with high output voltage. In that case, please connect multiple ceramic capacitors. These capacitors are rated in ripple current. The RMS values of the ripple current that can be obtained in the following equation and must not exceed the ripple current rating. () = 12 [A] Where: () is the value of the ripple electric current [A] is the peak to peak inductor current [A] Next, when the output setting voltage is 3.3 V or more, the output ceramic capacitor COUT is recommended for 22 F (Typ) or more. When the output setting voltage less than 3.3 V, the output ceramic capacitor COUT is recommended to the following equation. 72.6 [F] Where: is the output voltage [V] When selecting the capacitor ensure that the capacitance COUT_WORST of the following equation is maintained at the characteristics of DC Bias, AC Voltage, temperature and tolerance. The approximate value can be calculated by this formula. 54.5 _ [F] Where: is the output voltage [V] If the capacitance falls below this value, the oscillation may happen. When using the electrolytic capacitor and the conductive polymer hybrid aluminum electrolytic capacitor, please place it in addition to the ceramic capacitors with the capacity described above. Actually, the changes in the frequency characteristic are greatly affected by the type and the condition (temperature, etc.) of parts that are used, the wire routing and layout of the PCB. Please confirm stability and responsiveness in actual application. In addition, for the total value of capacitance in the output line COUT(Max), please choose a capacitance value less than the value obtained by the following equation: () < () x1.25x(() -_() ) [F] Where: () () _() is the OCP operation current (Min) [A] is the Soft Start Time (Min) [s] is the maximum load current during startup [A] is the output voltage [V] If the limits from the above-mentioned are exceeded, Startup failure may happen in 7.9 ms after VOUT starts up. If the capacitance value is extremely large, over-current protection may be activated by the inrush current at startup preventing the output to turn on. Please confirm this on the actual application. Also, in case of large changing input voltage and load current, select the capacitance by verifying that the actual application setup meets the required specification. www.rohm.com (c) 2019 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 32/57 TSZ02201-0J1J0AL01480-1-2 08.Apr.2020 Rev.002 BD9P1x5EFV-C Series Selection of Components Externally Connected - continued 3. Selection of Input Capacitor CIN, CBLK For input capacitors, there are two types of capacitor: decoupling capacitors C IN and bulk capacitors CBLK. Ceramic capacitors with total values 2.3 F or more are necessary for the decoupling capacitors CIN for ripple noise reduction. If a low ESR electrolytic capacitor with large capacitance is connected parallel to the decoupling capacitors as a bulk capacitor, ceramic capacitors with 0.5 F or more are necessary for the decoupling capacitors. (However, to reduce EMI noise level, 2.3 F or more are recommended for ceramic capacitors.) These capacitor values including device variation, temperature characteristics, DC bias characteristics, and aging change must be larger than minimum value. It is effective for switching noise reduction to place one of ceramic capacitor close to the PVIN and the VIN pins. The voltage rating of the capacitors is recommended to be 1.2 times or more the maximum input voltage, or twice the normal input voltage. Also, the IC might not operate properly when the PCB layout or the position of the capacitor is not good. Please check "PCB Layout Design" on page 48. The bulk capacitor is optional. The bulk capacitor prevents the decrease in the line voltage and serves as a backup power supply to keep the input voltage constant. A low ESR electrolytic capacitor with large capacitance is suitable for the bulk capacitor. It is necessary to select the best capacitance value for each of application. In that case, please take note not to exceed the rated ripple current of the capacitor. The RMS value of the input ripple current ICIN(RMS) is obtained in the following equation: () = {() 2 (1 - 1 ) + 12 2 } [A] Where: () is the output current (Max) [A] In addition, in automotive and other applications requiring high reliability, it is recommended to connect the capacitors in parallel to accommodate multiple electrolytic capacitors and minimize the chances of drying up. For ceramic capacitors, it is recommended to make two series + two parallel structures to decrease the risk of capacitor destruction due to short circuit conditions. When the impedance on the input side is high for some reason (because the wiring from the power supply to the VIN pin is long, etc.), then high capacitance is required. In actual conditions, it is necessary to verify that there are no problems like IC is turned off, or the output overshoots due to the change in VIN at transient response. www.rohm.com (c) 2019 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 33/57 TSZ02201-0J1J0AL01480-1-2 08.Apr.2020 Rev.002 BD9P1x5EFV-C Series Selection of Components Externally Connected - continued 4. Selection of Output Voltage Setting Resistor RFB1, RFB2 (BD9P105EFV-C) For the BD9P105EFV-C, the output voltage is set with external resistors RFB1 and RFB2. The reference voltage of GmAmp1 is set to 0.8 V and the IC operates to regulate FB voltage to 0.8 V. The output voltage is defined by the formula (1). RFB1 and RFB2 should be adjusted to set the required output voltage. If RFB1 and RFB2 are large, the current flowing through on these resistors is small and the circuit current at no load can be reduced. However, the phase shift is likely to happen because of the parasitic capacitance of IC and PCB on the FB pin. Therefore, the combined resistance RFB1//RFB2 should be set to 100 k or less. If the combined resistance RFB1//RFB2 is 100 k or more, CFB1 and CFB2 should be chosen to satisfy the formula (2). In this case, the value of CFB1 and CFB2 should be chose the capacitor of 47 pF or more that is much larger than CP. = 1 +2 1 x1 2 x2 2 x 0.8 [V] (1) 1 (2) VOUT CFB1 RFB1 Gm Amp1 FB comp CFB2 0.80 V RFB2 CP Figure 48. Setting for Output Setting Resistor If the voltage between input and output increases and the ON time of the SW decreases to under tONMIN, the switching frequency is decreased. To ensure stable switching frequency, the output voltage must satisfy the following equation. If this equation is not satisfied, the SW pulse is skipped. In this case, the switching frequency decreases and the output voltage ripple increases. () x () x () [V] Where: () () () is the Input Voltage (Max) [V] is the Switching Frequency (Max) [Hz] (Refer to page 11) is the SW Minimum ON time (Max) [s] (Refer to page 10) If the voltage between input and output decreases, the ON time of the SW increases by skipping the off time and the switching frequency is decreased. To keep switching frequency stably, the following equation must be satisfied. () x (1 - () x () ) [V] Where: () is the SW Minimum OFF Time (Max) [s] (Refer to page 10) 5. Selection of the Bootstrap Capacitor For Bootstrap capacitor CBST, please connect a 0.1 F (Typ) ceramic capacitor as close as possible between the BST pin and the SW pin. 6. Selection of the VREG Capacitor. For VREG capacitor CREG, please connect a 1.0 F (Typ) ceramic capacitor between the VREG pin and GND. www.rohm.com (c) 2019 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 34/57 TSZ02201-0J1J0AL01480-1-2 08.Apr.2020 Rev.002 BD9P1x5EFV-C Series Application Examples 1 Table 3. Specification Example 1 Parameter Symbol Specification Case Product Name IC BD9P105EFV-C Input Voltage VIN 8 V to 18 V Output Voltage VOUT 6.0 V Output Current IOUT Typ 0.5 A / Max 1.0 A Ta -40 C to +125 C Operating Temperature Range VBAT LF1 CBST VIN BST VIN PGND VCC_EX VOUT_DIS FB VOUT_SNS VREG RESET EN CF1 CF2 CBLK CIN2 CIN1 CREG L1 VOUT SW PVIN OCP_SEL GND RFB1 COUT1 RRST MODE VMODE SSCG VSSCG COUT2 RFB2 -type filter Figure 49. Reference Circuit 1 Table 4. Application Example 1 Parts List with -type filter No. Package Parameters CF1 (Note 1) 3216 3 Part Name (Series) Type Manufacturer 1 F, X7R, 50 V GCJ31MR71H105K Ceramic MURATA 2.2 H CLF6045NIT-2R2N-D Inductor TDK MURATA NICHICON LF1 W6.0 x H4.5 x L6.3 mm CF2 1005 0.1 F, X7R, 50 V GCM155R71H104K CBLK 10 mm x L10 mm 220 F, 35 V UWD1V221MCL1GS 3216 1 F, X7R, 50 V GCJ31MR71H105K Ceramic Electrolytic capacitor Ceramic CIN1 1005 0.1 F, X7R, 50 V GCM155R71H104K Ceramic MURATA CREG 2012 1 F, X7R, 16 V GCM21BR71C105K Ceramic MURATA CBST 1005 0.1 F, X7R, 50 V GCM155R71H104K Ceramic MURATA 10 k, 1 %, 1/16 W MCR01MZPF1002 Chip resistor ROHM 4.7 H CLF6045NIT-4R7N-D Inductor TDK 22 F, X7R, 10 V GCM32ER71A226K Ceramic MURATA CIN2 (Note 1) RRST 1005 L1 W6.0 x H4.5 x L6.3 mm COUT1 3225 3 MURATA COUT2 - Open - - - RFB1 1005 130 k, 1 %, 1/16 W MCR01MZPF1303 Chip resistor ROHM RFB2 1005 20 k, 1 %, 1/16 W MCR01MZPF2002 Chip resistor ROHM (Note 1) To reduce EMI noise level, 4.7 F, (3225, X7R, 50 V, GCM32ER71H475K) is recommended for CF1 and CIN2. Table 5. Application Example 1 Parts List without -type filter No. Package Parameters Part Name (Series) Type Manufacturer CF1 - Open - - - LF1 - Open - - - CF2 - Open - - - CBLK - Open - - - CIN2 3225 4.7 F, X7R, 50 V GCM32ER71H475K Ceramic MURATA CIN1 1005 0.1 F, X7R, 50 V GCM155R71H104K Ceramic MURATA www.rohm.com (c) 2019 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 35/57 TSZ02201-0J1J0AL01480-1-2 08.Apr.2020 Rev.002 BD9P1x5EFV-C Series Application Examples 1 - continued (Ta = 25 C) 1000 100 90 MODE = High 100 70 Input Current [mA] Efficiency [%] 80 MODE = Low 60 50 40 30 10 1 MODE = High 20 0.1 MODE = Low 10 0 0.01 0.01 0.1 1 10 100 Output Current [mA] 1000 1 10 100 1000 Figure 51. Input Current vs Output Current (VIN = 12 V) 180 135 Phase 40 90 20 45 0 VMODE (5 V/div) Phase [deg] 60 Gain [dB] 0.1 Output Current [mA] Figure 50. Efficiency vs Output Current (VIN = 12 V) 80 0.01 0 -20 -45 Gain VOUT (100 mV/div) offset 6 V -40 -90 -60 -135 -80 -180 100 1k 10k 100k Frequency [Hz] Time (200 s/div) 1M Figure 52. Frequency Characteristic (VIN = 12 V, IOUT = 0.5 A) www.rohm.com (c) 2019 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 VSW (5 V/div) Figure 53. MODE ON/OFF Response (VIN = 12 V, IOUT = 50 mA) 36/57 TSZ02201-0J1J0AL01480-1-2 08.Apr.2020 Rev.002 BD9P1x5EFV-C Series Application Examples 1 - continued (Ta = 25 C) IOUT (0.5 A/div) IOUT (0.5 A/div) VOUT (100 mV/div) offset 6 V VOUT (100 mV/div) offset 6 V Time (1 ms/div) Time (1 ms/div) Figure 54. Load Response 1 (VIN = 12 V, VMODE = 5 V, IOUT = 0 A to 1 A) Figure 55. Load Response 2 (VIN = 12 V, VMODE = 0 V, IOUT = 0 A to 1 A) VIN (5 V/div) VIN (2 V/div) VOUT (2 V/div) VOUT (100 mV/div) offset 6 V Time (200 s/div) Figure 56. Line Response 1 (VIN = 16 V to 8 V, IOUT = 1 A) www.rohm.com (c) 2019 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 Time (200 s/div) Figure 57. Line Response 2 (VIN = 16 V to 5 V, IOUT = 1 A) 37/57 TSZ02201-0J1J0AL01480-1-2 08.Apr.2020 Rev.002 BD9P1x5EFV-C Series Application Examples 1 - continued 8 8 7 7 6 6 Output Voltage [V] Output Voltage [V] (Ta = 25 C) 5 4 3 5 4 3 2 2 1 1 0 0 0 1 2 3 4 5 6 7 8 0 1 2 3 Input Voltage [V] 6.100 6.100 6.050 6.050 6.000 5.950 5.900 5.900 12 14 16 18 Input Voltage [V] 7 8 0 250 500 750 1000 Output Current [mA] Figure 60. Line Regulation (IOUT = 1 A) www.rohm.com (c) 2019 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 6 6.000 5.950 10 5 Figure 59. Output Voltage vs Input Voltage 2 (RLOAD = 6 ) Output Voltage [V] Output Voltage [V] Figure 58. Output Voltage vs Input Voltage 1 (RLOAD = 600 ) 8 4 Input Voltage [V] Figure 61. Load Regulation (VIN = 12 V) 38/57 TSZ02201-0J1J0AL01480-1-2 08.Apr.2020 Rev.002 BD9P1x5EFV-C Series Application Examples 2 Table 6. Specification Example 2 Parameter Symbol Specification Case Product Name IC BD9P135EFV-C Input Voltage VIN 8 V to 18 V Output Voltage VOUT 3.3 V Output Current IOUT Typ 0.5 A / Max 1.0 A Ta -40 C to +125 C Operating Temperature Range VBAT LF1 CBST VIN VIN BST CF2 CBLK CIN2 CIN1 PGND VOUT_SNS COUT1 RRST COUT2 RESET VREG CREG VOUT VCC_EX VOUT_DIS EN CF1 L1 SW PVIN OCP_SEL GND MODE VMODE SSCG VSSCG -type filter Figure 62. Reference Circuit 2 Table 7. Application Example 2 Parts List with -type filter No. Package Parameters CF1 (Note 1) 3216 3 Part Name (Series) Type Manufacturer 1 F, X7R, 50 V GCJ31MR71H105K Ceramic MURATA 2.2 H CLF6045NIT-2R2N-D Inductor TDK MURATA NICHICON LF1 W6.0 x H4.5 x L6.3 mm CF2 1005 0.1 F, X7R, 50 V GCM155R71H104K CBLK 10 mm x L10 mm 220 F, 35 V UWD1V221MCL1GS 3216 1 F, X7R, 50 V GCJ31MR71H105K Ceramic Electrolytic capacitor Ceramic CIN1 1005 0.1 F, X7R, 50 V GCM155R71H104K Ceramic MURATA CREG 2012 1 F, X7R, 16 V GCM21BR71C105K Ceramic MURATA CBST 1005 0.1 F, X7R, 50 V GCM155R71H104K Ceramic MURATA 10 k, 1 %, 1/16 W MCR01MZPF1002 Chip resistor ROHM 4.7 H CLF6045NIT-4R7N-D Inductor TDK CIN2 (Note 1) MURATA RRST 1005 L1 W6.0 x H4.5 x L6.3 mm COUT1 3225 22 F, X7R, 10 V GCM32ER71A226K Ceramic MURATA COUT2 - Open - - - 3 (Note 1) To reduce EMI noise level, 4.7 F, (3225, X7R, 50 V, GCM32ER71H475K) is recommended for CF1 and CIN2. Table 8. Application Example 2 Parts List without -type filter No. Package Parameters Part Name (Series) Type Manufacturer CF1 - Open - - - LF1 - Open - - - CF2 - Open - - - CBLK - Open - - - CIN2 3225 4.7 F, X7R, 50 V GCM32ER71H475K Ceramic MURATA CIN1 1005 0.1 F, X7R, 50 V GCM155R71H104K Ceramic MURATA www.rohm.com (c) 2019 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 39/57 TSZ02201-0J1J0AL01480-1-2 08.Apr.2020 Rev.002 BD9P1x5EFV-C Series Application Examples 2 - continued (Ta = 25 C) 1000 100 90 100 80 MODE = High Input Current [mA] Efficiency [%] 70 MODE = Low 60 50 40 30 MODE = High 20 10 1 0.1 10 MODE = Low 0 0.01 0.01 0.1 1 10 100 1000 0.01 0.1 Output Current [mA] Figure 63. Efficiency vs Output Current (VIN = 12 V) 80 1000 Figure 64. Input Current vs Output Current (VIN = 12 V) 180 60 135 Phase 90 VMODE (5 V/div) 20 45 VSW (5 V/div) 0 Phase [deg] 40 Gain [dB] 1 10 100 Output Current [mA] 0 -20 -45 Gain VOUT (100 mV/div) offset 3.3 V -40 -90 -60 -135 -80 Time (200 s/div) -180 100 1k 10k 100k Frequency [Hz] 1M Figure 65. Frequency Characteristic (VIN = 12 V, IOUT = 0.5 A) www.rohm.com (c) 2019 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 Figure 66. MODE ON/OFF Response (VIN = 12 V, IOUT = 50 mA) 40/57 TSZ02201-0J1J0AL01480-1-2 08.Apr.2020 Rev.002 BD9P1x5EFV-C Series Application Examples 2 - continued (Ta = 25 C) IOUT (0.5 A/div) IOUT (0.5 A/div) VOUT (100 mV/div) offset 3.3 V VOUT (100 mV/div) offset 3.3 V Time (1 ms/div) Time (1 ms/div) Figure 67. Load Response 1 (VIN = 12 V, VMODE = 5 V, IOUT = 0 A to 1 A) Figure 68. Load Response 2 (VIN = 12 V, VMODE = 0 V, IOUT = 0 A to 1 A) VIN (5 V/div) VIN (2 V/div) VOUT (100 mV/div) offset 3.3 V VOUT (2 V/div) Time (200 s/div) Time (200 s/div) Figure 69. Line Response 1 (VIN = 16 V to 8 V, IOUT = 1 A) www.rohm.com (c) 2019 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 Figure 70. Line Response 2 (VIN = 16 V to 3.5 V, IOUT = 1 A) 41/57 TSZ02201-0J1J0AL01480-1-2 08.Apr.2020 Rev.002 BD9P1x5EFV-C Series Application Examples 2 - continued 8 8 7 7 6 6 Output Voltage [V] Output Voltage [V] (Ta = 25 C) 5 4 3 5 4 3 2 2 1 1 0 0 0 1 2 3 4 5 6 7 8 0 1 2 Input Voltage [V] Figure 71. Output Voltage vs Input Voltage 1 (RLOAD = 330 ) 4 5 6 7 8 Figure 72. Output Voltage vs Input Voltage 2 (RLOAD = 3.3 ) 3.366 3.366 3.337 3.337 Output Voltage [V] Output Voltage [V] 3 Input Voltage [V] 3.308 3.279 3.308 3.279 3.250 3.250 8 10 12 14 16 18 Input Voltage [V] 250 500 750 1000 Output Current [mA] Figure 73. Line Regulation (IOUT = 1 A) www.rohm.com (c) 2019 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 0 Figure 74. Load Regulation (VIN = 12 V) 42/57 TSZ02201-0J1J0AL01480-1-2 08.Apr.2020 Rev.002 BD9P1x5EFV-C Series Application Examples 3 Table 9. Specification Example 3 Parameter Symbol Specification Case Product Name IC BD9P155EFV-C Input Voltage VIN 8 V to 18 V Output Voltage VOUT 5.0 V Output Current IOUT Typ 0.5 A / Max 1.0 A Ta -40 C to +125 C Operating Temperature Range VBAT LF1 CBST VIN VIN BST CF2 CBLK CIN2 CIN1 PGND VOUT_SNS COUT1 RRST COUT2 RESET VREG CREG VOUT VCC_EX VOUT_DIS EN CF1 L1 SW PVIN OCP_SEL GND MODE VMODE SSCG VSSCG -type filter Figure 75. Reference Circuit 3 Table 10. Application Example 3 Parts List with -type filter No. Package Parameters CF1 (Note 1) 3216 3 Part Name (Series) Type Manufacturer 1 F, X7R, 50 V GCJ31MR71H105K Ceramic MURATA 2.2 H CLF6045NIT-2R2N-D Inductor TDK MURATA NICHICON LF1 W6.0 x H4.5 x L6.3 mm CF2 1005 0.1 F, X7R, 50 V GCM155R71H104K CBLK 10 mm x L10 mm 220 F, 35 V UWD1V221MCL1GS 3216 1 F, X7R, 50 V GCJ31MR71H105K Ceramic Electrolytic capacitor Ceramic CIN1 1005 0.1 F, X7R, 50 V GCM155R71H104K Ceramic MURATA CREG 2012 1 F, X7R, 16 V GCM21BR71C105K Ceramic MURATA CBST 1005 0.1 F, X7R, 50 V GCM155R71H104K Ceramic MURATA 10 k, 1 %, 1/16 W MCR01MZPF1002 Chip resistor ROHM 4.7 H CLF6045NIT-4R7N-D Inductor TDK CIN2 (Note 1) MURATA RRST 1005 L1 W6.0 x H4.5 x L6.3 mm COUT1 3225 22 F, X7R, 10 V GCM32ER71A226K Ceramic MURATA COUT2 - Open - - - 3 (Note 1) To reduce EMI noise level, 4.7 F, (3225, X7R, 50 V, GCM32ER71H475K) is recommended for CF1 and CIN2. Table 11. Application Example 3 Parts List without -type filter No. Package Parameters Part Name (Series) Type Manufacturer CF1 - Open - - - LF1 - Open - - - CF2 - Open - - - CBLK - Open - - - CIN2 3225 4.7 F, X7R, 50 V GCM32ER71H475K Ceramic MURATA CIN1 1005 0.1 F, X7R, 50 V GCM155R71H104K Ceramic MURATA www.rohm.com (c) 2019 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 43/57 TSZ02201-0J1J0AL01480-1-2 08.Apr.2020 Rev.002 BD9P1x5EFV-C Series Application Examples 3 - continued (Ta = 25 C) 100 1000 90 80 Efficiency [%] 70 Input Current [mA] 100 MODE = Low 60 50 40 30 MODE = High 20 MODE = High 10 1 0.1 MODE = Low 10 0 0.01 0.01 0.1 1 10 100 1000 0.01 0.1 Output Current [mA] Figure 76. Efficiency vs Output Current (VIN = 12 V) 80 1000 Figure 77. Input Current vs Output Current (VIN = 12 V) 180 Phase 135 40 90 20 45 0 VMODE (5 V/div) Phase [deg] 60 Gain [dB] 1 10 100 Output Current [mA] 0 -20 -45 Gain VOUT (100 mV/div) offset 5 V -40 -90 -60 -135 -80 -180 100 1k 10k 100k Frequency [Hz] Time (200 s/div) 1M Figure 78. Frequency Characteristic (VIN = 12 V, IOUT = 0.5 A) www.rohm.com (c) 2019 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 VSW (5 V/div) Figure 79. MODE ON/OFF Response (VIN = 12 V, IOUT = 50 mA) 44/57 TSZ02201-0J1J0AL01480-1-2 08.Apr.2020 Rev.002 BD9P1x5EFV-C Series Application Examples 3 - continued (Ta = 25 C) IOUT (0.5 A/div) IOUT (0.5 A/div) VOUT (100 mV/div) offset 5 V VOUT (100 mV/div) offset 5 V Time (1 ms/div) Time (1 ms/div) Figure 80. Load Response 1 (VIN = 12 V, VMODE = 5 V, IOUT = 0 A to 1 A) Figure 81. Load Response 2 (VIN = 12 V, VMODE = 0 V, IOUT = 0 A to 1 A) VIN (5 V/div) VIN (2 V/div) VOUT (2 V/div) VOUT (100 mV/div) offset 5 V Time (200 s/div) Time (200 s/div) Figure 82. Line Response 1 (VIN = 16 V to 8 V, IOUT = 1 A) www.rohm.com (c) 2019 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 Figure 83. Line Response 2 (VIN = 16 V to 4 V, IOUT = 1 A) 45/57 TSZ02201-0J1J0AL01480-1-2 08.Apr.2020 Rev.002 BD9P1x5EFV-C Series Application Examples 3 - continued 8 8 7 7 6 6 Output Voltage [V] Output Voltage [V] (Ta = 25 C) 5 4 3 5 4 3 2 2 1 1 0 0 0 1 2 3 4 5 6 7 8 0 1 2 3 Input Voltage [V] 5 6 7 8 Input Voltage [V] Figure 84. Output Voltage vs Input Voltage 1 (RLOAD = 500 ) Figure 85. Output Voltage vs Input Voltage 2 (RLOAD = 5 ) 5.100 5.100 5.065 5.065 Output Voltage [V] Output Voltage [V] 4 5.030 4.995 4.960 5.030 4.995 4.960 4.925 4.925 8 10 12 14 16 18 Input Voltage [V] 250 500 750 1000 Output Current [mA] Figure 86. Line Regulation (IOUT = 1 A) www.rohm.com (c) 2019 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 0 Figure 87. Load Regulation (VIN = 12 V) 46/57 TSZ02201-0J1J0AL01480-1-2 08.Apr.2020 Rev.002 BD9P1x5EFV-C Series Automotive Power Supply Line Circuit Battery Line Reverse Polarity Protection Diode D VIN DC/DC Converter L C TVS C -type filter Figure 88. Automotive Power Supply Line Circuit As a reference, the automotive power supply line circuit example is given in figure above. The -type filter is a third-order LC filter. In general, it is used in combination with decoupling capacitors for high frequency. Since large attenuation characteristics can be obtained, excellent characteristic is also obtained as an EMI filter. Devices used for -type filters should be placed close to each other. TVS (Transient Voltage Suppressors) is used for primary protection of the automotive power supply line. Since it is necessary to withstand high energy of load dump surge, a general zener diode is insufficient. Recommended device is shown in the following table. In addition, a reverse polarity protection diode is needed considering if a power supply such as Battery is accidentally connected in the opposite direction. Table 12. Reference Parts of Automotive Power Supply Line Circuit Device Part name (series) Manufacturer Device Part name (series) Manufacturer L CLF series TDK TVS SMB series Vishay L XAL series Coilcraft D S3A to S3M series Vishay C CJ series / CZ series NICHICON Recommended Parts Manufacturer List Shown below is the list of the recommended parts manufacturers for reference. Type Manufacturer URL Electrolytic Capacitor NICHICON www.nichicon-us.com Ceramic Capacitor Murata www.murata.com Hybrid Capacitor Suncon www.sunelec.co.jp Inductor TDK product.tdk.com Inductor Coilcraft www.coilcraft.com Inductor SUMIDA www.sumida.com Diode Vishay www.vishay.com Diode/Resistor ROHM www.rohm.com www.rohm.com (c) 2019 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 47/57 TSZ02201-0J1J0AL01480-1-2 08.Apr.2020 Rev.002 BD9P1x5EFV-C Series PCB Layout Design PCB layout design for DC/DC converter power supply IC is as important as the circuit design. Appropriate layout can avoid various problems caused by power supply circuit. Figure 89 (a) to Figure 89 (c) figure the current path in a buck converter circuit. The Loop1 in Figure 89 (a) is a current path when High Side Switch is ON and Low Side Switch is OFF, the Loop2 in Figure 89 (b) is when High Side Switch is OFF and Low Side Switch is ON. The thick line in Figure 89 (c) shows the difference between Loop1 and Loop2. The current in thick line changes sharply each time the switching element High Side Switch and Low Side Switch change from OFF to ON, and vice versa. These sharp changes induce several harmonics in the waveform. Therefore, the loop area of thick line that is consisted by input capacitor and IC should be as small as possible to minimize noise. For more detail, refer to application note of switching regulator series "PCB Layout Techniques of Buck Converter". Loop1 VIN High Side Switch VOUT L CIN COUT Low Side Switch GND GND Figure 89 (a). Current Path when High Side Switch = ON, Low Side Switch = OFF VIN High Side Switch VOUT L CIN COUT Loop2 Low Side Switch GND GND Figure 89 (b). Current Path when High Side Switch = OFF, Low Side Switch = ON VIN VOUT L CIN High Side FET COUT Low Side FET GND GND Figure 89 (c). Difference of Current and Critical Area in Layout www.rohm.com (c) 2019 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 48/57 TSZ02201-0J1J0AL01480-1-2 08.Apr.2020 Rev.002 BD9P1x5EFV-C Series PCB Layout Design - continued When designing the PCB layout, please pay extra attention to the following points. 1. The decoupling capacitors (CIN1) for the VIN pin (pin 2) and the PVIN pins (pin 3, 4) should be placed closest to the PVIN pins and the PGND pins (pin 6, 7). In addition, placing a capacitor 0.1 F close to the PVIN pin results in minimizing the high-frequency noise. 2. The device, the input capacitor, the output inductor and the output capacitor should be placed on the same side of the board and the connection of each part should be made on the same layer. 3. Place the ground plane in a layer closest to the surface layer where the device is mounted. 4. The GND pin (pin 15) is the reference ground and the PGND pins are the power ground. These pins should be connected through the back side of the device. The power systems ground should be connected to the ground plane using as many vias as possible. 5. The capacitor for VREG should be placed closest to the VREG pin (pin 20), the GND pin and the PGND pin. As shown in the Recommended Board Layout Example, it can be realized that connecting with the shortest distance for the GND pin and the PGND pins by placing the capacitor for VREG on the closest to the VREG pin and wiring at the back side of the IC. 6. Place Bootstrap capacitor CBST close to the device with short traces to the SW pins (pin 8, 9) and the BST pin (pin 10). 7. To minimize the emission noise from switching node, the distance between the SW pins to inductor should be as short as possible and not to expand the copper area more than necessary. 8. Place the output capacitor close to the inductor and power ground area. 9. Make the feedback line from the output away from the inductor and the switching node. If this line is affected by external noise, an error may be occurred in the output voltage or the control may become unstable. Therefore, move the feedback line to back side layer of the board through via and connect it to the VOUT_SNS pin (pin 17). When the VCC_EX function and the output discharge function are used, connect it to the VCC_EX (pin 19) and the VOUT_DIS pin (pin 16) as well, respectively. 10. RFB1 and RFB2 Feedback resistors are needed for BD9P105EFV-C. Place RFB1, RFB2 close to the FB pin (pin 18). 11. RFB0 is for measuring the frequency characteristic of the feedback. By inserting a resistor in R FB0, the frequency characteristics (phase margin) of the feedback can be measured. RFB0 should be short-circuited for the normal use. Reference Ground Area Power Ground Area Figure 90. Recommended Board Layout Example (for BD9P1x5EFV-C) L1 VOUT SW VCC_EX ( RFB0 ) COUT VOUT_SNS RFB1 FB RFB2 Figure 91. The resistor for measuring the frequency characteristic of the feedback www.rohm.com (c) 2019 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 49/57 TSZ02201-0J1J0AL01480-1-2 08.Apr.2020 Rev.002 BD9P1x5EFV-C Series Power Dissipation For thermal design, be sure to operate the IC within the following conditions. (Since the temperatures described hereunder are all guaranteed temperatures, take margin into account.) 1. 2. The ambient temperature Ta is to be 125 C or less. The chip junction temperature Tj is to be 150 C or less. The chip junction temperature Tj can be considered in the following two patterns: 1. To obtain Tj from the package surface center temperature Tt in actual use = + x [C] 2. To obtain Tj from the ambient temperature Ta = + x [C] Where: is junction to top characterization parameter (Refer to page 9) is junction to ambient (Refer to page 9) The heat loss W of the IC can be obtained by the formula shown below. This formula is approximation, please confirm this on the actual application circuit. + x 2 (1 - ) 1 + x _4 + x __2 + 2 x ( + ) x x x [W] = x 2 x Where: _4 __2 tr is the High Side FET ON Resistance [] (Refer to page 11) is the Low Side FET ON Resistance [] (Refer to page 11) is the Load Current [A] is the Output Voltage [V] is the Input Voltage [V] is the Quiescent Current from VIN [A] (Refer to page 10) is the Quiescent Current from VCC_EX [A] (Refer to page 10) is the Switching Rise Time [s] (5 ns, Typ) is the Switching Fall Time [s] (5 ns, Typ) is the Switching Frequency [Hz] (Refer to page 11) tf 1. x 2 2. x 2 3. 1 2 x ( + ) x x x Figure 92. SW Waveform www.rohm.com (c) 2019 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 50/57 TSZ02201-0J1J0AL01480-1-2 08.Apr.2020 Rev.002 BD9P1x5EFV-C Series I/O Equivalence Circuits 1. EN 12. MODE VREG 10 k EN 50 k MODE 850 k GND GND GND GND 8,9. SW, 10.BST BST GND 14. RESET VREG PVIN RESET 100 SW VREG GND GND PGND GND 11. OCP_SEL, 13. SSCG 16. VOUT_DIS VREG VOUT_DIS 56 50 k OCP_SEL/ SSCG GND GND GND GND *Resistance value is Typ. www.rohm.com (c) 2019 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 51/57 TSZ02201-0J1J0AL01480-1-2 08.Apr.2020 Rev.002 BD9P1x5EFV-C Series I/O Equivalence Circuits - continued 17. VOUT_SNS, 18. FB (BD9P105EFV-C) 17. VOUT_SNS (BD9P155EFV-C) VOUT_SNS VOUT_SNS 21 M VREG 4 M VREG GND GND GND 10 k FB 10 k GND 17. VOUT_SNS (BD9P135EFV-C) 19. VCC_EX, 20. VREG VIN VOUT_SNS 12.5M VREG 4M VREG GND GND 10k GND VCC_EX 15 M GND GND *Resistance value is Typ. www.rohm.com (c) 2019 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 52/57 TSZ02201-0J1J0AL01480-1-2 08.Apr.2020 Rev.002 BD9P1x5EFV-C Series Operational Notes 1. Reverse Connection of Power Supply Connecting the power supply in reverse polarity can damage the IC. Take precautions against reverse polarity when connecting the power supply, such as mounting an external diode between the power supply and the IC's power supply pins. 2. Power Supply Lines Design the PCB layout pattern to provide low impedance supply lines. Furthermore, connect a capacitor to ground at all power supply pins. Consider the effect of temperature and aging on the capacitance value when using electrolytic capacitors. 3. Ground Voltage Ensure that no pins are at a voltage below that of the ground pin at any time, even during transient condition. However, pins that drive inductive loads (e.g. motor driver outputs, DC-DC converter outputs) may inevitably go below ground due to back EMF or electromotive force. In such cases, the user should make sure that such voltages going below ground will not cause the IC and the system to malfunction by examining carefully all relevant factors and conditions such as motor characteristics, supply voltage, operating frequency and PCB wiring to name a few. 4. Ground Wiring Pattern When using both small-signal and large-current ground traces, the two ground traces should be routed separately but connected to a single ground at the reference point of the application board to avoid fluctuations in the small-signal ground caused by large currents. Also ensure that the ground traces of external components do not cause variations on the ground voltage. The ground lines must be as short and thick as possible to reduce line impedance. 5. Recommended Operating Conditions The function and operation of the IC are guaranteed within the range specified by the recommended operating conditions. The characteristic values are guaranteed only under the conditions of each item specified by the electrical characteristics. 6. Inrush Current When power is first supplied to the IC, it is possible that the internal logic may be unstable and inrush current may flow instantaneously due to the internal powering sequence and delays, especially if the IC has more than one power supply. Therefore, give special consideration to power coupling capacitance, power wiring, width of ground wiring, and routing of connections. 7. Testing on Application Boards When testing the IC on an application board, connecting a capacitor directly to a low-impedance output pin may subject the IC to stress. Always discharge capacitors completely after each process or step. The IC's power supply should always be turned off completely before connecting or removing it from the test setup during the inspection process. To prevent damage from static discharge, ground the IC during assembly and use similar precautions during transport and storage. 8. Inter-pin Short and Mounting Errors Ensure that the direction and position are correct when mounting the IC on the PCB. Incorrect mounting may result in damaging the IC. Avoid nearby pins being shorted to each other especially to ground, power supply and output pin. Inter-pin shorts could be due to many reasons such as metal particles, water droplets (in very humid environment) and unintentional solder bridge deposited in between pins during assembly to name a few. 9. Unused Input Pins Input pins of an IC are often connected to the gate of a MOS transistor. The gate has extremely high impedance and extremely low capacitance. If left unconnected, the electric field from the outside can easily charge it. The small charge acquired in this way is enough to produce a significant effect on the conduction through the transistor and cause unexpected operation of the IC. So unless otherwise specified, unused input pins should be connected to the power supply or ground line. www.rohm.com (c) 2019 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 53/57 TSZ02201-0J1J0AL01480-1-2 08.Apr.2020 Rev.002 BD9P1x5EFV-C Series Operational Notes - continued 10. Regarding the Input Pin of the IC This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them isolated. P-N junctions are formed at the intersection of the P layers with the N layers of other elements, creating a parasitic diode or transistor. For example (refer to figure below): When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode. When GND > Pin B, the P-N junction operates as a parasitic transistor. Parasitic diodes inevitably occur in the structure of the IC. The operation of parasitic diodes can result in mutual interference among circuits, operational faults, or physical damage. Therefore, conditions that cause these diodes to operate, such as applying a voltage lower than the GND voltage to an input pin (and thus to the P substrate) should be avoided. Resistor Transistor (NPN) Pin A Pin B C E Pin A N P+ P N N P+ N Pin B B Parasitic Elements N P+ N P N P+ B N C E Parasitic Elements P Substrate P Substrate GND GND Parasitic Elements GND Parasitic Elements GND N Region close-by Figure 93. Example of Monolithic IC Structure 11. Ceramic Capacitor When using a ceramic capacitor, determine a capacitance value considering the change of capacitance with temperature and the decrease in nominal capacitance due to DC bias and others. 12. Thermal Shutdown Circuit(TSD) This IC has a built-in thermal shutdown circuit that prevents heat damage to the IC. Normal operation should always be within the IC's maximum junction temperature rating. If however the rating is exceeded for a continued period, the junction temperature (Tj) will rise which will activate the TSD circuit that will turn OFF power output pins. When the Tj falls below the TSD threshold, the circuits are automatically restored to normal operation. Note that the TSD circuit operates in a situation that exceeds the absolute maximum ratings and therefore, under no circumstances, should the TSD circuit be used in a set design or for any purpose other than protecting the IC from heat damage. 13. Over Current Protection Circuit (OCP) This IC incorporates an integrated overcurrent protection circuit that is activated when the load is shorted. This protection circuit is effective in preventing damage due to sudden and unexpected incidents. However, the IC should not be used in applications characterized by continuous operation or transitioning of the protection circuit. www.rohm.com (c) 2019 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 54/57 TSZ02201-0J1J0AL01480-1-2 08.Apr.2020 Rev.002 BD9P1x5EFV-C Series Ordering Information B D 9 Part Number P 1 x Output Voltage 0: Adjustable 3: 3.3V 5: 5.0V 5 E F V - Package EFV: HTSSOP-B20 CE2 Product Rank C: for Automotive Packaging Specification E2: Embossed tape and reel Marking Diagram HTSSOP-B20 (TOP VIEW) Part Number Marking LOT Number Pin 1 Mark Orderable Part Number BD9P105EFV-CE2 BD9P135EFV-CE2 BD9P155EFV-CE2 www.rohm.com (c) 2019 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 Output Voltage Adjustable 3.3 V 5.0 V 55/57 Part Number Making D9P105 D9P135 D9P155 TSZ02201-0J1J0AL01480-1-2 08.Apr.2020 Rev.002 BD9P1x5EFV-C Series Physical Dimension and Packing Information Package Name www.rohm.com (c) 2019 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 HTSSOP-B20 56/57 TSZ02201-0J1J0AL01480-1-2 08.Apr.2020 Rev.002 BD9P1x5EFV-C Series Revision History Date Revision 01.Oct.2019 001 Changes New Release Pin Description Add EXP-PAD explanation (regarding p substrate connection) Absolute Maximum Ratings Change comment "Not 100% tested" -> "Not tested" 08.Apr.2020 002 Electrical Characteristics Change comment "Not 100% tested" -> "Not tested" Change EN Input Voltage High (Max) "VIN" -> "40" Selection of Components Externally Connected Delete regarding Electrical capacitors explanation Add the output ceramic capacitor COUT (Min) conditions Application Examples Add CF2 at Reference Circuit Parts List with -type filter www.rohm.com (c) 2019 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 57/57 TSZ02201-0J1J0AL01480-1-2 08.Apr.2020 Rev.002 Notice Precaution on using ROHM Products 1. If you intend to use our Products in devices requiring extremely high reliability (such as medical equipment (Note 1), aircraft/spacecraft, nuclear power controllers, etc.) and whose malfunction or failure may cause loss of human life, bodily injury or serious damage to property ("Specific Applications"), please consult with the ROHM sales representative in advance. Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of any ROHM's Products for Specific Applications. (Note1) Medical Equipment Classification of the Specific Applications JAPAN USA EU CHINA CLASS CLASSb CLASS CLASS CLASS CLASS 2. ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which a failure or malfunction of our Products may cause. The following are examples of safety measures: [a] Installation of protection circuits or other protective devices to improve system safety [b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure 3. Our Products are not designed under any special or extraordinary environments or conditions, as exemplified below. Accordingly, ROHM shall not be in any way responsible or liable for any damages, expenses or losses arising from the use of any ROHM's Products under any special or extraordinary environments or conditions. If you intend to use our Products under any special or extraordinary environments or conditions (as exemplified below), your independent verification and confirmation of product performance, reliability, etc, prior to use, must be necessary: [a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents [b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust [c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2, H2S, NH3, SO2, and NO2 [d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves [e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items [f] Sealing or coating our Products with resin or other coating materials [g] Use of our Products without cleaning residue of flux (Exclude cases where no-clean type fluxes is used. However, recommend sufficiently about the residue.); or Washing our Products by using water or water-soluble cleaning agents for cleaning residue after soldering [h] Use of the Products in places subject to dew condensation 4. The Products are not subject to radiation-proof design. 5. Please verify and confirm characteristics of the final or mounted products in using the Products. 6. In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse, is applied, confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect product performance and reliability. 7. De-rate Power Dissipation depending on ambient temperature. When used in sealed area, confirm that it is the use in the range that does not exceed the maximum junction temperature. 8. Confirm that operation temperature is within the specified range described in the product specification. 9. ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in this document. Precaution for Mounting / Circuit board design 1. When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product performance and reliability. 2. In principle, the reflow soldering method must be used on a surface-mount products, the flow soldering method must be used on a through hole mount products. If the flow soldering method is preferred on a surface-mount products, please consult with the ROHM representative in advance. For details, please refer to ROHM Mounting specification Notice-PAA-E (c) 2015 ROHM Co., Ltd. All rights reserved. Rev.004 Precautions Regarding Application Examples and External Circuits 1. If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the characteristics of the Products and external components, including transient characteristics, as well as static characteristics. 2. You agree that application notes, reference designs, and associated data and information contained in this document are presented only as guidance for Products use. Therefore, in case you use such information, you are solely responsible for it and you must exercise your own independent verification and judgment in the use of such information contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of such information. Precaution for Electrostatic This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron, isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control). Precaution for Storage / Transportation 1. Product performance and soldered connections may deteriorate if the Products are stored in the places where: [a] the Products are exposed to sea winds or corrosive gases, including Cl 2, H2S, NH3, SO2, and NO2 [b] the temperature or humidity exceeds those recommended by ROHM [c] the Products are exposed to direct sunshine or condensation [d] the Products are exposed to high Electrostatic 2. Even under ROHM recommended storage condition, solderability of products out of recommended storage time period may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is exceeding the recommended storage time period. 3. Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads may occur due to excessive stress applied when dropping of a carton. 4. Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of which storage time is exceeding the recommended storage time period. Precaution for Product Label A two-dimensional barcode printed on ROHM Products label is for ROHM's internal use only. Precaution for Disposition When disposing Products please dispose them properly using an authorized industry waste company. Precaution for Foreign Exchange and Foreign Trade act Since concerned goods might be fallen under listed items of export control prescribed by Foreign exchange and Foreign trade act, please consult with ROHM in case of export. Precaution Regarding Intellectual Property Rights 1. All information and data including but not limited to application example contained in this document is for reference only. ROHM does not warrant that foregoing information or data will not infringe any intellectual property rights or any other rights of any third party regarding such information or data. 2. ROHM shall not have any obligations where the claims, actions or demands arising from the combination of the Products with other articles such as components, circuits, systems or external equipment (including software). 3. No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of ROHM or any third parties with respect to the Products or the information contained in this document. Provided, however, that ROHM will not assert its intellectual property rights or other rights against you or your customers to the extent necessary to manufacture or sell products containing the Products, subject to the terms and conditions herein. Other Precaution 1. This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM. 2. The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written consent of ROHM. 3. In no event shall you use in any way whatsoever the Products and the related technical information contained in the Products or this document for any military purposes, including but not limited to, the development of mass-destruction weapons. 4. The proper names of companies or products described in this document are trademarks or registered trademarks of ROHM, its affiliated companies or third parties. Notice-PAA-E (c) 2015 ROHM Co., Ltd. All rights reserved. Rev.004 Datasheet General Precaution 1. Before you use our Products, you are requested to carefully read this document and fully understand its contents. ROHM shall not be in any way responsible or liable for failure, malfunction or accident arising from the use of any ROHM's Products against warning, caution or note contained in this document. 2. All information contained in this document is current as of the issuing date and subject to change without any prior notice. Before purchasing or using ROHM's Products, please confirm the latest information with a ROHM sales representative. 3. The information contained in this document is provided on an "as is" basis and ROHM does not warrant that all information contained in this document is accurate and/or error-free. ROHM shall not be in any way responsible or liable for an y damages, expenses or losses incurred b y you or third parties resulting from inaccuracy or errors of or concerning such information. Notice - WE (c) 2015 ROHM Co., Ltd. All rights reserved. Rev.001