General Description
The MAX9880A is a high-performance, stereo audio
codec designed for portable consumer applications
such as smartphones and tablets. Operating from a sin-
gle 1.8V supply to ensure low-power consumption, the
MAX9880A offers a variety of input and output configu-
rations for design flexibility. The MAX9880A can be
combined with an audio subsystem, such as the
MAX9877 or MAX9879, for a complete audio solution
for portable applications.
The MAX9880A’s stereo differential microphone inputs
can support either analog or digital microphones. A
stereo single-ended line input, with a configurable pre-
amplifier, can either be recorded by the ADC or routed
directly to the headphone or line output amplifiers. The
stereo headphone amplifiers can be configured as dif-
ferential, single ended, or capacitorless. The stereo line
outputs have dedicated level adjustment.
There are two digital audio interfaces. The primary
interface is intended for voiceband applications, while
the secondary interface can be used for high perfor-
mance stereo audio data. Two digital input streams can
be processed simultaneously and both digital inter-
faces support TDM and I2S data formats.
The flexible clocking circuitry utilizes any available
10MHz to 60MHz system clock, eliminating the need for
an external PLL and multiple crystal oscillators. Both
the ADC and DAC can be operated synchronously or
asynchronously in master or slave mode. The ADC can
be operated from 8kHz to 48kHz sample rates, while
the DAC can be operated up to 96kHz.
The MAX9880A prevents click and pop during volume
changes and during power-up and power-down. Audio
quality is further enhanced with user-configurable digital
filters for voice and audio data. Voiceband filters pro-
vide extra attenuation at the GSM packet frequency and
greater than 70dB stopband attenuation at fS/2. An I2C
or SPI™ serial interface provides control for volume lev-
els, signal mixing, and general operating modes.
The MAX9880A is available in space-saving, 48-bump,
2.7mm x 3.5mm, 0.4mm-pitch WLP and 48-pin, 6mm x
6mm TQFN packages.
Applications
Cellular Phones
Tablet PCs
Portable Gaming Devices
Portable Multimedia Players
Features
o1.8V Single-Supply Operation
o10.6mW Playback Power Consumption
o8kHz to 96kHz Stereo DAC with 96dB Dynamic
Range
o8kHz to 48kHz Stereo ADC with 82dB Dynamic
Range
oSupport for Any Master Clock Between 10MHz to
60MHz
oStereo Microphone Inputs Support Digital
Microphones
oStereo Headphone Amplifiers: Differential
(30mW), Single-Ended, or Capacitorless (10mW)
oStereo Line Inputs and Stereo Line Outputs
oVoiceband Filters with Stopband Attenuation
Greater than 70dB
oBattery-Measurement Auxiliary ADC
oComprehensive Headset Detection
oDual I2S- and TDM-Compatible Digital Audio
Interfaces
oI2C- or SPI-Compatible Control Bus with 3.6V
Tolerant Inputs
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
________________________________________________________________
Maxim Integrated Products
1
Ordering Information
19-5139; Rev 1; 3/11
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
+
Denotes a lead(Pb)-free/RoHS-compliant package.
*
EP = Exposed pad.
EVALUATION KIT
AVAILABLE
PART TEMP RANGE PIN-PACKAGE
MAX9880AEWM+ -40°C to +85°C 48 WLP
MAX9880AETM+ -40°C to +85°C 48 TQFN-EP*
Functional Diagram/Typical Operating Circuit appears at
end of data sheet.
SPI is a trademark of Motorola, Inc.
MAX9880A
MIC
BIAS
MIX
LEFT
DIGITAL
FILTERING
RIGHT
LEFT
DAC
RIGHT
DAC
MIX
MIXMIXMIXMIX
DIGITAL
AUDIO
INTERFACE
1
MASTER
CLOCK
JACK SENSE/
MEASUREMENT
ADC
DIGITAL
AUDIO
INTERFACE
2
I2C
INTERFACE
Simplified Block Diagram
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VAVDD = VPVDD = VMICVDD = VDVDD = VDVDDS1 = +1.8V, RL= ∞, headphone load (RL) connected between _OUTP and _OUTN, dif-
ferential modes, CREF = 2.2µF, CMICBIAS = CPREG = CREG = 1µF, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB,
AVVOL = 0dB, AVLO = 0dB, fMCLK = 13MHz, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.) (Note 2)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
(Voltages with respect to AGND.)
DVDD, AVDD, PVDD ................................................-0.3V to +2V
DVDDS1, JACKSNS, MICVDD ..............................-0.3V to +3.6V
DGND, PGND........................................................-0.1V to +0.1V
PREG, REF, REG ....................................-0.3V to (VAVDD + 0.3V)
MICBIAS .............................................-0.3V to (VMICVDD + 0.3V)
MCLK, LRCLKS1, BCLKS1,
SDINS1, SDOUTS1..........................-0.3V to (VDVDDS1 + 0.3V)
X1, X2, LRCLKS2, BCLKS2, SDINS2,
SDOUTS2, DOUT, MODE ...................-0.3V to (VDVDD + 0.3V)
SDA/DIN, SCL/SCLK, CS, IRQ ..............................-0.3V to +3.6V
LOUTP, LOUTN, ROUTP, ROUTN,
LOUTL, LOUTR ....................(VPGND - 0.3V) to (VPVDD + 0.3V)
LINL, LINR, MICLP/DIGMICDATA,
MICLN/DIGMICCLK, MICRP/SPDMDATA,
MICRN/SPDMCLK ...............................-0.3V to (VAVDD + 0.3V)
Continuous Power Dissipation (TA= +70°C)
48-Bump WLP (derate 12.5mW/°C above +70°C) .....1000mW
48-Pin TQFN (derate 37mW/°C above +70°C) ..........2963mW
Junction Temperature......................................................+150°C
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
PVDD, DVDD, AVDD 1.65 1.8 1.95
Supply Voltage Range DVDDS1, MICVDD 1.65 1.8 3.6 V
Analog (AVDD + PVDD +
MICVDD) 5.33 8
Full-duplex 8kHz
mono (Note 3)
Digital (DVDD + DVDDS1) 1.4 2
Analog (AVDD + PVDD +
MICVDD) 3.5 6
DAC playback
48kHz stereo
(Note 3) Digital (DVDD + DVDDS1) 2.5 4
Analog (AVDD + PVDD +
MICVDD) 8.4 12
Full-duplex 48kHz
stereo (Note 3)
Digital (DVDD + DVDDS1) 3.0 5
Analog (AVDD + PVDD +
MICVDD) 4.9 8
Total Supply Current IVDD
Stereo line-in to
line-out only,
TA = +25°CDigital (DVDD + DVDDS1) 0.012 0.05
mA
Analog (AVDD + PVDD +
MICVDD) 0.3 2
Shutdown Supply
Current T
A = +25°C
Digital (DVDD + DVDDS1) 2.6 8
µA
Shutdown to Full
Operation Excludes PLL lock time 10 ms
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-
layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
PACKAGE THERMAL CHARACTERISTICS (Note 1)
TQFN
Junction-to-Ambient Thermal Resistance (θJA)...............27°C/W
Junction-to-Case Thermal Resistance (θJC)......................1°C/W
WLP
Junction-to-Ambient Thermal Resistance (θJA)................42°C/W
Junction-to-Case Thermal Resistance (θJC).......................5°C/W
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VPVDD = VMICVDD = VDVDD = VDVDDS1 = +1.8V, RL= ∞, headphone load (RL) connected between _OUTP and _OUTN, dif-
ferential modes, CREF = 2.2µF, CMICBIAS = CPREG = CREG = 1µF, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB,
AVVOL = 0dB, AVLO = 0dB, fMCLK = 13MHz, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.) (Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DAC (Note 4)
Master or slave mode 96
Dynamic Range
(Note 5) DR fS = 48kHz, AVVOL = 0dB,
TA = +25°CSlave mode 88 dB
Differential mode 1
Full-Scale Output Capacitorless and single-ended modes 0.56 VRMS
Gain Error DC accuracy, measured with respect to full-scale
output 1 5 %
fS = 8kHz 1.2
Voice Path Phase Delay PDLY
1kHz, 0dB input, highpass
filter disabled measured from
digital input to analog output;
MODE = 0 (IIR voice) fS = 16kHz 0.59
ms
Total Harmonic
Distortion THD fMCLK = 12.288MHz, fS = 48kHz, 0dBFS, measured
at headphone outputs -75 dB
DAC Attenuation Range AVDAC VDACA/SDACA = 0xF to 0x0 -15 0 dB
DAC Gain Adjust AVGAIN VDACG = 00 to 11 0 +18 dB
VAVDD = VPVDD = 1.65V to 1.95V 85
f = 217Hz, VRIPPLE = 100mVP-P, AVVOL = 0dB 85
f = 1kHz, VRIPPLE = 100mVP-P, AVVOL = 0dB 80
Power-Supply Rejection
Ratio PSRR
f = 10kHz, VRIPPLE = 100mVP-P, AVVOL = 0dB 74
dB
DAC VOICE MODE DIGITAL IIR LOWPASS FILTER (6x Interpolation)
With respect to fS within ripple; fS = 8kHz to 48kHz 0.448 x fS
Passband Cutoff fPLP -3dB cutoff 0.451 x fS
Hz
Passband Ripple f < fPLP ±0.1 dB
Stopband Cutoff fSLP With respect to fS; fS = 8kHz to 48kHz 0.476 x fSHz
Stopband Attenuation f > fSLP, f = 20Hz to 20kHz 75 dB
DAC VOICE MODE DIGITAL 5th-ORDER IIR HIGHPASS FILTER
DVFLT = 0x1
(Elliptical tuned for 16kHz GSM + 217Hz notch)
0.0161 x
fS
DVFLT = 0x2
(500Hz Butterworth tuned for 16kHz)
0.0312 x
fS
DVFLT = 0x3
(Elliptical tuned for 8kHz GSM + 217Hz notch)
0.0321 x
fS
DVFLT = 0x4
(500Hz Butterworth tuned for 8kHz)
0.0625 x
fS
5th-Order Passband
Cutoff
(-3dB from Peak,
I2C Register
Programmable)
fDHPPB
DVFLT = 0x5
(fS/240 Butterworth)
0.0042 x
fS
Hz
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
4 _______________________________________________________________________________________
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DVFLT = 0x1
(Elliptical tuned for 16kHz GSM + 217Hz notch)
0.0139 x
fS
DVFLT = 0x2
(500Hz Butterworth tuned for 16kHz)
0.0156 x
fS
DVFLT = 0x3
(Elliptical tuned for 8kHz GSM + 217Hz notch)
0.0279 x
fS
DVFLT = 0x4
(500Hz Butterworth tuned for 8kHz)
0.0312 x
fS
5th-Order Stopband
Cutoff
(-30dB from Peak,
I2C Register
Programmable)
fDHPSB
DVFLT = 0x5
(fS/240 Butterworth)
0.0021 x
fS
Hz
DC Attenuation DCATTEN DVFLT not equal to 000 90 dB
DAC STEREO AUDIO MODE DIGITAL FIR LOWPASS FILTER (DHF = 0 for fLRCLK < 50kHz)
With respect to fS within ripple; fS = 8kHz to 48kHz 0.43 x fS
-3dB cutoff 0.47 x fS
Passband Cutoff fPLP
-6.02dB cutoff 0.50 x fS
Hz
Passband Ripple f < fPLP ±0.1 dB
Stopband Cutoff fSLP With respect to fS; fS = 8kHz to 48kHz; f = 0.58 fS
to 7.42 fS 0.58 x fS Hz
Stopband Attenuation f > fSLP 60 dB
DAC STEREO AUDIO MODE DIGITAL FIR LOWPASS FILTER (DHF = 1 for fLRCLK > 50kHz)
Ripple limit cutoff 0.24 x fS
Passband Cutoff fPLP -3dB cutoff 0.33 x fS
Hz
Passband Ripple f < fPLP ±0.1 dB
Stopband Cutoff fSLP With respect to fS; f = 0.5 fS to 3.5 fS 0.5 x fS Hz
Stopband Attenuation f > fSLP 60 dB
DAC STEREO AUDIO MODE DIGITAL DC-BLOCKING HIGHPASS FILTER
Passband Cutoff
(-3dB from Peak) fDHPPB DVFLT = 0x1 (DAI1), DCB = 1 (DAI2) 0.000625 x
fS Hz
DC Attenuation DCATTEN DVFLT = 0x1 (DAI1), DCB = 1 (DAI2) 90 dB
ADC (Note 6)
fS = 8kHz, MODE = 0 (IIR voice), TA = +25°C 72 82
Dynamic Range
(Note 5) DR fS = 8kHz to 48kHz, MODE = 1 (FIR audio) (Note 7) 84 dB
Full-Scale Input Differential MIC input or stereo line inputs,
AVPRE = 0dB, AVPGAM = 0dB 1 VP-P
Gain Error (Note 7) DC accuracy, measured with respect to 80% of full-
scale output 1 5 %
fS = 8kHz 1.2
Voice Path Phase Delay
1kHz, 0dB input, highpass
filter disabled measured from
analog input to digital output;
MODE = 0
(
IIR voice
)
fS = 16kHz 0.61
ms
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VPVDD = VMICVDD = VDVDD = VDVDDS1 = +1.8V, RL= ∞, headphone load (RL) connected between _OUTP and _OUTN, dif-
ferential modes, CREF = 2.2µF, CMICBIAS = CPREG = CREG = 1µF, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB,
AVVOL = 0dB, AVLO = 0dB, fMCLK = 13MHz, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.) (Note 2)
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
_______________________________________________________________________________________ 5
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Total Harmonic
Distortion THD f = 1kHz, fS = 8kHz, TA = +25°C, -20dB input -80 -70 dB
ADC Level Adjust AVADC AVL/AVR = 0xF to 0x0 -12 +3 dB
VAVDD = 1.65V to 1.95V, input referred 60 80
f = 217Hz, VRIPPLE = 100mVP-P, AVADC = 0dB,
input referred 80
f = 1kHz, VRIPPLE = 100mVP-P, AVADC = 0dB, input
referred 78
Power-Supply Rejection
Ratio PSRR
f = 10kHz, VRIPPLE = 100mVP-P, AVADC = 0dB,
input referred 72
dB
ADC VOICE MODE DIGITAL IIR LOWPASS FILTER
With respect to fS within ripple; fS = 8kHz to 48kHz 0.445 x fS
Passband Cutoff fPLP -3dB cutoff 0.449 x fS
Hz
Passband Ripple f < fPLP ±0.1 dB
Stopband Cutoff fSLP With respect to fS; fS = 8kHz to 48kHz 0.469 x fS Hz
Stopband Attenuation f > fSLP, f = 20Hz to 20kHz 74 dB
ADC VOICE MODE DIGITAL 5th-ORDER IIR HIGHPASS FILTER
AVFLT = 0x1
(Elliptical tuned for 16kHz GSM + 217Hz notch)
0.0161 x
fS
AVFLT = 0x2
(500Hz Butterworth tuned for 16kHz)
0.0312 x
fS
AVFLT = 0x3
(Elliptical tuned for 8kHz GSM + 217Hz notch)
0.0321 x
fS
AVFLT = 0x4
(500Hz Butterworth tuned for 8kHz)
0.0625 x
fS
Passband Cutoff
(-3dB from Peak) fAHPPB
AVFLT = 0x5 (fS/240 Butterworth) 0.0042 x fS
Hz
AVFLT = 0x1 (Elliptical tuned for 16kHz GSM +
217Hz notch)
0.0139 x
fS
AVFLT = 0x2 (500Hz Butterworth tuned for 16kHz) 0.0156 x fS
AVFLT = 0x3 (Elliptical tuned for 8kHz GSM +
217Hz notch)
0.0279 x
fS
AVFLT = 0x4 (500Hz Butterworth tuned for 8kHz) 0.0312 x fS
Stopband Cutoff
(-30dB from Peak) fAHPSB
AVFLT = 0x5 (fS/240 Butterworth) 0.0021 x fS
Hz
DC Attenuation DCATTEN AVFLT 000 90 dB
ADC STEREO AUDIO MODE DIGITAL FIR LOWPASS FILTER
With respect to fS within ripple; fS = 8kHz to 48kHz 0.43 x fS
-3dB cutoff 0.48 x fS
Passband Cutoff fPLP
-6.02dB cutoff 0.5 x fS
Hz
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VPVDD = VMICVDD = VDVDD = VDVDDS1 = +1.8V, RL= ∞, headphone load (RL) connected between _OUTP and _OUTN, dif-
ferential modes, CREF = 2.2µF, CMICBIAS = CPREG = CREG = 1µF, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB,
AVVOL = 0dB, AVLO = 0dB, fMCLK = 13MHz, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.) (Note 2)
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
6 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VPVDD = VMICVDD = VDVDD = VDVDDS1 = +1.8V, RL= ∞, headphone load (RL) connected between _OUTP and _OUTN, dif-
ferential modes, CREF = 2.2µF, CMICBIAS = CPREG = CREG = 1µF, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB,
AVVOL = 0dB, AVLO = 0dB, fMCLK = 13MHz, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.) (Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Passband Ripple f < fPLP ±0.1 dB
Stopband Cutoff fSLP With respect to fS; fS = 8kHz to 48kHz 0.58 x fS Hz
Stopband Attenuation f > fSLP, f = 20Hz to 20kHz 60 dB
ADC STEREO AUDIO MODE DIGITAL DC-BLOCKING HIGHPASS FILTER
Passband Cutoff
(-3dB from Peak) fAHPPB AVFLT = 0x1 0.000625
x fS Hz
DC Attenuation DCATTEN AVFLT = 0x1 90 dB
OUTPUT VOLUME CONTROL
VOLL/VOLR = 0x00 8.1 8.6 9.2
VOLL/VOLR = 0x01 7.6 8.1 8.6
VOLL/VOLR = 0x02 7.1 7.6 8.1
VOLL/VOLR = 0x04 6.1 6.6 7.2
VOLL/VOLR = 0x08 3.1 3.6 4.3
VOLL/VOLR = 0x10 -5.9 -5.4 -4.9
VOLL/VOLR = 0x20 -60 -55.1 -52
Output Volume Control
(Note 8)
VOLL/VOLR = 0x27 -94 -84 -81
dB
VOLL/VOLR = 00x00 to 0x06 (+9dB to +6dB) 0.5
VOLL/VOLR = 00x06 to 0x0F (+6dB to +3dB) 1
VOLL/VOLR = 00x0F to 0x17 (-3dB to -19dB) 2
Output Volume Control
Step Size
VOLL/VOLR = 00x17 to 0x27 (-19dB to -81dB) 4
dB
Output Volume Control
Mute Attenuation f = 1kHz 100 dB
HEADPHONE AMPLIFIER (Note 9)
RL = 16 25 48
Output Power
(Differential Mode) POUT f = 1kHz, 0dBFS input,
THD < 1%, TA = +25°CRL = 32 30
mW
RL = 16 17
Output Power
(Capacitorless Mode) POUT f = 1kHz, 0dBFS input,
THD < 1%, TA = +25°CRL = 32 10
mW
RL = 16 -78 -67
Total Harmonic
Distortion + Noise
(Differential Mode)
THD+N f = 1kHz, -3dBFS input
RL = 32 -79
dB
RL = 16 -73 -60
Total Harmonic
Distortion + Noise
(Capacitorless Mode)
THD+N f = 1kHz, -3dBFS input
RL = 32 -75
dB
RL = 16 -70 -60
Total Harmonic
Distortion + Noise
(Single-Ended Mode)
THD+N f = 1kHz, -3dBFS input
RL = 32 -70
dB
Dynamic Range
(Notes 5, 7) DR AVVOL = +6dB 77 90 dB
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
_______________________________________________________________________________________ 7
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VPVDD = VMICVDD = VDVDD = VDVDDS1 = +1.8V, RL= ∞, headphone load (RL) connected between _OUTP and _OUTN, dif-
ferential modes, CREF = 2.2µF, CMICBIAS = CPREG = CREG = 1µF, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB,
AVVOL = 0dB, AVLO = 0dB, fMCLK = 13MHz, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.) (Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
VAVDD = VPVDD = 1.65V to 1.95V 60 80
f = 217Hz, VRIPPLE = 100mVP-P, AVVOL = 0dB 80
f = 1kHz, VRIPPLE = 100mVP-P, AVVOL = 0dB 78
Power-Supply Rejection
Ratio (Note 7) PSRR
f = 10kHz, VRIPPLE = 100mVP-P, AVVOL = 0dB 72
dB
AVVOL = -81dB,
differential mode
LOUTP to LOUTN, ROUTP to
ROUTN, TA = +25°C±0.2
Output Offset Voltage VOS AVVOL = -81dB,
capacitorless mode
LOUTP to LOUTN, ROUTP to
LOUTN, TA = +25°C±0.6
mV
Differential, POUT = 5mW, f = 1kHz 90
Crosstalk XTALK
Capacitorless mode, POUT = 5mW, f = 1kHz 45 dB
RL = 32 500
Capacitive Drive
Capability No sustained oscillations RL = 100 pF
Into shutdown -70
Click-and-Pop Level
(Differential,
Capacitorless Modes)
Peak voltage, A-weighted,
32 samples per second Out of shutdown -70
dBV
Into shutdown -70
Click-and-Pop Level
(Single-Ended Mode)
Peak voltage, A-weighted,
32 samples per second Out of shutdown -70 dBV
LINE OUTPUTS (Note 7)
Full-Scale Output 0.5 VRMS
LOGL/LOGR = 0x00 -0.7 -0.1 +0.6
LOGL/LOGR = 0x01 -2.6 -2.1 -1.6
LOGL/LOGR = 0x02 -4.6 -4.1 -3.6
LOGL/LOGR = 0x04 -8.6 -8.1 -7.6
LOGL/LOGR = 0x08 -16.6 -16 -15.6
Line Output Level
Adjust AVLO
LOGL/LOGR = 0x0F -31.1 -29.9 -29.1
dB
Line Output Mute
Attenuation f = 1kHz 90 dB
Total Harmonic
Distortion + Noise THD+N RL = 1k, f = 1kHz, VOUT = 1.4VP-P (Note 9) -67 -59 dB
20Hz < f < 20kHz 86
Signal-to-Noise Ratio RL = 1k, LINL/LINR =
1µF to GND A-weighted 90 dB
VAVDD = VPVDD = 1.65V to 1.95V 46
f = 217Hz, VRIPPLE = 100mVP-P, AVVOL = 0dB 78
f = 1kHz, VRIPPLE = 100mVP-P, AVVOL = 0dB 80
Power-Supply Rejection
Ratio PSRR
f = 10kHz, VRIPPLE = 100mVP-P, AVVOL = 0dB 76
dB
Capacitive Drive
Capability R
L = 10k, no sustained oscillations 100 pF
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
8 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VPVDD = VMICVDD = VDVDD = VDVDDS1 = +1.8V, RL= ∞, headphone load (RL) connected between _OUTP and _OUTN, dif-
ferential modes, CREF = 2.2µF, CMICBIAS = CPREG = CREG = 1µF, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB,
AVVOL = 0dB, AVLO = 0dB, fMCLK = 13MHz, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.) (Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
MICROPHONE AMPLIFIER
PALEN/PAREN = 01 -0.5 0 +0.5
PALEN/PAREN = 10 19.5 20 20.5
Preamplifier Gain AVPRE
PALEN/PAREN = 11 29.3 30 30.5
dB
PGAML/PGAMR = 0x1F -0.5 0 +0.6
MIC PGA Gain AVPGAM PGAML/PGAMR = 0x00 19.3 19.9 20.4 dB
Common-Mode
Rejection Ratio CMRR VIN = 100mVP-P, f = 217Hz 50 dB
MIC Input Resistance RIN_MIC All gain settings 30 50 k
AVPRE = 0dB
VIN = 1VP-P, f = 1kHz, A-weighted -80
Total Harmonic
Distortion + Noise THD+N
AVPRE = +30dB
VIN = 32mVP-P, f = 1kHz, A-weighted -65
dB
VAVDD = 1.65V to 1.95V, input referred 60 80
f = 217Hz, VRIPPLE = 100mV, AVADC = 0dB, input
referred 80
f = 1kHz, VRIPPLE = 100mV, AVADC = 0dB, input
referred 78
Power-Supply Rejection
Ratio PSRR
f = 10kHz, VRIPPLE = 100mV, AVADC = 0dB, input
referred 72
dB
MICROPHONE BIAS
VMICVDD = 1.8V, MBIAS = 0 1.48 1.52 1.56
MICBIAS Output Voltage VMICBIAS I
LOAD = 1mA VMICVDD = 3V, MBIAS = 0 2.15 2.2 2.25 V
Load Regulation ILOAD = 1mA to 2mA, MBIAS = 0 0.6 10 V/A
Line Regulation VAVDD = 1.8V, VMICVDD = 1.65V to 1.95V, MBIAS = 0 1.55 mV/V
f = 217Hz, VRIPPLE = 100mVP-P 100
Power-Supply Rejection
Ratio PSRR f = 10kHz, VRIPPLE = 100mVP-P 90
dB
Noise Voltage A-weighted 9.5 µVRMS
LINE INPUT
Full-Scale Input VIN AVLINE = 0dB 1.0 VP-P
LIGL/LIGR = 0x00 22.8 23.9 24.9
LIGL/LIGR = 0x01 20.7 21.9 22.9
LIGL/LIGR = 0x02 18.9 20 20.9
LIGL/LIGR = 0x04 14.9 16 16.9
Line Input Level Adjust AVLINE
LIGL/LIGR = 0x08 6.9 8 8.9
dB
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
_______________________________________________________________________________________ 9
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VPVDD = VMICVDD = VDVDD = VDVDDS1 = +1.8V, RL= ∞, headphone load (RL) connected between _OUTP and _OUTN, dif-
ferential modes, CREF = 2.2µF, CMICBIAS = CPREG = CREG = 1µF, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB,
AVVOL = 0dB, AVLO = 0dB, fMCLK = 13MHz, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.) (Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Line Input Mute
Attenuation f = 1kHz 100 dB
Input Resistance RIN_LINE AVLINE = +24dB 20 k
Total Harmonic
Distortion + Noise THD+N VIN = 0.1VP-P, f = 1kHz -74 dB
AUXIN INPUT
Input DC Voltage Range AUXEN = 1 0 0.738 V
AUXIN Input Resistance RIN AUXEN = 1, 0V VAUXIN 0.738V 10 40 M
JACK DETECT
SHDN = 1 0.92 x
VMICBIAS
0.95 x
VMICBIAS
0.98 x
VMICBIAS
JACKSNS High
Threshold VTH1
SHDN = 0 0.95 x
VMICVDD
D
V
SHDN = 1 0.06 x
VMICBIAS
0.10 x
VMICBIAS
0.17 x
VMICBIAS
JACKSNS Low
Threshold VTH2
SHDN = 0 0.08 x
VMICVDD
V
JACKSNS Sense
Voltage VSENSE SHDN = 0 VMICVDD V
JACKSNS Sense
Resistance RSENSE SHDN = 0 1.9 2.3 3.1 k
JACKSNS Deglitch
Period tGLITCH 12 300 ms
Headphone Sense
Threshold 8
1-BIT SPDM OUTPUT
Dynamic Range
(Note 5) DR fS = 48kHz, A-weighted, 20Hz to 20kHz,
AVVOL = 0dB; master or slave mode, TA = +25°C 90 dB
Output Operational
Range 0dB signal 1’s density 25 75 %
DIGITAL SIDETONE (MODE = 1 IIR Voice Mode Only)
Sidetone Gain Adjust
Range AVSTGA Differential output mode -60 0 dB
fS = 8kHz 2.2
Voice Path Phase Delay PDLY
MIC input to headphone
output, f = 1kHz, HP filter
disabled fS = 16kHz 1.1
ms
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
10 ______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VPVDD = VMICVDD = VDVDD = VDVDDS1 = +1.8V, RL= ∞, headphone load (RL) connected between _OUTP and _OUTN, dif-
ferential modes, CREF = 2.2µF, CMICBIAS = CPREG = CREG = 1µF, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB,
AVVOL = 0dB, AVLO = 0dB, fMCLK = 13MHz, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.) (Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
INPUT CLOCK CHARACTERISTICS
MCLK Input Frequency fMCLK For any LRCLK sample rate 10 60 MHz
Prescaler = /1 mode 40 60
MCLK Input Duty Cycle /2 or /4 modes 30 70 %
Maximum MCLK Input
Jitter Maximum allowable RMS for performance limits 100 ps
DHF = 0 8 48
LRCLK Sample Rate
(Note 10) DHF = 1 48 96 kHz
FREQ1 mode = 0x8 to 0xF 0 0
PCLK = 192x, 256x, 384x, 512x, 768x, and 1024x 0 0
LRCLK Average
Frequency Error (Master
and Slave Modes)
(Note 11) FREQ1 mode = Any clock other than above -0.025 +0.025
%
Rapid lock mode 2 7
LRCLK PLL Lock Time Any allowable LRCLK and
PCLK rate, slave mode Nonrapid lock mode 12 25 ms
LRCLK Acceptable
Jitter for Maintaining
PLL Lock
Allowable LRCLK period change from nominal for
slave PLL mode at any allowable LRCLK and PCLK
rates
±100 ns
Soft-Start/Stop Time 10 ms
CRYSTAL OSCILLATOR
Frequency Fundamental mode only 12.288 MHz
Maximum Crystal ESR 100
Input Leakage Current IIH, IIL X1, TA = +25°C -1 +1 µA
Input Capacitance CX1, CX2 4 pF
Maximum Load
Capacitor CL1, CL2 45 pF
DIGITAL INPUT (MCLK)
Input High Voltage VIH 1.2 V
Input Low Voltage VIL 0.6 V
Input Leakage Current IIH, IIL T
A = +25°C -1 +1 µA
Input Capacitance 10 pF
DIGITAL INPUTS (SDINS1, BCLKS1, LRCLKS1)
Input High Voltage VIH 0.7
x VDVDDS1 V
Input Low Voltage VIL 0.3
x VDVDDS1 V
Input Hysteresis 200 mV
Input Leakage Current IIH, IIL TA = +25°C -1 +1 µA
Input Capacitance 10 pF
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
______________________________________________________________________________________ 11
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VPVDD = VMICVDD = VDVDD = VDVDDS1 = +1.8V, RL= ∞, headphone load (RL) connected between _OUTP and _OUTN, dif-
ferential modes, CREF = 2.2µF, CMICBIAS = CPREG = CREG = 1µF, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB,
AVVOL = 0dB, AVLO = 0dB, fMCLK = 13MHz, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.) (Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DIGITAL INPUTS (SDA, SCL, DIN, SCLK, CS, MODE, SDINS2, BCLKS2, LRCLKS2)
Input High Voltage VIH 0.7
x VDVDD V
Input Low Voltage VIL 0.3
x VDVDD V
Input Hysteresis 200 mV
Input Leakage Current IIH, IIL T
A = +25°C -1 +1 µA
Input Capacitance 10 pF
DIGITAL INPUTS (DIGMICDATA)
Input High Voltage VIH 0.65
x VDVDD V
Input Low Voltage VIL 0.35
x VDVDD V
Input Hysteresis 100 mV
Input Leakage Current IIH, IIL TA = +25°C -35 +35 µA
Input Capacitance 10 pF
CMOS DIGITAL OUTPUTS (BCLKS1, LRCLKS1, SDOUTS1)
Output Low Voltage VOL I
OL = 3mA 0.4 V
Output High Voltage VOH I
OH = 3mA VDVDDS1
- 0.4 V
CMOS DIGITAL OUTPUTS (BCLKS2, LRCLKS2, SDOUTS2)
Output Low Voltage VOL I
OL = 3mA 0.4 V
Output High Voltage VOH I
OH = 3mA VDVDD
- 0.4 V
CMOS DIGITAL OUTPUTS (DOUT)
Output Low Voltage VOL I
OL = 1mA, CS = DVDD 0.4 V
Output High Voltage VOH I
OH = 1mA, CS = DVDD VDVDD
- 0.4 V
Output Low Current IOL MODE = DVDD, DOUT = 0, TA = +25°C -1 +1 µA
Output High Current IOH MODE = DVDD, DOUT = DVDD, TA = +25°C -1 +1 µA
CMOS DIGITAL OUTPUTS (DIGMICCLK, SPDMDATA, SPDMCLK)
Output Low Voltage VOL I
OL = 1mA 0.4 V
Output High Voltage VOH I
OH = 1mA VDVDD
- 0.4 V
OPEN-DRAIN DIGITAL OUTPUTS (SDA, IRQ)
Output High Current IOH V
OUT = VDVDD, TA = +25°C -1 +1 µA
Output Low Voltage VOL I
OL = 3mA 0.2
x VDVDD V
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
12 ______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VPVDD = VMICVDD = VDVDD = VDVDDS1 = +1.8V, RL= ∞, headphone load (RL) connected between _OUTP and _OUTN, dif-
ferential modes, CREF = 2.2µF, CMICBIAS = CPREG = CREG = 1µF, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB,
AVVOL = 0dB, AVLO = 0dB, fMCLK = 13MHz, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.) (Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DIGITAL MICROPHONE TIMING CHARACTERISTICS (VDVDD = 1.8V)
MICCLK = 00 1.536
MICCLK = 01 2.048
DIGMICCLK Frequency fMICCLK f
MCLK = 12.288MHz
MICCLK = 10 64fS
MHz
DIGMICDATA to
DIGMICCLK Setup Time tSU, MIC Either clock edge 20 ns
DIGMICDATA to
DIGMICCLK Hold Time tHD, M IC Either clock edge 0 ns
SPDM TIMING CHARACTERISTICS
SPDMCLK = 00 1.536
SPDMCLK = 01 2.048
SPDMCLK Frequency fSPDMCLK f
MCLK = 12.288MHz
SPDMCLK = 10 3.072
MHz
Minimum, fMCLK = 20MHz 15
SPDMCLK to
SPDMDATA Delay Time tDLY,S PDM
Rising edge SPDMCLK
to right-channel valid
SPDMDATA and falling
edge SPDMCLK to left-
channel valid
SPDMDATA
Maximum, fMCLK = 10MHz 65
ns
DIGITAL AUDIO INTERFACE TIMING CHARACTERISTICS (TDM = 0, VDVDD = 1.8V)
BCLK Cycle Time tBCLKS 75 ns
BCLK High Time tBCLKH T
A = +25°C 30 ns
BCLK Low Time tBCLKL T
A = +25°C 30 ns
BCLK or LRCLK Rise
and Fall Time tR, tF Master operation, CL = 15pF 7 ns
SDIN or LRCLK to BCLK
Setup Time tSU 20 ns
SDIN or LRCLK to BCLK
Hold Time tHD 5 ns
SDOUT Delay Time from
BCLK Rising Edge tDLY C
L = 30pF 0 40 ns
DIGITAL AUDIO INTERFACE TIMING CHARACTERISTICS (TDM = 1, Figure 3, VDVDD = 1.8V)
TDM Clock Frequency 1/tCLK TDM mode (TDM = 1) 128 2048 kHz
TDM Clock Time High tCLKH TDM mode (TDM = 1), TA = +25°C 220 ns
TDM Clock Time Low tCLKL TDM mode (TDM = 1), TA = +25°C 220 ns
Short TDM mode (TDM = 1, FSW = 0), master mode
(MAS = 1) 200
TDM Short-Sync Setup
Time tSYNCSET Short TDM mode (TDM = 1, FSW = 0), slave mode
(MAS = 0) 20
ns
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
______________________________________________________________________________________ 13
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VPVDD = VMICVDD = VDVDD = VDVDDS1 = +1.8V, RL= ∞, headphone load (RL) connected between _OUTP and _OUTN, dif-
ferential modes, CREF = 2.2µF, CMICBIAS = CPREG = CREG = 1µF, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB,
AVVOL = 0dB, AVLO = 0dB, fMCLK = 13MHz, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.) (Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Short TDM mode (TDM = 1, FSW = 0), master mode
(MAS = 1) 200
TDM Short Sync Hold
Time tSYNCHOLD Short TDM mode (TDM = 1, FSW = 0), slave mode
(MAS = 0) 20
ns
TDM Short Sync Tx Data
Delay tSYNCTX Short TDM mode (TDM = 1, FSW = 0) 12 ns
TDM Long Sync Start
Delay tCLKSYNC Long TDM mode (TDM = 1, FSW = 1) 3.4 ns
TDM Long Sync End
Time Setup tENDSYNC Long TDM mode (TDM = 1, FSW = 1) 51 ns
TDM Data Delay from
Clock tCLKTX TDM mode (TDM = 1) 40 ns
TDM High-Impedance
State Setup from Data tHIZOUT TDM mode (TDM = 1) 120 ns
TDM Rx Data Setup
Time tSETUP TDM mode (TDM = 1) 20 ns
TDM Rx Data Hold Time tHOLD TDM mode (TDM = 1) 20 ns
I2C TIMING CHARACTERISTICS (VDVDD = 1.65V)
Serial-Clock Frequency fSCL 0 400 kHz
Bus Free Time Between
STOP and START
Conditions
tBUF 1.3 µs
Hold Time (Repeated)
START Condition tHD,STA 0.6 µs
SCL Pulse-Width Low tLOW 1.3 µs
SCL Pulse-Width High tHIGH 0.6 µs
Setup Time for a
Repeated START
Condition
tSU,STA 0.6 µs
Data Hold Time tHD,DAT R
PU,SDA = 475 0 900 ns
Data Setup Time tSU,DAT 100 ns
SDA and SCL Receiving
Rise Time tR (Note 12) 20 +
0.1CB 300 ns
SDA and SCL Receiving
Fall Time tF (Note 12) 20 +
0.1CB 300 ns
SDA Transmitting Fall
Time tF R
PU,SDA = 475 (Note 12) 20 +
0.1CB 250 ns
Setup Time for STOP
Condition tSU,STO 0.6 µs
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
14 ______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VPVDD = VMICVDD = VDVDD = VDVDDS1 = +1.8V, RL= ∞, headphone load (RL) connected between _OUTP and _OUTN, dif-
ferential modes, CREF = 2.2µF, CMICBIAS = CPREG = CREG = 1µF, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB,
AVVOL = 0dB, AVLO = 0dB, fMCLK = 13MHz, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.) (Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Bus Capacitance CB 400 pF
Pulse Width of
Suppressed Spike tSP 0 50 ns
SPI TIMING CHARACTERISTICS
Minimum SCLK Clock
Period tCP 40 ns
Minimum SCLK Pulse-
Width Low tCL 18 ns
Minimum SCLK Pulse-
Width High tCH 18 ns
Minimum CS Setup
Time tCSS 20 ns
Minimum CS Hold Time tCSH 20 ns
Minimum CS Pulse-
Width High tCSW 20 ns
Minimum DIN Setup Time tDS 5 ns
Minimum DIN Hold Time tDH 5 ns
Minimum Output Data
Propagation Delay tDO C
L = 50pF 9 ns
Minimum Output Data
Enable Time tDEN 5 ns
Minimum Output Data
Disable Time tDZ 5 ns
Note 2: The MAX9880A is 100% production tested at TA= +25°C. Specifications over temperature limits are guaranteed by
design.
Note 3: Clocking all zeros into the DAC. Master mode. Differential headphone mode.
Note 4: DAC performance measured at headphone outputs.
Note 5: Dynamic range measured using the EIAJ method. -60dBFS 1kHz output signal, A-weighted, and normalized to 0dBFS.
f = 20Hz to 20kHz.
Note 6: Performance measured using microphone inputs, unless otherwise stated.
Note 7: Performance measured using line inputs.
Note 8: Performance measured using line inputs to line outputs.
Note 9: Performance measured using DAC. fMCLK = 12.288MHz, fLRCLK = 48kHz, unless otherwise stated.
Note 10: LRCLK can be any rate in the indicated range. Asynchronous or noninteger MCLK/LRCLK ratios can exhibit some full-
scale performance degradation compared to synchronous integer-related MCLK/LRCLK ratios.
Note 11: In master-mode operation, the accuracy of the MCLK input proportionally determines the accuracy of the sample clock
rate.
Note 12: CBis in pF.
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
______________________________________________________________________________________
15
TOTAL HARMONIC DISTORTION + NOISE
vs. POWER OUT (DAC TO HEADPHONE)
MAX9880A toc01
POWER OUT (mW)
THD+N (dB)
40302010
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-100
050
fMCLK = 13MHz
fLRCLK = 8kHz
RLOAD = 32Ω
DIFFERENTIAL MODE
3kHz 1kHz
20Hz
TOTAL HARMONIC DISTORTION + NOISE
vs. POWER OUT (DAC TO HEADPHONE)
MAX9880A toc02
POWER OUT (mW)
THD+N (dB)
5040302010
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-100
060
fMCLK = 13MHz
fLRCLK = 8kHz
RLOAD = 16Ω
DIFFERENTIAL MODE
3kHz
1kHz
20Hz
TOTAL HARMONIC DISTORTION + NOISE
vs. POWER OUT (DAC TO HEADPHONE)
MAX9880A toc03
POWER OUT (mW)
THD+N (dB)
40302010
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-100
050
fMCLK = 12.288MHz
fLRCLK = 48kHz
RLOAD = 32Ω
DIFFERENTIAL MODE
6kHz 1kHz
20Hz
TOTAL HARMONIC DISTORTION + NOISE
vs. POWER OUT (DAC TO HEADPHONE)
MAX9880A toc04
POWER OUT (mW)
THD+N (dB)
5040302010
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-100
060
fMCLK = 12.288MHz
fLRCLK = 48kHz
RLOAD = 16Ω
DIFFERENTIAL MODE
6kHz
1kHz
20Hz
TOTAL HARMONIC DISTORTION + NOISE
vs. POWER OUT (DAC TO HEADPHONE)
MAX9880A toc05
POWER OUT (mW)
THD+N (dB)
40302010
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-100
050
fMCLK = 12.288MHz
fLRCLK = 96kHz
RLOAD = 32Ω
DIFFERENTIAL MODE
6kHz
1kHz
20Hz
TOTAL HARMONIC DISTORTION + NOISE
vs. POWER OUT (DAC TO HEADPHONE)
MAX9880A toc06
POWER OUT (mW)
THD+N (dB)
5040302010
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-100
060
fMCLK = 12.288MHz
fLRCLK = 96kHz
RLOAD = 16Ω
DIFFERENTIAL MODE
6kHz
1kHz
20Hz
TOTAL HARMONIC DISTORTION + NOISE
vs. FREQUENCY (DAC TO HEADPHONE)
MAX9880A toc07
FREQUENCY (Hz)
THD+N (dB)
1000100
-85
-80
-75
-70
-90
10 10,000
fMCLK = 13MHz
fLRCLK = 8kHz
RLOAD = 32Ω
DIFFERENTIAL MODE
5mW
20mW
TOTAL HARMONIC DISTORTION + NOISE
vs. FREQUENCY (DAC TO HEADPHONE)
MAX9880A toc08
FREQUENCY (Hz)
THD+N (dB)
1000100
-88
-86
-84
-82
-80
-78
-76
-74
-72
-70
-90
10 10,000
fMCLK = 13MHz
fLRCLK = 8kHz
RLOAD = 16Ω
DIFFERENTIAL MODE
5mW
20mW
TOTAL HARMONIC DISTORTON + NOISE
vs. FREQUENCY (DAC TO HEADPHONE)
MAX9880A toc09
FREQUENCY (Hz)
THD+N (dB)
10k1k100
-88
-86
-84
-82
-80
-78
-76
-74
-72
-70
-90
10 100k
fMCLK = 12.288MHz
fLRCLK = 48kHz
RLOAD = 32Ω
DIFFERENTIAL MODE
5mW
20mW
Typical Operating Characteristics
(VAVDD = VPVDD = VMICVDD = VDVDD = VDVDDS1 = +1.8V, RL= ∞, headphone load (RL) connected between _OUTP and _OUTN,
CREF = 2.2µF, CMICBIAS = CPREG = CREG = 1µF, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB, AVVOL = 0dB,
AVLO = 0dB, fMCLK = 13MHz, differential output, unless otherwise noted.)
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
16 ______________________________________________________________________________________
TOTAL HARMONIC DISTORTON + NOISE
vs. FREQUENCY (DAC TO HEADPHONE)
MAX9880A toc10
FREQUENCY (Hz)
THD+N (dB)
10k1k100
-88
-86
-84
-82
-80
-78
-76
-74
-72
-70
-90
10 100k
fMCLK = 12.288MHz
fLRCLK = 48kHz
RLOAD = 16Ω
DIFFERENTIAL MODE
5mW
20mW
TOTAL HARMONIC DISTORTON + NOISE
vs. FREQUENCY (DAC TO HEADPHONE)
MAX9880A toc11
FREQUENCY (Hz)
THD+N (dB)
10k1k100
-88
-86
-84
-82
-80
-78
-76
-74
-72
-70
-90
10 100k
fMCLK = 12.288MHz
fLRCLK = 96kHz
RLOAD = 32Ω
DIFFERENTIAL MODE
5mW
20mW
TOTAL HARMONIC DISTORTON + NOISE
vs. FREQUENCY (DAC TO HEADPHONE)
MAX9880A toc12
FREQUENCY (Hz)
THD+N (dB)
10k1k100
-88
-86
-84
-82
-80
-78
-76
-74
-72
-70
-90
10 100k
fMCLK = 12.288MHz
fLRCLK = 96kHz
RLOAD = 16Ω
DIFFERENTIAL MODE
5mW
20mW
TOTAL HARMONIC DISTORTION + NOISE
vs. POWER OUT (DAC TO HEADPHONE)
MAX9880A toc13
POWER OUT (mW)
THD+N (dB)
105
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-100
015
fMCLK = 13MHz
fLRCLK = 8kHz
RLOAD = 32Ω
CAPACITORLESS MODE
3kHz
1kHz
20Hz
TOTAL HARMONIC DISTORTION + NOISE
vs. POWER OUT (DAC TO HEADPHONE)
MAX9880A toc14
POWER OUT (mW)
THD+N (dB)
105
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-100
015
fMCLK = 12.288MHz
fLRCLK = 48kHz
RLOAD = 32Ω
CAPACITORLESS MODE
6kHz 1kHz
20Hz
TOTAL HARMONIC DISTORTION + NOISE
vs. POWER OUT (DAC TO HEADPHONE)
MAX9880A toc15
POWER OUT (mW)
THD+N (dB)
105
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-100
015
fMCLK = 12.288MHz
fLRCLK = 96kHz
RLOAD = 32Ω
CAPACITORLESS MODE
1kHz
6kHz
20Hz
TOTAL HARMONIC DISTORTION + NOISE
vs. FREQUENCY (DAC TO HEADPHONE)
MAX9880A toc16
FREQUENCY (Hz)
THD+N (dB)
1000100
-85
-80
-75
-70
-65
-60
-90
10 10,000
fMCLK = 13MHz
fLRCLK = 8kHz
RLOAD = 32Ω
CAPACITORLESS MODE
1mW
5mW
TOTAL HARMONIC DISTORTION + NOISE
vs. FREQUENCY (DAC TO HEADPHONE)
MAX9880A toc17
FREQUENCY (Hz)
THD+N (dB)
10k1k100
-85
-80
-75
-70
-65
-60
-90
10 100k
fMCLK = 12.288MHz
fLRCLK = 48kHz
RLOAD = 32Ω
CAPACITORLESS MODE
1mW
5mW
TOTAL HARMONIC DISTORTION + NOISE
vs. FREQUENCY (DAC TO HEADPHONE)
MAX9880A toc18
FREQUENCY (Hz)
THD+N (dB)
10k1k100
-85
-80
-75
-70
-65
-60
-90
10 100k
fMCLK = 12.288MHz
fLRCLK = 96kHz
RLOAD = 32Ω
CAPACITORLESS MODE
5mW
20mW
Typical Operating Characteristics (continued)
(VAVDD = VPVDD = VMICVDD = VDVDD = VDVDDS1 = +1.8V, RL= ∞, headphone load (RL) connected between _OUTP and _OUTN,
CREF = 2.2µF, CMICBIAS = CPREG = CREG = 1µF, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB, AVVOL = 0dB,
AVLO = 0dB, fMCLK = 13MHz, differential output, unless otherwise noted.)
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
______________________________________________________________________________________
17
TOTAL HARMONIC DISTORTION + NOISE
vs. POWER OUT (DAC TO HEADPHONE)
MAX9880A toc19
POWER OUT (mW)
THD+N (%)
108642
-85
-80
-75
-70
-65
-60
-55
-50
-45
-40
-90
012
3kHz
1kHz
20Hz
fMCLK = 13MHz
fLRCLK = 8kHz
RLOAD = 32Ω
SINGLE-ENDED MODE
TOTAL HARMONIC DISTORTION + NOISE
vs. POWER OUT (DAC TO HEADPHONE)
MAX9880A toc20
POWER OUT (mW)
THD+N (%)
108642
-85
-80
-75
-70
-65
-60
-55
-50
-45
-40
-90
012
6kHz
1kHz
20Hz
fMCLK = 12.288MHz
fLRCLK = 48kHz
RLOAD = 32Ω
SINGLE-ENDED MODE
TOTAL HARMONIC DISTORTION + NOISE
vs. POWER OUT (DAC TO HEADPHONE)
MAX9880A toc21
POWER OUT (mW)
THD+N (dB)
12963
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-100
015
fMCLK = 12.288MHz
fLRCLK = 96kHz
RLOAD = 32Ω
SINGLE-ENDED MODE
1kHz
6kHz
20Hz
TOTAL HARMONIC DISTORTION + NOISE
vs. FREQUENCY (DAC TO HEADPHONE)
MAX9880A toc22
FREQUENCY (Hz)
THD+N (dB)
1000100
-85
-80
-75
-70
-65
-60
-90
10 10,000
fMCLK = 13MHz
fLRCLK = 8kHz
RLOAD = 32Ω
SINGLE-ENDED MODE
1mW
5mW
TOTAL HARMONIC DISTORTON + NOISE
vs. FREQUENCY (DAC TO HEADPHONE)
MAX9880A toc23
FREQUENCY (Hz)
THD+N (dB)
10k1k100
-88
-86
-84
-82
-80
-78
-76
-74
-72
-70
-90
10 100k
1mW
5mW
fMCLK = 12.288MHz
fLRCLK = 48kHz
RLOAD = 32Ω
SINGLE-ENDED MODE
TOTAL HARMONIC DISTORTION + NOISE
vs. FREQUENCY (DAC TO HEADPHONE)
MAX9880A toc24
FREQUENCY (Hz)
THD+N (dB)
10k1k100
-85
-80
-75
-70
-65
-60
-90
10 100k
fMCLK = 12.288MHz
fLRCLK = 96kHz
RLOAD = 32Ω
SINGLE-ENDED MODE
5mW
20mW
TOTAL HARMONIC DISTORTION + NOISE
vs. POWER OUT (LINE-IN TO HEADPHONE)
MAX9880A toc25
POWER OUT (mW)
THD+N (dB)
40302010
-80
-70
-60
-50
-40
-30
-20
-10
0
-90
050
LINE-IN PREAMP = +18dB
RLOAD = 32Ω
DIFFERENTIAL MODE
6kHz
1kHz
20Hz
TOTAL HARMONIC DISTORTION + NOISE
vs. POWER OUT (LINE-IN TO HEADPHONE)
MAX9880A toc26
POWER OUT (mW)
THD+N (dB)
40302010
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-100
050
6kHz
1kHz
20Hz
LINE-IN PREAMP = 0dB
RLOAD = 32Ω
DIFFERENTIAL MODE
TOTAL HARMONIC DISTORTION + NOISE
vs. FREQUENCY (LINE-IN TO HEADPHONE)
MAX9880A toc27
FREQUENCY (Hz)
THD+N (%)
10,0001000100
0.01
0.1
1
10
0.001
10 100,000
LINE-IN PREAMP = +18dB
RLOAD = 32I
DIFFERENTIAL MODE
5mW
20mW
Typical Operating Characteristics (continued)
(VAVDD = VPVDD = VMICVDD = VDVDD = VDVDDS1 = +1.8V, RL= ∞, headphone load (RL) connected between _OUTP and _OUTN,
CREF = 2.2µF, CMICBIAS = CPREG = CREG = 1µF, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB, AVVOL = 0dB,
AVLO = 0dB, fMCLK = 13MHz, differential output, unless otherwise noted.)
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
18 ______________________________________________________________________________________
TOTAL HARMONIC DISTORTION + NOISE
vs. FREQUENCY (LINE-IN TO HEADPHONE)
MAX9880A toc28
FREQUENCY (Hz)
THD+N (%)
10,0001000100
0.01
0.1
1
10
0.001
10 100,000
LINE-IN PREAMP = 0dB
RLOAD = 32I
DIFFERENTIAL MODE
5mW
20mW
TOTAL HARMONIC DISTORTION + NOISE
vs. FREQUENCY (DAC TO LINE-OUT)
MAX9880A toc29
FREQUENCY (Hz)
THD+N (dB)
1000100
-80
-70
-60
-50
-40
-30
-90
10 10,000
fMCLK = 13MHz
fLRCLK = 8kHz
0dBFS
FIR
IIR
POWER OUT vs. HEADPHONE LOAD
MAX9880A toc30
HEADPHONE LOAD (Ω)
POWER OUT (mW)
10010
5
10
15
20
25
30
35
40
45
50
0
1 1000
fMCLK = 12.288MHz
fLRCLK = 48kHz
THD+N ≤ 0.1%
DIFFERENTIAL MODE
OUTPUT POWER vs. LOAD RESISTANCE
(DAC TO HEADPHONE)
MAX9880A toc31
HEADPHONE LOAD (Ω)
POWER OUT (mW)
10010
5
10
15
20
25
0
1 1000
fMCLK = 12.288MHz
fLRCLK = 48kHz
THD+N ≤ 0.1%
CAPACITORLESS MODE
POWER OUT vs. HEADPHONE LOAD
MAX9880A toc32
HEADPHONE LOAD (Ω)
POWER OUT (mW)
10010
5
10
15
20
25
0
1 1000
fMCLK = 12.288MHz
fLRCLK = 48kHz
THD+N ≤ 0.1%
SINGLE-ENDED MODE
TOTAL HARMONIC DISTORTION + NOISE
vs. FREQUENCY (MICROPHONE TO ADC)
MAX9880A toc33
FREQUENCY (Hz)
THD+N (%)
1000100
0.01
0.1
1
10
0.001
10 10,000
fMCLK = 13MHz
fLRCLK = 8kHz
MICPRE = 0dB
VIN = 1VP-P
TOTAL HARMONIC DISTORTION + NOISE
vs. FREQUENCY (MICROPHONE TO ADC)
MAX9880A toc34
FREQUENCY (Hz)
THD+N (%)
1000100
0.01
0.1
1
10
0.001
10 10,000
fMCLK = 13MHz
fLRCLK = 8kHz
MICPRE = +20dB
VIN = 100mVP-P
TOTAL HARMONIC DISTORTION + NOISE
vs. FREQUENCY (MICROPHONE TO ADC)
MAX9880A toc35
FREQUENCY (Hz)
THD+N (%)
1000100
0.01
0.1
1
10
100
0.001
10 10,000
fMCLK = 13MHz
fLRCLK = 8kHz
MICPRE = +30dB
VIN = 32mVP-P
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY (DAC TO HEADPHONE)
MAX9880A toc36
FREQUENCY (Hz)
PSRR (dB)
10k1k10010
-100
-80
-60
-40
-20
0
-120
1 100k
fMCLK = 12.288MHz
fLRCLK = 48kHz
VRIPPLE = 100mVP-P
Typical Operating Characteristics (continued)
(VAVDD = VPVDD = VMICVDD = VDVDD = VDVDDS1 = +1.8V, RL= ∞, headphone load (RL) connected between _OUTP and _OUTN,
CREF = 2.2µF, CMICBIAS = CPREG = CREG = 1µF, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB, AVVOL = 0dB,
AVLO = 0dB, fMCLK = 13MHz, differential output, unless otherwise noted.)
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
______________________________________________________________________________________
19
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY (MICROPHONE TO ADC)
MAX9880A toc37
FREQUENCY (Hz)
PSRR (dB)
10k1k10010
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-100
1 100k
VRIPPLE = 100mVP-P
fMCLK = 12.288MHz
fLRCLK = 48kHz
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY (MICBIAS)
MAX9880A toc38
FREQUENCY (Hz)
PSRR (dB)
10k1k10010
-100
-80
-60
-40
-20
0
-120
1 100k
VRIPPLE = 100mVP-P
FFT, DAC TO HEADPHONE,
0dBFS, fMCLK = 13MHz, fLRCLK = 8kHz
MAX9880A toc39
FREQUENCY (Hz)
AMPLITUDE (dB)
15k10k5k
-120
-100
-80
-60
-40
-20
0
20
-140
020k
FREQ1 = 0xA
FFT, DAC TO HEADPHONE,
-60dBFS, fMCLK = 13MHz, fLRCLK = 8kHz
MAX9880A toc40
FREQUENCY (Hz)
AMPLITUDE (dB)
15k10k5k
-120
-100
-80
-60
-40
-20
0
20
-140
0 20k
FREQ1 = 0xA
FFT, DAC TO HEADPHONE,
0dBFS, fMCLK = 12.288MHz, fLRCLK = 48kHz
MAX9880A toc41
FREQUENCY (Hz)
AMPLITUDE (dB)
15k10k5k
-120
-100
-80
-60
-40
-20
0
20
-140
0 20k
NI = 0x6000
FFT, DAC TO HEADPHONE,
-60dBFS, fMCLK = 12.288MHz, fLRCLK = 48kHz
MAX9880A toc42
FREQUENCY (Hz)
AMPLITUDE (dB)
15k10k5k
-120
-100
-80
-60
-40
-20
0
20
-140
0 20k
NI = 0x6000
FFT, DAC TO HEADPHONE,
0dBFS, fMCLK = 12.288MHz, fLRCLK = 96kHz
MAX9880A toc43
FREQUENCY (Hz)
AMPLITUDE (dB)
15k10k5k
-120
-100
-80
-60
-40
-20
0
20
-140
0 20k
NI = 0x6000
DHF = 1
FFT, DAC TO HEADPHONE,
-60dBFS, fMCLK = 12.288MHz, fLRCLK = 96kHz
MAX9880A toc44
FREQUENCY (Hz)
AMPLITUDE (dB)
15k10k5k
-120
-100
-80
-60
-40
-20
0
20
-140
0 20k
NI = 0x6000
DHF = 1
FFT, DAC TO HEADPHONE,
0dBFS, fMCLK = 13MHz, fLRCLK = 48kHz
MAX9880A toc45
FREQUENCY (Hz)
AMPLITUDE (dB)
15k10k5k
-120
-100
-80
-60
-40
-20
0
20
-140
020k
PLL MODE
Typical Operating Characteristics (continued)
(VAVDD = VPVDD = VMICVDD = VDVDD = VDVDDS1 = +1.8V, RL= ∞, headphone load (RL) connected between _OUTP and _OUTN,
CREF = 2.2µF, CMICBIAS = CPREG = CREG = 1µF, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB, AVVOL = 0dB,
AVLO = 0dB, fMCLK = 13MHz, differential output, unless otherwise noted.)
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
20 ______________________________________________________________________________________
FFT, DAC TO HEADPHONE,
-60dBFS, fMCLK = 13MHz, fLRCLK = 48kHz
MAX9880A toc46
FREQUENCY (Hz)
AMPLITUDE (dB)
15k10k5k
-120
-100
-80
-60
-40
-20
0
20
-140
0 20k
PLL MODE
FFT, DAC TO HEADPHONE,
0dBFS, fMCLK = 13MHz, fLRCLK = 44.1kHz
MAX9880A toc47
FREQUENCY (Hz)
AMPLITUDE (dB)
15k10k5k
-120
-100
-80
-60
-40
-20
0
20
-140
0 20k
PLL MODE
FFT, DAC TO HEADPHONE,
-60dBFS, fMCLK = 13MHz, fLRCLK = 44.1kHz
MAX9880A toc48
FREQUENCY (Hz)
AMPLITUDE (dB)
15k10k5k
-120
-100
-80
-60
-40
-20
0
20
-140
020k
PLL MODE
FFT, MICROPHONE TO ADC,
0dBFS, fMCLK = 13MHz, fLRCLK = 8kHz
MAX9880A toc49
FREQUENCY (Hz)
AMPLITUDE (dB)
300020001000
-120
-100
-80
-60
-40
-20
0
-140
0 4000
FREQ1 = 0xA
FFT, MICROPHONE TO ADC,
-60dBFS, fMCLK = 13MHz, fLRCLK = 8kHz
MAX9880A toc50
FREQUENCY (Hz)
AMPLITUDE (dB)
300020001000
-120
-100
-80
-60
-40
-20
0
-140
0 4000
FREQ1 = 0xA
FFT, MICROPHONE TO ADC,
0dBFS, fMCLK = 12.288MHz, fLRCLK = 48kHz
MAX9880A toc51
FREQUENCY (Hz)
AMPLITUDE (dB)
15k10k5k
-120
-100
-80
-60
-40
-20
0
20
-140
020k
NI = 0x6000
FFT, MICROPHONE TO ADC,
-60dBFS, fMCLK = 12.288MHz, fLRCLK = 48kHz
MAX9880A toc52
FREQUENCY (Hz)
AMPLITUDE (dB)
15k10k5k
-120
-100
-80
-60
-40
-20
0
20
-140
0 20k
NI = 0x6000
FFT, MICROPHONE TO ADC,
0dBFS, fMCLK = 13MHz, fLRCLK = 48kHz
MAX9880A toc53
FREQUENCY (Hz)
AMPLITUDE (dB)
15k10k5k
-120
-100
-80
-60
-40
-20
0
20
-140
0 20k
PLL MODE
FFT, MICROPHONE TO ADC,
-60dBFS, fMCLK = 13MHz, fLRCLK = 48kHz
MAX9880A toc54
FREQUENCY (Hz)
AMPLITUDE (dB)
15k10k5k
-120
-100
-80
-60
-40
-20
0
-140
0 20k
PLL MODE
Typical Operating Characteristics (continued)
(VAVDD = VPVDD = VMICVDD = VDVDD = VDVDDS1 = +1.8V, RL= ∞, headphone load (RL) connected between _OUTP and _OUTN,
CREF = 2.2µF, CMICBIAS = CPREG = CREG = 1µF, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB, AVVOL = 0dB,
AVLO = 0dB, fMCLK = 13MHz, differential output, unless otherwise noted.)
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
______________________________________________________________________________________
21
WIDEBAND FFT, DAC TO HEADPHONE,
0dBFS, fMCLK = 13MHz, fLRCLK = 8kHz
MAX9880A toc55
FREQUENCY (Hz)
AMPLITUDE (dB)
100k80k20k 40k 60k
-120
-100
-80
-60
-40
-20
0
20
-140
0 120k
FREQ1 = 0xA
WIDEBAND FFT, DAC TO HEADPHONE,
-60dBFS, fMCLK = 13MHz, fLRCLK = 8kHz
MAX9880A toc56
FREQUENCY (Hz)
AMPLITUDE (dB)
100k80k60k40k20k
-120
-100
-80
-60
-40
-20
0
-140
0 120k
FREQ1 = 0xA
DAC IIR HIGHPASS FILTER FREQUENCY
RESPONSE, MODE = 0
MAX9880A toc57
FREQUENCY (Hz)
AMPLITUDE (dB)
500400300200100
-80
-60
-40
-20
0
20
-100
0 600
fLRCLK = 8kHz
DVFLT = 0
DVFLT = 3
DVFLT = 4
ADC IIR HIGHPASS FILTER FREQUENCY
RESPONSE, MODE = 0
MAX9880A toc58
FREQUENCY (Hz)
AMPLITUDE (dB)
500400300200100
-80
-60
-40
-20
0
20
-100
0 600
fLRCLK = 8kHz
AVFLT = 0
AVFLT = 3
AVFLT = 4
DAC IIR/FIR LOWPASS FILTER FREQUENCY
RESPONSE (fLRCLK = 8kHz)
MAX9880A toc59
FREQUENCY (Hz)
AMPLITUDE (dB)
3800360034003200
-80
-60
-40
-20
0
20
-100
3000 4000
MODE = 1
MODE = 0
DAC FIR LOWPASS FILTER FREQUENCY
RESPONSE (fLRCLK = 96kHz)
MAX9880A toc60
FREQUENCY (Hz)
AMPLITUDE (dB)
44k40k36k32k28k24k
-80
-60
-40
-20
0
20
-100
20k 48k
ADC IIR/FIR LOWPASS FILTER FREQUENCY
RESPONSE (fLRCLK = 8kHz)
MAX9880A toc61
FREQUENCY (Hz)
AMPLITUDE (dB)
3800360034003200
-80
-60
-40
-20
0
20
-100
3000 4000
MODE = 1
MODE = 0
SHUTDOWN TO FULL OPERATION
(DIFFERENTIAL)
MAX9880A toc62
TIME (4ms/div)
SCL (1V/div)LOUTP (500mV/div)
SHUTDOWN TO FULL OPERATION
(SE CLICKLESS)
MAX9880A toc63
TIME (40ms/div)
SCL (1V/div)LOUTP (500mV/div)
Typical Operating Characteristics (continued)
(VAVDD = VPVDD = VMICVDD = VDVDD = VDVDDS1 = +1.8V, RL= ∞, headphone load (RL) connected between _OUTP and _OUTN,
CREF = 2.2µF, CMICBIAS = CPREG = CREG = 1µF, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB, AVVOL = 0dB,
AVLO = 0dB, fMCLK = 13MHz, differential output, unless otherwise noted.)
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
22 ______________________________________________________________________________________
SHUTDOWN TO FULL OPERATION
(SE FAST TURN ON)
MAX9880A toc64
TIME (4ms/div)
SCL (1V/div)LOUTP (500mV/div)
FULL OPERATION TO SHUTDOWN
MAX9880A toc65
TIME (400µs/div)
SCL (1V/div)LOUTP (500mV/div)
SOFT-START ADC
MAX9880A toc66
TIME (1ms/div)
SCL (1V/div)ADC OUTPUT (500mV/div)
TOTAL HARMONIC DISTORTION + NOISE
vs. MCLK FREQUENCY, 0dBFS
MAX9880A toc67
MCLK FREQUENCY (MHz)
THD+N (dB)
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-100
10 100
fLRCLK = 48kHz
PLL MODE
DYNAMIC RANGE vs. MCLK FREQUENCY
MAX9880A toc68
MCLK FREQUENCY (MHz)
DYNAMIC RANGE (dB)
70
80
90
100
110
120
60
10 100
VIN = -60dBFS
fLRCLK = 48kHz
PLL MODE
LINE INPUT RESISTANCE
vs. GAIN SETTING
MAX9880A toc69
GAIN SETTING (dB)
INPUT RESISTANCE (kΩ)
20151050-5
50
100
150
200
250
300
0
-10 25
AUX CODE vs. INPUT VOLTAGE
MAX9880A toc70
INPUT VOLTAGE (V)
AUX CODE (SIGNED DECIMAL)
1.00.80.60.40.20-0.2
0
5000
10,000
15,000
20,000
25,000
30,000
-5000
-0.4 1.2
Typical Operating Characteristics (continued)
(VAVDD = VPVDD = VMICVDD = VDVDD = VDVDDS1 = +1.8V, RL= ∞, headphone load (RL) connected between _OUTP and _OUTN,
CREF = 2.2µF, CMICBIAS = CPREG = CREG = 1µF, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB, AVVOL = 0dB,
AVLO = 0dB, fMCLK = 13MHz, differential output, unless otherwise noted.)
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
______________________________________________________________________________________ 23
Pin Configurations
TOP VIEW
(BUMP SIDE DOWN)
1
A
B
C
D
234
WLP
E
F
5678
IRQ
X2X1DGND AGNDPREGAVDDMODE
CSSCL/SCLKSDA/DINDVDD MICBIASMICVDDREFDOUT
N.C.BCLKS2LRCLKS2SDINS2
MICRP/
SPDMDATA
MICLN/
DIGMICCLK
REGN.C.
N.C.SDINS1SDOUTS2MCLK
MICRN/
SPDMCLK
MICLP/
DIGMICDATA
N.C.
JACKSNS/
AUX
LOUTPPVDDBCLKS1LRCLKS1 LINLLOUTLPGNDROUTP
LOUTNPVDDDVDDS1SDOUTS1 LINRLOUTRPGNDROUTN
MAX9880A
+
TOP VIEW
THIN QFN
(6mm × 6mm)
13
14
15
16
17
18
19
20
21
22
23
24
REG
N.C.
AGND
MICVDD
MICBIAS
MICLN/DIGMICCLK
MICLP/DIGMICDATA
MICRP/SPDMDATA
MICRN/SPDMCLK
JACKSNS/AUX
LINL
LINR
48
47
46
45
44
43
42
41
40
39
38
37
12345678910
11 12
N.C.
DGND
DVDD
BCLKS2
LRCLKS2
SDINS2
SDOUTS2
MCLK
BCLKS1
LRCLKS1
SDINS1
SDOUTS1
PREG
N.C.
REF
AVDD
IRQ
MODE
DOUT
CS
X2
X1
SCL/SCLK
SDA/DIN
36 35 34 33 32 31 30 29 28 27 26 25
LOUTR
LOUTL
PGND
N.C.
ROUTP
ROUTN
LOUTN
LOUTP
N.C.
PVDD
N.C.
DVDDS1
+
MAX9880A
*EP
*EP = EXPOSED PAD
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
24 ______________________________________________________________________________________
Pin Description
PIN
TQFN-EP WL P NAME FUNCTION
1 B2 SDA/DIN
I2C Serial-Data Input/Output (MODE = 0). Connect a pullup resistor to DVDD for
full output swing. SPI compatible serial-data input (MODE = 1).
2 B3 SCL/SCLK
I2C Serial-Clock Input (MODE = 0). Connect a pullup resistor to DVDD for full
output swing. SPI-compatible serial clock input (MODE = 1).
3 A2 X1
Crystal Oscillator Input. Connect load capacitor and one terminal of the crystal
to this pin. Acceptable input frequency range: 10MHz to 30MHz.
4 A3 X2
Crystal Oscillator Output. Connect load capacitor and second terminal of the
crystal to this pin.
5 B4 CS SPI-Compatible, Active-Low Chip-Select Input
6 B5 DOUT SPI-Compatible Serial-Data Output
7 A5 MODE I2C/SPI Mode Select Input (MODE = 0 for I2C mode, MODE = 1 for SPI mode)
8 A4 IRQ
Hardware Interrupt Output. IRQ can be programmed to go low when bits in the
status register 0x00 are set. Read status register 0x00 to clear IRQ once set.
Repeat faults have no effect on IRQ until it is cleared by reading the I2C status
register 0x00. Connect a 10k pullup resistor to DVDD for full output swing.
9 A6 AVDD Analog Power Supply. Bypass to AGND with a 1µF capacitor.
10 B6 REF Converter Reference. Bypass to AGND with a 2.2µF capacitor (1.23V nominal).
11, 14,
28, 33,
35, 48
C4, D4,
C5, D6 N.C. No Connection. Connect to GND.
12 A7 PREG
Positive Internal Regulated Supply. Bypass to AGND with a 1µF capacitor (1.6V
nominal).
13 C6 REG
PREG/2 Voltage Reference. Bypass to AGND with a 1µF capacitor (0.8V
nominal)
15 A8 AGND Analog Ground
16 B7 MICVDD Microphone Bias Power Supply. Bypass to AGND with a 1µF capacitor.
17 B8 MICBIAS
Low-Noise Microphone Bias. Connect a 2.2k to 470 resistor to the positive
output of the microphone. Bypass to AGND with a 1µF capacitor.
18 C7 MICLN/
DIGMICCLK
Left Negative Differential Microphone Input. AC-couple a microphone with a series
1µF capacitor. Also digital microphone clock output. Selectable through I2C.
19 D7 MICLP/
DIGMICDATA
Left Positive Differential Microphone Input. AC-couple a microphone with a
series 1µF capacitor. Also digital microphone data input. Selectable through
I2C.
20 C8 MICRP/
SPDMDATA
Right Positive Differential Microphone Input or SPDM Data Output. AC-couple a
microphone with a series 1µF capacitor. Selectable through I2C.
21 D8 MICRN/
SPDMCLK
Right Negative Differential Microphone Input or SPDM Clock Output. AC-couple
a microphone with a series 1µF capacitor. Selectable through I2C.
22 D5 JACKSNS/AUX
Jack Sense. Detects the presence or absence of a jack. See the Headset
Detection section. When used as an auxiliary ADC input, AUX is used to
measure DC voltages.
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
______________________________________________________________________________________ 25
Pin Description (continued)
PIN
TQFN-EP WL P NAME FUNCTION
23 E8 LINL Left-Line Input. AC-couple analog audio signal to LINL with a 1µF capacitor.
24 F8 LINR Right-Line Input. AC-couple analog audio signal to LINR with a 1µF capacitor.
25 F7 LOUTR Right-Line Output
26 E7 LOUTL Left-Line Output
27 E6, F6 PGND Headphone Power Ground
29 E5 ROUTP
Positive Right-Channel Headphone Output. Connect directly to the load in
differential and capacitorless mode. AC-couple to the load in single-ended mode.
30 F5 ROUTN
Negative Right-Channel Headphone Output. Unused in capacitorless and
single-ended mode.
31 F4 LOUTN
Negative Left-Channel Headphone Output. Common headphone return in
capacitorless mode. Unused in single-ended mode.
32 E4 LOUTP
Positive Left-Channel Headphone Output. Connect directly to the load in
differential and capacitorless mode. AC-couple to the load in single-ended mode.
34 E3, F3 PVDD Headphone Power Supply. Bypass to PGND with a 1µF capacitor.
36 F2 DVDDS1
S1 Digital Audio Interface Power-Supply Input. Bypass to DGND with a 1µF
capacitor.
37 F1 SDOUTS1 S1 Digital Audio Serial-Data ADC Output
38 D3 SDINS1 S1 Digital Audio Serial-Data DAC Input
39 E1 LRCLKS1
S1 Digital Audio Left-Right Clock Input/Output. LRCLKS1 is the audio sample
rate clock and determines whether the audio data on SDINS1 is routed to the left
or right channel. In TDM mode, LRCLKS1 is a frame sync pulse. LRCLKS1 is an
input when the MAX9880A is in slave mode and an output when in master
mode.
40 E2 BCLKS1
S1 Digital Audio Bit Clock Input/Output. BCLKS1 is an input when the
MAX9880A is in slave mode and an output when in master mode.
41 D1 MCLK Master Clock Input. Acceptable input frequency range: 10MHz to 60MHz.
42 D2 SDOUTS2 S2 Digital Audio Serial-Data ADC Output
43 C1 SDINS2 S2 Digital Audio Serial-Data DAC Input
44 C2 LRCLKS2
S2 Digital Audio Left-Right Clock Input/Output. LRCLKS2 is the audio sample
rate clock and determines whether the audio data on SDINS2 is routed to the left
or right channel. In TDM mode, LRCLKS2 is a frame sync pulse. LRCLKS2 is an
input when the MAX9880A is in slave mode and an output when in master
mode.
45 C3 BCLKS2
S2 Digital Audio Bit Clock Input/Output. BCLKS2 is an input when the
MAX9880A is in slave mode and an output when in master mode.
46 B1 DVDD
Digital Power Supply. Supply for the digital core and I2C/SPI interface. Bypass to
DGND with a 1.0µF capacitor.
47 A1 DGND Digital Ground
— — EP Exposed Pad. Connect the exposed thermal pad to AGND.
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
26 ______________________________________________________________________________________
Detailed Description
The MAX9880A is a low-power stereo audio codec
designed for portable applications requiring minimum
power consumption.
The stereo playback path accepts digital audio through
flexible digital audio interfaces compatible with I2S,
TDM, and left-justified audio signals. The MAX9880A
can process two simultaneous digital input streams that
can be mixed digitally. The primary interface is intend-
ed for voiceband applications, while the secondary
interface can be used for stereo audio data. An over-
sampling sigma-delta DAC converts the mixed incom-
ing digital data stream to analog audio and outputs
through the stereo headphone amplifier and stereo-line
outputs. The headphone amplifier can be configured in
differential, single-ended, and capacitorless output
modes.
The stereo record path has two differential analog
microphone inputs with selectable gain. The micro-
phones are powered by an integrated microphone bias.
The MAX9880A can retask the left analog microphone
input to accept data from up to two digital micro-
phones. An oversampling sigma-delta ADC converts
the microphone signals and outputs the digital bit
stream over the digital audio interface. An auxiliary
ADC allows accurate measurements of DC voltages by
retasking the right audio ADC. DC voltages can be
read through the registers.
The MAX9880A also includes two line inputs. These
inputs allow a stereo single-ended signal to be gain
adjusted and then recorded by the ADCs and output by
the headphone amplifier and line output amplifiers. A
jack detection function allows the detection of head-
phone, microphone, and headset jacks. Insertion and
removal events can be programmed to trigger a hard-
ware interrupt and flag a register bit.
The MAX9880A’s flexible clock circuitry utilizes a pro-
grammable clock divider and a digital PLL to allow the
DAC and ADC to operate at maximum dynamic range
for all combinations of master clock (MCLK) and sam-
ple rate (LRCLK) without consuming extra supply cur-
rent. Any master clock between 10MHz and 60MHz is
supported as are all sample rates from 8kHz to 48kHz
for the record path and 8kHz to 96kHz for the playback
path. Master and slave modes are supported for maxi-
mum flexibility.
The right analog microphone input can be retasked to
output SPDM data. Integrated digital filtering provides a
range of notch and highpass filters for both the play-
back and record paths to limit undesirable low-frequen-
cy signals and GSM transmission noise. The digital
filtering provides attenuation of out-of-band energy by
over 70dB, eliminating audible aliasing. A digital
sidetone function allows audio from the record path to
be summed into the playback path after digital filtering.
I2C/SPI Registers
Forty internal registers program and report the status of
the MAX9880A. Table 1 lists all of the registers, their
addresses, and power-on-reset states. Registers
0x00–0x03 are read-only while all of the other registers
are read/write. Write zeros to all unused bits in the regis-
ter table when updating the register, unless otherwise
noted. All bits in the read-only registers are not pro-
grammable. Read operations of unused bits return zero.
I2C Slave Address
The MAX9880A is preprogrammed with a slave
address of 0x20 or 0010000. The address is defined as
the 7 most significant bits (MSBs) followed by the
read/write bit. Set the read/write bit to 1 to configure the
MAX9880A to read mode. Set the read/write bit to zero
to configure the MAX9880A to write mode. The address
is the first byte of information sent to the MAX9880A
after the START (S) condition.
REGISTER B7 B6 B5 B4 B3 B2 B1 B0
REGISTER
ADDRESS
(SEE NOTE)
POR
STATE R/W
STATUS
Status CLD SLD ULK — * * JDET — 0x00 — R
Jack Status JKSNS[1:0] — — — — — — 0x01 — R
AUX High AUX[15:8] 0x02 — R
AUX Low AUX[7:0] 0x03 — R
Interrupt Enable ICLD ISLD IULK 00* 0* IJDET 0 0x04 0x00 R/W
SYSTEM CLOCK CONTROL
System Clock 00 PSCLK FREQ1 0x05 0x00 R/W
Table 1. Register Map
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
______________________________________________________________________________________ 27
REGISTER B7 B6 B5 B4 B3 B2 B1 B0
REGISTER
ADDRESS
(SEE NOTE)
POR
STATE R/W
DAI1 CLOCK CONTROL
Stereo Audio Clock Control High PLL1 NI1[14:8] 0x06 0x00 R/W
Stereo Audio Clock Control Low NI1[7:1] RLK1/NI1[0] 0x07 0x00 R/W
DAI1 CONFIGURATION
Interface Mode A MAS1 WCI1 BCI 1 DLY1 HIZOFF1 TDM1 FSW1 0 0x08 0x00 R/W
Interface Mode B DL1 SEL1 SDOEN1 SDIEN1 DMONO1 BSEL1 0x09 0x00 R/W
Time-Division Multiplex SLOTL1 SLOTR1 SLOTDLY1[3:0] 0x0A 0x00 R/W
DAI2 CLOCK CONTROL
Stereo Audio Clock Control High PLL2 NI2[14:8] 0x0B 0x00 R/W
Stereo Audio Clock Control Low NI2[7:1] RLK2/NI2[0] 0x0C 0x00 R/W
DAI2 CONFIGURATION
Interface Mode A MAS2 WCI2 BCI 2 DLY2 HIZOFF2 TDM2 FSW2 WS2 0x 0D 0 x0 0 R/W
Interface Mode B DL2 SEL2 SDOEN2 SDIEN2 DHF BSEL2 0x0E 0x00 R/W
Time-Division Multiplex SLOTL2 SLOTR2 SLOTDLY2[3:0] 0x0F 0x00 R/W
DIGITAL MIXERS
DAC-L/R Mixer MIXDAL MIXDAR 0x10 0x00 R/W
DIGITAL FILTERING
Codec Filters MODE AVFLT DCB DVFLT 0x11 0x00 R/W
SPDM OUTPUTS
Configuration SPDMCLK SPDML SPDMR 0 0 0 0 0x12 0x00 R/W
Input MIXSPDML MIXSPDMR 0x13 0x00 R/W
REVISION ID
Rev ID location (replicated for
SPI mode) REV 0x14 0x42 R/W
LEVEL CONTROL
Sidetone DSTS 0 DVST 0x15 0x00 R/W
Stereo DAC Level 0 SDACM 00 SDACA 0x16 0x00 R/W
Voice DAC Level 0 VDACM VDACG VDACA 0x17 0x00 R/W
Left ADC Level 00 AVLG AVL 0x18 0x00 R/W
Right ADC Level 00 AVRG AVR 0x19 0x00 R/W
Left-Line Input Level 0 LILM 00 LIGL 0x1A 0x00 R/W
Right-Line Input Level 0 LIRM 00 LIGR 0x1B 0x00 R/W
Left Volume Control 0 VOLLM VOLL 0x1C 0x00 R/W
Right Volume Control 0 VOLRM VOLR 0x1D 0x00 R/W
Left-Line Output Level 0 LOLM 00 LOGL 0x1E 0x00 R/W
Right-Line Output Level 0 LORM 00 LOGR 0x1F 0x00 R/W
Left Microphone Gain 0 PALEN PGAML 0x20 0x00 R/W
Right Microphone Gain 0 PAREN PGAMR 0x21 0x00 R/W
CONFIGURATION
Input MX INL MXIN R AUXCAP AUXGAIN AUXCAL AUXEN 0x2 2 0x 00 R/W
Microphone MICCLK DIGMICL DIGMICR 0 0 0 MBIAS 0x23 0x00 R/W
Mode DSLEW VSEN ZDEN 00 HPMODE 0x24 0x00 R/W
Jack Detect JDETEN 0 JDWK 0 0 0 JDEB 0x25 0x00 R/W
Table 1. Register Map (continued)
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
28 ______________________________________________________________________________________
Device Status
Status registers 0x00 and 0x01 are read-only registers
that report the status of various device functions. The
status register bits are cleared upon reading the status
register and are set the next time the event occurs.
Registers 0x02 and 0x03 report the DC level applied to
AUX. See the
ADC
section for more details.
Bits in status register 0x00 are set when an alert condi-
tion exists. All bits in status register 0x00 are automati-
cally cleared upon a read operation of the register and
are set again if the condition remains or occurs follow-
ing the read of this register.
REGISTER B7 B6 B5 B4 B3 B2 B1 B0
REGISTER
ADDRESS
(SEE NOTE)
POR
STATE R/W
POWER MANAGEMENT
Enable LNLEN LNREN LOLEN LOREN DALEN DAREN ADLEN ADREN 0x26 0x00 R/W
System Shutdown SHDN 0 0 0 XTEN XTOSC 00 0x27 0x00 R/W
REVISION ID
Revision ID REV 0xFF 0x42 R/W
Table 1. Register Map (continued)
*
Reserved.
Grayed boxes = Not used.
Note: Register addresses listed are for I2C. To get the SPI address, add 0x200 with the following exception: Register 0xFF is not
accessible through SPI.
REGISTER B7 B6 B5 B4 B3 B2 B1 B0
REGISTER
ADDRESS
(SEE NOTE)
Status CLD SLD ULK — * * JDET — 0x00
Jack Status JKSNS[1:0] — ————— 0x01
AUX High AUX[15:8] 0x02
AUX Low AUX[7:0] 0x03
Table 2. Status Register
*
Reserved.
Grayed boxes = Not used.
Note: Register addresses listed are for I2C. To get the SPI address, add 0x200 with the following exception: Register 0xFF is not
accessible through SPI.
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
______________________________________________________________________________________ 29
BITS FUNCTION
CLD
Clip Detect Flag. Indicates that a signal has become clipped in the ADC or DAC. To resolve a clip condition in
the signal path, the DAC gain settings and analog input gain settings should be lowered. As the CLD bit does
not indicate where the overload has occurred, identify the source by lowering gains individually.
SLD
Slew Level Detect Flag. When volume or gain changes are made, the slewing circuitry smoothly steps through
all intermediate settings. When SLD is set high, all slewing has completed and the volume or gain is at its final
value. SLD is also set when soft start or stop is complete.
ULK Digital PLL Unlock Flag. Indicates that the digital audio PLL has become unlocked and digital signal data is not
reliable.
JDET Headset Configuration Change Flag. JDET reports changes in JKSNS[1:0]. Changes to JKSNS[1:0] are
debounced before setting JDET. The debounce period is programmable using the JDEB bits.
JKSNS reports the status of the JACKSNS pin when JDETEN = 1. JKSNS is not debounced and should be
interpreted according to the following information.
JKSNS[1:0] DESCRIPTION
00 JACKSNS is below VTH2.
01 JACKSNS is between VTH1 and VTH2.
10 Invalid.
JKSNS[1:0]
11 JACKSNS is above VTH1.
AUX
Auxiliary Input Measurement. AUX is a 16-bit signed two’s complement number representing the voltage
measured at JACKSNS/AUX. Before reading a value from AUX, set AUXCAP to 1 to ensure a stable reading. After
reading the value, set AUXCAP to 0.
Use the following formula to convert the AUX value into an equivalent JACKSNS/AUX voltage:
Voltage =0.738V AUX
k
k = AUX value when AUXGAIN = 1. See AUXGAIN for details on determining the value of k, the calibration
constant.
Table 3. Status Register Bits
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
30 ______________________________________________________________________________________
Hardware Interrupts
Hardware interrupts are reported on the open-drain IRQ
pin. When an interrupt occurs, IRQ remains low until the
interrupt is serviced by reading the status register 0x00.
If a flag is set, it is reported as a hardware interrupt only
if the corresponding interrupt enable is set. Each bit
enables interrupts for the status flag in the respective
bit location in register 0x00.
REGISTER B7 B6 B5 B4 B3 B2 B1 B0
REGISTER
ADDRESS
(SEE NOTE)
Interrupt Enable ICLD ISLD IULK 00* 0* IJDET 0 0x04
Table 4. Interrupt Enable
*
Reserved.
Grayed boxes = Not used.
Note: Register addresses listed are for I2C. To get the SPI address, add 0x200 with the following exception: Register 0xFF is not
accessible through SPI.
REGISTER B7 B6 B5 B4 B3 B2 B1 B0
REGISTER
ADDRESS
(SEE NOTE)
SYSTEM CLOCK CONTROL
System Clock 00 PSCLK FREQ1 0x05
DAI1 CLOCK CONTROL
Stereo Audio Clock Control High PLL1 NI1[14:8] 0x06
Stereo Audio Clock Control Low NI1[7:1] RLK1/NI1[0] 0x07
DAI2 CLOCK CONTROL
Stereo Audio Clock Control High PLL2 NI2[14:8] 0x0B
Stereo Audio Clock Control Low NI2[7:1] RLK2/NI2[0] 0x0C
Table 5. System and Audio Clock Registers
Grayed boxes = Not used.
Note: Register addresses listed are for I2C. To get the SPI address, add 0x200 with the following exception: Register 0xFF is not
accessible through SPI.
Clock Control
The MAX9880A can work with a master clock (MCLK)
supplied from any system clock within the 10MHz to
60MHz range. Internally the MAX9880A requires a
10MHz to 20MHz clock. A prescaler divides MCLK by
1, 2, or 4 to create the internal clock (PCLK). PCLK is
used to clock all portions of the MAX9880A.
The MAX9880A can support any sample rate from 8kHz
to 48kHz for the digital audio path DAI1 (DAC and
ADC) and 8kHz to 96kHz for the DAI2 (high-fidelity
DAC path), including all common sample rates (8kHz,
16kHz, 24kHz, 32kHz, 44.1kHz, 48kHz, 96kHz). To
accommodate a wide range of system architectures,
the MAX9880A supports three main clocking modes:
•Normal mode: This mode uses a 15-bit clock
divider coefficient to set the sample rate relative to
the prescaled MCLK input (PCLK). This allows high
flexibility in both the MCLK and LRCLK frequencies
and can be used in either master or slave mode.
•Exact integer mode: Common MCLK frequencies
(12MHz, 13MHz, 16MHz, and 19.2MHz) can be pro-
grammed to operate in exact integer mode for both
8kHz and 16kHz sample rates. In these modes, the
MCLK and LRCLK rates are selected by using the
FREQ1 bits instead of the NI high, NI low, and PLL con-
trol bits.
•PLL mode: When operating in slave mode, a PLL
can be enabled to lock onto externally generated
LRCLK signals that are not integer related to PCLK.
Prior to enabling the interface, program NI to the
nearest desired ratio and set the NI[0] = 1 to enable
the PLL’s rapid lock mode. If NI[0] = 0, then NI is
ignored and PLL lock time is slower.
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
______________________________________________________________________________________ 31
BITS FUNCTION
PSCLK
MCLK Prescaler. Divides MCLK down to generate a PCLK between 10MHz and 20MHz.
00 = Disable clock for low-power shutdown.
01 = Select if MCLK is between 10MHz and 20MHz. PCLK = MCLK.
10 = Select if MCLK is between 20MHz and 40MHz. PCLK = MCLK/2.
11 = Select if MCLK is greater than 40MHz. PCLK = MCLK/4.
Exact Integer Modes. Allows integer sampling for specific PCLK (prescaled MCLK) frequencies and 8kHz or
16kHz sample rates.
FREQ1[3:0] PCLK (MHz) LRCLK (kHz) PCLK/LRCLK
0x00 Normal or PLL mode
0x1–0x7 Reserved Reserved Reserved
0x8
0x9
12
12
8
16
1500
750
0xA
0xB
13
13
8
16
1625
812.5
0xC
0xD
16
16
8
16
2000
1000
0xE
0xF
19.2
19.2
8
16
2400
1200
FREQ1
Modes 0x8 to 0xF are available in either master or slave mode. In slave mode, if the indicated PCLK/LRCLK
ratio cannot be guaranteed, use PLL mode instead.
PLL1/PLL2
PLL Mode Enable
0 = (Valid for slave and master mode) The frequency of LRCLK is set by the NI divider bits. In master mode,
the MAX9880A generates LRCLK using the specified divide ratio. In slave mode, the MAX9880A expects
an LRCLK as specified by the divide ratio.
1 = (Valid for slave mode only) A digital PLL locks on to any externally supplied LRCLK signal.
RLK1/RLK2 Rapid Lock Mode. To enable rapid lock mode set NI_ to the nearest desired ratio and set RLK_ = 1 before
enabling the interface.
NI1/NI2
Normal Mode LRCLK Divider. When PLL = 0, the frequency of LRCLK is determined by NI. See Table 6 for
common NI values.
For LRCLK = 8kHz to 48kHz operation (DHF = 0 for DAI2):
NI = (65,536 x 96 x fLRCLK)/fPCLK
fLRCLK = LRCLK frequency
fPCLK = Prescaled internal MCLK frequency (PCLK)
For LRCLK > 50kHz operation (DHF = 1 for DAI2):
NI = (65,536 x 48 x fLRCLK)/fPCLK
fLRCLK = LRCLK frequency
fPCLK = Prescaled internal MCLK frequency (PCLK)
Table 5. System and Audio Clock Registers (continued)
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
32 ______________________________________________________________________________________
Digital Audio Interface
The MAX9880A’s dual digital audio interface supports a
wide range of operating modes to ensure maximum
compatibility. See Figures 1 to 5 for timing diagrams. In
master mode, the MAX9880A outputs LRCLK and
BCLK, while in slave mode they are inputs. When oper-
ating in master mode, BCLK can be configured in a
number of ways to ensure compatiblity with other audio
devices.
The MAX9880A has two sets of digital audio interface
pins, S1 and S2, that can be connected to one of two
digital audio paths, DAI1 or DAI2.
DAI1: Digital Audio Path 1 Operation
• DAC path with DR of 90dB and ADC path with DR of
82dB
• DAC path connectable to either S1 or S2
• ADC path connectable to either S1 or S2
• 8kHz to 48kHz sample rates
•I
2S and TDM-compatible modes
• Voice filters or audio filter modes
DAI2: Digital Audio Path 2 Operation
• High-fidelity DAC path with DR of 96dB
• DAC path connectable to either S1 or S2
• 8kHz to 96kHz sample rates
•I
2S and TDM-compatible modes
• Audio FIR filters
• No ADC clock control from DAI2 sample clock and
no voice filter modes available in DAI2
(DAI1, DAI2 for DHF = 0) (DAI2 for DHF = 1)
LRCLK (kHz)
8 11.025 12 16 22.05 24 32 44.1 48 64 88.2 96
10 13A9 1B18 1D7E 2752 3631 3AFB 4EA5 6C61 75F7 4EA5 6C61 75F7
11 11E0 18A2 1ACF 23BF 3144 359F 477E 6287 6B3E 477E 6287 6B3E
11.2896 116A 1800 1A1F 22D4 3000 343F 45A9 6000 687D 45A9 6000 687D
12 1062 1694 1893 20C5 2D29 3127 4189 5A51 624E 4189 5A51 624E
12.288 1000 160D 1800 2000 2C1A 3000 4000 5833 6000 4000 5833 6000
13 F20 14D8 16AF 1E3F 29AF 2D5F 3C7F 535F 5ABE 3C7F 535F 5ABE
14 E0B 135B 1511 1C16 26B5 2A21 382C 4D6A 5443 382C 4D6A 5443
15 D1B 1210 13A9 1A37 2420 2752 346E 4841 4EA5 346E 4841 4EA5
16 C4A 10EF 126F 1893 21DE 24DD 3127 43BD 49BA 3127 43BD 49BA
16.9344 B9C 1000 116A 1738 2000 22D4 2E71 4000 45A9 2E71 4000 45A9
17 B91 FF0 1159 1721 1FE0 22B2 2E43 3FC1 4564 2E43 3FC1 4564
18 AEC F0E 1062 15D8 1E1B 20C5 2BB1 3C36 4189 2BB1 3C36 4189
18.432 AAB EB3 1000 1555 1D66 2000 2AAB 3ACD 4000 2AAB 3ACD 4000
19 A59 E43 F86 14B2 1C85 1F0B 2964 390B 3E16 2964 390B 3E16
PCLK
(MHz):
(Note: Any
PCLK from
10MHz to
20MHz
with any
LRCLK
7.8kHz to
50kHz
can be
used.)
20 9D5 D8C EBF 13A9 1B18 1D7E 2752 3631 3AFB 2752 3631 3AFB
Table 6. Common NI Values
Note: Values in bold and underline are exact integers that provide maximum full-scale performance.
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
______________________________________________________________________________________ 33
REGISTER B7 B6 B5 B4 B3 B2 B1 B0
REGISTER
ADDRESS
(SEE NOTE)
DAI1 CONFIGURATION
Interface Mode A MAS1 WCI1 BCI1 DLY1 HIZOFF1 TDM1 FSW1 0 0x08
Interface Mode B DL1 SEL1 SDOEN1 SDIEN1 DMONO1 BSEL1 0x09
Time-Division Multiplex SLOTL1 SLOTR1 SLOTDLY1[3:0] 0x0A
DAI2 CONFIGURATION
Interface Mode A MAS2 WCI2 BCI2 DLY2 HIZOFF2 TDM2 FSW2 WS2 0x0D
Interface Mode B DL2 SEL2 SDOEN2 SDIEN2 DHF BSEL2 0x0E
Time-Division Multiplex SLOTL2 SLOTR2 SLOTDLY2[3:0] 0x0F
BITS FUNCTION
MAS1/2
Master Mode
0 = The MAX9880A operates in slave mode with LRCLK and BCLK configured as inputs.
1 = The MAX9880A operates in master mode with LRCLK and BCLK configured as outputs.
WCI1/2
LRCLK Invert (TDM1/2 = 0)
0 = Left-channel data is input and output while LRCLK is low.
1 = Right-channel data is input and output while LRCLK is low.
BCI1/2
BCLK Invert
In master and slave modes:
0 = SDIN is latched into the part on the rising edge of BCLK. SDOUT transitions immediately after the rising edge
of BCLK.
1 = SDIN is latched into the part on the falling edge of BCLK. SDOUT transitions immediately after the falling
edge of BCLK.
In master mode:
0 = LRCLK changes state immediately after the rising edge of BCLK.
1 = LRCLK changes state immediately after the falling edge of BCLK.
DLY1/2
Delay Mode. DLY1/2 have two different functions in TDM and non-TDM mode.
In Non-TDM Mode (TDM1/TDM2 = 0): The functionality is as follows:
1 = The most significant bit of an audio word is latched at the second BCLK edge after the LRCLK transition.
0 = The most significant bit of an audio word is latched at the first BCLK edge after the LRCLK transition.
In TDM Mode (TDM1/TDM2 = 1): The functionality is as follows:
1 = The HOLD time on the SDOUT output is increased to be greater than 150ns.
0 = The HOLD time on the SDOUT output is the default (greater than 20ns but less than 150ns).
HIZOFF1/2
SDOUT High-Impedance Mode
0 = SDOUT goes to a high-impedance state after all data bits have been transferred out of the MAX9880A,
allowing SDOUT to be shared by other devices.
1 = SDOUT is set either high or low after all data bits have been transferred out of the MAX9880A.
Note: High-impedance mode is intended for use when TDM = 1.
Table 7. Digital Audio Interface Registers
Grayed boxes = Not used.
Note: Register addresses listed are for I2C. To get the SPI address, add 0x200 with the following exception: Register 0xFF is not
accessible through SPI.
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
34 ______________________________________________________________________________________
BITS FUNCTION
TDM1/2
TDM Mode Select
1 = Enables time-division multiplex mode and configures the audio interface to accept PCM data.
0 = Disables time-division multiplex mode. LRCLK signal polarity indicates left and right audio.
FSW1/2
Frame Sync Width
1 = Frame sync pulse extended to the width of the entire 16-bit first slot 0 data word (TDM1/TDM2 = 1 only;
SLOTDLY[0] must be 0 when FSW is set to 1).
0 = Frame sync pulse is 1 bit wide.
WS2
Word Size
0 = The number of bits per input data word sample is 16 bits, and at least 16 BCLKs per input word are required.
1 = The number of bits per input data word sample is 18 bits, and at least 18 BCLKs per input word transfer is
required. These control bits are only recognized when TDM1/TDM2 are cleared to 0.
Data Loop. Enabling of these bits provides a bridge from one DAI interface to the other. Data format looping could
occur in both directions simultaneously.
BIT DESCRIPTION
DL1 = 0 Normal operation
DL1 = 1, SEL2 = 1 Enables SDINS1 to SDOUTS2.
DL2 = 0 Normal operation
DL2 = 1, SEL1 = 0 Enables SDINS2 to SDOUTS1.
DL1/2
Note: The LRCLKS1 and LRCLKS2 interfaces must be identical.
Set the SEL1/2, SDOEN1/2, and SDIEN1/2 bits as shown in the table below to connect the S1 and S2 pins to the
DAI1 and DAI2 paths in the MAX9880A.
SETTING SEL1 SEL2 SDIEN1 SDOEN1 SDIEN2 SDOEN2
Connect S1 pins to DAI1 (DAC and ADC) 0 X 1 1 0 0
Connect S2 pins to DAI1 (DAC and ADC) 1 0 1 0 0 1
Connect S1 pins (DAC only) to DAI2 1 0 0 0 1 0
Connect S2 pins (DAC only) to DAI2 X 1 0 0 1 0
Connect S1 pins (DAC and ADC) to DAI1,
connect S2 to DAI2 (DAC only) 0 1 1 1 1 0
SEL1/SEL2
Connect S2 pins (DAC and ADC) to DAI1,
connect S1 to DAI2 (DAC only) 1 0 1 0 1 1
SDOEN1/2
SDOUT Enable
1 = Serial-data output enabled on S1/S2 pins.
0 = Serial-data output disabled on S1/S2 pins.
SDIEN1/2
SDIN Enable
1 = Serial-data input to DAI1/2 audio path enabled.
0 = Serial-data input to DAI1/2 audio path disabled.
DMONO1
Mono Playback Mode
0 = Stereo data input on DAI1 path is processed separately.
1 = Stereo data input on DAI1 path is mixed to a single channel and routed to both the left and right DAC.
When operating in mono voice mode (MODE = 1), stereo data may still be input through DAI1 path and optionally
mixed using DMONO1 = 1.
Table 7. Digital Audio Interface Registers (continued)
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
______________________________________________________________________________________ 35
BITS FUNCTION
BCLK Select. Configures BCLK when operating in master mode. BSEL has no effect in slave mode. Set BSEL =
010, unless sharing the bus with multiple devices.
BSEL DESCRIPTION
000 Off (BCLK output held low)
001 64x LRCLK (192x internal clock divided by 3)
010 48x LRCLK (192x internal clock divided by 4)
011 128x LRCLK (Note: Not a valid BSEL2 choice when DHF = 1.)
100 PCLK/2
101 PCLK/4
110 PCLK/8
BSEL1/2
111 PCLK/16
TDM Slot Select. Selects the time slot to use for left/right data according to the following information when
operating in time-division multiplex mode.
SLOT DESCRIPTION
00 Time slot 1
01 Time slot 2
10 Time slot 3
SLOTL1/2
SLOTR1/2
11 Time slot 4
Slot Data Delay (SLOTDLY1/SLOTDLY2)
In TDM Mode: Configures the data delay for each slot in TDM mode of operation according to the following
information.
In Non-TDM Mode (TDM = 0): SLOTDLY[1:0] does not have any effect.
SLOTDLY1/2[3:0] DESCRIPTION
0xxx Data for slot 4 begins immediately.
1xxx Data for slot 4 delayed 1 BCLK cycle.
x0xx Data for slot 3 begins immediately.
x1xx Data for slot 3 delayed 1 BCLK cycle.
xx0x Data for slot 2 begins immediately.
xx1x Data for slot 2 delayed 1 BCLK cycle.
xxx0 Data for slot 1 begins immediately.
SLOTDLY1/2
xxx1 Data for slot 1 delayed 1 BCLK cycle (not valid when FSW = 1).
DHF
DAC High Sample Rate Mode (DHF) (Valid only for DAI2 audio path)
1 = LRCLK is greater than 50kHz. 4x FIR interpolation filter used.
0 = LRCLK is less than 50kHz. 8x FIR interpolation filter used.
Table 7. Digital Audio Interface Registers (continued)
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
36 ______________________________________________________________________________________
D15 D14
RELATIVE TO PCLK (SEE NOTE)
7ns (typ)
LEFT
1/fS
RIGHT
D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D14D15 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0D14D15 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LRCLK
AUDIO MASTER MODES:
LEFT JUSTIFIED: TDM = 0, WCI = 0, BCI = 0, DLY = 0, SLOTDLY = 0
SDOUT
BCLK
20ns (min) 5ns (min) CONFIGURED BY BSEL
SDIN
LEFT JUSTIFIED + LRCLK INVERT: TDM = 0, WCI = 1, BCI = 0, DLY = 0, SLOTDLY = 0
40ns (max)
0ns (min)
D15 D14
RELATIVE TO PCLK (SEE NOTE)
LEFT
1/fS
RIGHT
D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D14D15 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D14D15 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LRCLK
SDOUT
BCLK
20ns (min) 5ns (min) CONFIGURED BY BSEL
SDIN
40ns (max)
0ns (min)
D15 D14
RELATIVE TO PCLK (SEE NOTE)
LEFT
1/fS
RIGHT
D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D14D15 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D14D15 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LRCLK
SDOUT
BCLK
20ns (min) 5ns (min) CONFIGURED BY BSEL
SDIN
SDIN
D14D15 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LEFT JUSTIFIED + BCLK INVERT: TDM = 0, WCI = 1, BCI = 0, DLY = 0, SLOTDLY = 0
40ns (max)
0ns (min)
RELATIVE TO PCLK (SEE NOTE)
LEFT
1/fS
RIGHT
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LRCLK
BCLK
20ns (min) 5ns (min) CONFIGURED BY BSEL
SDIN
I2S: TDM = 0, WCI = 1, BCI = 0, DLY = 0, SLOTDLY = 0
40ns (max)
0ns (min)
D14D15 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SDIN
D14D15 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
RELATIVE TO PCLK (SEE NOTE)
LEFT
1/fS
RIGHT
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LRCLK
BCLK
20ns (min) 5ns (min) CONFIGURED BY BSEL
SDIN
LEFT JUSTIFIED: TDM = 0, WCI = 1, BCI = 0, DLY = 0, SLOTDLY = 1
40ns (max)
0ns (min)
7ns (typ) 7ns (typ)
7ns (typ) 7ns (typ)
7ns (typ) 7ns (typ)
7ns (typ)
7ns (typ)7ns (typ)
7ns (typ)7ns (typ)
7ns (typ)7ns (typ)
7ns (typ)7ns (typ)
7ns (typ) 7ns (typ)
7ns (typ)7ns (typ)
NOTE:
THE DELAY FROM A BCLK EDGE AND AN LRCLK EDGE IS DETERMINED BY LENGTH OF TIME THAT PCLK (THE INTERNALLY DIVIDED-DOWN VERSION OF MCLK AS DEFINED BY THE PSCLK BITS) PERIOD OF MCLK PLUS THE
INTERNAL DELAY. FOR EXAMPLE: IF fPCLK = 12.288MHz, THEN THE DELAY BETWEEN BCLK AND LRCLK IS TYPICALLY 45ns.
Figure 1. Digital Audio Interface Audio Master Mode
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
______________________________________________________________________________________ 37
D15 D14
20ns (min)
LEFT
1/fS
RIGHT
D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D14D15 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0D14D15 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LRCLK
AUDIO SLAVE MODES:
LEFT JUSTIFIED: TDM = 0, WCI = 0, BCI = 0, DLY = 0, SLOTDLY = 0
SDOUT
BCLK
20ns (min) 5ns (min) 75ns (min) 30ns (min)
SDIN
0ns (min)
LEFT JUSTIFIED + LRCLK INVERT: TDM = 0, WCI = 1, BCI = 0, DLY = 0, SLOTDLY = 0
40ns (max)
0ns (min) 30ns (min)
D15 D14
20ns (min)
LEFT
1/fS
RIGHT
D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D14D15 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D14D15 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LRCLK
SDOUT
BCLK
20ns (min) 5ns (min) 75ns (min) 30ns (min)
SDIN
0ns (min)
40ns (max)
0ns (min) 30ns (min)
D15
D15
D14
20ns (min)
LEFT
1/fS
RIGHT
D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D14D15 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D14D15 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LRCLK
SDOUT
BCLK
20ns (min) 5ns (min) 75ns (min) 30ns (min)
SDIN
0ns (min)
D13D14D15 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SDIN
D13D14D15 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LEFT JUSTIFIED + LRCLK INVERT: TDM = 0, WCI = 1, BCI = 0, DLY = 0, SLOTDLY = 0
40ns (max)
0ns (min) 30ns (min)
20ns (min)
LEFT
1/fS
RIGHT
D14D15 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LRCLK
BCLK
20ns (min) 5ns (min) 75ns (min) 30ns (min)
SDIN
0ns (min)
I2S: TDM = 0, WCI = 0, BCI = 0, DLY = 1, SLOTDLY = 0
40ns (max)
0ns (min) 30ns (min)
D14D15 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SDIN
D14D15 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
20ns (min)
LEFT
1/fS
RIGHT
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LRCLK
BCLK
20ns (min) 5ns (min) 75ns (min) 30ns (min)
SDIN
0ns (min)
LEFT JUSTIFIED: TDM = 0, WCI = 1, BCI = 0, DLY = 0, SLOTDLY = 1
40ns (max)
0ns (min) 30ns (min)
Figure 2. Digital Audio Interface Audio Slave Mode
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
38 ______________________________________________________________________________________
R14R15 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0
SDOUT
200ns
1/fS
LRCLK
BCLK
20ns (min) 0ns (min) CONFIGURED BY BSEL
SDIN
TDM = 1, BCI = 1, HIZOFF = 0, SLOTDLY = 0, SLOT = 00
40ns (max)
0ns (min)
7ns (typ)
7ns (typ) 7ns (typ)
VOICE (TDM/PCM) MASTER MODES:
TDM = 1, BCI = 0, HIZOFF = 0, SLOTDLY = 0, SLOT = 00, DLY = 0
7ns (typ)
R14R15 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0
SDIN
R14R15 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0
SDOUT
200ns
1/fS
LRCLK
BCLK
20ns (min) 0ns (min) CONFIGURED BY BSEL
SDIN
40ns (max)
0ns (min)
7ns (typ)
7ns (typ) 7ns (typ)
7ns (typ)
R14R15 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0
R14R15 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0
SDOUT
200ns
1/fS
LRCLK
BCLK
20ns (min) 0ns (min) CONFIGURED BY BSEL
SDIN
TDM = 1, BCI = 0, HIZOFF = 1, SLOTDLY = 0, SLOT = 00, DLY = 0
40ns (max)
0ns (min)
7ns (typ)
7ns (typ) 7ns (typ)
7ns (typ)
R14R15 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0
Figure 3. Digital Audio Interface Voice Master Mode
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
______________________________________________________________________________________ 39
R14R15 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0
SDOUT
20ns 0ns (min) 0ns (min)
1/fS
LRCLK
BCLK
20ns (min) 0ns (min) 75ns (min)
SDIN
TDM = 1, BCI = 1, HIZOFF = 0, SLOTDLY = 0, SLOT = 00, DLY = 0
40ns (max)
0ns (min)
30ns (min)
30ns (min) 7ns (typ)
VOICE (TDM/PCM) SLAVE MODES:
TDM = 1, BCI = 0, HIZOFF = 0, SLOTDLY = 0, SLOT = 00, DLY = 0
R14R15 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0
SDIN
R14R15 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0
SDOUT
20ns 0ns (min) 0ns (min)
1/fS
LRCLK
BCLK
20ns (min) 0ns (min) 75ns (min)
SDIN
TDM = 1, BCI = 0, HIZOFF = 1, SLOTDLY = 0, SLOT = 00, DLY = 0
40ns (max)
0ns (min)
30ns (min)
30ns (min) 7ns (typ)
R14R15 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0
SDIN
R14R15 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0
SDOUT
20ns 0ns (min) 0ns (min)
1/fS
LRCLK
BCLK
20ns (min) 0ns (min) 75ns (min)
SDIN
40ns (max)
0ns (min)
30ns (min)
30ns (min)
R14R15 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0
SDIN
Figure 4. Digital Audio Interface Voice Slave Mode
REGISTER B7 B6 B5 B4 B3 B2 B1 B0
REGISTER
ADDRESS
(SEE NOTE)
DIGITAL MIXERS
DAC-L/R Mixer MIXDAL MIXDAR 0x10
Table 8. Digital Mixers
Note: Register addresses listed are for I2C. To get the SPI address, add 0x200 with the following exception: Register 0xFF is not
accessible through SPI.
BITS FUNCTION
Digital Mixers (MIXDAL/MIXDAR). Selects and mixes the audio source(s) for the DACs according to the
information below.
MIXDAL/MIXDAR SOURCE
1xxx DAI1 left-channel data
x1xx DAI1 right-channel data
xx1x DAI2 left-channel data
MIXDAL/
MIXDAR
xxx1 DAI2 right-channel data
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
40 ______________________________________________________________________________________
CODE FILTER TYPE VALID SAMPLE
RATE (kHz) HIGHPASS CORNER FREQUENCY 217Hz NOTCH
0x0 Disabled
0x1 Elliptical 16 256Hz Yes
0x2 Butterworth 16 500Hz No
0x3 Elliptical 8 256Hz Yes
0x4 Butterworth 8 500Hz No
0x5 Butterworth 8 to 24 fS/240 No
0x6 to 0x7 Reserved
Table 10. IIR Highpass Digital Filters
Digital Filtering
The MAX9880A incorporates both IIR (voice) and FIR
(audio) digital filters to accomodate a wide range of
audio sources. The IIR fiilters provide over 70dB of
stopband attenuation as well as selectable highpass fil-
ters. The FIR filters provide low power consumption and
are linear phase to maintain stereo imaging.
REGISTER B7 B6 B5 B4 B3 B2 B1 B0
REGISTER
ADDRESS
(SEE NOTE)
DIGITAL FILTERING
Codec Filters MODE AVFLT DCB DVFLT 0x11
BITS FUNCTION
MODE
Digital Audio Filter Mode. Selects the filtering mode for the DAI1 DAC and ADC signal paths.
0 = IIR voice filters
1 = FIR audio filters
AVFLT
ADC Digital Audio Filter. Configures the highpass filters for the DAI1 signal path.
MODE = 0
Select the desired digital filter response from Table 10. See the frequency response graphs in the Typical
Operating Characteristics section for details on each filter.
MODE = 1
0x0 = DC-blocking filter disabled.
0x1 = DC-blocking filter enabled.
DCB 1 = DC-blocking filter for DAI2 enabled.
0 = DC-blocking filter for DAI2 disabled.
DVFLT
DAC Digital Audio Filter. Configures the highpass filters for the DAI1 signal path.
MODE = 0
Select the desired digital filter response from Table 10. See the frequency response graphs in the Typical
Operating Characteristics section for details on each filter.
MODE = 1
0x0 = DC-blocking filter disabled.
0x1 = DC-blocking filter enabled.
Table 9. Digital Filtering Register
Note: Register addresses listed are for I2C. To get the SPI address, add 0x200 with the following exception: Register 0xFF is not
accessible through SPI.
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
______________________________________________________________________________________ 41
REGISTER B7 B6 B5 B4 B3 B2 B1 B0
REGISTER
ADDRESS
(SEE NOTE)
Configuration SPDMCLK SPDML SPDMR 0000 0x12
Input MIXSPDML MIXSPDMR 0x13
BITS FUNCTION
SPDMCLK
SPDM Clock Rate (SPDMCLK)
00 = SPDMCLK is set to PCLK/8.
01 = SPDMCLK is set to PCLK6.
10 = SPDMCLK is set to PCLK/4.
11 = Reserved
SPDML/SPDMR 0 = Disables SPDM data.
1 = Enables SPDM data.
SPDM Input Mixers. Selects and mixes the audio source(s) for the SPDM output according to following
information.
MIXSPDML/MIXSPDMR SOURCE
1xxx DAI1 left-channel data
x1xx DAI1 right-channel data
xx1x DAI2 left-channel data
MIXSPDML/
MIXSPDMR
xxx1 DAI2 right-channel data
Table 11. SPDM Output Registers
Grayed boxes = Not used.
Note: Register addresses listed are for I2C. To get the SPI address, add 0x200 with the following exception: Register 0xFF is not
accessible through SPI.
The MAX9880A supports stereo PDM outputs. The PDM
signals consist of PDM data outputs (SPDMDATA) and a
clock output (SPDMCLK). The mixer at the input to the
PDM modulators allows a mix/mux of the audio digital data
stream from the digital audio ports SDINS1 and SDINS2.
Figure 5 shows the SPDM interface timing diagram.
SPDMCLK
SPDMDATA LEFT CH RIGHT CH LEFT CH RIGHT CH
tDLY, DSD
tDLY, DSD
Figure 5. SPDM Timing Diagram
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
42 ______________________________________________________________________________________
Digital Gain Control
The MAX9880A includes gain adjustment for the play-
back and record paths. Independent gain adjustment is
provided for the two record channels. Sidetone gain
adjustment is also provided to set the sidetone level rel-
ative to the playback level.
REGISTER B7 B6 B5 B4 B3 B2 B1 B0
REGISTER
ADDRESS
(SEE NOTE)
LEVEL CONTROL
Sidetone DSTS 0 DVST 0x15
Stereo DAC Level 0 SDACM 00 SDACA 0x16
Voice DAC Level 0 VDACM VDACG VDACA 0x17
Left ADC Level 00 AVLG AVL 0x18
Right ADC Level 00 AVRG AVR 0x19
BITS FUNCTION
DSTS
Digital Sidetone Source Mixer
00 = No sidetone selected.
01 = Left ADC
10 = Right ADC
11 = Left and right ADC
Digital Sidetone Level Control. All gain settings are relative to the ADC input voltage.
Differential Headphone Output Mode
SETTING GAIN (dB) SETTING GAIN (dB) SETTING GAIN (dB)
0x00 Off 0x0B -20 0x16 -42
0x01 0 0x0C -22 0x17 -44
0x02 -2 0x0D -24 0x18 -46
0x03 -4 0x0E -26 0x19 -48
0x04 -6 0x0F -28 0x1A -50
0x05 -8 0x10 -30 0x1B -52
0x06 -10 0x11 -32 0x1C -54
0x07 -12 0x12 -34 0x1D -56
0x08 -14 0x13 -36 0x1E -58
0x09 -16 0x14 -38 0x1F -60
0x0A -18 0x15 -40 — —
Capacitorless and Single-Ended Headphone Output Mode
SETTING GAIN (dB) SETTING GAIN (dB) SETTING GAIN (dB)
0x00 Off 0x0B -25 0x16 -47
0x01 -5 0x0C -27 0x17 -49
0x02 -7 0x0D -29 0x18 -51
0x03 -9 0x0E -31 0x19 -53
0x04 -11 0x0F -33 0x1A -55
0x05 -13 0x10 -35 0x1B -57
0x06 -15 0x11 -37 0x1C -59
0x07 -17 0x12 -39 0x1D -61
0x08 -19 0x13 -41 0x1E -63
0x09 -21 0x14 -43 0x1F -65
DVST
0x0A -23 0x15 -45 — —
Table 12. Digital Gain Registers
Grayed boxes = Not used.
Note: Register addresses listed are for I2C. To get the SPI address, add 0x200 with the following exception: Register 0xFF is not
accessible through SPI.
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
______________________________________________________________________________________ 43
BITS FUNCTION
SDACM/
VDACM
DAC Mute Enable
0 = No mute
1 = Mute
VDACG
DAC Gain
00 = 0dB
01 = +6dB
10 = +12dB
11 = +18dB
Note: VDACG is only used when MODE = 0. If MODE = 1, then the DAC gain is always 0dB.
DAC Level Control. VDACA/SDACA works in all modes.
SETTING GAIN (dB) SETTING GAIN (dB)
0x0 0 0x8 -8
0x1 -1 0x9 -9
0x2 -2 0xA -10
0x3 -3 0xB -11
0x4 -4 0xC -12
0x5 -5 0xD -13
0x6 -6 0xE -14
VDACA/SDACA
0x7 -7 0xF -15
ADC Gain Control. Applies the specified gain to the digital ADC paths according to the following
information.
SETTING GAIN (dB)
0x0 0
0x1 +6
0x2 +12
AVLG/AVRG
0x3 +18
ADC Left/Right Level Control
SETTING GAIN (dB) SETTING GAIN (dB)
0x0 +3 0x8 -5
0x1 +2 0x9 -6
0x2 +1 0xA -7
0x3 0 0xB -8
0x4 -1 0xC -9
0x5 -2 0xD -10
0x6 -3 0xE -11
AVL/AVR
0x7 -4 0xF -12
Table 12. Digital Gain Registers (continued)
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
44 ______________________________________________________________________________________
Line Inputs
The MAX9880A include one pair of single-ended line
inputs. When enabled the line inputs connect directly to
the headphone amplifier and line outputs and can be
optionally connected to the ADC for recording.
Playback Volume
The MAX9880A incorporates volume and mute control to
allow level control for the playback audio path. Program
registers 0x1C and 0x1D to set the desired volume.
Line Output Level
The MAX9880A incorporates gain and mute control to
allow level control for the line outputs.
REGISTER B7 B6 B5 B4 B3 B2 B1 B0
REGISTER
ADDRESS
(SEE NOTE)
Left-Line Input Level 0 LILM 00 LIGL 0x1A
Right-Line Input Level 0 LIRM 00 LIGR 0x1B
BITS FUNCTION
LILM/LIRM
Line Input Left/Right Playback Mute
0 = Line input is connected to the headphone amplifiers.
1 = Line input is disconnected from the headphone amplifiers.
Line Input Left/Right Gain
SETTING GAIN (dB) SETTING GAIN (dB)
0x0 +24 0x8 +8
0x1 +22 0x9 +6
0x2 +20 0xA +4
0x3 +18 0xB +2
0x4 +16 0xC 0
0x5 +14 0xD -2
0x6 +12 0xE -4
LIGL/LIGR
0x7 +10 0xF -6
Table 13. Line Input Registers
REGISTER B7 B6 B5 B4 B3 B2 B1 B0
REGISTER
ADDRESS
(SEE NOTE)
Left Volume Control 0 VOLLM VOLL 0x1C
Right Volume Control 0 VOLRM VOLR 0x1D
BITS FUNCTION
VOLLM/
VOLRM
Left/Right Playback Mute. VOLLM and VOLRM mute both the DAC and line input audio signals.
0 = Audio playback is unmuted.
1 = Audio playback is muted.
Note: VSEN has no effect on the mute function. When VOLLM or VOLRM is set, the output is muted
immediately (ZDEN = 1) or at the next zero-crossing (ZDEN = 0).
Table 14. Playback Volume Registers
Grayed boxes = Not used.
Note: Register addresses listed are for I2C. To get the SPI address, add 0x200 with the following exception: Register 0xFF is not
accessible through SPI.
Grayed boxes = Not used.
Note: Register addresses listed are for I2C. To get the SPI address, add 0x200 with the following exception: Register 0xFF is not
accessible through SPI.
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
______________________________________________________________________________________ 45
BITS FUNCTION
Left/Right Playback Volume. VOLL and VOLR control the playback volume for both the DAC and line input
audio signals.
SETTING GAIN (dB) SETTING GAIN (dB) SETTING GAIN (dB)
0x00 +9 0x0E -2 0x1C -39
0x01 +8.5 0x0F -3 0x1D -43
0x02 +8 0x10 -5 0x1E -47
0x03 +7.5 0x11 -7 0x1F -51
0x04 +7 0x12 -9 0x20 -55
0x05 +6.5 0x13 -11 0x21 -59
0x06 +6 0x14 -13 0x22 -63
0x07 +5 0x15 -15 0x23 -67
0x08 +4 0x16 -17 0x24 -71
0x09 +3 0x17 -19 0x25 -75
0x0A +2 0x18 -23 0x26 -79
0x0B +1 0x19 -27 0x27 -81
0x0C 0 0x1A -31
0x0D -1 0x1B -35
0x28 to 0x3F MUTE
VOLL/VOLR
Note: Gain settings apply when the headphone amplifier is configured in differential mode. In the single-
ended and capacitorless modes, the actual gain is 5dB lower. Assuming LOGL/LOGR = 0dB, line output
gain is 6dB lower.
Table 14. Playback Volume Registers (continued)
REGISTER B7 B6 B5 B4 B3 B2 B1 B0
REGISTER
ADDRESS
(SEE NOTE)
Left-Line Output Level 0 LOLM 00 LOGL 0x1E
Right-Line Output Level 0 LORM 00 LOGR 0x1F
BITS FUNCTION
LOLM/LORM
Left/Right Line Output Mute. LOLM and LORM mute both the DAC and line input audio signals.
0 = Line output is unmuted.
1 = Line output is muted.
Note: VSEN has no effect on the mute function. When LOLM or LORM is set the output is muted immediately
(ZDEN = 1) or at the next zero-crossing (ZDEN = 0).
Left/Right Line Output Gain. LOGL and LOGR set the line output gain according to the following information.
SETTING GAIN (dB) SETTING GAIN (dB)
0x00 0 0x08 -16
0x01 -2 0x09 -18
0x02 -4 0x0A -20
0x03 -6 0x0B -22
0x04 -8 0x0C -24
0x05 -10 0x0D -26
0x06 -12 0x0E -28
LOGL/LOGR
0x07 -14 0x0F -30
Table 15. Output Line-Level Registers
Grayed boxes = Not used.
Note: Register addresses listed are for I2C. To get the SPI address, add 0x200 with the following exception: Register 0xFF is not
accessible through SPI.
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
46 ______________________________________________________________________________________
Microphone Inputs
Two differential microphone inputs and a low noise 1.5V
microphone bias for powering the microphones are
provided by the MAX9880A. In typical applications, the
left microphone records a voice signal and the right
microphone records a background noise signal. In
applications that require only one microphone, use the
left microphone input and disable the right ADC. The
microphone signals are amplified by two stages of gain
and then routed to the ADCs. The first stage offers
selectable 0dB, 20dB, or 30dB settings. The second
stage is a programmable gain amplifier (PGA)
adjustable from 0dB to 20dB in 1dB steps. Zero-cross-
ing detection is included on the PGA to minimize zipper
noise while making gain changes. See Figure 6 for a
detailed diagram of the microphone input structure.
REGISTER B7 B6 B5 B4 B3 B2 B1 B0
REGISTER
ADDRESS
(SEE NOTE)
Left Microphone Gain 0 PALEN PGAML 0x20
Right Microphone Gain 0 PAREN PGAMR 0x21
BITS FUNCTION
PALEN/
PAREN
Left/Right Microphone Preamplifier Gain. Enables the microphone circuitry and sets the preamplifier gain.
00 = Disabled
01 = 0dB
10 = +20dB
11 = +30dB
Table 16. Microphone Input Registers
MICLN
MICLP
MICBIAS
PGA
PGA
-
PREAMP
MICRN
ADC
L
ADC
R
MICRP
1.5V
0/20/30dB
0dB TO +20dB
0dB TO +20dB
VREG
VREG
0/20/30dB
PREAMP
MAX9880A
Figure 6. Microphone Input Block Diagram
Grayed boxes = Not used.
Note: Register addresses listed are for I2C. To get the SPI address, add 0x200 with the following exception: Register 0xFF is not
accessible through SPI.
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
______________________________________________________________________________________ 47
BITS FUNCTION
Left/Right Microphone Programmable Gain Amplifier
SETTING GAIN (dB) SETTING GAIN (dB)
0x00 +20 0x0B +9
0x01 +19 0x0C +8
0x02 +18 0x0D +7
0x03 +17 0x0E +6
0x04 +16 0x0F +5
0x05 +15 0x10 +4
0x06 +14 0x11 +3
0x07 +13 0x12 +2
0x08 +12 0x13 +1
0x09 +11 0x14 to 0x1F 0
PGAML/
PGAMR
0x0A +10
Table 16. Microphone Input Registers (continued)
ADC
The MAX9880A includes two 18-bit ADCs. The first
ADC is used to record left-channel microphone and
line-input audio signals. The second ADC can be used
to record right-channel microphone and line-input sig-
nals or it can be configured to accurately measure DC
voltages.
When measuring DC voltages both the left and right ADC
must be enabled by setting ADLEN and ADREN in regis-
ter 0x26. The input to the second ADC is JACKSNS/
AUX and the output is reported in AUX (registers 0x02
and 0x03). Since the audio ADC is used to perform the
measurement, the digital audio interface must be prop-
erly configured. If the left ADC is being used to convert
audio, then the DC measurement is performed at the
same sample rate. When not using the left ADC, config-
ure the digital interface for a 48kHz sample rate to
ensure the fastest possible settling time.
To ensure accurate results, the MAX9880A includes
two calibration routines. Calibrate the ADC each time
the MAX9880A is powered on. Calibration settings are
not lost if the MAX9880A is placed in shutdown. When
making a measurement, set AUXCAP to 1 to prevent
AUX from changing while reading the registers.
Setup Procedure
1) Ensure a valid MCLK signal is provided and config-
ure PSCLK appropriately.
2) Choose a clocking mode. The following options are
possible:
a. Slave mode with LRCLK and BCLK signals
provided. The measurement sample rate is
determined by the external clocks.
b. Slave mode with no LRCLK and BCLK signals
provided. Configure the device for normal clock
mode using the NI ratio. Select fS= 48kHz to
allow for the fastest settling times.
c. Master mode with audio. Configure the device
in normal mode using the NI ratio or exact inte-
ger mode using FREQ1 as required by the audio
signal.
d. Master mode without audio. Configure the
device in normal mode using the NI ratio. Select
fS= 48kHz to allow for the fastest settling times.
3) Ensure jack sense is disabled.
4) Enable the left and right ADC; take the MAX9880A
out of shutdown.
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
48 ______________________________________________________________________________________
Offset Calibration Procedure
Perform before the first DC measurement is taken after
applying power to the MAX9880A.
1) Enable the AUX input (AUXEN = 1).
2) Enable the offset calibration (AUXCAL = 1).
3) Wait the appropriate time (see Table 17).
4) Complete calibration (AUXCAL = 0).
Gain Calibration Procedure
Perform the first time a DC measurement is taken after
applying power to the MAX9880A or if the temperature
changes significantly.
1) Enable the AUX input (AUXEN = 1).
2) Start gain calibration (AUXGAIN = 1).
3) Wait the appropriate time (see Table 17).
4) Freeze the measurement results (AUXCAP = 1).
5) Read AUX and store the value in memory to correct
all future measurements (k = AUX[15:0], k is typical-
ly 19,500).
6) Complete calibration (AUXGAIN = AUXCAP = 0).
DC Measurement Procedure
Perform after offset and gain calibration are complete.
1) Enable the AUX input (AUXEN = 1).
2) Wait the appropriate time (see Table 17).
3) Freeze the measurement results (AUXCAP = 1).
4) Read AUX and correct with the gain calibration value
5) Complete measurement (AUXCAP = 0).
Complete DC Measurement Example
fMCLK = 13MHz, slave mode, BCLK, and LRCLK are
not externally supplied.
1) Configure the digital audio interface for fs= 48kHz
(PSCLK = 01, FREQ1 = 0x0, PLL = 0, NI = 0x5ABE,
MAS = 0).
2) Disable jack sense (JDETEN = 0).
3) Enable the left and right ADC; take the MAX9880A
out of shutdown (ADLEN = ADREN = SHDN = 1).
4) Calibrate the offset:
a. Enable the AUX input (AUXEN = 1).
b. Enable the offset calibration (AUXCAL = 1).
c. Wait 40ms.
d. Complete calibration (AUXCAL = 0).
5) Calibrate the gain:
a. Start gain calibration (AUXGAIN = 1).
b. Wait 40ms.
c. Freeze the measurement results (AUXCAP = 1).
d. Read AUX and store the value in memory to cor-
rect all future measurements (k = AUX[15:0]).
e. Complete calibration (AUXGAIN = AUXCAP =
AUXEN = 0).
6) Measure the voltage on JACKSNS/AUX.
a. Enable the AUX input (AUXEN = 1).
b. Wait 40ms.
c. Freeze the measurement results (AUXCAP = 1).
d. Read AUX and correct with the gain calibration
value.
e. Complete measurement (AUXCAP = 0).
7) DC measurement is complete.
VAUX
k
AUX =⎛
⎝
⎜⎞
⎠
⎟
⎛
⎝
⎜⎞
⎠
⎟
0 738 15 0
.[:] .
LRCLK (kHz) WAIT TIME (ms)
48 40
44.1 44
32 60
24 80
22.05 90
16 120
12 160
11.025 175
8 240
Table 17. AUX ADC Wait Times
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
______________________________________________________________________________________ 49
REGISTER B7 B6 B5 B4 B3 B2 B1 B0
REGISTER
ADDRESS
(SEE NOTE)
Input MXINL MXINR AUXCAP AUXGAIN AUXCAL AUXEN 0x22
BITS FUNCTION
MXINL/MXINR
Left/Right ADC Audio Input Mixer
00 = No input selected
01 = Left/right analog microphone
10 = Left/right line input
11 = Left/right analog microphone + line input
Note: If the right line input is disabled, then the left line input is connected to both mixers. Enabling the left
and right digital microphones disables the left and right audio mixer, respectively. See the DIGMICL/
DIGMICR bit description for more details.
AUXCAP
Auxiliary Input Capture
0 = Update AUX with the voltage at JACKSNS/AUX.
1 = Hold AUX for reading.
AUXGAIN
Auxiliary Input Gain Calibration
0 = Normal operation
1 = The input buffer is disconnected from JACKSNS/AUX and connected to an internal voltage reference.
While in this mode, read the AUX register and store the value. Use the stored value as a gain
calibration factor, k, on subsequent readings. AUXCAL must remain set for time indicated in Table 17 to
guarantee an accurate offset calibration.
AUXCAL
Auxiliary Input Offset Calibration
0 = Normal operation
1 = JACKSNS/AUX is disconnected from the input and the ADC automatically calibrates out any internal
offsets. AUXCAL must remain set for time indicated in Table 17 to guarantee an accurate offset
calibration.
AUXEN
Auxiliary Input Enable
0 = Use JACKSNS/AUX for jack detection.
1 = Use JACKSNS/AUX for DC measurements.
Note: Set MXINR = 00, ADLEN = 1, and ADREN = 1 when AUXEN = 1.
Table 18. ADC Input Register
Note: Register addresses listed are for I2C. To get the SPI address, add 0x200 with the following exception: Register 0xFF is not
accessible through SPI.
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
50 ______________________________________________________________________________________
Digital Microphone Input
The MAX9880A can accept audio from up to two digi-
tal microphones. When using digital microphones, the
left analog microphone input is retasked as a digital
microphone input. The right analog microphone input is
still available to allow a combination of analog and digi-
tal microphones to be used. Figure 7 shows the digital
microphone interface timing diagram.
DIGMICCLK
DIGMICDATA
tSU, MIC
tHD, MIC tSU, MIC
tHD, MIC
LEFT RIGHT LEFT RIGHT
1/fMICCLK
Figure 7. Digital Microphone Timing Diagram
REGISTER B7 B6 B5 B4 B3 B2 B1 B0
REGISTER
ADDRESS
(SEE NOTE)
Microphone MICCLK DIGMICL DIGMICR 0 0 0 MBIAS 0x23
BITS FUNCTION
MICCLK
Digital Microphone Clock
00 = PCLK/8
01 = PCLK/6
10 = 64fS (high jitter clock)
11 = Reserved
Digital Left/Right Microphone Enable
DIGMICL DIGMICR LEFT ADC INPUT RIGHT ADC INPUT
0 0 ADC input mixer ADC input mixer
0 1
Line input (left analog
microphone unavailable) Right digital microphone
1 0 Left digital microphone ADC input mixer
1 1 Left digital microphone Right digital microphone
DIGMICL/
DIGMICR
Note: The left analog microphone input is never available when DIGMICL or DIGMICR = 1.
MBIAS
Microphone Bias Output Voltage
Set MBIAS = 0 for nominal output of 1.52V (VMICVDD = 1.8V)
Set MBIAS = 1 for nominal output of 2.2V (VMICVDD = 3V)
Table 19. Digital Microphone Input Register
Grayed boxes = Not used.
Note: Register addresses listed are for I2C. To get the SPI address, add 0x200 with the following exception: Register 0xFF is not
accessible through SPI.
Jack Configuration Change Flag (JDET)
1 = Jack configuration has changed.
0 = No change in jack configuration.
JDET reports changes in JKSNS[1:0]. Changes to
JKSNS[1:0] are debounced before setting JDET. The
debounce period is programmable using the JDEB bits.
Jack status register 0x01 is a read-only register that reports
the status of the jack-detect circuitry when enabled.
Jack Sense (JKSNS)
JKSNS[1:0] reports the status of the JACKSNS pin
when JDETEN = 1. JKSNS[1:0] should be interpreted
according to Table 21.
Jack-Detect Interrupt Enable (IJDET)
Hardware interrupts are reported on the open-drain IRQ
pin. When an interrupt occurs, IRQ remains low until the
interrupt is serviced by reading the status register 0x00.
If a flag is set, it is reported as a hardware interrupt only
if the corresponding interrupt enable is set. Each bit
enables interrupts for the status flag in the respective
bit location in register 0x00. So IJDET must be set to
enable interrupts for jack detect.
Jack-Detect Enable (JDETEN)
Enables the jack-detect circuitry.
Jack-Sense Weak Pullup (JDWK)
Enables a weak internal pullup current for reduced
power loss when the chip is in shutdown or the
MICBIAS is disabled.
JDWK = 0 enables a 2.2kΩpullup to obtain full jack-
detect operation. This mode can be used to detect
insertion and removal of a plug as well as distinguish
between headphone and headset accessories.
JDWK = 1 enables a 4µA pullup current source when
SHDN = 0 or MICBIAS disabled. In this power-saving
configuration, the circuit can detect insertion and
removal of a plug but cannot distinguish between head-
phone and headset accessories.
The recommended usage follows: Set JDWK = 0 (or set
any bit in the microphone preamplifier gain registers
PALEN[1:0] or PAREN[1:0]). This enables the 2.2kΩ
pullup. Once the jack has been inserted and the type of
accessory determined, set JDWK = 1 to save power.
Once the plug is removed, set JDWK = 0.
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
______________________________________________________________________________________ 51
Mode Configuration
The MAX9880A includes circuitry to minimize click-and-
pop during volume changes, detect headsets, and con-
figure the headphone amplifier mode. Both volume
slewing and zero-crossing detection are included to
ensure click-and-pop free volume transitions.
Headset Detection Overview
The MAX9880A contains headset detect circuitry that is
capable of detecting the insertion or removal of a plug
and providing information to assist the system controller
in determining the configuration of an inserted plug. If
programmed to do so, upon insertion or removal of a
plug, the IRQ output is asserted (pulled low).
Table 20 shows the registers associated with the jack
detect function in MAX9880A.
Table 21. Jack Sense (JKSNS)
Table 20. Jack-Detect Registers
REGISTER B7 B6 B5 B4 B3 B2 B1 B0 REGISTER
ADDRESS POR STATE R/W
Status CLD SLD ULK — * * JDET — 0x00 — R
Jack Status JKSNS[1:0] — — — — — — 0x01 — R
Interrupt Enable ICLD ISLD IULK 00* 0* IJDET 0 0x04 0x00 R/W
Jack Detect JDETEN 0 JDWK 0 0 0 JDEB 0x25 0x00 R/W
JKSNS[1:0] DESCRIPTION
00 JACKSNS is below VTH2 (low).
01 JACKSNS is between VTH1 and VTH2 (mid).
10 Invalid.
11 JACKSNS is above VTH1 (high).
Grayed boxes = Not used.
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
52 ______________________________________________________________________________________
MIC GND HPR HPL
LOUTP
ROUTP
MICBIAS
JACKSNS/AUX
MICLP
Figure 8. Typical Configuration for Headset Detection
Debounce (JDEB)
Configures the JDET debounce time for changes to
JKSNS[1:0] according to Table 22.
For jack plug insertion/removal, the sequence of events
is as follows:
Jack insertion: No jack is present. The MAX9880A has
a power supply and is in low-power sleep mode
(LOUTP/ROUTP are high impedance). When the
JDETEN I2C bit is set, the JACKSNS pin has weak
pullups to MICVDD. When a jack is subsequently insert-
ed, JACKSNS should change state (indicated by I2C
bits JKSNS[1:0]), and this causes the IRQ pin to be
pulled low, which can trigger a system wakeup.
Jack present: After an interrupt has been sent to the
system controller, the I2C must indicate unambiguously
that a jack is present when the I2C registers are read.
This is done with the JDET I2C bit, which goes high
when there is a change of state of the JKSNS[1:0] bits.
The MAX9880A jack-detect system monitors the
JACKSNS pin and reports the voltage level as high
(> 95% x MICBIAS), mid, or low (< 10% x MICBIAS).
When connected to the microphone pin of the headset
jack, this window comparator allows detection of:
• No headset (high)
• Cellular headset with microphone (high →mid)
• Stereo headset without microphone (high →low)
• Cellular headset button press (mid →low →mid)
• Headset removal (low or mid →high)
Jack removal: A jack is present. All output poles
(headphones/line outs) are assumed driven by a low
impedance amplifier. All input poles (microphones) are
assumed to be biased with a voltage above ground but
below 95% of the MICBIAS voltage. For the MAX9880A
to sense when a jack is removed, the JACKSNS pin
must be connected to the jack in such a way as to
ensure either the JACKSNS pin gets pulled above 95%
of MICBIAS (as would happen if JACKSNS is hooked to
a microphone pole) or it changes state from low to high
or vice versa (as would happen if JACKSNS is hooked
to a ground pole which goes high impedance when the
jack is removed, or is hooked to a regular jack insertion
tab that shorts to ground when the jack is removed).
Subsequently, IRQ is pulled low.
Jack absent: After an interrupt has been sent to the
system controller, the I2C must indicate unambiguously
that a jack is not present when the I2C registers are
read. This is indicated by reading the status of the
JKSNS[1:0] I2C read bits.
Table 22. Debounce Time
JDEB DEBOUNCE (ms)
00 25
01 50
10 100
11 200
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
______________________________________________________________________________________ 53
Table 23. Headset Detect Configuration
JACK ACTION JKSNS IRQ TOGGLES?
SHDN MICBIAS JDWK FROM TO FROM TO IJDET = 1 IJDET = 0
0 — 0 None Headset 11 01 Yes No
0 — 0 None Headphone 11 00 Yes No
0 — 0 Headset None 01 11 Yes No
0 — 0 Headphone None 00 11 Yes No
0 — 1 None Headset 11 00 Yes No
0 — 1 None Headphone 11 00 Yes No
0 — 1 Headset None 00 11 Yes No
0 — 1 Headphone None 00 11 Yes No
1 0 0 None Headset 11 01 Yes No
1 0 0 None Headphone 11 00 Yes No
1 0 0 Headset None 01 11 Yes No
1 0 0 Headphone None 00 11 Yes No
1 0 1 None Headset 11 00 Yes No
1 0 1 None Headphone 11 00 Yes No
1 0 1 Headset None 00 11 Yes No
1 0 1 Headphone None 00 11 Yes No
1 1 — None Headset 11 01 Yes No
1 1 — None Headphone 11 00 Yes No
1 1 — Headset None 01 11 Yes No
1 1 — Headphone None 00 11 Yes No
Note: JDETEN = 1; MICBIAS enable; any bit of PALEN/PAREN set.
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
54 ______________________________________________________________________________________
LOUTP
LOUTN
ROUTP
ROUTN
DIFFERENTIAL
LOUTP
LOUTN
ROUTP
ROUTN
CAPACITORLESS
1µF
LOUTP
220µF
LOUTN
SINGLE-ENDED
1µF
ROUTP
220µF
ROUTN
OPTIONAL COMPONENTS REQUIRED FOR CLICK-AND-POP SUPPRESSION ONLY.
Figure 9. Headphone Amplifier Modes
REGISTER B7 B6 B5 B4 B3 B2 B1 B0
REGISTER
ADDRESS
(SEE NOTE)
Mode DSLEW VSEN ZDEN 00 HPMODE 0x24
Jack Detect JDETEN 0 JDWK 0 0 0 JDEB 0x25
BITS FUNCTION
DSLEW
Digital Volume Slew Speed
0 = Digital volume changes are slewed over 10ms.
1 = Digital volume changes are slewed over 80ms.
VSEN
Volume Change Smoothing
0 = Volume changes slew through all intermediate values.
1 = Volume changes occur in one step.
ZDEN
Line Input Zero-Crossing Detection
0 = Line input volume changes occur at zero crossings in the audio waveform or after 62ms if no zero
crossing occurs.
1 = Line input volume changes occur immediately.
Table 24. Mode Configuration Register
Headphone Modes
The MAX9880A’s headphone amplifier supports differen-
tial, single-ended, and capacitorless output modes, as
shown in Figure 9. In each mode, the amplifier can be
configured for stereo or mono operation. The single-
ended mode optionally includes click-and-pop reduc-
tion to eliminate the click-and-pop that would normally
be caused by the output coupling capacitor. When
click-and-pop reduction is not required leave LOUTN
and ROUTN unconnected.
Grayed boxes = Not used.
Note: Register addresses listed are for I2C. To get the SPI address, add 0x200 with the following exception: Register 0xFF is not
accessible through SPI.
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
______________________________________________________________________________________ 55
BITS FUNCTION
Headphone Amplifier Mode
HPMODE MODE
000 Stereo differential
001 Mono (left) differential
010 Stereo capacitorless
011 Mono (left) capacitorless
100 Stereo single-ended (clickless)
101 Mono (left) single-ended (clickless)
110 Stereo single-ended (fast turn-on)
111 Mono (left) single-ended (fast turn-on)
HPMODE
Note: In mono operation, the right amplifier is disabled.
JDETEN
Jack-Detection Enable
SHDN = 0: Sleep Mode. Enables pullups on JACKSNS/AUX to detect jack insertion.
SHDN = 1: Normal Mode. Enables the comparator circuitry on JACKSNS/AUX to detect voltage changes.
Note: AUXEN must be set to 0 for jack detection to function.
JDWK Jack-Sense Weak Pullup. Enables an internal pullup. Set JDWK = 1 to enable an internal 4µA current
source. Set JDWK = 0 for external pullup.
Jack Detect Debounce. Configures the JDET debounce time for changes to JKSNS[1:0] according to
information below.
JDEB DEBOUNCE TIME (ms)
00 25
01 50
10 100
JDEB
11 200
Table 24. Mode Configuration Register (continued)
Power Management
The MAX9880A includes complete power management
control to minimize power usage. The DAC and both
ADCs can be independently enabled so that only the
required circuitry is active.
Revision Code
The MAX9880A includes a revision code to allow easy
identification of the device revision. Revision code at
register address 0xFF is not accessible through the SPI
interface and so the revision code is accessible
through SPI at an additional address of 0x214. The cur-
rent revision code is 0x42.
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
56 ______________________________________________________________________________________
REGISTER B7 B6 B5 B4 B3 B2 B1 B0
REGISTER
ADDRESS
(SEE NOTE)
Enable LNLEN LNREN LOLEN LOREN DALEN DAREN ADLEN ADREN 0x26
System Shutdown SHDN 0 0 0 XTEN XTOSC 00 0x27
BITS FUNCTION
LNLEN
Left-Line Input Enable. Enables the left-line input preamp and automatically enables the left and right
headphone amplifiers. If LNREN = 0, the left-line input signal is also routed to the right ADC input mixer and
right headphone amplifier.
Note: Control of the right headphone amplifier can be overridden by HPMODE.
LNREN
Right-Line Input Enable. Enables the right-line input preamp and automatically enables the right headphone
amplifiers.
Note: Control of the right headphone amplifier can be overridden by HPMODE.
LOLEN Left-Line Output Enable. Enables the left-line output.
LOREN Right-Line Output Enable. Enables the right-line output.
DALEN
Left DAC Enable. Enables the left DAC and automatically enables the left and right headphone amplifiers. If
DAREN = 0, the left DAC signal is also routed to the right headphone amplifier.
Note: Control of the right headphone amplifier can be overridden by HPMODE.
DAREN Right DAC Enable. Enables the right DAC. Right DAC operation requires DALEN = 1.
ADLEN Left ADC Enable.
ADREN
Right ADC Enable. Enabling the right ADC must be done in the same I2C write operation that enables the left
ADC. The right ADC can be enabled while the left ADC is running if used for DC measurements. SHDN must
be toggled to disable the right ADC in this case. Right ADC operation requires ADLEN = 1.
SHDN Shutdown. Places the device in low power shutdown mode.
XTEN
Crystal Clock Enable
1 = Output of crystal oscillator and buffer routed to the clock prescaler. MCLK input disabled.
0 = MCLK input routed to the clock prescaler. Crystal oscillator and buffer disabled.
XTOSC
Crystal Clock Source
1 = Disables the internal crystal oscillator. Provide an external clock on X1.
0 = Enables the internal crystal oscillator. Attach a crystal between X1 and X2. XTOSC is ignored if XTEN = 0.
Table 25. Power Management Register
REGISTER B7 B6 B5 B4 B3 B2 B1 B0
REGISTER
ADDRESS
(SEE NOTE)
Revision ID REV 0x14
Revision ID REV 0xFF
Table 26. Revision Code Register
Grayed boxes = Not used.
Note: Register addresses listed are for I2C. To get the SPI address, add 0x200 with the following exception: Register 0xFF is not
accessible through SPI.
Note: Register addresses listed are for I2C. To get the SPI address, add 0x200 with the following exception: Register 0xFF is not
accessible through SPI.
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
______________________________________________________________________________________ 57
CS
SCLK
DIN
DOUT
tCSS
tCH
tDH tDS tDO tDZ
tDEN
tCL
tCSH
tCP
tCSW
Figure 10. SPI Interface Timing Diagram
CS
SCLK
DIN
DOUT HIGH-Z
R/W ADDR9 ADDR0 UNUSED4 UNUSED0 D7 D0
1 DATA BYTE
Figure 11. Writing 1 Byte of Data to the MAX9880A
Serial Peripheral Interface (SPI)
Chip Select (CS)
The MAX9880A SPI interface is active only when CS is
low. When CS is high, the MAX9880A configures the
DOUT output for high impedance and resets the inter-
nal SPI logic. If CS goes high in the middle of an SPI
transfer, all the data is discarded. When CS is low,
unless the register address is correctly decoded by the
MAX9880A, the DOUT output is high impedance.
Serial Clock (SCLK)
The SPI master provides the SCLK signal to clock the
SPI interface. SCLK has an upper frequency limit of
25MHz. The MAX9880A samples the DIN input data on
the falling edge of SCLK and changes the output data
on the rising edge of SCLK. The MAX9880A ignores
SCLK transitions when CS is high.
Serial-Data In (DIN) and Serial-Data Out (DOUT)
The SPI frame is organized into 24 bits. The first 16 bits
consist of the R/W enable bit, followed by the 10 regis-
ter address bits and 5 unused bits. The next 8 bits are
data bits, sent most significant bit first.
For an SPI write transfer, write a 1 to the R/W bit, fol-
lowed by the 10 register address bits, 5 unused bits,
then the 8 data bits.
Figure 11 illustrates the proper frame format for writing
one byte of data to the MAX9880A. Additional 24-bit
frames can be sent while CS remains low. The DOUT
output is high impedance during a write operation.
For an SPI read transfer, write a zero to the R/W bit, fol-
lowed by the 10 register address bits and 5 unused
bits. Any data sent after the register address bits are
ignored. The internal contents of the register being read
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
58 ______________________________________________________________________________________
CS
SCLK
DIN
DOUT HIGH-Z
R/W ADDR9 ADDR0 UNUSED4 UNUSED0
D7 D0
1 DATA BYTE
Figure 12. Reading 1 Byte of Data from the MAX9880A
SCLK
DIN
DOUT HIGH-Z
R/W ADDR9 ADDR0 UNUSED4 UNUSED0
D7 D0
1 DATA BYTE 1 DATA BYTE
CS
D7 D0
AUTOINCREMENT INTERNAL
REGISTER ADDRESS POINTER
Figure 13. Reading n Bytes of Data from the MAX9880A
SMBus is a trademark of Intel Corp.
do not change until the transfer is complete. The DOUT
output is high impedance when writing the register
address bits. If the correct register address is decod-
ed, DOUT is driven low at the first rising clock edge
after the first unused bit.
Figure 12 illustrates the proper frame format for reading
1 byte of data from the MAX9880A.
When reading data from the MAX9880A, the address
pointer autoincrements by one register address if CS is
held low after reading the first 8 data bits. For each
subsequent eight clock cycles, a byte of data is read.
This autoincrement feature allows a master to read
sequential registers within one continuous SPI register
address range from 0x200 to 0x227. The register
address does not autoincrement if a read is initiated at
a register address lower than 0x200. If the register
address increments beyond 0x227, the DOUT output is
high impedance. Figure 13 illustrates the proper format
for reading multiple bytes of data.
I2C Serial Interface
The MAX9880A features an I2C/SMBus™-compatible,
2-wire serial interface consisting of a serial-data line
(SDA) and a serial-clock line (SCL). SDA and SCL
facilitate communication between the MAX9880A and
the master at clock rates up to 400kHz. Figure 14
shows the 2-wire interface timing diagram. The master
generates SCL and initiates data transfer on the bus.
The master device writes data to the MAX9880A by
transmitting the proper slave address followed by the
register address and then the data word. Each transmit
sequence is framed by a START (S) or repeated
START (Sr) condition and a STOP (P) condition. Each
word transmitted to the MAX9880A is 8 bits long and is
followed by an acknowledge clock pulse. A master
reading data from the MAX9880A transmits the proper
slave address followed by a series of nine SCL pulses.
The MAX9880A transmits data on SDA in sync with the
master-generated SCL pulses. The master acknowl-
edges receipt of each byte of data. Each read
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
______________________________________________________________________________________ 59
SCL
SDA
tRtF
tBUF
START
CONDITION
STOP
CONDITION
REPEATED START CONDITION
START CONDITION
tSU,STO
tHD,STA
tSU,STA
tHD,DAT
tSU,DAT
tLOW
tHIGH
tHD,STA
tSP
Figure 14. 2-Wire Interface Timing Diagram
SCL
SDA
SSrP
Figure 15. START, STOP, and Repeated START Conditions
sequence is framed by a START or repeated START
condition, a not acknowledge, and a STOP condition.
SDA operates as both an input and an open-drain out-
put. A pullup resistor, typically greater than 500Ω, is
required on SDA. SCL operates only as an input. A
pullup resistor, typically greater than 500Ω, is required
on SCL if there are multiple masters on the bus, or if the
single master has an open-drain SCL output. Series
resistors in line with SDA and SCL are optional. Series
resistors protect the digital inputs of the MAX9880A
from high voltage spikes on the bus lines and minimize
crosstalk and undershoot of the bus signals.
Bit Transfer
One data bit is transferred during each SCL cycle. The
data on SDA must remain stable during the high period
of the SCL pulse. Changes in SDA while SCL is high
are control signals (see the
START and STOP
Conditions
section).
START and STOP Conditions
SDA and SCL idle high when the bus is not in use. A
master initiates communication by issuing a START
condition. A START condition is a high-to-low transition
on SDA with SCL high. A STOP condition is a low-to-
high transition on SDA while SCL is high (Figure 15). A
START condition from the master signals the beginning
of a transmission to the MAX9880A. The master termi-
nates transmission and frees the bus by issuing a STOP
condition. The bus remains active if a repeated START
condition is generated instead of a STOP condition.
Early STOP Conditions
The MAX9880A recognizes a STOP condition at any
point during data transmission except if the STOP con-
dition occurs in the same high pulse as a START condi-
tion. For proper operation, do not send a STOP
condition during the same SCL high pulse as the
START condition.
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
60 ______________________________________________________________________________________
1
SCL
START
CONDITION
SDA
29
CLOCK PULSE FOR
ACKNOWLEDGMENT
ACKNOWLEDGE
NOT ACKNOWLEDGE
Figure 16. Acknowledge
A
0SLAVE ADDRESS REGISTER ADDRESS DATA BYTE
ACKNOWLEDGE FROM MAX9880A
R/W 1 BYTE
AUTOINCREMENT INTERNAL
REGISTER ADDRESS POINTER
ACKNOWLEDGE FROM MAX9880A
ACKNOWLEDGE FROM MAX9880A
B1 B0B3 B2B5 B4B7 B6
S AA P
Figure 17. Writing 1 Byte of Data
Slave Address
The slave address is defined as the seven most signifi-
cant bits (MSBs) followed by the read/write bit. For the
MAX9880A, the seven most significant bits are
0010000. Setting the read/write bit to 1 (slave address
= 0x21) configures the MAX9880A for read mode.
Setting the read/write bit to 0 (slave address = 0x20)
configures the MAX9880A for write mode. The address
is the first byte of information sent to the MAX9880A
after the START condition.
Acknowledge
The acknowledge bit (ACK) is a clocked 9th bit that the
MAX9880A uses to handshake receipt each byte of
data when in write mode (see Figure 16). The
MAX9880A pulls down SDA during the entire master-
generated 9th clock pulse if the previous byte is suc-
cessfully received. Monitoring ACK allows for detection
of unsuccessful data transfers. An unsuccessful data
transfer occurs if a receiving device is busy or if a sys-
tem fault has occurred. In the event of an unsuccessful
data transfer, the bus master retries communication.
The master pulls down SDA during the 9th clock cycle
to acknowledge receipt of data when the MAX9880A is
in read mode. An acknowledge is sent by the master
after each read byte to allow data transfer to continue.
A not acknowledge is sent when the master reads the
final byte of data from the MAX9880A, followed by a
STOP condition.
Write Data Format
A write to the MAX9880A includes transmission of a
START condition, the slave address with the R/Wbit set
to 0, 1 byte of data to configure the internal register
address pointer, 1 or more bytes of data, and a STOP
condition. Figure 17 illustrates the proper frame format
for writing 1 byte of data to the MAX9880A. Figure 18
illustrates the frame format for writing n bytes of data to
the MAX9880A.
The slave address with the R/Wbit set to 0 indicates
that the master intends to write data to the MAX9880A.
The MAX9880A acknowledges receipt of the address
byte during the master-generated 9th SCL pulse.
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
______________________________________________________________________________________ 61
1 BYTE
AUTOINCREMENT INTERNAL
REGISTER ADDRESS POINTER
ACKNOWLEDGE FROM MAX9880A
ACKNOWLEDGE FROM MAX9880A
B1 B0B3 B2B5 B4B7 B6
AA0
ACKNOWLEDGE FROM MAX9880A
R/W
SA
1 BYTE
ACKNOWLEDGE FROM MAX9880A
B1 B0B3 B2B5 B4B7 B6
P
A
SLAVE ADDRESS REGISTER ADDRESS DATA BYTE 1 DATA BYTE n
Figure 18. Writing n Bytes of Data
ACKNOWLEDGE FROM MAX9880A
1 BYTE
AUTOINCREMENT INTERNAL
REGISTER ADDRESS POINTER
ACKNOWLEDGE FROM MAX9880A
NOT ACKNOWLEDGE FROM MASTER
AA
AP
A
0
ACKNOWLEDGE FROM MAX9880A
R/W
S
R/WREPEATED START
Sr 1SLAVE ADDRESS REGISTER ADDRESS SLAVE ADDRESS DATA BYTE
Figure 19. Reading 1 Byte of Data
The second byte transmitted from the master config-
ures the MAX9880A’s internal register address pointer.
The pointer tells the MAX9880A where to write the next
byte of data. An acknowledge pulse is sent by the
MAX9880A upon receipt of the address pointer data.
The third byte sent to the MAX9880A contains the data
that is written to the chosen register. An acknowledge
pulse from the MAX9880A signals receipt of the data
byte. The address pointer autoincrements to the next
register address after each received data byte. This
autoincrement feature allows a master to write to
sequential registers within one continuous frame. The
master signals the end of transmission by issuing a
STOP condition. Register addresses greater than 0x17
are reserved. Do not write to these addresses.
Read Data Format
Send the slave address with the R/Wbit set to 1 to initi-
ate a read operation. The MAX9880A acknowledges
receipt of its slave address by pulling SDA low during
the 9th SCL clock pulse. A START command followed
by a read command resets the address pointer to reg-
ister 0x00.
The first byte transmitted from the MAX9880A is the
contents of register 0x00. Transmitted data is valid on
the rising edge of SCL. The address pointer autoincre-
ments after each read data byte. This autoincrement
feature allows all registers to be read sequentially within
one continuous frame. A STOP condition can be issued
after any number of read data bytes. If a STOP condi-
tion is issued followed by another read operation, the
first data byte to be read is from register 0x00.
The address pointer can be preset to a specific register
before a read command is issued. The master presets
the address pointer by first sending the MAX9880A’s
slave address with the R/Wbit set to 0 followed by the
register address. A repeated START condition is then
sent followed by the slave address with the R/Wbit set
to 1. The MAX9880A then transmits the contents of the
specified register. The address pointer autoincrements
after transmitting the first byte.
The master acknowledges receipt of each read byte
during the acknowledge clock pulse. The master must
acknowledge all correctly received bytes except the
last byte. The final byte must be followed by a not
acknowledge from the master and then a STOP condi-
tion. Figure 19 illustrates the frame format for reading 1
byte from the MAX9880A. Figure 20 illustrates the frame
format for reading multiple bytes from the MAX9880A.
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
62 ______________________________________________________________________________________
ACKNOWLEDGE FROM MAX9880A
1 BYTE
AUTOINCREMENT INTERNAL
REGISTER ADDRESS POINTER
ACKNOWLEDGE FROM MAX9880A
AAA
NOT ACKNOWLEDGE FROM MASTER
AP
0
ACKNOWLEDGE FROM MAX9880A
R/W
S
R/W
REPEATED START
Sr 1SLAVE ADDRESS REGISTER ADDRESS SLAVE ADDRESS DATA BYTE
Figure 20. Reading n Bytes of Data
SEQUENCE DESCRIPTION REGISTERS
1SHDN = 0 0x27
2 Configure clocks 0x05, 0x06, 0x07, 0x0B, 0x0C
3 Configure digital audio interface 0x08, 0x09, 0x0A, 0x0D, 0x0E, 0x0F
Table 27. Clock Initialization (Perform Before Any Playback or Record Setup)
SEQUENCE DESCRIPTION REGISTERS
1 Select DAC audio source 0x10
2 Select music filters 0x11
3 Set output volume 0x1C, 0x1D
4 Set line output volume 0x1E, 0x1F
5 Select headphone mode 0x24
6 Enable line outputs and DAC as required 0x26
7 Enable LRCLK and BCLK (if operating in slave mode) N/A
8 Enable MAX9880A 0x27
9 Enable external amplifier (if using) N/A
Table 28. Music Playback
Applications Information
Proper layout and grounding are essential for optimum
performance. When designing a PCB for the
MAX9880A, partition the circuitry so that the analog
sections of the MAX9880A are separated from the digi-
tal sections. This ensures that the analog audio traces
are not routed near digital traces.
Use a large continuous ground plane on a dedicated
layer of the PCB to minimize loop areas. Connect
AGND and DGND directly to the ground plane using
the shortest trace length possible. Proper grounding
improves audio performance, minimizes crosstalk
between channels, and prevents any digital noise from
coupling into the analog audio signals.
Ground the bypass capacitors on MICBIAS, REG,
PREG, and REF directly to the ground plane with mini-
mum trace length. Also be sure to minimize the path
length to AGND. Bypass AVDD directly to AGND.
Connect all digital I/O termination to the ground plane
with minimum path length to DGND. Bypass DVDD and
DVDDS1 directly to DGND.
Route microphone signals from the microphone to the
MAX9880A as a differential pair, ensuring that the posi-
tive and negative signals follow the same path as
closely as possible with equal trace length. When using
single-ended microphones or other single-ended audio
sources, ground the negative microphone input as
close to the audio source as possible and then treat the
positive and negative traces as differential pairs.
The MAX9880A TQFN package features an exposed
thermal pad on its underside. Connect the exposed
thermal pad to AGND.
An evaluation kit (EV kit) is available to provide an
example layout for the MAX9880A. The EV kit allows
quick setup of the MAX9880A and includes easy-to-use
software allowing all internal registers to be controlled.
Startup Sequences
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
______________________________________________________________________________________ 63
SEQUENCE DESCRIPTION REGISTERS
1 Set line input gain 0x1A, 0x1B
2 Set volume 0x1C, 0x1D
3 Set line output volume (if using) 0x1E, 0x1F
4 Select headphone mode 0x24
5 Enable line outputs and line inputs as required 0x26
6 Enable MAX9880A 0x27
7 Enable external amplifier (if using) N/A
Table 29. Line Input Playback
SEQUENCE DESCRIPTION REGISTERS
1 Select music filters 0x11
2 Set line input gain 0x1A, 0x1B
3 Set volume 0x1C, 0x1D
4 Set line output volume (if using) 0x1E, 0x1F
5 Configure ADC input mixer 0x22
6 Select headphone mode 0x24
7 Enable line outputs, line inputs, and ADC as required 0x26
8 Enable LRCLK and BCLK (if operating in slave mode) N/A
9 Enable MAX9880A 0x27
10 Enable external amplifier (if using) N/A
Table 30. Line Input Playback with Record
SEQUENCE DESCRIPTION REGISTERS
1 Select DAC audio source 0x10
2 Select voice filters 0x11
3 Set volume 0x1C, 0x1D
4 Set line output volume (if using) 0x1E, 0x1F
5 Select headphone mode 0x24
6 Enable line outputs and DAC as required 0x26
7 Enable LRCLK and BCLK (if operating in slave mode) N/A
8 Enable MAX9880A 0x27
9 Enable external amplifier (if using) N/A
Table 31. Voice Playback
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
64 ______________________________________________________________________________________
SEQUENCE DESCRIPTION REGISTERS
1 Select voice filters 0x11
2 Set ADC level to 0dB 0x18, 0x19
3 Configure microphone gain 0x20, 0x21
4 Set line output volume (if using) 0x1E, 0x1F
5 Configure ADC input mixer 0x22
6 Configure MICBIAS voltage 0x23
7 Enable ADC 0x26
8 Enable LRCLK and BCLK (if operating in slave mode) N/A
9 Enable MAX9880A 0x27
Table 32. Voice Microphone Record
SEQUENCE DESCRIPTION REGISTERS
1 Select voice filters 0x11
2 Set ADC level to 0dB 0x18, 0x19
3 Configure microphone gain 0x20, 0x21
4 Set line output volume (if using) 0x1E, 0x1F
5 Configure ADC input mixer 0x22
6 Configure MICBIAS voltage 0x23
7 Enable ADCs and DACs as required 0x26
8 Enable LRCLK and BCLK (if operating in slave mode) N/A
9 Enable MAX9880A 0x27
Table 33. Voice Playback with Record
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
______________________________________________________________________________________ 65
SEQUENCE DESCRIPTION REGISTER ADDRESS REGISTER VALUE
1SHDN = 0 0x27 04h
2 Configure system clock 0x05 10h
3 Configure DAI2 clock 0x0B 60h
4 Configure DAI2 clock 0x0C 00h
5 Configure DAI2 audio path 0x0D 11h
6 Configure DAI2 audio path 0x0E 50h
7 Select DAC audio source 0x10 21h
8 Select music filters 0x11 80h
9 Set output volume (0dB) 0x1C, 0x1D 09h
10 Set line output volume (muted) 0x1E, 0x1F 40h
11 Select headphone mode (output capacitorless mode) 0x24 02h
12 Enable line outputs and DAC as required 0x26 0Ch
13 Enable MAX9880A 0x27 84h
Table 34. Music Playback
SEQUENCE DESCRIPTION REGISTER ADDRESS REGISTER VALUE
1SHDN = 0 0x27 04h
2 Configure system clock 0x05 10h
3 Configure DAI1 clock 0x0B 0Fh
4 Configure DAI1 clock 0x0C 1Fh
5 Configure DAI1 audio path 0x0D 04h
6 Configure DAI2 audio path 0x0E 30h
7 Select DAC audio source 0x10 21h
8 Select voice GSM filters 0x11 33h
9 Set ADC level to 0dB 0x18, 0x19 03h
10 Configure microphone gain (20dB preamp gain) 0x20, 0x21 54h
11 Set headphone volume 0x1C, 0x1D 09h
12 Set line output volume (if using) 0x1E, 0x1F 40h
13 Configure ADC input mixer 0x22 50h
14 Configure MICBIAS voltage (2.2V) 0x23 01h
15 Select headphone mode 0x24 01h
16 Enable line outputs, ADC and DAC as required 0x26 0Bh
17 Enable MAX9880A 0x27 84h
Table 35. Voice Duplex
Example of Register Settings for Music
Playback and Voice Duplex Senarios
Music Playback
fMCLK = 12.288MHz (master clock supplied to codec),
fLRCLK = 48kHz, standard I2S format, codec in slave
mode, music source connected through S2 pins to
DAI2 audio path, and output on headphone amplifiers
(output capacitorless mode).
Voice Duplex
fMCLK = 13MHz (master clock supplied to codec),
fLRCLK = 8kHz, TDM/PCM format, codec in slave
mode, voice signals on S1 pins to DAI1 audio path and
output on headphone amplifier left (differential mode).
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
66 ______________________________________________________________________________________
MIX
VCM PREG
REF
VOICE/AUDIO
FILTER
DIGITAL AUDIO PATH 1
(8kHz TO 48kHz)
PLL1, NI1,
REGS 08-OA
LINEAR
REG
XTAL
OSC
XTEN,
XTOSC
CLOCK
GEN
I2C/SPI AUDIO SOURCE SELECTION SEL1, SEL2
ADCL
SPDML
MODEADLEN
AVFLT
VOICE/AUDIO
FILTER
FM
RECEIVER
MODE
AVFLTADREN
VOICE/AUDIO
FILTER
MODE, DVFLT
AUDIO
FILTER
DCB
MIXSPDML
SPDMDATA
VOICE/AUDIO
FILTER
MODE, DVFLT
MXINL
PGAML:
+20dB TO 0dB
PALEN:
0/20/30dB
19
(D7)
18
(C7)
LOUTP
HPMODE
LOUTN
MIX/MUX
MIX
ADCR
DGND
47
(A1)
PGND
27
(E6, F6)
AGND
15
(A8)
MIXINR
PGAMR:
+20dB TO 0dB
PAREN:
0/20/30dB
LIGL:
+30dB TO 0dB
AVL:
+4dB TO -11dB
AVLG:
0/6/12/18dB
AVRG:
0/6/12/18dB
AVR:
+4dB TO -11dB
1µF
1µF
MICLP/
DIGMICDATA
1µF13
(C6)
2.2µF10
(B6)
MICBIAS
MICBIAS
REF
REG
17
(B8)
MICLN/
DIGMICCLK
MICRP/
SPDMDATA
SPDMDATA
LNREN
LINL
MICRN/
SPDMCLK
20
(C8)
23
(E8)
LNLEN
LIGR:
+30dB TO 0dB
LINR
24
(F8)
21
(D8)
MIX/MUX
VDACG:
0/6/12/18dB
DSTS
39
(E1)
40
(E2)
DVST:
-9dB TO -69dB
_DACA:
0dB TO -15dB
VDACG:
0/6/12/18dB
_DACA:
0dB TO -15dB
VOLL:
+6dB TO -84dB
LOGL:
0dB TO -30dB
VOLR:
+6dB TO -84dB
MIX/MUX
_DACA:
0dB TO -15dB
VOLL:
+6dB TO -84dB
_DACA:
0dB TO -15dB
VOLR:
+6dB TO -84dB
AUDIO
FILTER
DCB
HPMODE
32
(E4)
31
(F4)
X1
X2
3
(A2)
4
(A3)
ROUTP
ROUTN
HEADPHONE
SENSE
AUXEN
29
(E5)
JACKSNS
/
AUX
22
(D5)
30
(F5)
LOLEN
LOUTL
LOGR:
0dB TO -30dB
26
(E7)
LOREN
LOUTR
25
(F7)
MIX
SPDMR
DAC
DAC
DALEN
DAREN
MIXSPDMR
MIX
1b
I/F
MIXDAL
MIX
MIXDAR
MIX
41
(D1)
MCLK
BCLKS1
LRCLKS1
SDINS1
SDOUTS1
2
(B3)
SCL/SCLK
7
(A5)
MODE
8
(A4)
36
(F2)
DVDDS1
1.8V
37
(F1)
38
(D3)
DIGITAL AUDIO PATH 2
(8kHz TO 96kHz)
PLL2, NI2,
REGS 0D-0F
44
(C2)
45
(C3)
BCLKS2
LRCLKS2
SDINS2
SDOUTS2
42
(D2)
43
(C1)
IRQ
6
(B5)
DOUT
1
(B2)
SDA/DIN
5
(B4)
CS
SPDMCLK
PSCLK
FREQ1
1µF
16
(B7)
MICVDD
1.8V
DVDD
1µF
46
(B1)
1.8V
AVDD
1µF
34
(E3, F3)
1.8V
1µF
9
(A6)
1.8V
PVDD
PREG
1µF
12
(A7)
SPDMCLK
MAX9880A
Functional Diagram/Typical Operating Circuit
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
______________________________________________________________________________________ 67
Package Information
For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”, “#”, or
“-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing per-
tains to the package regardless of RoHS status.
PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND
PATTERN NO.
48 TQFN-EP T4866+1 21-0141 90-0057
48 WLP W482A3+1 21-0230 Refer to Application Note 1891
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
68 ______________________________________________________________________________________
Package Information (continued)
For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”, “#”, or
“-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing per-
tains to the package regardless of RoHS status.
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
______________________________________________________________________________________ 69
Package Information (continued)
For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”, “#”, or
“-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing per-
tains to the package regardless of RoHS status.
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
70
____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2011 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
Revision History
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 7/10 Initial release —
1 3/11 Various data sheet errors
15–22, 24, 29, 31,
47, 49, 51, 52,
55–58, 60, 61,
62, 66
