TPS2041, TPS2051 POWER-DISTRIBUTION SWITCHES SLVS172A -AUGUST 1998 - REVISED APRIL 1999 D D D D D D D D D D D D D 135-m -Maximum (5-V Input) High-Side MOSFET Switch 500 mA Continuous Current Short-Circuit and Thermal Protection With Overcurrent Logic Output Operating Range . . . 2.7 V to 5.5 V Logic-Level Enable Input 2.5-ms Typical Rise Time Undervoltage Lockout 10 A Maximum Standby Supply Current Bidirectional Switch Available in 8-pin SOIC and PDIP Packages Ambient Temperature Range, -40C to 85C 2-kV Human-Body-Model, 200-V Machine-Model ESD Protection UL Listed - File No. E169910 TPS2041 D OR P PACKAGE (TOP VIEW) GND IN IN EN 1 8 2 7 3 6 4 5 OUT OUT OUT OC TPS2051 D OR P PACKAGE (TOP VIEW) GND IN IN EN 1 8 2 7 3 6 4 5 OUT OUT OUT OC description The TPS2041 and TPS2051 power distribution switches are intended for applications where heavy capacitive loads and short circuits are likely to be encountered. The TPS2041 and the TPS2051 are 135-m N-channel MOSFET high-side power switches. Each switch is controlled by a logic enable compatible with 5-V and 3-V logic. Gate drive is provided by an internal charge pump that controls the power-switch rise times and fall times to minimize current surges during switching. The charge pump requires no external components and allows operation from supplies as low as 2.7 V. When the output load exceeds the current-limit threshold or a short is present, the TPS2041 and TPS2051 limit the output current to a safe level by switching into a constant-current mode, pulling the overcurrent (OC) logic output low. When continuous heavy overloads and short circuits increase the power dissipation in the switch, causing the junction temperature to rise, a thermal protection circuit shuts off the switch in overcurrent to prevent damage. Recovery from a thermal shutdown is automatic once the device has cooled sufficiently. Internal circuitry ensures the switch remains off until valid input voltage is present. The TPS2041 and TPS2051 are designed to limit at 0.9-A load. These power distribution switches are available in 8-pin small-outline integrated circuit (SOIC) and 8-pin plastic dual-in-line packages (PDIP) and operate over an ambient temperature range of -40C to 85C. AVAILABLE OPTIONS TA ENABLE RECOMMENDED MAXIMUM CONTINUOUS LOAD CURRENT (A) TYPICAL SHORT-CIRCUIT CURRENT LIMIT AT 25C (A) -40C to 85C Active low 0.5 -40C to 85C Active high 0.5 PACKAGED DEVICES SOIC (D) PDIP (P) 0.9 TPS2041D TPS2041P 0.9 TPS2051D TPS2051P The D package is available taped and reeled. Add an R suffix to device type (e.g., TPS2041DR) Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1999, Texas Instruments Incorporated This document contains information on products in more than one phase of development. The status of each device is indicated on the page(s) specifying its electrical characteristics. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 TPS2041, TPS2051 POWER-DISTRIBUTION SWITCHES SLVS172A -AUGUST 1998 - REVISED APRIL 1999 TPS2041 functional block diagram Power Switch CS IN OUT Charge Pump EN Driver Current Limit OC UVLO Thermal Sense GND Current Sense Terminal Functions TERMINAL NO. NAME I/O D OR P DESCRIPTION TPS2041 TPS2051 EN 4 - I Enable input. Logic low turns on power switch. EN - 4 I Enable input. Logic high turns on power switch. GND 1 1 I Ground IN 2, 3 2, 3 I Input voltage OC 5 5 O Over current. Logic output active low 6, 7, 8 6, 7, 8 O Power-switch output OUT 2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TPS2041, TPS2051 POWER-DISTRIBUTION SWITCHES SLVS172A -AUGUST 1998 - REVISED APRIL 1999 detailed description power switch The power switch is an N-channel MOSFET with a maximum on-state resistance of 135 m (VI(IN) = 5 V). Configured as a high-side switch, the power switch prevents current flow from OUT to IN and IN to OUT when disabled. The power switch supplies a minimum of 500 mA per switch. charge pump An internal charge pump supplies power to the driver circuit and provides the necessary voltage to pull the gate of the MOSFET above the source. The charge pump operates from input voltages as low as 2.7 V and requires very little supply current. driver The driver controls the gate voltage of the power switch. To limit large current surges and reduce the associated electromagnetic interference (EMI) produced, the driver incorporates circuitry that controls the rise times and fall times of the output voltage. The rise and fall times are typically in the 2-ms to 4-ms range. enable (EN or EN) The logic enable disables the power switch and the bias for the charge pump, driver, and other circuitry to reduce the supply current to less than 10 A when a logic high is present on EN (TPS2041) or a logic low is present on EN (TPS2051). A logic zero input on EN or a logic high on EN restores bias to the drive and control circuits and turns the power on. The enable input is compatible with both TTL and CMOS logic levels. overcurrent (OC) The OC open drain output is asserted (active low) when an overcurrent or overtemperature condition is encountered. The output will remain asserted until the overcurrent or overtemperature condition is removed. current sense A sense FET monitors the current supplied to the load. The sense FET measures current more efficiently than conventional resistance methods. When an overload or short circuit is encountered, the current-sense circuitry sends a control signal to the driver. The driver in turn reduces the gate voltage and drives the power FET into its saturation region, which switches the output into a constant current mode and holds the current constant while varying the voltage on the load. thermal sense An internal thermal-sense circuit shuts off the power switch when the junction temperature rises to approximately 140C. Hysteresis is built into the thermal sense circuit. After the device has cooled approximately 20C, the switch turns back on. The switch continues to cycle off and on until the fault is removed. undervoltage lockout A voltage sense circuit monitors the input voltage. When the input voltage is below approximately 2 V, a control signal turns off the power switch. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 TPS2041, TPS2051 POWER-DISTRIBUTION SWITCHES SLVS172A -AUGUST 1998 - REVISED APRIL 1999 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Input voltage range, VI(IN) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 6 V Output voltage range, VO(OUT) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to VI(IN) + 0.3 V Input voltage range, VI(ENx) or VI(ENx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 6 V Continuous output current, IO(OUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . internally limited Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to 125C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . 260C Electrostatic discharge (ESD) protection: Human body model MIL-STD-883C . . . . . . . . . . . . . . . . . . . . . 2 kV Machine model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.2 kV Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltages are with respect to GND. DISSIPATION RATING TABLE PACKAGE TA 25C POWER RATING DERATING FACTOR ABOVE TA = 25C TA = 70C POWER RATING TA = 85C POWER RATING D 725 mW 5.8 mW/C 464 mW 377 mW P 1175 mW 9.4 mW/C 752 mW 611 mW recommended operating conditions Input voltage, VI(IN) TPS2041 TPS2051 MIN MAX MIN MAX 2.7 5.5 2.7 5.5 UNIT V Input voltage, VI(EN) or VI(EN) 0 5.5 0 5.5 V Continuous output current, IO(OUT) 0 500 0 500 mA -40 125 -40 125 C Operating virtual junction temperature, TJ 4 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TPS2041, TPS2051 POWER-DISTRIBUTION SWITCHES SLVS172A -AUGUST 1998 - REVISED APRIL 1999 electrical characteristics over recommended operating junction temperature range, VI(IN)= 5.5 V, IO = rated current, VI(EN) = 0 V, VI(EN) = Hi (unless otherwise noted) power switch TEST CONDITIONS PARAMETER Static St ti drain-source d i on-state t t resistance 5-V o resistance, operation eration rDS(on) DS( ) Static St ti drain-source d i on-state t t resistance, o eration resistance 3.3-V 3 3-V operation tr tf Rise time time, output Fall time, time output TPS2041 MIN TYP TPS2051 MAX MIN TYP MAX VI(IN) = 5 V, VI(IN) = 5 V, TJ = 25C TJ = 85C 80 95 80 95 90 120 90 120 VI(IN) = 5 V, VI(IN) = 3.3 V, TJ = 125C TJ = 25C 100 135 100 135 85 105 85 105 VI(IN) = 3.3 V, VI(IN) = 3.3 V, TJ = 85C TJ = 125C 100 135 100 135 115 150 115 150 VI(IN) = 5.5 V, CL = 1 F, TJ = 25C, RL = 10 2.5 2.5 VI(IN) = 2.7 V, CL = 1 F, TJ = 25C, RL = 10 3 3 VI(IN) = 5.5 V, CL = 1 F, VI(IN) = 2.7 V, CL = 1 F, TJ = 25C, RL = 10 TJ = 25C, RL = 10 4.4 4.4 2.5 2.5 UNIT m ms ms Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately. enable input EN or EN PARAMETER VIH VIL TEST CONDITIONS 2.7 V VI(IN) 5.5 V High-level input voltage Low level input voltage Low-level II Input current ton toff Turnon time TPS2041 TPS2051 Turnoff time TPS2041 MIN TYP TPS2051 MAX 2 MIN TYP MAX 2 V 4.5 V VI(IN) 5.5 V 0.8 0.8 2.7 V VI(IN) 4.5 V 0.4 0.4 VI(EN) = 0 V or VI(EN) = VI(IN) VI(EN) = VI(IN) or VI(EN) = 0 V -0.5 0.5 -0.5 CL = 100 F, RL = 10 CL = 100 F, RL = 10 UNIT 0.5 20 20 40 40 V A ms current limit PARAMETER IOS Short-circuit output current TPS2041 TEST CONDITIONS MIN VI(IN) = 5 V, OUT connected to GND, Device enabled into short circuit TYP 0.7 0.9 TPS2051 MAX MIN 1.1 0.7 TYP 0.9 MAX 1.1 UNIT A Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 TPS2041, TPS2051 POWER-DISTRIBUTION SWITCHES SLVS172A -AUGUST 1998 - REVISED APRIL 1999 electrical characteristics over recommended operating junction temperature range, VI(IN)= 5.5 V, IO = rated current, VI(EN) = 0 V, VI(EN) = Hi (unless otherwise noted) (continued) supply current PARAMETER TPS2041 TEST CONDITIONS Supply y current,, low-level output EN = VI(IN) TJ = 25C -40C TJ 125C TPS2041 EN = 0 V TJ = 25C -40C TJ 125C TPS2051 EN = 0 V TJ = 25C -40C TJ 125C EN = VI(IN) TJ = 25C -40C TJ 125C TPS2051 OUT connected to ground EN = VI(IN) -40C TJ 125C TPS2041 EN= 0 V -40C TJ 125C TPS2051 IN = High g impedance VI(EN) = 0 V VI(EN) = Hi TJ = 25C No Load on OUT Supply y current,, high-level output No Load on OUT Leakage current Reverse leakage g current MIN TYP TPS2051 MAX 0.015 MIN TYP MAX 0.015 1 UNIT 1 10 A 10 80 TPS2041 100 100 80 100 A 100 100 A 100 TPS2041 0.3 TPS2051 A 0.3 undervoltage lockout PARAMETER TEST CONDITIONS Low-level input voltage Hysteresis TPS2041 MIN TYP 2 TJ = 25C TPS2051 MAX MIN 2.5 2 100 TYP MAX 2.5 100 UNIT V mV overcurrent OC PARAMETER Sink current Output low voltage Off-state current TEST CONDITIONS VO = 5 V IO = 5 V, VOL(OC) VO = 5 V, VO = 3.3 V TPS2041 MIN Specified by design, not production tested. 6 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TYP TPS2051 MAX MIN TYP MAX UNIT 10 10 mA 0.5 0.5 V 1 1 A TPS2041, TPS2051 POWER-DISTRIBUTION SWITCHES SLVS172A -AUGUST 1998 - REVISED APRIL 1999 PARAMETER MEASUREMENT INFORMATION OUT RL tf tr CL VO(OUT) 90% 10% 90% 10% TEST CIRCUIT 50% VI(EN) 50% toff ton toff ton 90% VO(OUT) 50% 50% VI(EN) 90% VO(OUT) 10% 10% VOLTAGE WAVEFORMS Figure 1. Test Circuit and Voltage Waveforms VI(EN) (5 V/div) VI(EN) (5 V/div) VI(IN) = 5 V TA = 25C CL = 0.1 F VO(OUT) (2 V/div) 0 1 2 3 4 5 6 7 8 9 VI(IN) = 5 V TA = 25C CL = 0.1 F VO(OUT) (2 V/div) 10 0 1000 2000 3000 4000 5000 t - Time - ms t - Time - ms Figure 2. Turnon Delay and Rise Time with 0.1-F Load POST OFFICE BOX 655303 Figure 3. Turnoff Delay and Fall Time with 0.1-F Load * DALLAS, TEXAS 75265 7 TPS2041, TPS2051 POWER-DISTRIBUTION SWITCHES SLVS172A -AUGUST 1998 - REVISED APRIL 1999 PARAMETER MEASUREMENT INFORMATION VI(EN) (5 V/div) VI(EN) (5 V/div) VI(IN) = 5 V TA = 25C CL = 1 F RL = 10 VO(OUT) (2 V/div) 0 1 2 3 4 5 6 7 8 VI(IN) = 5 V TA = 25C CL = 1 F RL = 10 VO(OUT) (2 V/div) 9 10 0 2 4 6 t - Time - ms 8 10 12 14 16 18 20 t - Time - ms Figure 4. Turnon Delay and Rise Time with 1-F Load Figure 5. Turnoff Delay and Fall Time with 1-F Load VI(IN) = 5 V TA = 25C VI(IN) = 5 V TA = 25C VI(EN) (5 V/div) VO(OUT) (2 V/div) IO(OUT) (0.5 A/div) IO(OUT) (0.2 A/div) 0 1 2 3 4 5 6 7 8 9 10 0 10 Figure 6. TPS2041, Short-Circuit Current, Device Enabled into Short 8 20 30 40 50 60 70 80 90 100 t - Time - ms t - Time - ms POST OFFICE BOX 655303 Figure 7. TPS2041, Threshold Trip Current with Ramped Load on Enabled Device * DALLAS, TEXAS 75265 TPS2041, TPS2051 POWER-DISTRIBUTION SWITCHES SLVS172A -AUGUST 1998 - REVISED APRIL 1999 PARAMETER MEASUREMENT INFORMATION VI(IN) = 5 V TA = 25C RL = 10 VI(EN) (5 V/div) VO(OC) (5 V/div) 470 F 220 F 100 F VI(IN) = 5 V Load Ramp,1A/100 ms TA = 25C IO(OUT) (0.5 A/div) IO(OUT) (o.2 A/div) 0 2 4 6 8 10 12 14 16 0 18 20 20 40 60 80 100 120 140 160 180 200 t - Time - ms t - Time - ms Figure 8. Inrush Current with 100-F, 220-F and 470-F Load Capacitance Figure 9. Ramped Load on Enabled Device VI(IN) = 5 V TA = 25C VI(IN) = 5 V TA = 25C VO(OC) (5 V/div) VO(OC) (5 V/div) IO(OUT) (0.5 A/div) IO(OUT) (1 A/div) 0 400 800 1200 1600 2000 0 20 t - Time - s 40 60 80 100 120 140 160 180 200 t - Time - s Figure 10. 4- Load Connected to Enabled Device POST OFFICE BOX 655303 Figure 11. 1- Load Connected to Enabled Device * DALLAS, TEXAS 75265 9 TPS2041, TPS2051 POWER-DISTRIBUTION SWITCHES SLVS172A -AUGUST 1998 - REVISED APRIL 1999 TYPICAL CHARACTERISTICS TURNON DELAY vs INPUT VOLTAGE TURNOFF DELAY vs INPUT VOLTAGE 6 17 CL = 1 F RL = 10 TA = 25C 5.5 16 CL = 1 F RL = 10 TA = 25C Turn-Off Delay - ms Turn-On Delay - ms 15 5 4.5 4 14 13 12 11 3.5 3 2.5 10 3 3.5 4 4.5 5 5.5 3 2.5 6 3 VI - Input Voltage - V 5 3.5 4 4.5 VI - Input Voltage - V Figure 12 3.3 f t - Fall Time - ms r t - Rise Time - ms 0.9 3.5 VI(IN) = 5 V CL = 1 F TA = 25C 2.8 2.7 2.6 VI(IN) = 5 V TA = 25C CL = 1 F 3.1 2.9 2.7 0.2 0.3 0.4 0.5 0.6 0.7 IL - Load Current - A 0.8 0.9 2.5 0.1 0.2 Figure 14 10 0.8 FALL TIME vs LOAD CURRENT 3 2.5 0.1 6 Figure 13 RISE TIME vs LOAD CURRENT 2.9 5.5 0.3 0.4 0.5 0.6 0.7 IL - Load Current - A Figure 15 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TPS2041, TPS2051 POWER-DISTRIBUTION SWITCHES SLVS172A -AUGUST 1998 - REVISED APRIL 1999 TYPICAL CHARACTERISTICS SUPPLY CURRENT, OUTPUT ENABLED vs JUNCTION TEMPERATURE SUPPLY CURRENT, OUTPUT DISABLED vs JUNCTION TEMPERATURE 1000 I I(IN) - Supply Current, Output Disabled - nA I I(IN) - Supply Current, Output Enabled - A 100 VI(IN) = 5.5 V VI(IN) = 5 V 90 VI(IN) = 4 V 80 VI(IN) = 2.7 V 70 VI(IN) = 3.3 V 60 50 -50 -25 75 100 125 0 25 50 TJ - Junction Temperature - C 900 700 VI(IN) = 4 V 600 500 VI(IN) = 2.7 V 400 300 200 100 0 -100 -50 150 VI(IN) = 5.5 V VI(IN) = 5 V 800 -25 Figure 16 SUPPLY CURRENT, OUTPUT DISABLED vs INPUT VOLTAGE 1000 - Supply Current, Output Disabled - nA I I(IN) 100 I I(IN) - Supply Current, Output Enabled - A 150 Figure 17 SUPPLY CURRENT, OUTPUT ENABLED vs INPUT VOLTAGE TJ = 125C 90 TJ = 85C 80 TJ = 25C 70 TJ = 0C TJ = -40C 60 50 2.5 100 125 0 25 50 75 TJ - Junction Temperature - C 3 3.5 4 4.5 5 5.5 6 TJ = 125C 800 600 400 200 TJ = 85C TJ = 25C 0 TJ = -40C -200 2.5 3 VI - Input Voltage - V 3.5 4 4.5 5 VI - Input Voltage - V TJ = 0C 5.5 6 Figure 19 Figure 18 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 11 TPS2041, TPS2051 POWER-DISTRIBUTION SWITCHES SLVS172A -AUGUST 1998 - REVISED APRIL 1999 STATIC DRAIN-SOURCE ON-STATE RESISTANCE vs JUNCTION TEMPERATURE 175 IO = 0.5 A VI(IN) = 2.7 V 150 VI(IN) = 3.3 V 125 100 VI(IN) = 4.5 V VI(IN) = 5 V 75 50 -50 -25 0 25 50 100 75 125 150 r DS(on) - Static Drain-Source On-State Resistance - m r DS(on) - Static Drain-Source On-State Resistance - m TYPICAL CHARACTERISTICS STATIC DRAIN-SOURCE ON-STATE RESISTANCE vs INPUT VOLTAGE 175 IO = 0.5 A 150 TJ = 125C 125 TJ = 85C 100 TJ = 25C 75 TJ = 0C TJ = -40C 50 2.5 3 TJ - Junction Temperature - C Figure 20 6 SHORT-CURCUIT OUTPUT CURRENT vs INPUT VOLTAGE 100 0.95 TA = 25C I OS - Short-circuit Output Current - A VI(IN) - VO(OUT) - Input-to-Output Voltage - mV 5.5 Figure 21 INPUT-TO-OUTPUT VOLTAGE vs LOAD CURRENT 75 VI(IN) = 2.7 V VI(IN) = 3.3 V 50 VI(IN) = 5 V 25 VI(IN) = 4.5 V 0 0.1 0.2 0.4 0.5 0.6 TJ = -40C 0.9 TJ = 25C TJ = 125C 0.85 0.8 2.5 3 IL - Load Current - A Figure 22 12 3.5 4 4.5 5 VI - Input Voltage - V 4.5 5 3.5 4 VI - Input Voltage - V Figure 23 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5.5 6 TPS2041, TPS2051 POWER-DISTRIBUTION SWITCHES SLVS172A -AUGUST 1998 - REVISED APRIL 1999 TYPICAL CHARACTERISTICS THRESHOLD TRIP CURRENT vs INPUT VOLTAGE SHORT CIRCUIT OUTPUT CURRENT vs JUNCTION TEMPERATURE 1.2 0.95 I OS - Short-circuit Output Current - A Threshold Trip Current - A TA = 25C Load Ramp = 1 A/10 ms 1.175 1.15 1.125 1.1 2.5 3 4.5 5 3.5 4 VI - Input Voltage - V 5.5 VI(IN) = 5 V 0.9 VI(IN) = 4 V VI(IN) = 2.7 V 0.85 0.8 -50 6 -25 75 100 0 25 50 TJ - Junction Temperature - C Figure 24 Figure 25 UNDERVOLTAGE LOCKOUT vs JUNCTION TEMPERATURE CURRENT LIMIT RESPONSE vs PEAK CURRENT 2.5 500 VI(IN) = 5 V TA = 25C 450 2.4 Current Limit Response - s UVLO - Undervoltage Lockout - V 125 Start Threshold 2.3 Stop Threshold 2.2 2.1 400 350 300 250 200 150 100 50 2 -50 0 -25 100 125 0 25 50 75 TJ - Junction Temperature - C 150 0 2.5 5 7.5 10 12.5 Peak Current - A Figure 26 Figure 27 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 13 TPS2041, TPS2051 POWER-DISTRIBUTION SWITCHES SLVS172A -AUGUST 1998 - REVISED APRIL 1999 TYPICAL CHARACTERISTICS OVERCURRENT RESPONSE TIME (OC) vs PEAK CURRENT 8 VI(IN) = 5 V TA = 25C Response Time - s 6 4 2 0 0 2.5 5 7.5 10 12.5 Peak Current - A Figure 28 APPLICATION INFORMATION TPS2041 Power Supply 2.7 V to 5.5 V 2,3 IN 0.1 F OUT 6,7,8 Load 0.1 F 5 4 22 F OC EN GND 1 Figure 29. Typical Application power-supply considerations A 0.01-F to 0.1-F ceramic bypass capacitor between INx and GND, close to the device, is recommended. Placing a high-value electrolytic capacitor on the output pin(s) is recommended when the output load is heavy. This precaution reduces power-supply transients that may cause ringing on the input. Additionally, bypassing the output with a 0.01-F to 0.1-F ceramic capacitor improves the immunity of the device to short-circuit transients. 14 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TPS2041, TPS2051 POWER-DISTRIBUTION SWITCHES SLVS172A -AUGUST 1998 - REVISED APRIL 1999 APPLICATION INFORMATION overcurrent A sense FET is employed to check for overcurrent conditions. Unlike current-sense resistors, sense FETs do not increase the series resistance of the current path. When an overcurrent condition is detected, the device maintains a constant output current and reduces the output voltage accordingly. Complete shutdown occurs only if the fault is present long enough to activate thermal limiting. Three possible overload conditions can occur. In the first condition, the output has been shorted before the device is enabled or before VI(IN) has been applied (see Figure 6). The TPS2041 and TPS2051 sense the short and immediately switch into a constant-current output. In the second condition, the short occurs while the device is enabled. At the instant the short occurs, very high currents may flow for a short time before the current-limit circuit can react. After the current-limit circuit has tripped (reached the overcurrent trip threshhold) the device switches into constant-current mode. In the third condition, the load has been gradually increased beyond the recommended operating current. The current is permitted to rise until the current-limit threshold is reached or until the thermal limit of the device is exceeded (see Figure 7). The TPS2041 and TPS2051 are capable of delivering current up to the current-limit threshold without damaging the device. Once the threshold has been reached, the device switches into its constant-current mode. OC response The OC open-drain output is asserted (active low) when an overcurrent or overtemperature condition is encountered. The output will remain asserted until the overcurrent or overtemperature condition is removed. Connecting a heavy capacitive load to an enabled device can cause momentary false overcurrent reporting from the inrush current flowing through the device, charging the downstream capacitor. An RC filter of 500 s (see Figure 30) can be connected to the OC pin to reduce false overcurrent reporting. Using low-ESR electrolytic capacitors on the output lowers the inrush current flow through the device during hot-plug events by providing a low-impedance energy source, thereby reducing erroneous overcurrent reporting. TPS2041 TPS2041 GND OUT IN OUT IN OUT EN V+ Rpullup GND OUT IN OUT IN OUT EN OC V+ OC Rpullup Rfilter To USB Controller Cfilter Figure 30. Typical Circuit for OC Pin and RC Filter for Damping Inrush OC Responses POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 15 TPS2041, TPS2051 POWER-DISTRIBUTION SWITCHES SLVS172A -AUGUST 1998 - REVISED APRIL 1999 APPLICATION INFORMATION power dissipation and junction temperature The low on-resistance on the n-channel MOSFET allows small surface-mount packages, such as SOIC, to pass large currents. The thermal resistances of these packages are high compared to those of power packages; it is good design practice to check power dissipation and junction temperature. The first step is to find rDS(on) at the input voltage and operating temperature. As an initial estimate, use the highest operating ambient temperature of interest and read rDS(on) from Figure 21. Next, calculate the power dissipation using: PD + rDS(on) I2 Finally, calculate the junction temperature: TJ Where: + PD R qJA ) TA TA = Ambient Temperature C RJA = Thermal resistance SOIC = 172C/W, PDIP = 106C/W Compare the calculated junction temperature with the initial estimate. If they do not agree within a few degrees, repeat the calculation, using the calculated value as the new estimate. Two or three iterations are generally sufficient to get a reasonable answer. thermal protection Thermal protection prevents damage to the IC when heavy-overload or short-circuit faults are present for extended periods of time. The faults force the TPS2041 and TPS2051 into constant current mode, which causes the voltage across the high-side switch to increase; under short-circuit conditions, the voltage across the switch is equal to the input voltage. The increased dissipation causes the junction temperature to rise to high levels. The protection circuit senses the junction temperature of the switch and shuts it off. Hysteresis is built into the thermal sense circuit, and after the device has cooled approximately 20 degrees, the switch turns back on. The switch continues to cycle in this manner until the load fault or input power is removed. undervoltage lockout (UVLO) An undervoltage lockout ensures that the power switch is in the off state at powerup. Whenever the input voltage falls below approximately 2 V, the power switch will be quickly turned off. This facilitates the design of hot-insertion systems where it is not possible to turn off the power switch before input power is removed. The UVLO will also keep the switch from being turned on until the power supply has reached at least 2 V, even if the switch is enabled. Upon reinsertion, the power switch will be turned on, with a controlled rise time to reduce EMI and voltage overshoots. universal serial bus (USB) applications The universal serial bus (USB) interface is a 12-Mb/s, or 1.5-Mb/s, multiplexed serial bus designed for low-to-medium bandwidth PC peripherals (e.g., keyboards, printers, scanners, and mice). The four-wire USB interface is conceived for dynamic attach-detach (hot plug-unplug) of peripherals. Two lines are provided for differential data, and two lines are provided for 5-V power distribution. USB data is a 3.3-V level signal, but power is distributed at 5 V to allow for voltage drops in cases where power is distributed through more than one hub across long cables. Each function must provide its own regulated 3.3 V from the 5-V input or its own internal power supply. 16 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TPS2041, TPS2051 POWER-DISTRIBUTION SWITCHES SLVS172A -AUGUST 1998 - REVISED APRIL 1999 APPLICATION INFORMATION The USB specification defines the following five classes of devices, each differentiated by power-consumption requirements: D D D D D Hosts/self-powered hubs (SPH) Bus-powered hubs (BPH) Low-power, bus-powered functions High-power, bus-powered functions Self-powered functions Self-powered and bus-powered hubs distribute data and power to downstream functions. The TPS2041 and TPS2051 can provide power-distribution solutions for many of these classes of devices. host/self-powered and bus-powered hubs Hosts and self-powered hubs have a local power supply that powers the embedded functions and the downstream ports (see Figure 31). This power supply must provide from 5.25 V to 4.75 V to the board side of the downstream connection under full-load and no-load conditions. Hosts and SPHs are required to have current limit protection and must report overcurrent conditions to the USB controller. Typical SPHs are desktop PCs, monitors, printers, and stand-alone hubs. Power Supply 3.3 V Downstream USB Ports 5V TPS2041 2, 3 IN 0.1 F USB Control D+ OUT D- 7 0.1 F 5 4 120 F VBUS GND OC EN GND May need RC Filter (see Figure 34) Figure 31. One-Port Solution Bus-powered hubs obtain all power from upstream ports and often contain an embedded function. The hubs are required to power up with less than one unit load. The BPH usually has one embedded function, and power is always available to the controller of the hub. If the embedded function and hub require more than 100 mA on powerup, the power to the embedded function may need to be kept off until enumeration is completed. This can be accomplished by removing power or by shutting off the clock to the embedded function. Power switching the embedded function is not necessary if the aggregate power draw for the function and controller is less than one unit load. The total current drawn by the bus-powered device is the sum of the current to the controller, the embedded function, and the downstream ports, and it is limited to 500 mA from an upstream port. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 17 TPS2041, TPS2051 POWER-DISTRIBUTION SWITCHES SLVS172A -AUGUST 1998 - REVISED APRIL 1999 APPLICATION INFORMATION low-power bus-powered functions and high-power bus-powered functions Both low-power and high-power bus-powered functions obtain all power from upstream ports; low-power functions always draw less than 100 mA; high-power functions must draw less than 100 mA at powerup and can draw up to 500 mA after enumeration. If the load of the function is more than the parallel combination of 44 and 10 F at powerup, the device must implement inrush current limiting (see Figure 32). Power Supply D+ 3.3 V TPS2041 D- VBUS GND 2,3 0.1 F 10 F IN OUT 6, 7, 8 0.1 F 5 USB Control 4 10 F Internal Function OC EN GND 1 Figure 32. High-Power Bus-Powered Function USB power-distribution requirements USB can be implemented in several ways, and, regardless of the type of USB device being developed, several powe- distribution features must be implemented. D D D Hosts/self-powered hubs must: - Current-limit downstream ports - Report overcurrent conditions on USB VBUS Bus-powered hubs must: - Enable/disable power to downstream ports - Power up at <100 mA - Limit inrush current (<44 and 10 F) Functions must: - Limit inrush currents - Power up at <100 mA The feature set of the TPS2041 and TPS2051 allows them to meet each of these requirements. The integrated current-limiting and overcurrent reporting is required by hosts and self-powered hubs. The logic-level enable and controlled rise times meet the need of both input and output ports on bus-power hubs, as well as the input ports for bus-power functions (see Figure 33). 18 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TPS2041, TPS2051 POWER-DISTRIBUTION SWITCHES SLVS172A -AUGUST 1998 - REVISED APRIL 1999 APPLICATION INFORMATION TUSB2040 Hub Controller Upstream Port SN75240 BUSPWR A C B D GANGED D+ D- DP0 DP1 DM0 DM1 Tie to TPS2041 EN Input D+ A C B D GND OC 5V IN DM2 5 V Power Supply EN 5V DM3 TPS76333 4.7 F GND 33 F A C B D 0.1 F SN75240 D+ D- Ferrite Beads GND DP4 IN 3.3 V 4.7 F D- DP3 OUT 1 F Ferrite Beads SN75240 DP2 TPS2041 Downstream Ports VCC DM4 5V TPS2041 GND GND PWRON1 EN OVRCUR1 OC IN 0.1 F 33 F OUT D+ TPS2041 48-MHz Crystal XTAL1 PWRON2 EN OVRCUR2 OC D- IN Ferrite Beads 0.1 F GND OUT Tuning Circuit XTAL2 OCSOFF 5V TPS2041 PWRON3 EN OVRCUR3 OC IN 0.1 F 33 F OUT D+ GND TPS2041 PWRON4 EN OVRCUR4 OC Ferrite Beads IN 0.1 F OUT D- GND 5V 33 F USB rev 1.1 requires 120 F per hub. Figure 33. Hybrid Self/Bus-Powered Hub Implementation POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 19 TPS2041, TPS2051 POWER-DISTRIBUTION SWITCHES SLVS172A -AUGUST 1998 - REVISED APRIL 1999 APPLICATION INFORMATION generic hot-plug applications (see Figure 34) In many applications it may be necessary to remove modules or pc boards while the main unit is still operating. These are considered hot-plug applications. Such implementations require the control of current surges seen by the main power supply and the card being inserted. The most effective way to control these surges is to limit and slowly ramp the current and voltage being applied to the card, similar to the way in which a power supply normally turns on. Due to the controlled rise times and fall times of the TPS2041 and TPS2051, these devices can be used to provide a softer start-up to devices being hot-plugged into a powered system. The UVLO feature of the TPS2041 and TPS2051 also ensures the switch will be off after the card has been removed, and the switch will be off during the next insertion. The UVLO feature guarantees a soft start with a controlled rise time for every insertion of the card or module. PC Board TPS2041 Power Supply 2.7 V to 5.5 V 1000 F Optimum 0.1 F GND OUT IN OUT IN OUT EN Block of Circuitry OC Overcurrent Response Figure 34. Typical Hot-Plug Implementation By placing the TPS2041 and TPS2051 between the VCC input and the rest of the circuitry, the input power will reach these devices first after insertion. The typical rise time of the switch is approximately 2.5 ms, providing a slow voltage ramp at the output of the device. This implementation controls system surge currents and provides a hot-plugging mechanism for any device. 20 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 3-Jun-2011 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) TPS2041D NRND SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart TPS2041DG4 NRND SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart TPS2041DR NRND SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart TPS2041DRG4 NRND SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart TPS2041P NRND PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type Add to cart TPS2041PE4 NRND PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type Add to cart TPS2051D NRND SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart TPS2051DG4 NRND SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart TPS2051DR NRND SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart TPS2051DRG4 NRND SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart TPS2051P NRND PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type Add to cart TPS2051PE4 NRND PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type Add to cart (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 3-Jun-2011 Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 29-Jul-2010 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS2041DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TPS2051DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 29-Jul-2010 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS2041DR SOIC D 8 2500 340.5 338.1 20.6 TPS2051DR SOIC D 8 2500 340.5 338.1 20.6 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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