© KEMET Electronics Corporation • P.O. Box 5928 • Greenville, SC 29606 (864) 963-6300 • www.kemet.com C1020_X7R_KPS_SMD • 5/30/2013 1
One world. One KEMET
Overview
KEMET Power Solutions (KPS) Commercial Series stacked
capacitors utilize a proprietary lead-frame technology to
vertically stack one or two multilayer ceramic chip capacitors
into a single compact surface mount package. The attached
lead-frame mechanically isolates the capacitor/s from the
printed circuit board, therefore offering advanced mechanical
and thermal stress performance. Isolation also addresses
concerns for audible, microphonic noise that may occur when
a bias voltage is applied. A two chip stack offers up to double
the capacitance in the same or smaller design footprint when
compared to traditional surface mount MLCCs devices.
Providing up to 10 mm of board ex capability, KPS Series
capacitors are environmentally friendly and in compliance with
RoHS legislation. Available in X7R dielectric, these devices are
capable of Pb-Free reow proles and provide lower ESR, ESL
and higher ripple current capability when compared to other
dielectric solutions.
Combined with the stability of an X7R dielectric, KEMET’s KPS
Series devices exhibit a predictable change in capacitance
with respect to time and voltage and boast a minimal change in
capacitance with reference to ambient temperature. Capacitance
change is limited to ±15% from -55°C to +125°C.
Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)
KPS Series, X7R Dielectric, 10 – 250 VDC (Commercial Grade)
Ordering Information
C1210 C225 M 4 R 1 C 7186
Ceramic Case Size
(L" x W")
Specication/
Series
Capacitance
Code (pF)
Capacitance
Tolerance1Voltage Dielectric Failure Rate/Design Leadframe
Finish2
Packaging/Grade
(C-Spec)3
1210
1812
2220
C = Standard 2 signicant
digits + number
of zeros
K = ±10%
M = ±20%
8 = 10 V
4 = 16 V
3 = 25 V
5 = 50 V
1 = 100 V
A = 250 V
R = X7R 1 = KPS Single Chip Stack
2 = KPS Double Chip Stack
C = 100%
Matte Sn
7186 = 7" Reel
Unmarked
7289 = 13" Reel
Unmarked
1 Double chip stacks ("2" in the 13th character position of the ordering code) are only available in M (±20%) capacitance tolerance. Single chip stacks ("1" in the
13th character position of the ordering code) are available in K (±10%) or M (±20%) tolerances.
2 Additional leadframe nish options may be available. Contact KEMET for details.
3 Additional reeling or packaging options may be available. Contact KEMET for details.
Benets
• -55°C to +125°C operating temperature range
• Reliable and robust termination system
• EIA 1210, 1812, and 2220 case sizes
• DC voltage ratings of 10 V, 16 V, 25 V, 50 V, 100 V, and 250 V
• Capacitance offerings ranging from 0.1 μF up to 47 μF
• Available capacitance tolerances of ±10% and ±20%
• Higher capacitance in the same footprint
• Potential board space savings
• Advanced protection against thermal and mechanical stress
• Provides up to 10 mm of board ex capability
• Reduces audible, microphonic noise
• Extremely low ESR and ESL
• Pb-Free and RoHS Compliant
• Capable of Pb-Free reow proles
• Non-polar device, minimizing
installation concerns
• Tantalum and electrolytic alternative
© KEMET Electronics Corporation • P.O. Box 5928 • Greenville, SC 29606 (864) 963-6300 • www.kemet.com C1020_X7R_KPS_SMD • 5/30/2013 22
Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)
KPS Series, X7R Dielectric, 10 – 250 VDC (Commercial Grade)
Dimensions – Millimeters (Inches)
Top View Prole View
Single or Double Double Chip Stack Single Chip Stack
Chip Stack
Number
of Chips
EIA Size
Code
Metric Size
Code L Length W Width H Height LW Lead Width Mounting
Technique
Single
1210 3225 3.50 (.138) ±0.30 (.012) 2.60 (.102) ±0.30 (.012) 3.35 (.132) ±0.10 (.004) 0.80 (.032) ±0.15 (.006)
Solder Reow
Only
1812 4532 5.00 (.197) ±0.50 (.020) 3.50 (.138) ±0.50 (.020) 2.65 (.104) ±0.35 (.014) 1.10 (.043) ±0.30 (.012)
2220 5650 6.00 (.236) ±0.50 (.020) 5.00 (.197) ±0.50 (.020) 3.50 (.138) ±0.30 (.012) 1.60 (.063) ±0.30 (.012)
Double
1210 3225 3.50 (.138) ±0.30 (.012) 2.60 (.102) ±0.30 (.012) 6.15 (.242) ±0.15 (.006) 0.80 (.031) ±0.15 (.006)
1812 4532 5.00 (.197) ±0.50 (.020) 3.50 (.138) ±0.50 (.020) 5.00 (.197) ±0.50 (.020) 1.10 (.043) ±0.30 (.012)
2220 5650 6.00 (.236) ±0.50 (.020) 5.00 (.197) ±0.50 (.020) 5.00 (.197) ±0.50 (.020) 1.60 (.063) ±0.30 (.012)
Applications
Typical applications include smoothing circuits, DC/DC converters, power supplies (input/output lters), noise reduction (piezoelectric/
mechanical), circuits with a direct battery or power source connection, critical and safety relevant circuits without (integrated) current
limitation and any application that is subject to high levels of board exure or temperature cycling. Markets include industrial, military,
automotive and telecom.
Qualication/Certication
Commercial Grade products are subject to internal qualication. Details regarding test methods and conditions are referenced in
Table 4, Performance & Reliability.
Environmental Compliance
Pb-Free and RoHS Compliant.
© KEMET Electronics Corporation • P.O. Box 5928 • Greenville, SC 29606 (864) 963-6300 • www.kemet.com C1020_X7R_KPS_SMD • 5/30/2013 33
Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)
KPS Series, X7R Dielectric, 10 – 250 VDC (Commercial Grade)
Electrical Parameters/Characteristics
Item Parameters/Characteristics
Operating Temperature Range -55°C to +125°C
Capacitance Change with Reference to +25°C and 0 VDC Applied (TCC) ±15%
Aging Rate (Maximum % Capacitance Loss/Decade Hour) 3.0%
Dielectric Withstanding Voltage (DWV)
250% of rated voltage
(5 ±1 seconds and charge/discharge not exceeding 50 mA)
Dissipation Factor (DF) Maximum Limit @ 25ºC 5%(10 V), 3.5%(16 V and 25 V) and 2.5%(50 V to 250 V)
Insulation Resistance (IR) Limit @ 25°C
See Insulation Resistance Limit Table
(Rated voltage applied for 120 ±5 seconds @ 25°C)
Regarding aging rate: Capacitance measurements (including tolerance) are indexed to a referee time of 48 or 1,000 hours. Please refer to a part number specic
datasheet for referee time details.
To obtain IR limit, divide MΩ-µF value by the capacitance and compare to GΩ limit. Select the lower of the two limits.
Capacitance and dissipation factor (DF) measured under the following conditions:
1 kHz ±50 Hz and 1.0 ±0.2 Vrms if capacitance ≤ 10 µF
120 Hz ±10 Hz and 0.5 ±0.1 Vrms if capacitance > 10 µF
Note: When measuring capacitance it is important to ensure the set voltage level is held constant. The HP4284 and Agilent E4980 have a feature known as
Automatic Level Control (ALC). The ALC feature should be switched to "ON."
Post Environmental Limits
High Temperature Life, Biased Humidity, Moisture Resistance
Dielectric Rated DC
Voltage
Capacitance
Value
Dissipation Factor
(Maximum %)
Capacitance
Shift
Insulation
Resistance
X7R
> 25
All
3.0
±20% 10% of Initial Limit16/25 5.0
< 16 7.5
Insulation Resistance Limit Table
EIA Case Size
1,000 Megohm
Microfarads or 100 GΩ
500 Megohm
Microfarads or 10 GΩ
1210 < 0.39 µF ≥ 0.39 µF
1812 < 2.2 µF ≥ 2.2 µF
2220 < 10 µF ≥ 10 µF
© KEMET Electronics Corporation • P.O. Box 5928 • Greenville, SC 29606 (864) 963-6300 • www.kemet.com C1020_X7R_KPS_SMD • 5/30/2013 44
Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)
KPS Series, X7R Dielectric, 10 – 250 VDC (Commercial Grade)
Electrical Characteristics
Z and ESR C2220C476M3R2C
Z and ESR C2220C225MAR2C
Z and ESR C1210C475M5R1C
C1210C475M5R1C Z and ESR
Frequency (Hz)
Magnitude Ohms
10
0
2
4
10
6
8
10
-3
-2
-1
10
0
10
1
10
2
10
3
ESR
Z
Frequency (Hz)
Magnitude Ohms
0
2
4
6
8
10
10
-3
-2
-1
0
1
2
3
4
ESR
Z
Frequency (Hz)
Magnitude Ohms
10
0
2
4
6
8
10
10
10
-6
10
-4
10
-2
10
0
10
2
10
4
ESR
Z
© KEMET Electronics Corporation • P.O. Box 5928 • Greenville, SC 29606 (864) 963-6300 • www.kemet.com C1020_X7R_KPS_SMD • 5/30/2013 55
Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)
KPS Series, X7R Dielectric, 10 – 250 VDC (Commercial Grade)
Impedance – 1210, .22 µF, 50 V X7RESR – 1210, .22 µF, 50 V X7R
Impedance – 1812, .10 µF, 50 V X7R
ESR – 1812, .10 µF, 50 V X7R
Electrical Characteristics cont'd
0.01
0.1
1
10
1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 1.E+08
ESR (Ohms)
Frequency (Hz)
ESR vs. Frequency
C1210C224K5R2C (2 Chip Stack)
C1210C224K5R1C (1 Chip Stack)
0.01
0.1
1
10
100
1000
1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 1.E+08
Impedance (Ohms)
Frequency (Hz)
Impedance vs. Frequency
C1210C224K5R2C (2 Chip Stack)
C1210C224K5R1C (1 Chip Stack)
0.01
0.1
1
10
100
1000
10000
1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 1.E+08
Impedance (Ohms)
Frequency (Hz)
Impedance vs. Frequency
C1812C104K5R2C (2 Chip Stack)
C1812C104K5R1C (1 Chip Stack)
0.01
0.1
1
10
1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 1.E+08
ESR (Ohms)
Frequency (Hz)
ESR vs. Frequency
C1812C104K5R2C (2 Chip Stack)
C1812C104K5R1C (1 Chip Stack)
© KEMET Electronics Corporation • P.O. Box 5928 • Greenville, SC 29606 (864) 963-6300 • www.kemet.com C1020_X7R_KPS_SMD • 5/30/2013 66
Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)
KPS Series, X7R Dielectric, 10 – 250 VDC (Commercial Grade)
Ripple Current (Arms) 2220, 22 µF, 50 VMicrophonics – 1210, 4.7 µF, 50 V, X7R
Microphonics – 2220, 47 µF, 25 V, X7R Microphonics – 1210, 22 µF, 25 V, X7R
Microphonics – 2220, 22 µF, 50 V, X7R
Microphonics – 1210, 4.7 µF, 50 V, X7R
0
20
40
60
80
100
120
010 20 30
Absolute Temperature (C)
Ripple Current (Arms)
KEMET KPS, 2220, 22µF, 50V rated (2 Chip Stack)
Competitor 2220, 22µF, 50V rated (2 Chip Stack)
0
10
20
30
40
50
60
0 5 10 15
Sound Pressure (dB)
Vp-p
Competitor
KEMET - KPS
0
10
20
30
40
50
0 2 4 6
Sound Pressure (dB)
Vp-p
Standard SMD MLCC
KPS - 2 Chip Stack
0
10
20
30
40
50
0 5 10 15 20
Sound Pressure (dB)
Vp-p
Standard SMD MLCC
KPS - 2 Chip Stack
0
10
20
30
40
50
0 2 4 6
Sound Pressure (dB)
Vp-p
Standard SMD MLCC
KPS - 2 Chip Stack
0
10
20
30
40
50
60
0 5 10 15
Sound Pressure (dB)
Vp-p
Standard SMD MLCC
KPS - 1 Chip Stack
Note: Refer to Table 4 for test method.
Electrical Characteristics cont'd
Competitive Comparision
© KEMET Electronics Corporation • P.O. Box 5928 • Greenville, SC 29606 (864) 963-6300 • www.kemet.com C1020_X7R_KPS_SMD • 5/30/2013 77
Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)
KPS Series, X7R Dielectric, 10 – 250 VDC (Commercial Grade)
Electrical Characteristics cont'd
Board Flex vs. Termination Type
Board Flex vs. Termination Type
Board Flexure to 10 mmBoard Flexure to 10 mm
101
90
80
70
60
50
40
30
20
10
Percent
2
Weibull
X7R 1812 47uF 16V
Board Flexure (mm)
10.0
9.0
8.0
7. 0
6.0
5
.0
4.0
3.0
2
.0
1
.5
1.0
90
80
70
60
50
40
30
20
10
Percent
2
Weibull
X7R 2220 22uF 25V – (47uF KPS Stacked)
Board Flexure (mm)
Standard Termination
KPS – 2 Chip Stack
10.0
9.0
8.0
7.0
6.0
5.0
4.0
3.0
2.0
1.5
1.0
90
80
70
60
50
40
30
20
10
Percent
2
Weibull
X7R 1210 4.7 uF 50V
Board Flexure (mm)
10.0
9.0
8.0
7.0
6.0
5.0
4.0
3.0
2
.0
1.5
1.0
90
80
70
60
50
40
30
20
10
Percent
2
Weibull
X7R 1210 10 uF – (22uF KPS Stacked)
Board Flexure (mm)
Standard Termination
KPS – 2 Chip Stack
© KEMET Electronics Corporation • P.O. Box 5928 • Greenville, SC 29606 (864) 963-6300 • www.kemet.com C1020_X7R_KPS_SMD • 5/30/2013 88
Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)
KPS Series, X7R Dielectric, 10 – 250 VDC (Commercial Grade)
Table 1 – Capacitance Range/Selection Waterfall (1210 – 2220 Case Sizes)
Capacitance Cap
Code
Series C1210 C1812 C2220
Voltage Code 8 4 3 5 1 A 4 3 5 1 A 4 3 5 1 A
Voltage DC 10 16 25 50 100 250 16 25 50 100 250 16 25 50 100 250
Capacitance Tolerance Product Availability and Chip Thickness Codes
See Table 2 for Chip Thickness Dimensions
Single Chip Stack
0.10 µF 104 K M FV FV FV FV FV FV GP GP GP GP GP JP JP JP JP JP
0.22 µF 224 K M FV FV FV FV FV GP GP GP GP GP JP JP JP JP JP
0.47 µF 474 K M FV FV FV FV FV GP GP GP GP GP JP JP JP JP JP
1.0 µF 105 K M FV FV FV FV FV GP GP GP GP JP JP JP JP JP
2.2 µF 225 K M FV FV FV FV FV GP GP GP JP JP JP JP
3.3 µF 335 K M FV FV FV FV GP GP GP JP JP JP JP
4.7 µF 475 K M FV FV FV FV GP GP GP JP JP JP
10 µF 106 K M FV FV FV GP GP JP JP JP
15 µF 156 K M FV JP JP
22 µF 226 K M FV JP JP
33 µF 336 K M
47 µF 476 K M
100 µF 107 K M
Double Chip Stack
0.10 µF 104 MFW FW FW FW FW FW GR GR GR GR GR JR JR JR JR JR
0.22 µF 224 MFW FW FW FW FW FW GR GR GR GR GR JR JR JR JR JR
0.47 µF 474 MFW FW FW FW FW GR GR GR GR GR JR JR JR JR JR
1.0 µF 105 MFW FW FW FW FW GR GR GR GR GR JR JR JR JR JR
2.2 µF 225 MFW FW FW FW FW GR GR GR GR JR JR JR JR JR
3.3 µF 335 MFW FW FW FW FW GR GR GR GR JR JR JR JR
4.7 µF 475 MFW FW FW FW FW GR GR GR JR JR JR JR
10 µF 106 MFW FW FW FW GR GR GR JR JR JR
22 µF 226 MFW FW FW GR GR JR JR JR
33 µF 336 MFW JR JR
47 µF 476 MFW JR JR
100 µF 107 M
220 µF 227 M
Capacitance Cap
Code
Voltage DC 10 16 25 50 100 250 16 25 50 100 250 16 25 50 100 250
Voltage Code 8 4 3 5 1 A 4 3 5 1 A 4 3 5 1 A
Series C1210 C1812 C2220
These products are protected under US Patent 8,331,078 other patents pending, and any foreign counterparts.
Table 2 – Chip Thickness/Packaging Quantities
Thickness
Code
Case
Size
Thickness ±
Range (mm)
Paper Quantity Plastic Quantity
7" Reel 13" Reel 7" Reel 13" Reel
FV
1210
3.35 ± 0.10
0
0
600
2,000
FW
1210
6.15 ± 0.15
0
0
300
1,000
GP
1812
2.65 ± 0.35
0
0
500
2,000
GR
1812
5.00 ± 0.50
0
0
400
1,700
JP
2220
3.50 ± 0.30
0
0
300
1,300
JR
2220
5.00 ± 0.50
0
0
200
800
Thickness
Code
Case
Size
Thickness ±
Range (mm)
7" Reel 13" Reel 7" Reel 13" Reel
Paper Quantity Plastic Quantity
Package quantity based on nished chip thickness specications.
Roll Over for
Order Info.
© KEMET Electronics Corporation • P.O. Box 5928 • Greenville, SC 29606 (864) 963-6300 • www.kemet.com C1020_X7R_KPS_SMD • 5/30/2013 99
Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)
KPS Series, X7R Dielectric, 10 – 250 VDC (Commercial Grade)
Table 3 – KPS Land Pattern Design Recommendations (mm)
EIA SIZE
CODE
METRIC
SIZE
CODE
Median (Nominal) Land Protrusion
C
Y
X
V1
V2
1210 3225 1.50 1.14 1.75 5.05 3.40
1812 4532 2.20 1.35 2.87 6.70 4.50
2220 5650 2.69 2.08 4.78 7.70 6.00
Soldering Process
KEMET’s KPS Series devices are compatible with IR reow
techniques. Preheating of these components is recommended
to avoid extreme thermal stress. KEMET's recommended prole
conditions for IR reow reect the prole conditions of the
IPC/J–STD–020D standard for moisture sensitivity testing.
To prevent degradation of temperature cycling capability, care
must be taken to prevent solder from owing into the inner side
of the lead frames (inner side of "J" lead in contact with the
circuit board).
After soldering, the capacitors should be air cooled to room
temperature before further processing. Forced air cooling is not
recommended.
Hand soldering should be performed with care due to the
difculty in process control. If performed, care should be taken
to avoid contact of the soldering iron to the capacitor body. The
iron should be used to heat the solder pad, applying solder
between the pad and the lead, until reow occurs. Once reow
occurs, the iron should be removed immediately. (Preheating is
required when hand soldering to avoid thermal shock.)
Prole Feature
SnPb Assembly
Pb-Free Assembly
Preheat/Soak
Temperature Minimum (T
Smin
)100°C 150°C
Temperature Maximum (T
Smax
)150°C 200°C
Time (t
s
) from T
smin
to T
smax
) 60 – 120 seconds 60 – 120 seconds
Ramp-up Rate (T
L
to T
P
)3°C/seconds maximum 3°C/seconds maximum
Liquidous Temperature (T
L
)183°C 217°C
Time Above Liquidous (t
L
) 60 – 150 seconds 60 – 150 seconds
Peak Temperature (T
P
)235°C 250°C
Time within 5°C of Maximum
Peak Temperature (tP)
20 seconds maximum 10 seconds maximum
Ramp-down Rate (T
P
to T
L
)6°C/seconds maximum 6°C/seconds maximum
Time 25°C to Peak Temperature 6 minutes maximum 8 minutes maximum
Note: All temperatures refer to the center of the package, measured on the
package body surface that is facing up during assembly reow.
Time
Temperature
T
smin
25ºC to Peak
t
L
t
S
25
t
P
T
smax
T
L
T
P
Maximum Ramp Up Rate = 3ºC/seconds
Maximum Ramp Down Rate = 6ºC/seconds
© KEMET Electronics Corporation • P.O. Box 5928 • Greenville, SC 29606 (864) 963-6300 • www.kemet.com C1020_X7R_KPS_SMD • 5/30/2013 1010
Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)
KPS Series, X7R Dielectric, 10 – 250 VDC (Commercial Grade)
Table 4 – Performance & Reliability: Test Methods and Conditions
Stress Reference Test or Inspection Method
Terminal Strength JIS–C–6429 Appendix 1, Note: Force of 1.8 kg for 60 seconds.
Board Flex JIS–C–6429 Appendix 2, Note: 5.0 mm minimum
Solderability J–STD–002
Magnication 50 X. Conditions:
a) Method B, 4 hours @ 155°C, dry heat @ 235°C
b) Method B @ 215°C category 3
c) Method D, category 3 @ 250°C
Temperature Cycling JESD22 Method JA–104 1,000 cycles (-55°C to +125°C). Measurement at 24 hours +/- 2 hours after test conclusion.
Biased Humidity MIL–STD–202 Method 103
Load Humidity: 1,000 hours 85°C/85% RH and 200 VDC maximum. Add 100 K ohm resistor.
Measurement at 24 hours +/- 2 hours after test conclusion.
Low Volt Humidity: 1,000 hours 85°C/85% RH and 1.5 V. Add 100 K ohm resistor.
Measurement at 24 hours +/- 2 hours after test conclusion.
Moisture Resistance MIL–STD–202 Method 106
t = 24 hours/cycle. Steps 7a and 7b not required. Unpowered.
Measurement at 24 hours +/- 2 hours after test conclusion.
Thermal Shock MIL–STD–202 Method 107
-55°C/+125°C. Note: Number of cycles required – 300. Maximum transfer time – 20 seconds. Dwell
time – 15 minutes. Air-Air.
High Temperature Life MIL–STD–202 Method 108 1,000 hours at 125°C with rated voltage applied.
Storage Life MIL–STD–202 Method 108 150°C, 0 VDC for 1,000 hours.
Vibration MIL–STD–202 Method 204
5 g's for 20 minutes, 12 cycles each of 3 orientations. Note: Use 8" X 5" PCB .031" thick, 7 secure
points on one long side and 2 secure points at corners of opposite sides. Parts mounted within 2"
from any secure point. Test from 10 – 2,000 Hz.
Mechanical Shock MIL–STD–202 Method 213 Figure 1 of Method 213, Condition F.
Resistance to Solvents MIL–STD–202 Method 215 Add aqueous wash chemical, OKEM Clean or equivalent.
Storage & Handling
Ceramic chip capacitors should be stored in normal working environments. While the chips themselves are quite robust in other
environments, solderability will be degraded by exposure to high temperatures, high humidity, corrosive atmospheres, and long term
storage. In addition, packaging materials will be degraded by high temperature– reels may soften or warp and tape peel force may
increase. KEMET recommends that maximum storage temperature not exceed 40ºC and maximum storage humidity not exceed 70%
relative humidity. Temperature uctuations should be minimized to avoid condensation on the parts and atmospheres should be free of
chlorine and sulfur bearing compounds. For optimized solderability chip stock should be used promptly, preferably within 1.5 years of
receipt.
© KEMET Electronics Corporation • P.O. Box 5928 • Greenville, SC 29606 (864) 963-6300 • www.kemet.com C1020_X7R_KPS_SMD • 5/30/2013 1111
Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)
KPS Series, X7R Dielectric, 10 – 250 VDC (Commercial Grade)
Construction
Reference
Item
Material
ALeadframe Phosphor Bronze – Alloy 510
BLeadframe Attach HMP Solder
C
Termination
Cu
DNi
ESn
FInner Electrode Ni
GDielectric Material BaTiO3
Note: Image is exaggerated in order to clearly identify all components of construction.
HMP = High Melting Point
Product Marking
Laser marking option is not available on:
• C0G, Ultra Stable X8R and Y5V dielectric devices
• EIA 0402 case size devices
• EIA 0603 case size devices with Flexible Termination option.
• KPS Commercial and Automotive grade stacked devices.
These capacitors are supplied unmarked only.
© KEMET Electronics Corporation • P.O. Box 5928 • Greenville, SC 29606 (864) 963-6300 • www.kemet.com C1020_X7R_KPS_SMD • 5/30/2013 1212
Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)
KPS Series, X7R Dielectric, 10 – 250 VDC (Commercial Grade)
Tape & Reel Packaging Information
KEMET offers multilayer ceramic chip capacitors packaged in 8, 12 and 16 mm tape on 7" and 13" reels in accordance with EIA
Standard 481. This packaging system is compatible with all tape-fed automatic pick and place systems. See Table 2 for details on
reeling quantities for commercial chips.
Table 5 – Carrier Tape Con guration – Embossed Plastic (mm)
EIA Case Size Tape Size (W)* Pitch (P
1
)*
01005 – 0402 8 2
0603 – 1210 8 4
1805 – 1808 12 4
≥ 1812 12 8
KPS 1210 12 8
KPS 1812 & 2220 16 12
Array 0508 & 0612 8 4
*Refer to Figure 1 for W and P1 carrier tape reference locations.
*Refer to Table 5 for tolerance speci cations.
© KEMET Electronics Corporation • P.O. Box 5928 • Greenville, SC 29606 (864) 963-6300 • www.kemet.com C1020_X7R_KPS_SMD • 5/30/2013 1313
Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)
KPS Series, X7R Dielectric, 10 – 250 VDC (Commercial Grade)
Figure 1 – Embossed (Plastic) Carrier Tape Dimensions
Po
T
F
W
Center Lines of Cavity
Ao
Bo
User Direction of Unreeling
Cover Tape
Ko
B
1
is for tape feeder reference only,
including draft concentric about B
o.
T
2
ØD
1
ØDo
B
1
S
1
T
1
E
1
E
2
P
1
P
2
Embossment
For cavity size,
see Note 1 Table 4
[10 pitches cumulative
tolerance on tape ± 0.2 mm]
Table 6 – Embossed (Plastic) Carrier Tape Dimensions
Metric will govern
Constant Dimensions — Millimeters (Inches)
Tape Size D0
D
1
Minimum
Note 1
E1P0 P2
R Reference
Note 2
S
1
Minimum
Note 3
T
Maximum
T
1
Maximum
8 mm
1.5 +0.10/-0.0
(0.059 +0.004/-0.0)
1.0
(0.039)
1.75 ±0.10
(0.069 ±0.004)
4.0 ±0.10
(0.157 ±0.004)
2.0 ±0.05
(0.079 ±0.002)
25.0
(0.984)
0.600
(0.024)
0.600
(0.024)
0.100
(0.004)
12 mm 1.5
(0.059)
30
(1.181)
16 mm
Variable Dimensions — Millimeters (Inches)
Tape Size Pitch
B
1
Maximum
Note 4
E
2
Minimum
F P1
T
2
Maximum
W
Maximum
A0,B0 & K0
8 mm Single (4 mm)
4.35
(0.171)
6.25
(0.246)
3.5 ±0.05
(0.138 ±0.002)
4.0 ±0.10
(0.157 ±0.004)
2.5
(0.098)
8.3
(0.327)
Note 512 mm
Single (4 mm) &
Double (8 mm)
8.2
(0.323)
10.25
(0.404)
5.5 ±0.05
(0.217 ±0.002)
8.0 ±0.10
(0.315 ±0.004)
4.6
(0.181)
12.3
(0.484)
16 mm Triple (12 mm)
12.1
(0.476)
14.25
(0.561)
7.5 ± 0.05
(0.138 ± 0.002)
12.0 ± 0.10
(0.157 ± 0.004)
4.6
(0.181)
16.3
(0.642)
1. The embossment hole location shall be measured from the sprocket hole controlling the location of the embossment. Dimensions of embossment location and
hole location shall be applied independent of each other.
2. The tape with or without components shall pass around R without damage (see Figure 5).
3. If S1 < 1.0 mm, there may not be enough area for cover tape to be properly applied (see EIA Standard 481 paragraph 4.3 section b).
4. B1 dimension is a reference dimension for tape feeder clearance only.
5. The cavity de ned by A0, B0 and K0 shall surround the component with suf cient clearance that:
(a) the component does not protrude above the top surface of the carrier tape.
(b) the component can be removed from the cavity in a vertical direction without mechanical restriction, after the top cover tape has been removed.
(c) rotation of the component is limited to 20° maximum for 8 and 12 mm tapes and 10° maximum for 16 mm tapes (see Figure 2).
(d) lateral movement of the component is restricted to 0.5 mm maximum for 8 and 12 mm wide tape and to 1.0 mm maximum for 16 mm tape (see Figure 3).
(e) for KPS Series product, A0 and B0 are measured on a plane 0.3 mm above the bottom of the pocket.
(f) see Addendum in EIA Standard 481 for standards relating to more precise taping requirements.
© KEMET Electronics Corporation • P.O. Box 5928 • Greenville, SC 29606 (864) 963-6300 • www.kemet.com C1020_X7R_KPS_SMD • 5/30/2013 1414
Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)
KPS Series, X7R Dielectric, 10 – 250 VDC (Commercial Grade)
Packaging Information Performance Notes
1. Cover Tape Break Force: 1.0 Kg minimum.
2. Cover Tape Peel Strength: The total peel strength of the cover tape from the carrier tape shall be:
Tape Width Peel Strength
8 mm 0.1 to 1.0 Newton (10 to 100 gf)
12 and 16 mm 0.1 to 1.3 Newton (10 to 130 gf)
The direction of the pull shall be opposite the direction of the carrier tape travel. The pull angle of the carrier tape shall be 165° to 180°
from the plane of the carrier tape. During peeling, the carrier and/or cover tape shall be pulled at a velocity of 300 ±10 mm/minute.
3. Labeling: Bar code labeling (standard or custom) shall be on the side of the reel opposite the sprocket holes. Refer to EIA
Standards 556 and 624.
Figure 2 – Maximum Component Rotation
Ao
Bo
°
T
°
s
Maximum Component Rotation
Top View
Maximum Component Rotation
Side View
Tape Maximum
Width (mm) Rotation (°
T)
8,12 20
16 – 200 10 Tape Maximum
Width (mm) Rotation ( °
S)
8,12 20
16 – 56 10
72 – 200 5
Typical Pocket Centerline
Typical Component Centerline
Figure 3 – Maximum Lateral Movement
0.5 mm maximum
0.5 mm maximum
8 mm & 12 mm Tape
1.0 mm maximum
1.0 mm maximum
16 mm Tape
Figure 4 – Bending Radius
RR
Bending
Radius
Embossed
Carrier
Punched
Carrier
© KEMET Electronics Corporation • P.O. Box 5928 • Greenville, SC 29606 (864) 963-6300 • www.kemet.com C1020_X7R_KPS_SMD • 5/30/2013 1515
Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)
KPS Series, X7R Dielectric, 10 – 250 VDC (Commercial Grade)
Figure 5 – Reel Dimensions
AD(See Note)
Full Radius,
See Note
B(see Note)
Access Hole at
Slot Location
(Ø 40 mm minimum)
If present,
tape slot in core
for tape start:
2.5 mm minimum width x
10.0 mm minimum depth
W3(Includes
flange distortion
at outer edge)
W2(Measured at hub)
W1(Measured at hub)
C
(Arbor hole
diameter)
Note: Drive spokes optional; if used, dimensions B and D shall apply.
N
Table 7 – Reel Dimensions
Metric will govern
Constant Dimensions — Millimeters (Inches)
Tape Size A B Minimum CD Minimum
8 mm 178 ±0.20
(7.008 ±0.008)
or
330 ±0.20
(13.000 ±0.008)
1.5
(0.059)
13.0 +0.5/-0.2
(0.521 +0.02/-0.008)
20.2
(0.795)
12 mm
16 mm
Variable Dimensions — Millimeters (Inches)
Tape Size N Minimum W
1
W
2
Maximum W
3
8 mm
50
(1.969)
8.4 +1.5/-0.0
(0.331 +0.059/-0.0)
14.4
(0.567)
Shall accommodate tape width
without interference
12 mm
12.4 +2.0/-0.0
(0.488 +0.078/-0.0)
18.4
(0.724)
16 mm
16.4 +2.0/-0.0
(0.646 +0.078/-0.0)
22.4
(0.882)
© KEMET Electronics Corporation • P.O. Box 5928 • Greenville, SC 29606 (864) 963-6300 • www.kemet.com C1020_X7R_KPS_SMD • 5/30/2013 1616
Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)
KPS Series, X7R Dielectric, 10 – 250 VDC (Commercial Grade)
Figure 6 – Tape Leader & Trailer Dimensions
Trailer
160 mm Minimum
Carrier Tape
END START
Round Sprocket Holes
Elongated Sprocket Holes
(32 mm tape and wider)
Top Cover Tape
Top Cover Tape
Punched Carrier
8 mm & 12 mm only
Embossed Carrier
Components
100 mm
Minimum Leader
400 mm Minimum
Figure 7 – Maximum Camber
Carrier Tape
Round Sprocket Holes
1 mm Maximum, either direction
Straight Edge
250 mm
Elongated sprocket holes
(32 mm & wider tapes)
© KEMET Electronics Corporation • P.O. Box 5928 • Greenville, SC 29606 (864) 963-6300 • www.kemet.com C1020_X7R_KPS_SMD • 5/30/2013 1717
Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)
KPS Series, X7R Dielectric, 10 – 250 VDC (Commercial Grade)
KEMET Corporation
World Headquarters
2835 KEMET Way
Simpsonville, SC 29681
Mailing Address:
P.O. Box 5928
Greenville, SC 29606
www.kemet.com
Tel: 864-963-6300
Fax: 864-963-6521
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Note: KEMET reserves the right to modify minor details of internal and external construction at any time in the interest of product improvement. KEMET does not
assume any responsibility for infringement that might result from the use of KEMET Capacitors in potential circuit designs. KEMET is a registered trademark of
KEMET Electronics Corporation.
© KEMET Electronics Corporation • P.O. Box 5928 • Greenville, SC 29606 (864) 963-6300 • www.kemet.com C1020_X7R_KPS_SMD • 5/30/2013 1818
Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)
KPS Series, X7R Dielectric, 10 – 250 VDC (Commercial Grade)
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verifying the extent to which the Information contained in this publication is applicable to an order at the time the order is placed.
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Although KEMET designs and manufactures its products to the most stringent quality and safety standards, given the current state of the art, isolated component failures may still
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be required.
© KEMET Electronics Corporation • P.O. Box 5928 • Greenville, SC 29606 (864) 963-6300 • www.kemet.com C1020_X7R_KPS_SMD • 5/30/2013 1919
Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)
KPS Series, X7R Dielectric, 10 – 250 VDC (Commercial Grade)
Digitally signed by Jeannette Calvo
DN: c=US, st=FL, l=Fort Lauderdale, o=KEMET Corp., ou=Marketing
Communications, cn=Jeannette Calvo, email=jeannettecalvo@kemet.com
Date: 2013.06.07 15:57:29 -04'00'