TC74AC74P/F/FT
2014-03-01
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TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC74AC74P, TC74AC74F, TC74AC74FT
Dual D-Type Flip Flop with Preset and Clear
The TC74AC74 is an advanced high speed CMOS D-FLIP
FLOP fabricated with silicon gate and double-layer metal wiring
C2MOS technology.
It achieves the high speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low power
dissipation.
The signal level applied to the D INPUT is transferred to Q
OUTPUT during the positive going transition of the CK pulse.
CLR and PR are independent of the CK and are
accomplished by setting the appropriate input to an “L” level.
All inputs are equipped with protection circuits against static
discharge or transient excess voltage.
Features
High speed: fmax = 200 MHz (typ.) at VCC = 5 V
Low power dissipation: ICC = 4 μA (max) at Ta = 25°C
High noise immunity: VNIH = VNIL = 28% VCC (min)
Symmetrical output impedance: |IOH| = IOL = 24 mA (min)
Capability of driving 50
transmission lines.
Balanced propagation delays: tpLH
tpHL
Wide operating voltage range: VCC (opr) = 2 V to 5.5 V
Pin and function compatible with 74F74
TC74AC74P
TC74AC74F
TC74AC74FT
Weight
DIP14-P-300-2.54 : 0.96 g (typ.)
SOP14-P-300-1.27A : 0.18 g (typ.)
TSSOP14-P-0044-0.65A : 0.06 g (typ.)
Start of commercial production
1986-05
TC74AC74P/F/FT
2014-03-01
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Pin Assignment IEC Logic Symbol
Truth Table
Inputs Outputs
CLR PR D CK Q Q
Function
L H X X L H Clear
H L X X H L Preset
L L X X H H
H H L L H
H H H H L
H H X Qn n
Q No Change
X: Don’t care
System Diagram
Q1
PR1
VCC
CLR2
2D
2CK
PR2
2Q
CLR1
1D
1CK
1Q
Q2
CK
Q
D
Q
CK
Q
D
Q9
8
14
13
12
11
10
1
2
3
4
5
6
7
(top view)
GND
CLR2
CLR1
(12)
(3)
S
(4)
(1)
(2)
(11)
(10)
1CK
PR1
1D
2CK
2D
(5)
(6)
(9)
(8)
1Q
Q1
2Q
Q2
C1
1D
R
(13)
PR2
D
CLR
CK
PR
1/13
4/10
2/12
Q
6/8
Q
5/9
φ
ϕ
3/11 φ
ϕ
φ
ϕ
TC74AC74P/F/FT
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Absolute Maximum Ratings (Note 1)
Characteristics Symbol Rating Unit
Supply voltage range VCC 0.5 to 7.0 V
DC input voltage VIN 0.5 to VCC + 0.5 V
DC output voltage VOUT 0.5 to VCC + 0.5 V
Input diode current IIK ±20 mA
Output diode current IOK ±50 mA
DC output current IOUT ±50 mA
DC VCC/ground current ICC ±100 mA
Power dissipation PD 500 (DIP) (Note 2)/180 (SOP/TSSOP) mW
Storage temperature Tstg 65 to 150 °C
Note 1: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or
even destruction.
Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the
significant change in temperature, etc.) may cause this product to decrease in the reliability significantly
even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute
maximum ratings and the operating ranges.
Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook
(“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test
report and estimated failure rate, etc).
Note 2: 500 mW in the range of Ta = 40°C to 65°C. From Ta = 65°C to 85°C, a derating factor of 10 mW/°C
should be applied up to 300 mW.
Operating Ranges (Note)
Characteristics Symbol Rating Unit
Supply voltage VCC 2.0 to 5.5 V
Input voltage VIN 0 to VCC V
Output voltage VOUT 0 to VCC V
Operating temperature Topr 40 to 85 °C
Input rise and fall time dt/dV 0 to 100 (VCC = 3.3 ± 0.3 V)
0 to 20 (VCC = 5 ± 0.5 V) ns/V
Note: The operating ranges must be maintained to ensure the normal operation of the device.
Unused inputs must be tied to either VCC or GND.
TC74AC74P/F/FT
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Electrical Characteristics
DC Characteristics
Test Condition Ta = 25°C Ta =
40 to 85°C
Characteristics Symbol
VCC
(V) Min Typ. Max Min Max
Unit
High-level input
voltage VIH
2.0
3.0
5.5
1.50
2.10
3.85
1.50
2.10
3.85
V
Low-level input
voltage VIL
2.0
3.0
5.5
0.50
0.90
1.65
0.50
0.90
1.65
V
IOH = 50 μA
2.0
3.0
4.5
1.9
2.9
4.4
2.0
3.0
4.5
1.9
2.9
4.4
High-level output
voltage VOH
VIN
= VIH or
VIL IOH = 4 mA
IOH = 24 mA
IOH = 75 mA (Note)
3.0
4.5
5.5
2.58
3.94
2.48
3.80
3.85
V
IOL = 50 μA
2.0
3.0
4.5
0.0
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
Low-level output
voltage VOL
VIN
= VIH or
VIL IOL = 12 mA
IOL = 24 mA
IOL = 75 mA (Note)
3.0
4.5
5.5
0.36
0.36
0.44
0.44
1.65
V
Input leakage
current IIN VIN = VCC or GND 5.5 ±0.1 ±1.0 μA
Quiescent supply
current ICC VIN = VCC or GND 5.5 4.0 40.0 μA
Note: This spec indicates the capability of driving 50 transmission lines.
One output should be tested at a time for a 10 ms maximum duration.
Timing Requirements (input: tr = tf = 3 ns)
Test Condition Ta =
25°C
Ta =
40 to
85°C
Characteristics Symbol
VCC (V) Limit Limit
Unit
Minimum pulse width
(CK)
tw (L)
tw (H)
3.3 ± 0.3
5.0 ± 0.5
7.0
5.0
7.0
5.0 ns
Minimum pulse width
(CLR , PR ) tw (L) 3.3 ± 0.3
5.0 ± 0.5
7.0
5.0
7.0
5.0 ns
Minimum set-up time ts 3.3 ± 0.3
5.0 ± 0.5
6.0
3.5
6.0
3.5 ns
Minimum hold time th 3.3 ± 0.3
5.0 ± 0.5
1.0
1.0
1.0
1.0 ns
Minimum removal time
(CLR , PR ) trem 3.3 ± 0.3
5.0 ± 0.5
4.0
2.0
4.0
2.0 ns
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AC Characteristics (CL = 50 pF, RL = 500 , input: tr = tf = 3 ns)
Test Condition Ta = 25°C Ta =
40 to 85°C
Characteristics Symbol
V
CC (V) Min Typ. Max Min Max
Unit
Propagation delay
time
(CK-Q, Q)
tpLH
tpHL
3.3 ± 0.3
5.0 ± 0.5
8.2
6.1
13.9
8.7
1.0
1.0
16.0
10.0 ns
Propagation delay
time
(CLR , PR -Q, Q)
tpLH
tpHL
3.3 ± 0.3
5.0 ± 0.5
8.0
5.7
13.1
8.2
1.0
1.0
15.0
9.4 ns
Maximum clock
frequency fmax 3.3 ± 0.3
5.0 ± 0.5
60
100
120
160
60
100
MHz
Input capacitance CIN 5 10 10 pF
Power dissipation
capacitance CPD (Note) 77 pF
Note: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating
current consumption without load.
Average operating current can be obtained by the equation:
ICC (opr) = CPD·VCC·fIN + ICC/2 (per F/F)
TC74AC74P/F/FT
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Package Dimensions
Weight: 0.96 g (typ.)
TC74AC74P/F/FT
2014-03-01
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Package Dimensions
Weight: 0.18 g (typ.)
TC74AC74P/F/FT
2014-03-01
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Package Dimensions
Weight: 0.06 g (typ.)
TC74AC74P/F/FT
2014-03-01
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