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
74F161A, 74F163A
4-bit binary counter
2000 Jun 30
INTEGRATED CIRCUITS
Product specification
Supersedes data of 1996 Jan 29
IC15 Data Handbook
Philips Semiconductors Product specification
74F161A, 74F163A4-bit binary counters
2
2000 Jun 30 853–0347 24024
FEATURES
•Synchronous counting and loading
•Two count enable inputs for n-bit cascading
•Positive edge-triggered clock
•Asynchronous Master Reset (74F161A)
•Synchronous Reset (74F163A)
•High speed synchronous expansion
•Typical count rate of 130MHz
•Industrial range (–40°C to +85°C) available
DESCRIPTION
4-bit binary counters feature an internal carry look-ahead and can be
used for high-speed counting. Synchronous operation is provided by
having all flip-flops clocked simultaneously on the positive-going
edge of the clock. The clock input is buffered.
The outputs of the counters may be preset to High or Low level. A
Low level at the Parallel Enable (PE) input disables the counting
action and causes the data at the D0–D3 inputs to be loaded into
the counter on the positive-going edge of the clock (provided that
the setup and hold requirements for PE are met). Preset takes place
regardless of the levels at Count Enable (CEP, CET) inputs.
A Low level at the Master Reset (MR) input sets all the four outputs
of the flip-flops (Q0 – Q3) in 74F161A to Low levels, regardless of
the levels at CP, PE, CET and CEP inputs (thus providing an
asynchronous clear function). For the 74F163A, the clear function is
synchronous. A Low level at the Synchronous Reset (SR) input sets
all four outputs of the flip-flops (Q0 – Q3) to Low levels after the next
positive-going transition on the clock (CP) input (provided that the
setup and hold time requirements for SR are met). This action
occurs regardless of the levels at PE, CET, and CEP inputs. The
synchronous reset feature enables the designer to modify the
maximum count with only one external NAND gate (see Figure 1).
The carry look-ahead simplifies serial cascading of the counters.
Both Count Enable (CEP and CET) inputs must be High to count.
The CET input is fed forward to enable the TC output. The TC
output thus enabled will produce a High output pulse of a duration
approximately equal to the High level output of Q0. This pulse can
be used to enable the next cascaded stage (see Figure 2). The TC
output is subjected to decoding spikes due to internal race
conditions. Therefore, it is not recommended for use as clock or
asynchronous reset for flip-flops, registers, or counters.
TYPE TYPICAL
fMAX TYPICAL SUPPLY CURRENT
(TOTAL)
74F161A
74F163A 130MHz 46mA
ORDERING INFORMATION
ORDER CODE
DRAWING
DESCRIPTION COMMERCIAL RANGE
VCC = 5V ±10%, Tamb = 0°C to +70°CINDUSTRIAL RANGE
VCC = 5V ±10%, Tamb = –40°C to +85°C
DRAWING
NUMBER
16-pin plastic DIP N74F161AN, N74F163AN I74F161AN, I74F163AN SOT38-4
16-pin plastic SO N74F161AD, N74F163AD I74F161AD, I74F163AD SOT109-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS DESCRIPTION 74F (U.L.) HIGH/LOW LOAD VALUE HIGH/LOW
D0 – D3 Data inputs 1.0/1.0 20µA/0.6mA
CEP Count Enable Parallel input 1.0/1.0 20µA/0.6mA
CET Count Enable T rickle input 1.0/2.0 20µA/1.2mA
CP Clock input (active rising edge) 1.0/1.0 20µA/0.6mA
PE Parallel Enable input (active Low) 1.0/2.0 20µA/1.2mA
MR Asynchronous Master Reset input
(active Low) for 74F161A 1.0/1.0 20µA/0.6mA
SR Synchronous Reset input
(active Low) for 74F163A 1.0/1.0 20µA/0.6mA
TC Terminal count output 50/33 1.0mA/20mA
Q0 – Q3 Flip-flop outputs 50/33 1.0mA/20mA
NOTE:
One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.
Philips Semiconductors Product specification
74F161A, 74F163A4-bit binary counters
2000 Jun 30 3
74F161A PIN CONFIGURATION
16
15
14
13
12
11
107
6
5
4
3
2
1
CEP
VCC
Q2
Q3
CET
Q1
TC
Q0
MR
CP
D3
D0
D1
D2
98GND PE
SF00656
74F163A PIN CONFIGURATION
16
15
14
13
12
11
107
6
5
4
3
2
1
CEP
VCC
Q2
Q3
CET
Q1
TC
Q0
SR
CP
D3
D0
D1
D2
98GND PE
SF00657
74F161A LOGIC SYMBOL
Q0 Q1 Q2 Q3
14 13 12 11VCC = Pin 16
GND = Pin 8
9
7
10
2
PE
CEP
CET
CP
D1 D2
56
SF00658
D3D0
34
1MR
TC 15
74F163A LOGIC SYMBOL
Q0 Q1 Q2 Q3
14 13 12 11VCC = Pin 16
GND = Pin 8
9
7
10
2
PE
CEP
CET
CP
D1 D2
56
SF00659
D3D0
34
1SR
TC 15
74F161A LOGIC SYMBOL (IEEE/IEC)
SF00660
31,2 D
1
9M1
4
5
6
14
13
12
11
15
4 CT=15
7G3
10 G4
2C2 /1,3,4+
RCTR DIV 16
74F163A LOGIC SYMBOL (IEEE/IEC)
SF00661
31,2 D
1
9M1
4
5
6
14
13
12
11
15
4 CT=15
7G3
10 G4
2C2 /1,3,4+
2R CTR DIV 16
Philips Semiconductors Product specification
74F161A, 74F163A4-bit binary counters
2000 Jun 30 4
STATE DIAGRAM
8
7
6
5
4
12 11 10 9
13
14
15
0 1 2 3
SF00664
APPLICATIONS
Q0 Q1 Q2 Q3
CLOCK
PE
CEP
CET
CP
D1 D2
SF00665
D3D0
SR
TC74F163A
+VCC
Figure 1. Maximum count modifying scheme
Terminal count = 6
Q0 Q1 Q2 Q3
PE
CEP
CET
CP
D1 D2
SF00666
D3D0
SR
TC74F163A
Q0 Q1 Q2 Q3
PE
CEP
CET
CP
D1 D2 D3D0
SR
TC74F163A
Q0 Q1 Q2 Q3
PE
CEP
CET
CP
D1 D2 D3D0
SR
TC74F163A
Q0 Q1 Q2 Q3
PE
CEP
CET
CP
D1 D2 D3D0
SR
TC74F163A
Q0 Q1 Q2 Q3
PE
CEP
CET
CP
D1 D2 D3D0
SR
TC74F163A
CP
H H = Enable count
or
L L = Disable count
Figure 2. Synchronous multistage counting scheme
74F161A MODE SELECT – FUNCTION TABLE
INPUTS OUTPUTS
OPERATING MODE
MR CP CEP CET PE Dn Qn TC
OPERATING
MODE
L X X X X X L L Reset (clear)
H↑X X l l L L
Parallel load
H↑X X l h H (1)
Parallel
load
H↑h h h X count (1) Count
H X l X h X qn(1)
Hold (do nothing)
H X X l h X qnL
Hold
(do
nothing)
Philips Semiconductors Product specification
74F161A, 74F163A4-bit binary counters
2000 Jun 30 5
74F163A MODE SELECT – FUNCTION TABLE
INPUTS OUTPUTS
OPERATING MODE
SR CP CEP CET PE Dn Qn TC
OPERATING
MODE
l↑X X X X L L Reset (clear)
h↑X X l l L L
Parallel load
h↑X X l h H (2)
Parallel
load
h↑h h h X count (2) Count
h X l X h X qn(2)
Hold (do nothing)
h X X l h X qnL
Hold
(do
nothing)
H = High voltage level
h = High voltage level one setup prior to the Low-to-High clock transition
L = Low voltage level
l = Low voltage level one setup prior to the Low-to-High clock transition
qn= Lower case letters indicate the state of the referenced output prior to the Low-to-High clock transition
X = Don’t care
↑= Low-to-High clock transition
(1) = The TC output is High when CET is High and the counter is at Terminal Count (HHHH for 74F161A)
(2) = The TC output is High when CET is High and the counter is at Terminal Count (HHHH for 74F163A)
74F161A LOGIC DIAGRAM
R
D
CP
Q
Q
R
D
CP
Q
Q
R
D
CP
Q
Q
R
D
CP
Q
Q14 Q0
13 Q1
12 Q2
11 Q3
15 TC
6
D3
5
D2
4
D1
3
D0
7
CEP
10
CET
9
PE
1
MR
2
CP
SF00662
VCC = Pin 16
GND = Pin 8
Philips Semiconductors Product specification
74F161A, 74F163A4-bit binary counters
2000 Jun 30 6
74F163A LOGIC DIAGRAM
D
CP
Q
Q
D
CP
Q
Q
D
CP
Q
Q
D
CP
Q
Q14 Q0
13 Q1
12 Q2
11 Q3
15 TC
6
D3
5
D2
4
D1
3
D0
7
CEP
10
CET
9
PE
1
SR
2
CP
SF00663
VCC = Pin 16
GND = Pin 8
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limits set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free-air temperature range.)
SYMBOL PARAMETER RATING UNIT
VCC Supply voltage –0.5 to +7.0 V
VIN Input voltage –0.5 to +7.0 V
IIN Input current –30 to +5 mA
VOUT Voltage applied to output in High output state –0.5 to VCC V
IOUT Current applied to output in Low output state 40 mA
T
O
p
erating free air tem
p
erature range
Commercial range 0 to +70 °C
T
amb
Operating
free
-
air
temperat
u
re
range
Industrial range –40 to +85 °C
Tstg Storage temperature range –65 to +150 °C
Philips Semiconductors Product specification
74F161A, 74F163A4-bit binary counters
2000 Jun 30 7
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMITS
UNIT
SYMBOL
PARAMETER
MIN NOM MAX
UNIT
VCC Supply voltage 4.5 5.0 5.5 V
VIH High-level input voltage 2.0 V
VIL Low-level input voltage 0.8 V
IIK Input clamp current –18 mA
IOH High-level output current –1 mA
IOL Low-level output current 20 mA
T
O
p
erating free air tem
p
erature range
Commercial range 0 +70 °C
T
amb
Operating
free
-
air
temperat
u
re
range
Industrial range –40 +85 °C
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL
PARAMETER
TEST CONDITIONS1
LIMITS
UNIT
SYMBOL
PARAMETER
TEST
CONDITIONS1
MIN TYP2MAX
UNIT
VO
High level out
p
ut voltage
V
= MIN, VIL = MAX,
IO= MAX
±10%VCC 2.5 V
V
OH
High
-
le
v
el
o
u
tp
u
t
v
oltage
VIH = MIN
I
OH =
MAX
±5%VCC 2.7 3.4 V
VO
Low level out
p
ut voltage
V
= MIN, VIL = MAX,
IO= MAX
±10%VCC 0.30 0.50 V
V
OL
Lo
w-
le
v
el
o
u
tp
u
t
v
oltage
VIH = MIN
I
OL =
MAX
±5%VCC 0.30 0.50 V
VIK Input clamp voltage VCC = MIN, II = IIK –0.73 –1.2 V
IIInput current at maximum input voltage VCC = MAX, VI = 7.0V 100 µA
IIH High-level input current VCC = MAX, VI = 2.7V 20 µA
I
Low level in
p
ut current
CET, PE
VCC = MAX V =05V
–1.2 mA
I
IL
Lo
w-
le
v
el
inp
u
t
c
u
rrent
others
V
CC =
MAX
,
V
I =
0
.
5V
–0.6 mA
IOS Short-circuit output current3VCC = MAX -60 –150 mA
ICC
Su
pp
ly current (total)
ICCH
VCC = MAX
42 55 mA
I
CC
S
u
ppl
y
c
u
rrent
(total)
ICCL
V
CC =
MAX
49 65 mA
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at VCC = 5V, Tamb = 25°C.
3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, IOS tests should be performed last.
Philips Semiconductors Product specification
74F161A, 74F163A4-bit binary counters
2000 Jun 30 8
AC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL PARAMETER TEST
CONDITION
Tamb = +25°C
VCC = +5.0V
CL = 50pF
RL = 500Ω
Tamb = 0°C to +70°C
VCC = +5.0V ± 10%
CL = 50pF
RL = 500Ω
Tamb = –40°C to +85°C
VCC = +5.0V ± 10%
CL = 50pF
RL = 500ΩUNIT
MIN TYP MAX MIN MAX MIN MAX
fmax Maximum clock frequency Waveform 1 100 130 90 75 MHz
tPLH
tPHL Propagation delay
CP to Qn (PE = High) W aveform 1 2.0
4.0 4.0
6.5 6.5
10.0 2.0
4.0 7.0
11.0 2.0
4.0 7.0
11.0 ns
tPLH
tPHL Propagation delay
CP to Qn (PE = Low) W aveform 1 2.0
3.5 4.5
5.5 6.5
8.5 2.0
3.5 7.5
9.5 2.0
3.5 7.5
9.5 ns
tPLH
tPHL Propagation delay
CP to TC Waveform 1 5.0
4.5 7.5
7.5 10.5
10.5 5.0
4.0 11.5
11.5 5.0
4.0 11.5
11.5 ns
tPLH
tPHL Propagation delay
CET to TC W aveform 2 1.5
2.5 3.5
5.0 6.5
7.5 1.5
2.5 7.0
8.0 1.5
2.5 7.0
8.0 ns
tPHL Propagation delay
MR to Qn ’F161A W aveform 3 6.0 8.5 12.0 5.5 13.0 5.5 13.0 ns
tPHL Propagation delay
MR to TC ’F161A W aveform 3 5.0 8.5 10.0 5.0 11.0 5.0 11.0 ns
AC SETUP REQUIREMENTS
LIMITS
SYMBOL PARAMETER TEST
CONDITION
Tamb = +25°C
VCC = +5.0V
CL = 50pF
RL = 500Ω
Tamb = 0°C to +70°C
VCC = +5.0V ± 10%
CL = 50pF
RL = 500Ω
Tamb = –40°C to +85°C
VCC = +5.0V ± 10%
CL = 50pF
RL = 500ΩUNIT
MIN TYP MIN MIN
ts(H)
ts(L) Setup time, High or Low
Dn to CP W aveform 6 5.0
5.0 5.0
5.0 5.0
5.0 ns
th(H)
th(L) Hold time, High or Low
Dn to CP W aveform 6 0
00
00
0ns
ts(H)
ts(L) Setup time, High or Low
PE or SR to CP Waveform
5 or 6 9.0
6.5 9.5
7.0 9.5
7.0 ns
th(H)
th(L) Hold time, High or Low
PE or SR to CP Waveform
5 or 6 0
00
00
0ns
ts(H)
ts(L) Setup time, High or Low
CET or CEP to CP Waveform 4 10.5
6.0 10.5
7.0 10.5
7.0 ns
th(H)
th(L) Hold time, High or Low
CET or CEP to CP Waveform 4 0
00
00
0ns
tw(H)
tw(L) CP pulse width (Load)
High or Low W aveform 1 4.0
5.0 4.0
5.5 4.0
7.0 ns
tw(H)
tw(L) CP pulse width (Count)
High or Low W aveform 1 4.0
6.0 4.0
7.0 4.0
7.0 ns
tw(L) MR pulse width
Low ’F161A W aveform 3 4.5 4.5 4.5 ns
tREC Recovery time
MR to CP ’F161A W aveform 3 6.0 6.5 6.5 ns
Philips Semiconductors Product specification
74F161A, 74F163A4-bit binary counters
2000 Jun 30 9
AC WAVEFORMS
For all waveforms, VM = 1.5V.
The shaded areas indicate when the input is permitted to change for predictable output performance.
VM
SF00667
VMVM
VMVM
1/fMAX
tw(H) tw(L)
tPLH
tPHL
CP
Qn, TC
W aveform 1. Propagation Delay, Clock Input to Output,
Clock Pulse Width, and Maximum Clock Frequency
VM
SF00668
VMVM
tPLH
CET
TC
VM
tPHL
W aveform 2. Propagation Delay, CET Input to TC Output
SF00669
MR
CP
VMVM
VM
VM
tw(L)
tPHL
tREC
Qn, TC
W aveform 3. Master Reset Pulse Width, Master Reset to
Output Delay, and Master Reset to Recovery Time
SF00670
VMVMVMVM
VMVM
ts(H) ts(L)th(H) th(L)
CEP
CET
CP
W aveform 4. CEP and CET Reset Setup and Hold Times
SF00671
VMVMVMVM
VMVM
ts(L) ts(H)th(L) th(H)
SR
CP
W aveform 5. Synchronous Reset Setup and Hold Times
SF00672
VMVMVMVM
VMVM
ts(L) ts(H)th(L) th(H)
PE
CP
VMVM
Dn
tsth
W aveform 6. Parallel Data and Parallel Enable
Setup and Hold Times
Philips Semiconductors Product specification
74F161A, 74F163A4-bit binary counters
2000 Jun 30 10
TEST CIRCUIT AND WAVEFORMS
tw90%
VM
10%
90%
VM10%
90%
VM10%
90%
VM
10%
NEGATIVE
PULSE
POSITIVE
PULSE
tw
AMP (V)
0V
0V
tTHL (tf )
INPUT PULSE REQUIREMENTS
rep. rate twtTLH tTHL
1MHz 500ns 2.5ns 2.5ns
Input Pulse Definition
VCC
family
74F
D.U.T.
PULSE
GENERATOR
RL
CL
RT
VIN VOUT
Test Circuit for Totem-Pole Outputs
DEFINITIONS:
RL= Load resistor;
see AC ELECTRICAL CHARACTERISTICS for value.
CL= Load capacitance includes jig and probe capacitance;
see AC ELECTRICAL CHARACTERISTICS for value.
RT= Termination resistance should be equal to ZOUT of
pulse generators.
tTHL (tf )
tTLH (tr )
tTLH (tr )AMP (V)
amplitude
3.0V 1.5V
VM
SF00006
Philips Semiconductors Product specification
74F161A, 74F163A
4-bit binary counters
2000 Jun 30 11
DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4
Philips Semiconductors Product specification
74F161A, 74F163A
4-bit binary counters
2000 Jun 30 12
SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
Philips Semiconductors Product specification
74F161A, 74F163A
4-bit binary counters
2000 Jun 30 13
NOTES
Philips Semiconductors Product specification
74F161A, 74F163A4-bit binary counter
yyyy mmm dd 14
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may af fect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Copyright Philips Electronics North America Corporation 2000
All rights reserved. Printed in U.S.A.
Date of release: 06-00
Document order number: 9397-750 07285


Data sheet
status
Objective
specification
Preliminary
specification
Product
specification
Product
status
Development
Qualification
Production
Definition [1]
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make changes at any time without notice in order to
improve design and supply the best possible product.
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
Data sheet status
[1] Please consult the most recently issued datasheet before initiating or completing a design.