ZL60505 Parallel Fiber Optic Transceiver (4 + 4) x 3.125 Gbps Data Sheet July 2009 Ordering Information ZL60505MKDB QSFP Transceiver 0C to +70C Applications Features * High-speed interconnects within and between switches, routers and transport equipment Four independently addressable transmit and receive channels * Server-Server Clusters, Super-computing interconnections Highly compact: saving of 60% on edge and board usage compared to four comparable SFP modules * Proprietary backplanes * * Differential, internally AC-coupled data I/Os * Electrically z-pluggable, allowing port population on demand * * * Interconnects rack-to-rack, shelf-to-shelf, boardto-board, board-to-optical backplane XAUI over fiber-ribbon 2xGbE applications InfiniBand SDR applications * Electrically hot-pluggable * XFP-like latch mechanism for ease-of-insertion * Digital Diagnostics Monitoring Interface. Allows customer management and monitoring of key modules parameters, analogous to SFP * Optical connectivity via industry standard MPO/MTP terminated fiber ribbon * QSFP MSA compatible * * Tx1p 1 Tx1n 2 PIN Array TIA/LA 3 Tx4p 4 Tx4n Rx1p 4 Rx1n VCSEL Array VCSEL Driver Rx4p 3 2 1 Rx4n VCCRx VCCTx VCC1 GND Laser Diode Supervisor Diagnostic Supervisor ModPrsL IntL ModSelL LPMode SCL SDA ResetL Figure 1 - ZL60505 QSFP Parallel Fiber Optic Transceiver 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2009, Zarlink Semiconductor Inc. All Rights Reserved. ZL60505 Data Sheet Description Quad Small Form Factor Pluggable (QSFP) modules are the next generation of pluggable modules intended for high density applications. A QSFP module is a parallel fiber optical transceiver module with four independent optical transmit and receive channels. It combines the higher density attractions of parallel modules with some of the key advantages normally associated with SFP based modules. It is intended for use in switches, routers and data center applications where it provides: * a saving of greater than 60% in edge and board density as compared to the use of four SFP modules. This allows the end-user to shrink system size and lower overall costs. * simplified heat management through reduction in power consumption of > 50% compared to 4xSFP solution. * z-axis electrically hot-pluggability allowing port population on demand and in the field. Utilises XFP-like latching mechanism into board mounted cage. * a digital diagnostic monitoring interface similar to that used by SFP modules. This allows customer access to key module parameters as well as providing alarm and warning flags. This improves customer system management capability. The QSFP also benefits from the existence of a multi-source agreement (MSA) which defines the mechanical formfactor, electrical pin-out and diagnostic management interface. Reliability assurance is based on Telcordia GR-468-CORE and the parts are compliant to the EU directive 2002/95/EC issued 27 January 2003 [RoHS]. 2 Zarlink Semiconductor Inc. Below is a listing of the datums, for various components, referenced to in this document. Datum A B C D E F G H J K L M X&Y Description Host Board top surface Centerline of bezel Distance between Connector terminal thru holes on host board Hard stop on transceiver W idth of transceiver Height of transceiver housing W idth of transceiver pc board Leading edge of signal contact pads on transceiver pc board Top surface of transceiver pc board Host Board thru hole #1 to accept connector guide post Host Board thru hole #2 to accept connector guide post W idth of bezel cut-out Host board horizontal and depth datum established by customers' fiducials Projection Method Package code (c) Zarlink Semiconductor 2007. All rights reserved. ISSUE 1 2 3 ACN 116641 Rev 1 116641 Rev 2 116641 Rev 3 DATE 12-JUL-06 15-MAR-07 20-FEB-09 25-MAR-09 APPRD. Previous package codes Drawing type QSFP Definition of datums 116641 Rev 4 M.Andersson M.Andersson M.Andersson M.Andersson MK Title 116641 DETAIL VIEW B j 0,1 E Label For label contents, see separate drawing. Contact pad numbers 21, 22, 36 and 37 are visible. H 15,5 TYP 2,5 Optical q NOTES:- 2,2 MIN 33,4 in locked position. 35,7 in un-locked position. 13 MIN 7,8 6 0,2 (2x) 1,1 MAX B 16,5 MIN 32 MIN 1. All dimensions in mm. 2. Gen. tol. ISO-2768-mK 1 2 3 4 ACN 116641 Rev 1 116641 Rev 2 116641 Rev 3 116641 Rev 4 DATE 12-JUL-06 15-MAR-07 20-FEB-09 25-MAR-09 APPRD. M.Andersson M.Andersson M.Andersson M.Andersson 4,4 0,2 DETAIL VIEW A Break out view of Latch mechanism. E Flatness tolerance applies for indicated area. Surface thermally conductive. Projection Method Package code (c) Zarlink Semiconductor 2007. All rights reserved. ISSUE F 0,5 MIN A 0,6 0,05 2 0,15 qof E 10,7 2,25 0,1 18,35 0,1 n3 0,1 Thru hole 3,6 MIN Valid for 48,40,2 Label For label contents, see separate drawing. 5,5 MIN j 0,1 F 2 MIN 0,5 0,2 2,3 c 0,075 8,5 0,1 29,6 0,1 3,2 0,1 o1,5 MIN 4,25 0,15 5,2 0,15 48,4 0,2 8 Applies for section that extends outside of cage. 1,1 0,18 D 1,7 0,1 19 MAX (16,4) 13,68 0,1 D Previous package codes MK Drawing type QSFP Transceiver Title 116641 TOP VIEW OF MODULE PCB BOTTOM VIEW OF MODULE PCB H H 1,55 MIN 1,55 MIN 0,9 0,05 0,9 0,05 0,8 MIN 0,4 0,05 0,8 MIN G 38 0,4 0,05 7,4 0,8 (18x) Solder mask keep out area qof G 0,6 0,05 7 0,6 0,05 16,4 0,1 qof G 20 1 1,45 0,1 j 0,2 J G H j 0,2 J G H j 0,1 J G J j 0,1 J G 19x PCB Top surface 1. All dimensions in mm. 2. Contact pad plating: 0,38 m MIN Au over 1,27 m MIN Ni. Projection Method Package code (c) Zarlink Semiconductor 2007. All rights reserved. 1 2 3 4 ACN 116641 Rev 1 116641 Rev 2 116641 Rev 3 116641 Rev 4 DATE 12-JUL-06 15-MAR-07 20-FEB-09 25-MAR-09 APPRD. 19x 0,3 x45~ MIN (2x) NOTES:- ISSUE 7 0,8 (18x) Solder mask keep out area 7,4 19 M.Andersson M.Andersson M.Andersson M.Andersson Previous package codes MK Drawing type Pattern layout for QSFP PCB Title 116641 NOTE:All dimensions in mm. DETAIL VIEW A Host Board Top Surface 0,350,03 A j 0,05 K L qof K & L n1,550,05 38x 2,5 5,18 j 0,05 A X K 37 MAX 11,3 MIN Location of edge of PCB is application specific qof K & L 38 1 10,6 Optional 1 38 16,8 7,2 (17,9) 19 22,15 MIN 20 19 L n1,550,05 1,80,03 j 0,05 A X K j 0,05 K L 1,1 K 19 15,8 Optional 0,4 3,4 12x qof C 0,8 (36x) 19,2 MAX j n0,1 A K L 3,1 7,6 9 (6x) 15,02 MAX n1,050,05 38x 1,69 MAX 20 3,05 MIN 10,3 MAX C Hatched area denotes component and trace keep out (except chassis ground). See detail view A 3,1 7,6 Area denotes component keep out (traces allowed). Projection Method Package code (c) Zarlink Semiconductor 2007. All rights reserved. ISSUE 1 2 3 4 ACN 116641 Rev 1 116641 Rev 2 116641 Rev 3 116641 Rev 4 DATE 12-JUL-06 15-MAR-07 20-FEB-09 25-MAR-09 APPRD. M.Andersson M.Andersson M.Andersson M.Andersson Previous package codes MK Drawing type QSFP Host Mechanical Layout Title 116641 SECTION VIEW A-A 21 0,1; Note 3 0,15 0,1; Note 2 R0,3 MAX (4x each cut-out) 10,15 0,1 B A A 20 0,1 qof K & L A 37 REF 43,8 Tolerance; Note 4 NOTES:1. All dimensions in mm. 2. Not recommended for PCI add-in card application. 3. Calculation of tolerance = 1/2 x Bezel thickness + 0,3 4. Minimum pitch dimension for individual cages. For ganged (1-by-x) applications, the port spacing can be reduced to 19.0 MIN. Projection Method Package code (c) Zarlink Semiconductor 2007. All rights reserved. ISSUE 1 2 3 4 ACN 116641 Rev1 116641 Rev2 116641 Rev3 116641 Rev4 DATE 12-JUL-06 15-MAR-07 20-FEB-09 25-MAR-09 APPRD. M.Andersson M.Andersson M.Andersson M.Andersson Previous package codes MK Drawing type QSFP Recommended Bezel Design Title 116641 For more information about all Zarlink products visit our Web Site at www.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively "Zarlink") is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. 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It is the user's responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink's conditions of sale which are available on request. Purchase of Zarlink's I2C components conveys a license under the Philips I2C Patent rights to use these components in and I2C System, provided that the system conforms to the I2C Standard Specification as defined by Philips. Zarlink, ZL, the Zarlink Semiconductor logo and the Legerity logo and combinations thereof, VoiceEdge, VoicePort, SLAC, ISLIC, ISLAC and VoicePath are trademarks of Zarlink Semiconductor Inc. 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