TL/F/5373
MM54HC4511/MM74HC4511 BCD-to-7 Segment Latch/Decoder/Driver
January 1988
MM54HC4511/MM74HC4511
BCD-to-7 Segment Latch/Decoder/Driver
General Description
This high speed latch/decoder/driver utilizes advanced sili-
con-gate CMOS technology. It has the high noise immunity
and low power consumption of standard CMOS integrated
circuits, as well as the ability to drive 10 LS-TTL loads. The
circuit provides the functions of a 4-bit storage latch, an
8421 BCD-to-seven segment decoder, and an output drive
capability. Lamp test (LT), blanking (Bl), and latch enable
(LE) inputs are used to test the display, to turn-off or pulse
modulate the brightness of the display, and to store a BCD
code, respectively. It can be used with seven-segment light
emitting diodes (LED), incandescent, fluorescent, gas dis-
charge, or liquid crystal readouts either directly or indirectly.
Applications include instrument (e.g., counter, DVM, etc.)
display driver, computer/calculator display driver, cockpit
display driver, and various clock, watch, and timer uses.
The 54HC/74HC logic family is speed, function, and pinout
compatible with the standard 54LS/74LS logic family. All
inputs are protected from damage due to static discharge by
internal diode clamps to VCC and ground.
Features
YLatch storage of input data
YBlanking input
YLamp test input
YLow power consumption characteristics of CMOS
devices
YWide operating voltage range: 2 to 6 volts
YLow input current: 1 mA maximum
YLow quiescent current: 80 mA maximum over full tem-
perature range (74 Series)
Connection Diagram
Dual-In-Line Package
TL/F/5373–1
Order Number MM54HC4511 or MM74HC4511
Truth Table
INPUTS OUTPUTS
LE BI LT D C B A a b c d e f g DISPLAY
x x L xxxxHHHHHHH 8
x L H xxxxLLLLLLL
L H H LLLLHHHHHHL 0
L H H LLLHLHHLLLL 1
L H H LLHLHHLHHLH 2
L H H LLHHHHHHLLH 3
L H H LHL L LHHLLHH 4
L H H LHLHHLHHLHH 5
L H H LHHL L LHHHHH 6
L H H LHHHHHHL L L L 7
L H H HLL LHHHHHHH 8
L H H HLLHHHHLLHH 9
L H H HLHLLLLLLLL
L H H HLHHLLLLLLL
L H H HHLLLLLLLLL
L H H HHLHLLLLLLL
L H H HHHLLLLLLLL
L H H HHHHLLLLLLL
H H H xxxx **
x
e
Don’t care
*eDepends upon the BCD code applied during the 0 to 1 transition of LE.
C1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.
Absolute Maximum Ratings (Notes 1 and 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (VCC)b0.5 to a7.0V
DC Input Voltage (VIN)b1.5 to VCCa1.5V
DC Output Voltage (VOUT)b0.5 to VCCa0.5V
Clamp Diode Current (IIK,I
OK)g20 mA
DC Output Current, per pin (IOUT)g25 mA
DC VCC or GND Current, per pin (ICC)g50 mA
Storage Temperature Range (TSTG)b65§Ctoa
150§C
Power Dissipation (PD)
(Note 3) 600 mW
S.O. Package only 500 mW
Lead Temp. (TL) (Soldering 10 seconds) 260§C
Operating Conditions
Min Max Units
Supply Voltage (VCC)26V
DC Input or Output Voltage 0 VCC V
(VIN,V
OUT)
Operating Temp. Range (TA)
MM74HC b40 a85 §C
MM54HC b55 a125 §C
Input Rise or Fall Times
VCCe2.0V(tr,t
f
) 1000 ns
VCCe4.5V 500 ns
VCCe6.0V 400 ns
DC Electrical Characteristics (Note 4)
TAe25§C74HC 54HC
Symbol Parameter Conditions VCC TAeb40 to 85§CT
A
eb55 to 125§CUnits
Typ Guaranteed Limits
VIH Minimum High Level 2.0V 1.5 1.5 1.5 V
Input Voltage 4.5V 3.15 3.15 3.15 V
6.0V 4.2 4.2 4.2 V
VIL Maximum Low Level 2.0V 0.5 0.5 0.5 V
Input Voltage** 4.5V 1.35 1.35 1.35 V
6.0V 1.8 1.8 1.8 V
VOH Minimum High Level VINeVIH or VIL
Output Voltage
l
IOUT
l
s20 mA 2.0V 2.0 1.9 1.9 1.9 V
4.5V 4.5 4.4 4.4 4.4 V
6.0V 6.0 5.9 5.9 5.9 V
VINeVIH or VIL
l
IOUT
l
s6.0 mA 4.5V 4.2 3.98 3.84 3.7 V
l
IOUT
l
s7.8 mA 6.0V 5.7 5.48 5.34 5.2 V
VOL Maximum Low Level VINeVIH or VIL
Output Voltage
l
IOUT
l
s20 mA 2.0V 0 0.1 0.1 0.1 V
4.5V 0 0.1 0.1 0.1 V
6.0V 0 0.1 0.1 0.1 V
VINeVIH or VIL
l
IOUT
l
s4.0 mA 4.5V 0.2 0.26 0.33 0.4 V
l
IOUT
l
s5.2 mA 6.0V 0.2 0.26 0.33 0.4 V
IIN Maximum Input VINeVCC or GND 6.0V g0.1 g1.0 g1.0 mA
Current
ICC Maximum Quiescent VINeVCC or GND 6.0V 8.0 80 160 mA
Supply Current IOUTe0mA
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating Ð plastic ‘‘N’’ package: b12 mW/§C from 65§Cto85
§
C; ceramic ‘‘J’’ package: b12 mW/§C from 100§Cto125
§
C.
Note 4: For a power supply of 5V g10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when
designing with this supply. Worst case VIH and VIL occur at VCCe5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN,
ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.
**VIL limits are currently tested at 20% of VCC. The above VIL specification (30% of VCC) will be implemented no later than Q1, CY’89.
2
AC Electrical Characteristics VCCe5V, TAe25§C, CLe15 pF, tretfe6ns
Symbol Parameter Conditions Typ Guaranteed Units
Limit
tPHL,t
PLH Maximum Propagation 60 120 ns
Delay from Inputs A thru D to any Output
tPHL,t
PLH Maximum Propagation 60 120 ns
Delay from BI to any Output
tPHL,t
PLH Maximum Propagation 60 120 ns
Delay from LT to any Output
tSMinimum Setup Time 10 20 ns
Inputs A thru D to LE
tHMinimum Hold Time b30 ns
Inputs A thru D to LE
tWMinimum Pulse Width 16 ns
for LE
AC Electrical Characteristics CLe50 pF, tretfe6 ns (unless otherwise specified)
TAe25§C74HC 54HC
Symbol Parameter Conditions VCC TAeb40 to 85§CT
A
eb55 to 125§CUnits
Typ Guaranteed Limits
tPHL,t
PLH Maximum Propagation LEe0V 2.0V 300 600 756 894 ns
Delay from Inputs LTeVCC 4.5V 60 120 151 179 ns
A thru D to any Output BIeVCC 6.0V 51 102 129 152 ns
tPHL,t
PLH Maximum Propagation LTeVCC 2.0V 300 600 756 894 ns
Delay from BI to 4.5V 60 120 151 179 ns
any Output 6.0V 51 102 129 152 ns
tPHL,t
PLH Maximum Propagation BIe0V 2.0V 300 600 756 894 ns
Delay from LT to 4.5V 60 120 151 179 ns
any Output 6.0V 51 102 129 152 ns
tSMinimum Setup Time 2.0V 100 126 149 ns
Inputs A thru D to LE 4.5V 20 25 30 ns
6.0V 17 21 25 ns
tHMinimum Hold Time 2.0V 0 0 0 ns
Inputs A thru D to LE 4.5V 0 0 0 ns
6.0V 0 0 0 ns
tWMinimum Pulse Width 2.0V 80 100 120 ns
for LE 4.5V 16 20 24 ns
6.0V 14 17 20 ns
tr,t
fMaximum Input Rise and 2.0V 1000 1000 1000 ns
Fall Time 4.5V 500 500 500 ns
6.0V 400 400 400 ns
CPD Power Dissipation pF
Capacitance (Note 5)
CIN Maximum Input 5 10 10 10 pF
Capacitance
Note 5: CPD determines the no load dynamic power consumption, PDeCPD VCC2faICC VCC, and the no load dynamic current consumption, ISeCPD VCC faICC.
3
INPUTS
A, B, C, D (Pins 7, 1, 2, 6)ÐBCD data inputs. A (pin 7) is the
least-significant data bit and D (pin 6) is the most significant
bit. Hexadecimal data A– F at these inputs will cause the
outputs to assume a logic low, offering an alternate method
of blanking the display.
OUTPUTS
a–gÐDecoded, buffered outputs. These outputs, unlike the
4511, have CMOS drivers, which will produce typical CMOS
output voltage levels.
CONTROLS
BI (Pin 4)ÐActive-low display blanking input. A logic low on
this input will cause all outputs to be held at a logic low,
thereby blanking the display. LT is the only input that will
override the Bl input.
LT (Pin 3)ÐActive-low lamp test. A low logic level on this
input causes all outputs to assume a logic high. This input
allows the user to test all segments of a display, with a
single control input. This input is independent of all other
inputs.
LE (Pin 5)ÐLatch enable input. This input controls the 4-bit
transparent latch. A logic high on this input latches the data
present at the A, B, C and D inputs; a logic low allows the
data to be transmitted through the latch to the decoder.
Output Characteristics (VCCe5V)
TL/F/5373–2
*The expected minimum curves are not guarantees, but are design aids.
TL/F/5373–3
Typical Applications
TL/F/5373–4
Typical Common Cathode LED Connection
TL/F/5373–5
Incandescent Bulb Driving Circuit
4
Logic Diagram
TL/F/5373–6
Display
TL/F/5373–7
Segment Identification
TL/F/5373–8
5
MM54HC4511/MM74HC4511 BCD-to-7 Segment Latch/Decoder/Driver
Physical Dimensions inches (millimeters)
Dual-In-Line Package
Order Number MM54HC4511J or MM74HC4511J
NS Package J16A
Dual-In-Line Package
Order Number MM74HC4511N
NS Package N16E
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or 2. A critical component is any component of a life
systems which, (a) are intended for surgical implant support device or system whose failure to perform can
into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life
failure to perform, when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can effectiveness.
be reasonably expected to result in a significant injury
to the user.
National Semiconductor National Semiconductor National Semiconductor National Semiconductor
Corporation Europe Hong Kong Ltd. Japan Ltd.
1111 West Bardin Road Fax: (
a
49) 0-180-530 85 86 13th Floor, Straight Block, Tel: 81-043-299-2309
Arlington, TX 76017 Email: cnjwge
@
tevm2.nsc.com Ocean Centre, 5 Canton Rd. Fax: 81-043-299-2408
Tel: 1(800) 272-9959 Deutsch Tel: (
a
49) 0-180-530 85 85 Tsimshatsui, Kowloon
Fax: 1(800) 737-7018 English Tel: (
a
49) 0-180-532 78 32 Hong Kong
Fran3ais Tel: (
a
49) 0-180-532 93 58 Tel: (852) 2737-1600
Italiano Tel: (
a
49) 0-180-534 16 80 Fax: (852) 2736-9960
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
