MF1190-02 CMOS 4-BIT SINGLE CHIP MICROCOMPUTER S1C60N11 Technical Manual S1C60N11 Technical Hardware NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license from the Ministry of International Trade and Industry or other approval from another government agency. (c) SEIKO EPSON CORPORATION 2001 All rights reserved. The information of the product number change Starting April 1, 2001, the product number will be changed as listed below. To order from April 1, 2001 please use the new product number. For further information, please contact Epson sales representative. Configuration of product number Devices S1 C 60N01 F 0A01 00 Packing specification Specification Package (D: die form; F: QFP) Model number Model name (C: microcomputer, digital products) Product classification (S1: semiconductor) Development tools C 60R08 S5U1 D1 1 00 Packing specification Version (1: Version 1 2) Tool type (D1: Development Tool 1) Corresponding model number (60R08: for S1C60R08) Tool classification (C: microcomputer use) Product classification (S5U1: development tool for semiconductor products) 1: For details about tool types, see the tables below. (In some manuals, tool types are represented by one digit.) 2: Actual versions are not written in the manuals. Comparison table between new and previous number S1C60 Family processors Previous No. E0C6001 E0C6002 E0C6003 E0C6004 E0C6005 E0C6006 E0C6007 E0C6008 E0C6009 E0C6011 E0C6013 E0C6014 E0C60R08 New No. S1C60N01 S1C60N02 S1C60N03 S1C60N04 S1C60N05 S1C60N06 S1C60N07 S1C60N08 S1C60N09 S1C60N11 S1C60N13 S1C60140 S1C60R08 S1C62 Family processors Previous No. E0C621A E0C6215 E0C621C E0C6S27 E0C6S37 E0C623A E0C623E E0C6S32 E0C6233 E0C6235 E0C623B E0C6244 E0C624A E0C6S46 New No. S1C621A0 S1C62150 S1C621C0 S1C6S2N7 S1C6S3N7 S1C6N3A0 S1C6N3E0 S1C6S3N2 S1C62N33 S1C62N35 S1C6N3B0 S1C62440 S1C624A0 S1C6S460 Previous No. E0C6247 E0C6248 E0C6S48 E0C624C E0C6251 E0C6256 E0C6292 E0C6262 E0C6266 E0C6274 E0C6281 E0C6282 E0C62M2 E0C62T3 New No. S1C62470 S1C62480 S1C6S480 S1C624C0 S1C62N51 S1C62560 S1C62920 S1C62N62 S1C62660 S1C62740 S1C62N81 S1C62N82 S1C62M20 S1C62T30 Comparison table between new and previous number of development tools Development tools for the S1C60/62 Family Previous No. ASM62 DEV6001 DEV6002 DEV6003 DEV6004 DEV6005 DEV6006 DEV6007 DEV6008 DEV6009 DEV6011 DEV60R08 DEV621A DEV621C DEV623B DEV6244 DEV624A DEV624C DEV6248 DEV6247 New No. S5U1C62000A S5U1C60N01D S5U1C60N02D S5U1C60N03D S5U1C60N04D S5U1C60N05D S5U1C60N06D S5U1C60N07D S5U1C60N08D S5U1C60N09D S5U1C60N11D S5U1C60R08D S5U1C621A0D S5U1C621C0D S5U1C623B0D S5U1C62440D S5U1C624A0D S5U1C624C0D S5U1C62480D S5U1C62470D Previous No. DEV6262 DEV6266 DEV6274 DEV6292 DEV62M2 DEV6233 DEV6235 DEV6251 DEV6256 DEV6281 DEV6282 DEV6S27 DEV6S32 DEV6S37 EVA6008 EVA6011 EVA621AR EVA621C EVA6237 EVA623A New No. S5U1C62620D S5U1C62660D S5U1C62740D S5U1C62920D S5U1C62M20D S5U1C62N33D S5U1C62N35D S5U1C62N51D S5U1C62560D S5U1C62N81D S5U1C62N82D S5U1C6S2N7D S5U1C6S3N2D S5U1C6S3N7D S5U1C60N08E S5U1C60N11E S5U1C621A0E2 S5U1C621C0E S5U1C62N37E S5U1C623A0E Previous No. EVA623B EVA623E EVA6247 EVA6248 EVA6251R EVA6256 EVA6262 EVA6266 EVA6274 EVA6281 EVA6282 EVA62M1 EVA62T3 EVA6S27 EVA6S32R ICE62R KIT6003 KIT6004 KIT6007 New No. S5U1C623B0E S5U1C623E0E S5U1C62470E S5U1C62480E S5U1C62N51E1 S5U1C62N56E S5U1C62620E S5U1C62660E S5U1C62740E S5U1C62N81E S5U1C62N82E S5U1C62M10E S5U1C62T30E S5U1C6S2N7E S5U1C6S3N2E2 S5U1C62000H S5U1C60N03K S5U1C60N04K S5U1C60N07K CONTENTS CONTENTS CHAPTER 1 INTRODUCTION ____________________________________________ 1 1.1 1.2 1.3 1.4 CHAPTER Features ......................................................................................................... 1 Block Diagram .............................................................................................. 2 Pin Layout ..................................................................................................... 3 Pin Description ............................................................................................. 4 2 POWER SUPPLY AND INITIAL RESET ____________________________ 5 2.1 2.2 Power Supply ................................................................................................ 5 Initial Reset ................................................................................................... 6 2.2.1 Power-on reset circuit ................................................................................ 6 2.2.2 Reset terminal (RESET) ............................................................................. 6 2.2.3 Internal register following initialization ................................................... 7 2.3 CHAPTER 3 CPU, ROM, RAM ________________________________________ 8 3.1 3.2 3.3 CHAPTER Test Terminal (TEST) .................................................................................... 7 CPU ............................................................................................................... 8 ROM .............................................................................................................. 8 RAM .............................................................................................................. 8 4 PERIPHERAL CIRCUITS AND OPERATION __________________________ 9 4.1 4.2 Memory Map ................................................................................................. 9 Oscillation Circuit ....................................................................................... 11 4.2.1 CR oscillation circuit ................................................................................ 11 4.2.2 Mask option ............................................................................................... 11 4.2.3 I/O memory for peripheral system clock .................................................. 12 4.3 Input Ports (K00-K03) ................................................................................ 13 4.3.1 Configuration of input port ....................................................................... 13 4.3.2 Interrupt function ...................................................................................... 13 4.3.3 Mask option ............................................................................................... 14 4.3.4 I/O memory of input port .......................................................................... 15 4.3.5 Programming note ..................................................................................... 15 4.4 Output Ports (R00-R03) .............................................................................. 16 4.4.1 Configuration of output port ..................................................................... 16 4.4.2 Mask option ............................................................................................... 16 4.4.3 I/O memory of output port ........................................................................ 18 4.4.4 Programming note ..................................................................................... 19 4.5 I/O Ports (P00-P03, P10-P13) ................................................................... 20 4.5.1 Configuration of I/O port .......................................................................... 20 4.5.2 I/O control register and I/O mode ............................................................ 20 4.5.3 Mask option ............................................................................................... 20 4.5.4 I/O memory of I/O port ............................................................................. 21 4.5.5 Programming notes ................................................................................... 22 4.6 LCD Driver (COM0-COM3, SEG0-SEG37) ............................................. 23 4.6.1 Configuration of LCD driver .................................................................... 23 4.6.2 Switching between dynamic and static drive ............................................ 28 4.6.3 Mask option ............................................................................................... 29 4.6.4 I/O memory of LCD driver ........................................................................ 30 4.6.5 Programming notes ................................................................................... 31 S1C60N11 TECHNICAL MANUAL EPSON i CONTENTS 4.7 Clock Timer .................................................................................................. 32 4.7.1 Configuration of clock timer ..................................................................... 32 4.7.2 Interrupt function ...................................................................................... 32 4.7.3 I/O memory of clock timer ........................................................................ 33 4.7.4 Programming notes ................................................................................... 34 4.8 Interrupt and HALT/SLEEP ........................................................................ 35 4.8.1 Interrupt factors ........................................................................................ 37 4.8.2 Specific masks for interrupt ...................................................................... 37 4.8.3 Interrupt vectors ........................................................................................ 38 4.8.4 I/O memory of interrupt ............................................................................ 38 4.8.5 Programming notes ................................................................................... 39 CHAPTER 5 BASIC EXTERNAL WIRING DIAGRAM ____________________________ 40 CHAPTER 6 ELECTRICAL CHARACTERISTICS ________________________________ 41 6.1 6.2 6.3 6.4 6.5 CHAPTER 7 PACKAGE ________________________________________________ 44 7.1 7.2 CHAPTER ii Plastic Package ............................................................................................ 44 Ceramic Package for Test Samples .............................................................. 45 8 PAD LAYOUT _____________________________________________ 46 8.1 8.2 CHAPTER Absolute Maximum Rating ........................................................................... 41 Recommended Operating Conditions .......................................................... 41 DC Characteristics ...................................................................................... 41 Analog Circuit Characteristics and Current Consumption ........................ 42 Oscillation Characteristics .......................................................................... 43 Pad Layout Diagram .................................................................................... 46 Pad Coordinates ........................................................................................... 46 9 PRECAUTIONS ON MOUNTING _________________________________ 47 EPSON S1C60N11 TECHNICAL MANUAL CHAPTER 1: INTRODUCTION CHAPTER 1 INTRODUCTION The S1C60N11 single-chip microcomputer features an S1C6200B CMOS 4-bit CPU as the core. It contains a 1,536 (words) x 12 (bits) ROM, 144 (words) x 4 (bits) RAM, LCD driver, 4-bit input port (K00-K03), 4-bit output port (R00-R03), 8-bit I/O port (P00-P03, P10-P13) and a timer. 1.1 Features Core CPU ........................................... S1C6200B Built-in oscillation circuit ............. CR oscillation circuit Typ. 65 kHz, 130 kHz, 195 kHz or 260 kHz is selectable by mask option. (C, R built-in) Instruction set .................................. 101 instructions (supports SLEEP mode.) ROM capacity ................................... 1,536 words x 12 bits RAM capacity ................................... 144 words x 4 bits Input port .......................................... 4 bits Pull-down resistors are available by mask option. Output port ....................................... 4 bits Clock and buzzer outputs are selectable by mask option. I/O port .............................................. 8 bits LCD driver ........................................ 38 segments x 4, 3 or 2 commons 1/4, 1/3 or 1/2 duty and 1/3 bias for 4.5 V LCD panel or 1/2 bias for 3 V LCD panel are selectable by mask option. LCD frame frequency (fOSC/2,048 Hz, fOSC/4,096 Hz, fOSC/6,144 Hz or fOSC/8,192 Hz) is selectable by software. Time base counter ........................... 1 system (clock timer) built-in Interrupt ............................................ External: Input port interrupt Internal: Timer interrupt 1 system 1 system Reset input ........................................ Supports differential pulse reset. Supply voltage ................................. 1.2 to 1.8 V Current consumption ..................... During SLEEP: During HALT: Max. 0.3 A Typ. 4 A (65 kHz) (without panel load) Typ. 8 A (130 kHz) Typ. 11 A (195 kHz) Typ. 14 A (260 kHz) During operation: Typ. 8 A (65 kHz) (without panel load) Typ. 15 A (130 kHz) Typ. 20 A (195 kHz) Typ. 26 A (260 kHz) Supply form ..................................... Die form, QFP5-80pin plastic package or QFP14-80pin plastic package S1C60N11 TECHNICAL MANUAL EPSON 1 CHAPTER 1: INTRODUCTION RESET 1.2 Block Diagram ROM 1,536 words x 12 bits OSC fOSC Frequency fCLK System Reset Control Control Core CPU S1C6200B RAM Interrupt Generator 144 words x 4 bits COM0-3 SEG0-37 VDD VL1-VL3 CA, CB VSS K00-K03 LCD Driver Input Port 38 SEG x 4 COM TEST Power Controller Output Port Clock Timer I/O Port R00, R03 (BZ, BZ)1 R01 R02 (FOUT)1 P00-P03 P10-P13 1: Terminal specifications can be selected by mask option. Fig. 1.2.1 S1C60N11 block diagram 2 EPSON S1C60N11 TECHNICAL MANUAL CHAPTER 1: INTRODUCTION 1.3 Pin Layout QFP14-80pin 60 No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 41 40 61 INDEX 21 80 1 20 Name N.C. N.C. SEG19 TEST SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 No. 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Name SEG36 N.C. N.C. SEG37 K03 K02 K01 K00 P13 P12 P11 P10 P03 P02 P01 P00 R02 R01 R00 R03 No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Name No. Name N.C. 61 N.C. N.C. 62 SEG1 VSS 63 SEG2 RESET 64 SEG3 N.C. 65 SEG4 N.C. 66 SEG5 N.C. 67 SEG6 VDD 68 SEG7 VL3 69 SEG8 VL2 70 SEG9 VL1 71 SEG10 CB 72 SEG11 CA 73 SEG12 COM3 74 SEG13 COM2 75 SEG14 COM1 76 SEG15 COM0 77 SEG16 SEG0 78 SEG17 N.C. 79 SEG18 N.C. 80 N.C. N.C. : No Connection No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Name No. Name N.C. 61 N.C. N.C. 62 N.C. SEG1 63 N.C. SEG2 64 SEG19 SEG3 65 TEST SEG4 66 SEG20 SEG5 67 SEG21 SEG6 68 SEG22 SEG7 69 SEG23 SEG8 70 SEG24 SEG9 71 SEG25 SEG10 72 SEG26 SEG11 73 SEG27 SEG12 74 SEG28 SEG13 75 SEG29 SEG14 76 SEG30 SEG15 77 SEG31 SEG16 78 SEG32 SEG17 79 SEG33 SEG18 80 SEG34 N.C. : No Connection Fig. 1.3.1 Pin layout (QFP14-80pin) QFP5-80pin 64 41 40 65 INDEX 25 80 1 24 No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Name SEG35 N.C. N.C. SEG36 SEG37 K03 K02 K01 K00 P13 P12 P11 P10 P03 P02 P01 P00 R02 R01 R00 No. 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Name R03 N.C. N.C. N.C. VSS RESET N.C. N.C. N.C. VDD VL3 VL2 VL1 CB CA COM3 COM2 COM1 COM0 SEG0 Fig. 1.3.2 Pin layout (QFP5-80pin) S1C60N11 TECHNICAL MANUAL EPSON 3 CHAPTER 1: INTRODUCTION 1.4 Pin Description Table 1.4.1 Pin description Pin No. Pin name QFP14 QFP5 48 30 VDD VSS 43 25 VL1-3 51-49 33-31 CA, CB 53, 52 35, 34 K00-03 28-25 9-6 P00-03 36-33 17-14 P10-13 32-29 13-10 R00 39 20 R03 40 21 R01 38 19 R02 37 18 SEG0-37 58, 62-79, 40, 43-60, 3-21, 24 64, 66-80, 1, 4, 5 COM0-3 57-54 39-36 RESET 44 26 TEST 4 65 Can be selected by mask option 4 I/O (I) (I) - - I I/O I/O O O O O O O I I Function Power supply terminal (+) Power supply terminal (-) Power source for LCD Booster capacitor connecting terminal Input port terminal I/O port terminal I/O port terminal Output port terminal (BZ output is selectable *) Output port terminal (BZ output is selectable *) Output port terminal Output port terminal (FOUT output is selectable *) LCD segment output (DC output is selectable *) LCD common output terminal (1/4, 1/3 or 1/2 duty are selectable *) Initial reset input terminal Test input terminal EPSON S1C60N11 TECHNICAL MANUAL CHAPTER 2: POWER SUPPLY AND INITIAL RESET CHAPTER 2 POWER SUPPLY AND INITIAL RESET 2.1 Power Supply With a single external power supply () supplied to VDD through VSS, the S1C60N11 generates the necessary internal voltages (<VL1-VL3> for driving LCD) with the internal power supply circuit. Supply voltage: 1.5 V (1.2 V to 1.8 V) The internal power supply circuit is configured according to the LCD drive voltage specification selected by mask option. Figure 2.1.1 shows the configuration of the power supply circuit. 4.5 V LCD Panel 1/4, 1/3 or 1/2 duty, 1/3 bias 3 V LCD Panel 1/4, 1/3 or 1/2 duty, 1/2 bias VDD VDD VDD VDD VL1=VSS VL1 VL1=VSS VL1 VL2=2VL1 VL2 VL3=3VL1 LCD voltage circuit VL3 C2 0.1F C3 0.1F VL2=VSS VL3=2VL1 CA CB 1.5 V C1 Note: VL1 and VSS are shorted internally. VL3 VSS C2 0.1F CA CB 0.1F VSS VSS VL2 LCD voltage circuit 1.5 V C1 0.1F VSS Note: VL1 and VSS are shorted internally. Fig. 2.1.1 Power supply configuration and external elements Notes: * External loads cannot be driven by the output voltage of the internal power supply circuit. * See Chapter 6, "ELECTRICAL CHARACTERISTICS", for voltage values. S1C60N11 TECHNICAL MANUAL EPSON 5 CHAPTER 2: POWER SUPPLY AND INITIAL RESET 2.2 Initial Reset To initialize the S1C60N11 circuits, an initial reset must be executed. There are two ways of doing this. (1) Initial reset by the power-on reset circuit (2) External initial reset via the RESET terminal Figure 2.2.1 shows the configuration of the initial reset circuit. OSC1 oscillation circuit Power-on reset circuit fOSC (to CPU) Frequency select circuit fCLK Divider Initial reset Reset detection RESET VSS fCLK is selectable from fOSC Hz, fOSC/2 Hz, fOSC/3 Hz or fOSC/4 Hz using the CLKFQ1-CLKFQ0 register. Fig. 2.2.1 Configuration of initial reset circuit 2.2.1 Power-on reset circuit The power-on reset circuit outputs the initial reset signal at power-on until the oscillation circuit starts oscillating. Note: The power-on reset circuit may not work properly due to unstable or lower voltage input. The following initial reset method is recommended to generate the initial reset signal. 2.2.2 Reset terminal (RESET) Initial reset can be executed externally by setting the reset terminal to a high level (VDD). There exists the external reset pulse detect circuit inside of the S1C60N11. When this circuit detects the external reset signal, the internal reset signal turns high at the rising edge of the reset signal detect pulse. After about 10 msec (when fCLK = 65 kHz) has passed, the internal reset signal goes low to canceling the reset even if the external reset signal (RESET) keeps high level. An external reset must keep high level at least 1 msec (when fCLK = 65 kHz). Figure 2.2.2.1 shows the timing waveform of initial reset. Min. 1 msec External reset signal 1 kHz clock Reset detection Internal reset signal Approx. 10 msec Fig. 2.2.2.1 Initial reset timing waveform 6 EPSON S1C60N11 TECHNICAL MANUAL CHAPTER 2: POWER SUPPLY AND INITIAL RESET 2.2.3 Internal register following initialization An initial reset initializes the CPU as shown in the table below. Table 2.2.3.1 Initial values CPU Core Name Symbol Bit size Program counter step PCS 8 Program counter page PCP 4 New page pointer NPP 4 Stack pointer SP 8 Index register X X 8 Index register Y Y 8 Register pointer RP 4 General-purpose register A A 4 General-purpose register B B 4 Interrupt flag I 1 Decimal flag D 1 Zero flag Z 1 Carry flag C 1 Initial value 00H 1H 1H Undefined Undefined Undefined Undefined Undefined Undefined 0 0 Undefined Undefined Peripheral Circuits Bit size Initial value RAM 4 Undefined Display memory 4 Undefined Other peripheral circuits 4 See Section 4.1, "Memory Map". Name 2.3 Test Terminal (TEST) This terminal is used when IC is inspected for shipment. During normal operation connect it to VSS or leave it open. S1C60N11 TECHNICAL MANUAL EPSON 7 CHAPTER 3: CPU, ROM, RAM CHAPTER 3 CPU, ROM, RAM 3.1 CPU The S1C60N11 employs the S1C6200B core CPU, so that register configuration, instructions, and so forth are virtually identical to those in other processors in the family using the S1C6200/6200A/6200B. Refer to the "S1C6200/6200A Core CPU Manual" for details of the S1C6200B. Note the following points with regard to the S1C60N11: (1) Since the S1C60N11 provides the SLEEP function, the SLP instruction can be used. (2) Because the ROM capacity is 1,536 words, 12 bits per word, bank bits are unnecessary, and PCB and NBP are not used. (3) The RAM page is set to 0 only, so the page part (XP, YP) of the index register that specifies addresses is invalid. PUSH XP POP XP LD XP,r LD r,XP PUSH YP POP YP LD YP,r LD r,YP 3.2 ROM The built-in ROM, a mask ROM for the program, has a capacity of 1,536 x 12-bit steps. The program area is 6 pages (0-5), each consisting of 256 steps (00H-FFH). After an initial reset, the program start address is set to page 1, step 00H. The interrupt vectors are allocated to page l, steps 01H-0FH. Bank 0 Step 00H Page 0 Step 01H Interrupt vector area Page 1 Page 2 Page 3 Program start address Step 0FH Step 10H Page 4 Program area Page 5 Step FFH 12 bits Fig. 3.2.1 ROM configuration 3.3 RAM The RAM, a data memory for storing a variety of data, has a capacity of 144 words, 4-bit words. When programming, keep the following points in mind: (1) Part of the data memory is used as stack area when saving subroutine return addresses and registers, so be careful not to overlap the data area and stack area. (2) Subroutine calls and interrupts take up three words on the stack. (3) Data memory 000H-00FH is the memory area pointed by the register pointer (RP). 8 EPSON S1C60N11 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map) CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Peripheral circuits (timer, I/O, and so on) of the S1C60N11 are memory mapped. Thus, all the peripheral circuits can be controlled by using memory operations to access the I/O memory. The following sections describe how the peripheral circuits operate. 4.1 Memory Map The data memory of the S1C60N11 has an address space of 205 words, of which 48 words are allocated to display memory and 13 words, to I/O memory. Figure 4.1.1 show the overall memory map for the S1C60N11, and Table 4.1.1, the memory maps for the peripheral circuits (I/O space). Address Page Low High 0 0 1 2 3 4 5 6 7 8 9 A B C D E F M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF 1 2 3 RAM area 112 words x 4 bits (R/W) 4 5 6 0 I/O memory 7 8 See Table 4.1.1 RAM area 32 words x 4 bits (R/W) 9 A B Unused area C D E F I/O memory See Table 4.1.1 Fig. 4.1.1 Memory map Address Page Low High 4 or C 0 5 or D 6 or E 0 1 2 3 4 5 6 7 8 9 A B C D E F Display memory 48 words x 4 bits 40H-6FH = R/W C0H-EFH = W only Fig. 4.1.2 Display memory map Notes: * The display memory area can be selected from between 40H-6FH and C0H-EFH by mask option. When 40H-6FH is selected, the display memory is assigned in the RAM area. So read/write operation is allowed. When C0H-EFH is selected, the display memory is assigned as a write-only memory. * Memory is not mounted in unused area within the memory map and in memory area not indicated in this chapter. For this reason, normal operation cannot be assured for programs that have been prepared with access to these areas. S1C60N11 TECHNICAL MANUAL EPSON 9 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map) Table 4.1.1 I/O memory map Address Register D3 D2 D1 TM3 TM2 TM1 070H R K03 K02 K01 073H R EIK03 EIK02 EIK01 075H R/W CSDC EIT2 EIT8 078H R/W 0 IT2 IT8 079H R 0 IK0 0 07AH R R03 R02 R01 07CH R/W P03 P02 P01 07DH R/W TMRST 0 0 07EH W R BZFQ 0 0 0F6H R/W R P13 P12 P11 0FDH R/W 0 0 0 0FEH R CLKFQ1 CLKFQ0 0 R/W R 0FFH 1 Initial value at initial reset 2 Not set in the circuit 3 Always "0" being read 10 D0 Name TM3 TM0 TM2 TM1 TM0 K03 K00 K02 K01 K00 EIK03 EIK00 EIK02 EIK01 EIK00 CSDC EIT32 EIT2 EIT8 EIT32 0 3 IT32 IT2 4 IT8 4 IT32 4 0 3 0 IK0 4 0 3 0 3 R03 R00 R02 R01 R00 P03 P00 P02 P01 P00 TMRST IOC0 0 3 0 3 R/W IOC0 BZFQ 0 0 3 0 3 0 3 P13 P10 P12 P11 P10 0 3 IOC1 0 3 0 3 R/W IOC1 CLKFQ1 LCDON CLKFQ0 0 3 R/W LCDON 4 5 Comment 1 0 Init 1 Clock timer data (2 Hz) 0 Clock timer data (4 Hz) 0 When fCLK = 65,536 Hz Clock timer data (8 Hz) 0 Clock timer data (16 Hz) 0 Low - 2 High - 2 High Low Input port data (K00-K03) - 2 High Low - 2 High Low 0 Enable Mask 0 Enable Mask Interrupt mask register (K00-K03) 0 Enable Mask 0 Enable Mask 0 Static Dynamic LCD drive switch 0 Enable Mask Interrupt mask register (clock timer 2 Hz) When fCLK 0 Enable Mask Interrupt mask register (clock timer 8 Hz) = 65,536 Hz 0 Enable Mask Interrupt mask register (clock timer 32 Hz) - 2 Unused - - 0 Interrupt factor flag (clock timer 2 Hz) Yes No When fCLK 0 Interrupt factor flag (clock timer 8 Hz) Yes No = 65,536 Hz 0 Interrupt factor flag (clock timer 32 Hz) Yes No - 2 - Unused - 0 Yes Interrupt factor flag (K00-K03) No - 2 - Unused - - 2 - Unused - 0 High Low Output port (R03, BZ) 0 High Low Output port (R02, FOUT) 0 High Low Output port (R01) 0 High Low Output port (R00, BZ) - 2 High Low - 2 High I/O port data (P00-P03) Low - 2 High Output latch is reset at initial reset Low - 2 High Low Clock timer reset Reset Reset - Unused - 2 - - - 2 Unused - - 0 Output Input I/O control register 0 (P00-P03) 0 fCLK/32 fCLK/16 Buzzer frequency selection 5 Unused - 2 - - - 2 Unused - - - 2 Unused - - - 2 High Low - 2 High I/O port data (P10-P13) Low - 2 High Output latch is reset at initial reset Low - 2 High Low Unused - 2 - - - 2 Unused - - - 2 Unused - - 0 Output Input I/O control register 1 (P10-P13) Peripheral system [CLKFQ1, 0]: 00 0 10 11 01 fCLK: fOSC fOSC/2 fOSC/3 fOSC/4 clock selection 0 - - Unused - 2 1 On Off LCD display On/Off conrol Reset (0) immediately after being read fCLK is selectable from fOSC, fOSC/2, fOSC/3 and fOSC/4 using the CLKFQ1-CLKFQ0 register. EPSON S1C60N11 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit) 4.2 Oscillation Circuit The S1C60N11 has a built-in CR oscillation circuit that generates the operating clock of the CPU and the peripheral circuit. 4.2.1 CR oscillation circuit The CR oscillation circuit has a built-in capacitor and resistors, and an oscillation frequency can be selected by mask option. The S1C60N11 has a frequency divider circuit controlled by the CLKFQ1 and CLKFQ0 registers. These registers control the peripheral clock frequency fCLK. The CPU operate with the fOSC clock generated by the oscillation circuit. Figure 4.2.1.1 shows the configuration of the CR oscillation circuit. fOSC RCR To CPU System clock fCLK select circuit CCR To peripheral circuits CLKFQ1 CLKFQ0 Mask option Fig. 4.2.1.1 Configuration of CR oscillation circuit As Figure 4.2.1.1 indicates, the CR oscillation circuit can be configured using the built-in resistor RCR with different frequency selected by mask option. 4.2.2 Mask option The mask option allows selection of an oscillation frequency using the built-in resistor. The following shows the alternatives of the mask option. Table 4.2.2.1 Mask option for CR oscillation circuit No. 1 2 3 4 S1C60N11 TECHNICAL MANUAL Clock frequency fOSC = 65 kHz fOSC = 130 kHz fOSC = 195 kHz fOSC = 260 kHz EPSON 11 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit) 4.2.3 I/O memory for peripheral system clock Table 4.2.3.1 lists the peripheral system clock control bits and their address. Table 4.2.3.1 Peripheral system clock control bits Address Register D3 D2 D1 CLKFQ1 CLKFQ0 0 R/W R 0FFH 1 Initial value at initial reset 2 Not set in the circuit Comment Name Init 1 1 0 CLKFQ1 Peripheral system [CLKFQ1, 0]: 00 0 01 10 11 LCDON fOSC fOSC/2 fOSC/3 fOSC/4 fCLK: CLKFQ0 clock selection 0 - - 0 3 Unused - 2 R/W LCDON 1 On Off LCD display On/Off conrol 3 Always "0" being read 4 Reset (0) immediately after being read D0 CLKFQ1, CLKFQ0: Peripheral system clock select registers (0FFH*D3, D2) Select an operating clock frequency fCLK for the peripheral system. This selection affects the LCD frame frequency, timer data output, power-on reset time and differential pulse reset time. Table 4.2.3.2 Selecting pheripheral system clock CLKFQ1 CLKFQ0 0 0 1 1 0 1 0 1 LCD frame frequency 1/4, 1/2 duty fOSC fOSC/2048 32 Hz when fOSC = 65 kHz fOSC/2 fOSC/(2x2048) 32 Hz when fOSC = 130 kHz fOSC/3 fOSC/(3x2048) 32 Hz when fOSC = 195 kHz fOSC/4 fOSC/(4x2048) 32 Hz when fOSC = 260 kHz fCLK 1/3 duty 42.7 Hz 42.7 Hz 42.7 Hz 42.7 Hz After an initial reset, these registers are set to "0". 12 EPSON S1C60N11 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports) 4.3 Input Ports (K00-K03) 4.3.1 Configuration of input port The S1C60N11 has a 4-bit general-purpose input port. Each of the input port terminals (K00-K03) has an internal pull-down resistor. The pull-down resistor can be selected for each bit with the mask option. Figure 4.3.1.1 shows the configuration of input port. VDD Data bus Interrupt request Kxx Address VSS Mask option Fig. 4.3.1.1 Configuration of input port Selecting "pull-down resistor enabled" with the mask option allows input from a push button, key matrix, and so forth. When "pull-down resistor disabled" is selected, the port can be used for slide switch input and interfacing with other LSIs. 4.3.2 Interrupt function All four input port bits (K00-K03) provide the interrupt function. The conditions for issuing an interrupt can be set by the software for the four bits. Also, whether to mask the interrupt function can be selected individually for all four bits by the software. Figure 4.3.2.1 shows the configuration of K00-K03. Data bus Kxx Noise rejector Address Interrupt factor flag (IK0) Interrupt request Address Interrupt mask register (EIK) Mask option (K00-K03) Address Fig. 4.3.2.1 Input interrupt circuit configuration (K00-K03) The interrupt mask registers (EIK00-EIK03) enable the interrupt mask to be selected individually for K00-K03. An interrupt occurs when the input value which are not masked change and the interrupt factor flag (IK0) is set to "1". S1C60N11 TECHNICAL MANUAL EPSON 13 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports) Input interrupt programming related precautions Port K input Active status Mask register Factor flag set Not set When the content of the mask register is rewritten, while the port K input is in the active status. The input interrupt factor flag is set at . Fig. 4.3.2.2 Input interrupt timing When using an input interrupt, if you rewrite the content of the mask register, when the value of the input terminal which becomes the interrupt input is in the active status (input terminal = high status), the factor flag for input interrupt may be set. For example, a factor flag is set with the timing of shown in Figure 4.3.2.2. However, when clearing the content of the mask register with the input terminal kept in the high status and then setting it, the factor flag of the input interrupt is again set at the timing that has been set. Consequently, when the input terminal is in the active status (high status), do not rewrite the mask register (clearing, then setting the mask register), so that a factor flag will only set at the rising edge in this case. When clearing, then setting the mask register, set the mask register, when the input terminal is not in the active status (low status). 4.3.3 Mask option The contents that can be selected with the input port mask option are as follows: (1) An internal pull-down resistor can be selected for each of the four bits of the input ports (K00-K03). Having selected "pull-down resistor disabled", take care that the input does not float. Select "pulldown resistor enabled" for input ports that are not being used. (2) The input interrupt circuit contains a noise rejection circuit to prevent interrupts form occurring through noise. The mask option enables selection of the noise rejection circuit. When "use" is selected, a maximum delay of 0.5 msec (fCLK = 65 kHz) occurs from the time an interrupt condition is established until the interrupt factor flag (IK0) is set to "1". 14 EPSON S1C60N11 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports) 4.3.4 I/O memory of input port Table 4.3.4.1 list the input port control bits and their addresses. Table 4.3.4.1 Input port control bits Address Register D3 D2 D1 D0 K03 K02 K01 K00 EIK01 EIK00 073H R EIK03 EIK02 075H R/W 0 IK0 0 0 07AH R Name K03 K02 K01 K00 EIK03 EIK02 EIK01 EIK00 0 3 IK0 4 0 3 0 3 1 Initial value at initial reset 2 Not set in the circuit Comment Init 1 1 0 Low - 2 High - 2 High Low Input port data (K00-K03) - 2 High Low 2 - High Low 0 Enable Mask 0 Enable Mask Interrupt mask register (K00-K03) 0 Enable Mask 0 Enable Mask - 2 - Unused - 0 Yes Interrupt factor flag (K00-K03) No - 2 - Unused - - 2 - Unused - 3 Always "0" being read 4 Reset (0) immediately after being read K00-K03: Input port data (073H) The input data of the input port terminals can be read with these registers. When "1" is read: High level When "0" is read: Low level Writing: Invalid The value read is "1" when the terminal voltage of the input port (K00-K03) goes high (VDD), and "0" when the voltage goes low (VSS). These are read only bits, so writing cannot be done. EIK00-EIK03: Interrupt mask registers (075H) Masking the interrupt of the input port terminals can be done with these registers. When "1" is written: Enable When "0" is written: Mask Reading: Valid With these registers, masking of the input port bits can be done for each of the four bits. After an initial reset, these registers are all set to "0". IK0: Interrupt factor flag (07AH*D2) This flag indicates the occurrence of an input interrupt. When "1" is read: Interrupt has occurred When "0" is read: Interrupt has not occurred Writing: Invalid The interrupt factor flag IK0 is associated with K00-K03. From the status of this flag, the software can decide whether an input interrupt has occurred. This flag is reset when the software has read it. Reading of interrupt factor flag is available at EI, but be careful in the following cases. If the interrupt mask register value corresponding to the interrupt factor flag to be read is set to "1", an interrupt request will be generated by the interrupt factor flag set timing, or an interrupt request will not be generated. After an initial reset, this flag is set to "0". 4.3.5 Programming note When modifying the input port from high level to low level with pull-down resistor, a delay will occur at the fall of the waveform due to time constant of the pull-down resistor and input gate capacities. Provide appropriate waiting time in the program when performing input port reading. S1C60N11 TECHNICAL MANUAL EPSON 15 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports) 4.4 Output Ports (R00-R03) 4.4.1 Configuration of output port The S1C60N11 has a 4-bit general output port (R00-R03). Output specification of the output port can be selected in a bit units with the mask option. Two kinds of output specifications are available: complementary output and Pch open drain output. Also, the mask option enables the output ports R00, R02 and R03 to be used as special output ports. Figure 4.4.1.1 shows the configuration of the output port. Data bus VDD Register Rxx Complementary Pch open drain Address VSS Mask option Fig. 4.4.1.1 Configuration of output port 4.4.2 Mask option The mask option enables the following output port selection. (1) Output specification of output port The output specifications for the output port (R00-R03) may be set to either complementary output or Pch open drain output for each of the four bits. However, even when Pch open drain output is selected, a voltage exceeding the source voltage must not be applied to the output port. (2) Special output In addition to the regular DC output, special output can be selected for output ports R00, R02 and R03, as shown in Table 4.4.2.1. Figure 4.4.2.1 shows the structure of output ports R00-R03. Table 4.4.2.1 Special output 16 Output port Special output R00 R03 R02 BZ output BZ output FOUT output EPSON S1C60N11 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports) BZ R00 Register R00 R03 Data bus Register R03 Register R01 R01 FOUT R02 Register R02 Address 07CH Mask option Fig. 4.4.2.1 Structure of output ports R00-R03 BZ, BZ (R00, R03) The output ports R00 and R03 may be set to BZ output and BZ output (BZ reverse output), respectively, allowing for direct driving of the piezo-electric buzzer. The BZ output is controlled by the R00 register. For the BZ output, the R00 register or the R03 register can be selected as the control register by mask option. When the R00 register is selected, the BZ and BZ outputs are controlled by the R00 register simultaneously. The frequency of buzzer output may be selected by software to be either 2 kHz or 4 kHz (when fCLK = 65 kHz). Figure 4.4.2.2 shows the output waveform. R00(R03) register "0" "1" "0" BZ output (R00 terminal) BZ output (R03 terminal) Fig. 4.4.2.2 Output waveform of BZ and BZ Notes: * A hazard may occur when the buzzer signal is turned on or off. * When the R00 port is set for DC output, the R03 port cannot be set for the BZ output. FOUT (R02) When the output port R02 is set as the FOUT output port, the R02 will output the fCLK (peripheral system clock frequency) clock or the clock that is generated by dividing the fCLK clock. The clock frequency can be selected from among 8 types by mask option. The types of frequency which can be selected are shown in Table 4.4.2.2. Table 4.4.2.2 FOUT clock frequency Setting value Clock frequency (Hz)* fCLK/2 32,768 fCLK/4 16,384 8,192 fCLK/8 4,096 fCLK/16 fCLK/32 2,048 fCLK/64 1,024 fCLK/128 512 256 fCLK/256 * When 65 kHz peripheral clock is selected S1C60N11 TECHNICAL MANUAL EPSON 17 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports) The FOUT output is controlled by the R02 register. Figure 4.4.2.3 shows the output waveform. R02 register "0" "1" "0" FOUT output (R02 terminal) Fig. 4.4.2.3 Output waveform of FOUT Note: A hazard may occur when the FOUT signal is turned on or off. 4.4.3 I/O memory of output port Table 4.4.3.1 lists the output port control bits and their addresses. Table 4.4.3.1 Control bits of output port Address Register D3 D2 D1 D0 R03 R02 R01 R00 0 0 07CH R/W BZFQ 0 0F6H R/W 1 Initial value at initial reset 2 Not set in the circuit 3 Always "0" being read R Comment Name Init 1 1 0 R03 0 High Low Output port (R03, BZ) R02 0 High Low Output port (R02, FOUT) R01 0 High Low Output port (R01) R00 0 High Low Output port (R00, BZ) BZFQ 0 fCLK/32 fCLK/16 Buzzer frequency selection 5 Unused 0 3 - 2 - - 0 3 - 2 Unused - - 0 3 - 2 Unused - - 4 Reset (0) immediately after being read 5 fCLK is selectable from fOSC, fOSC/2, fOSC/3 and fOSC/4 using the CLKFQ1-CLKFQ0 register. R00-R03 (when DC output is selected): Output port data (07CH) Sets the output data for the output ports. When "1" is written: High output When "0" is written: Low output Reading: Valid The output port terminals output the data written to the corresponding registers (R00-R03) without changing it. When "1" is written to the register, the output port terminal goes high (VDD), and when "0" is written, the output port terminal goes low (VSS). After an initial reset, all the registers are set to "0". R00, R03 (when buzzer output is selected): Buzzer output control (07CH*D0, D3) Controls the buzzer output. When "1" is written: Buzzer output When "0" is written: Low level (DC) output Reading: Valid The BZ signal is output from the R00 terminal by writing "1" to the R00 register. When "0" is written, the R00 terminal goes low. For the BZ signal, either "R03 control" or "R00 control" can be selected by mask option. When "R03 control" is selected, the BZ signal is output from the R03 terminal by writing "1" to the R03 register. When "0" is written to the R03 register, the R03 terminal goes low. When "R00 control" is selected, the BZ and BZ signals are output simultaneously by writing "1" to the R00 register. When "0" is written to the R00 register, the R00 and R03 terminals go low. After an initial reset, these registers are set to "0". 18 EPSON S1C60N11 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports) BZFQ: Buzzer frequency selection (0F6H*D3) Selects the frequency of the buzzer signal. When "1" is written: fCLK/32 Hz When "0" is written: fCLK/16 Hz Reading: Valid When R00 and R03 ports are set to buzzer output, the frequency of the buzzer signal can be selected using this register. When "1" is written to this register, the frequency is set to fCLK/32 (2 kHz when fCLK = 65 kHz) and when "0" is written, it is set to fCLK/16 (4 kHz when fCLK = 65 kHz). fCLK is the peripheral system clock controlled by the CLKFQ1-CLKFQ0 register. After an initial reset, this register is set to "0". R02 (when FOUT is selected): FOUT output control (07CH*D2) Controls the FOUT (fosc clock) output. When "1" is written: Clock output When "0" is written: Low level (DC) output Reading: Valid The FOUT signal is output from the R02 terminal by writing "1" to the R02 register. When "0" is written, the R02 terminal goes low. After an initial reset, this register is set to "0". 4.4.4 Programming note The buzzer (BZ, BZ) or FOUT signal may produce hazards when it is turned on or off by the control register. S1C60N11 TECHNICAL MANUAL EPSON 19 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports) 4.5 I/O Ports (P00-P03, P10-P13) 4.5.1 Configuration of I/O port Data bus The S1C60N11 has 8 bits of general-purpose I/O ports. Figure 4.5.1.1 shows the configuration of the I/O port. Each 4-bit I/O port (P00-P03 and P10-P13) can be set to either input mode or output mode by writing data to the I/O control register. Input control Register Pxx Address Address I/O control register (IOC) Vss Fig. 4.5.1.1 Configuration of I/O port 4.5.2 I/O control register and I/O mode Input or output mode can be set for each 4-bit I/O port (P00-P03, P10-P13) by writing data to the I/O control register (IOC0, IOC1). To set the input mode, write "0" to the I/O control register. When an I/O port is set to input mode, it becomes high impedance status and works as an input port. However, the input line is pulled down when input data is read. The output mode is set when "1" is written to the I/O control register. When an I/O port is set to output mode, it works as an output port. The port terminal goes high (VDD) when the port output data is set to "1", and goes low (VSS) when the port output data is set to "0". After an initial reset, the I/O control registers are set to "0", and the I/O ports enter the input mode. 4.5.3 Mask option The output specification during output mode (IOCx = "1") of the I/O port can be set with the mask option for either complementary output or Pch open drain output. This setting can be performed for each bit of the I/O port. However, when Pch open drain output has been selected, voltage in excess of the supply voltage must not be applied to the port. 20 EPSON S1C60N11 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports) 4.5.4 I/O memory of I/O port Table 4.5.4.1 lists the I/O port control bits and their addresses. Table 4.5.4.1 I/O port control bits Address Register D3 D2 D1 D0 P03 P02 P01 P00 0 IOC0 07DH R/W TMRST 0 07EH W P13 R P12 R/W P11 P10 0 IOC1 0FDH R/W 0 0 0FEH R 1 Initial value at initial reset 2 Not set in the circuit R/W Comment 1 0 Name Init 1 P03 Low - 2 High - 2 High I/O port data (P00-P03) P02 Low - 2 High Output latch is reset at initial reset P01 Low - 2 High P00 Low TMRST Reset Reset Clock timer reset - 0 3 Unused - 2 - - 0 3 - 2 Unused - - IOC0 0 Output Input I/O control register 0 (P00-P03) P13 - 2 High Low - 2 High I/O port data (P10-P13) P12 Low - 2 High Output latch is reset at initial reset P11 Low - 2 High P10 Low 0 3 Unused - 2 - - 0 3 - 2 Unused - - 0 3 - 2 Unused - - IOC1 0 Output Input I/O control register 1 (P10-P13) 3 Always "0" being read 4 Reset (0) immediately after being read P00-P03, P10-P13: I/O port data registers (07DH, 0FDH) I/O port data can be read and output data can be set through these registers. Writing When "1" is written: High level When "0" is written: Low level When an I/O port is set to the output mode, the written data is output from the I/O port terminal. When "1" is written as the port data, the port terminal goes high (VDD), and when "0" is written, the terminal goes low (VSS). Data can also be written in the input mode. Reading When "1" is read: High level When "0" is read: Low level The terminal voltage level of the I/O port is read out. When the I/O port is in the input mode the voltage level being input to the port can be read; in the output mode the output voltage level can be read. When the terminal voltage is high (VDD), the port data read is "1", and when the terminal voltage is low (VSS) the data read is "0". Also, the built-in pull-down resistor functions during reading, so the I/O port terminal is pulled down. Note: When the I/O port is set to the input mode and a low-level voltage (Vss) is input, an erroneous input results if the time constant of the capacitive load of the input line and the built-in pull-down resistor load is greater than the read-out time. When the input data is being read, the time that the input line is pulled down is equivalent to 0.5 cycles of the CPU system clock. Hence, the electric potential of the terminals must settle within 0.5 cycles. If this condition cannot be met, some measure must be devised, such as arranging a pull-down resistor externally, or performing multiple read-outs. S1C60N11 TECHNICAL MANUAL EPSON 21 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports) IOC0, IOC1: I/O control registers (07EH*D0, 0FEH*D0) The input or output mode of the I/O port can be set with these registers. When "1" is written: Output mode When "0" is written: Input mode Reading: Valid The input or output mode of the I/O port is set in units of four bits. For instance, IOC0 sets the mode for P00-P03 and IOC1 sets the mode for P10-P13. Writing "1" to the I/O control register makes the corresponding I/O port enter the output mode, and writing "0" induces the input mode. After an initial reset, these registers are set to "0", so the I/O ports are in the input mode. 4.5.5 Programming notes (1) When the I/O port is set to the output mode and a low-impedance load is connected to the port terminal, the data written to the register may differ from the data read. (2) When the I/O port is set to the input mode and a low-level voltage (Vss) is input, an erroneous input results if the time constant of the capacitive load of the input line and the built-in pull-down resistor load is greater than the read-out time. When the input data is being read, the time that the input line is pulled down is equivalent to 0.5 cycles of the CPU system clock. Hence, the electric potential of the terminals must settle within 0.5 cycles. If this condition cannot be met, some measure must be devised, such as arranging a pull-down resistor externally, or performing multiple read-outs. 22 EPSON S1C60N11 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) 4.6 LCD Driver (COM0-COM3, SEG0-SEG37) 4.6.1 Configuration of LCD driver The S1C60N11 has four common terminals and 38 (SEG0-SEG37) segment terminals, so that an LCD with a maximum of 152 (38 x 4) segments can be driven. The power for driving the LCD is generated by the internal circuit, so there is no need to supply power externally. The driving method is 1/4 duty (or 1/3, 1/2 duty is selectable by mask option) dynamic drive, adopting the four types of potential (1/3 bias), VDD, VL1, VL2 and VL3. Moreover, the 1/2 bias dynamic drive that uses three types of potential, VDD, VL1 = VL2 and VL3, can be selected by setting the mask option (drive duty can also be selected from 1/4, 1/3 or 1/2). The LCD drive voltages VL1 to VL3 are generated by the internal power supply circuit as shown in Table 4.6.1.1. Table 4.6.1.1 LCD drive voltage Mask option selection 4.5 V LCD, 1/3 bias 3 V LCD, 1/2 bias VL1 VSS VSS Drive voltage VL2 2 VSS VSS VL3 3 VSS 2 VSS When 1/2 bias drive option is selected, the VL1 terminal should be connected with the VL2 terminal outside the IC. Refer to Section 2.1, "Power Supply", for details of the power supply circuit. The frame frequency is 32 Hz for 1/4 duty and 1/2 duty, and 42.7 Hz for 1/3 duty (in the case of fCLK = 65 kHz). Figures 4.6.1.1 to 4.6.1.6 show the drive waveform for each duty and bias. Note: "fCLK" indicates the peripheral system clock frequency selected by the CLKFQ1-CLKFQ0 register. S1C60N11 TECHNICAL MANUAL EPSON 23 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) VDD VL1 VL2 VL3 COM0 COM1 LCD status COM0 COM1 COM2 COM3 COM2 SEG0-37 COM3 Off On VDD VL1 VL2 VL3 SEG0 -SEG37 Frame frequency Fig. 4.6.1.1 Drive waveform for 1/4 duty (1/3 bias) 24 EPSON S1C60N11 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) VDD VL1 VL2 VL3 COM0 COM1 LCD status COM0 COM1 COM2 SEG0-37 COM2 Off On COM3 VDD VL1 VL2 VL3 SEG0 -SEG37 Frame frequency Fig. 4.6.1.2 Drive waveform for 1/3 duty (1/3 bias) VDD VL1 VL2 VL3 COM0 COM1 LCD status COM0 COM1 SEG0-37 COM2 COM3 VDD VL1 VL2 VL3 Off On SEG0 -SEG37 Frame frequency Fig. 4.6.1.3 Drive waveform for 1/2 duty (1/3 bias) S1C60N11 TECHNICAL MANUAL EPSON 25 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) -VDD -VL1, L2 -VL3 COM0 COM1 LCD lighting status COM0 COM1 COM2 COM3 SEG0-37 COM2 Off On COM3 -VDD -VL1, L2 -VL3 SEG 0-37 Frame frequency Fig. 4.6.1.4 Drive waveform for 1/4 duty (1/2 bias) 26 EPSON S1C60N11 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) -VDD -VL1, L2 -VL3 COM0 COM1 LCD lighting status COM0 COM1 COM2 SEG0-37 COM2 Off On COM3 -VDD -VL1, L2 -VL3 SEG 0-37 Frame frequency Fig. 4.6.1.5 Drive waveform for 1/3 duty (1/2 bias) -VDD -VL1, L2 -VL3 COM0 COM1 LCD lighting status COM0 COM1 SEG0-37 COM2 Off On COM3 -VDD -VL1, L2 -VL3 SEG 0-37 Frame frequency Fig. 4.6.1.6 Drive waveform for 1/2 duty (1/2 bias) S1C60N11 TECHNICAL MANUAL EPSON 27 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) 4.6.2 Switching between dynamic and static drive The S1C60N11 provides software setting of the LCD static drive. This function enables easy adjustment (cadence adjustment) of the oscillation frequency of the oscillation circuit. The procedure for executing static drive of the LCD is as follows: (1) Write "1" to register CSDC at address 078H*D3. (2) Write the same value to all registers corresponding to COM0-COM3 of the display memory. Notes: * Even when 1/3 duty is selected, COM3 is valid for static drive. However, the output frequency is the same as for the frame frequency. * For cadence adjustment, set the display data corresponding to COM0-COM3, so that all the LCDs light. Figure 4.6.2.1 shows the drive waveform for static drive. LCD lighting status -VDD -VL1 -VL2 -VL3 COM 0-3 COM0 COM1 COM2 COM3 Frame frequency SEG0-37 Off On -VDD -VL1 -VL2 -VL3 SEG 0-37 -VDD -VL1 -VL2 -VL3 Fig. 4.6.2.1 LCD static drive waveform 28 EPSON S1C60N11 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) 4.6.3 Mask option (1) Segment allocation As shown in Figure 4.l.1, display data is decided by the data written to the display memory at address 040H-06FH or C0H-EFH. * The mask option enables the display memory to be allocated entirely to either 040H-06FH (R/W) or C0H-EFH (W only). * The address and bits of the display memory can be made to correspond to the segment terminals (SEG0-SEG37) in any combination through mask option. This simplifies design by increasing the degree of freedom with which the liquid crystal panel can be designed. Figure 4.6.3.1 shows an example of the relationship between the LCD segments (on the panel) and the display memory (when 040H-06FH is selected) in the case of 1/3 duty. Address Common 0 Common 1 Common 2 6A, D0 6B, D1 6B, D0 (a) (f) (e) SEG11 6A, D1 6B, D2 6A, D3 (b) (g) (d) SEG12 6D, D1 6A, D2 6B, D3 (f') (c) (p) Data D3 D2 D1 D0 06AH d c b a 06BH p g f e 06CH d' c' b' a' 06DH p' g' f' e' SEG10 Display data memory allocation Pin address allocation a a' b f e g' c d SEG10 SEG11 Common 0 b' f' g c' e' p p' d' SEG12 Common 1 Common 2 Fig. 4.6.3.1 Segment allocation (2) Drive duty According to the mask option, either 1/4, 1/3 or 1/2 duty can be selected as the LCD drive duty. Table 4.6.3.1 shows the differences in the number of segments according to the selected duty. Table 4.6.3.1 Differences according to selected duty Duty COM used 1/4 COM0-COM3 1/3 COM0-COM2 1/2 COM0-COM1 S1C60N11 TECHNICAL MANUAL Max. number of segments Frame frequency * 152 (38 x 4) fCLK/2,048 (32 Hz) 114 (38 x 3) fCLK/1,536 (42.7 Hz) fCLK/2,048 (32 Hz) 76 (38 x 2) ( ) indicates the frequency when fCLK = 65 kHz. fCLK is controlled by the CLKFQ1-CLKFQ0 register. (fCLK = fOSC, fOSC/2, fOSC/3 or fOSC/4) EPSON 29 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) (3) Output specification * The segment terminals (SEG0-SEG37) are selected by mask option in pairs for either segment signal output or DC output (VDD and VSS binary output). When DC output is selected, the data corresponding to COM0 of each segment terminal is output. * When DC output is selected, either complementary output or Pch open drain output can be selected for each terminal by mask option. Note: The terminal pairs are the combination of SEG (2n) and SEG (2n + 1) (where n is an integer from 0 to 18). (4) Drive bias For the drive bias, either 1/3 bias or 1/2 bias can be selected by the mask option. 4.6.4 I/O memory of LCD driver Table 4.6.4.1 shows the control bits of the LCD driver and their addresses. Figure 4.6.4.1 shows the display memory map. Table 4.6.4.1 Control bits of LCD driver Address Register D3 D2 D1 CSDC EIT2 EIT8 078H R/W CLKFQ1 CLKFQ0 0 R/W R 0FFH 1 Initial value at initial reset 2 Not set in the circuit Address Page Comment Name Init 1 1 0 CSDC 0 Static Dynamic LCD drive switch EIT32 EIT2 0 Enable Mask Interrupt mask register (clock timer 2 Hz) EIT8 0 Enable Mask Interrupt mask register (clock timer 8 Hz) EIT32 0 Enable Mask Interrupt mask register (clock timer 32 Hz) CLKFQ1 Peripheral system [CLKFQ1, 0]: 00 0 10 11 01 LCDON fCLK: fOSC fOSC/2 fOSC/3 fOSC/4 CLKFQ0 clock selection 0 - - 0 3 Unused - 2 R/W LCDON 1 On Off LCD display On/Off conrol 3 Always "0" being read 4 Reset (0) immediately after being read D0 Low High 0 1 2 3 5 6 7 8 9 A B C D E F Display memory 48 words x 4 bits 40H-6FH = R/W C0H-EFH = W only 4 or C 0 4 5 or D 6 or E Fig. 4.6.4.1 Display memory map LCDON: LCD display control (0FFH*D0) Controls the LCD display. When "1" is written: LCD displayed When "0" is written: LCD is all off Reading: Valid By writing "0" to the LCDON register, all the LCD dots goes off, and when "1" is written, it returns to normal display. Writing "0" outputs an off waveform to the SEG terminals, and does not affect the content of the display memory. After an initial reset, this register is set to "1". CSDC: LCD drive switch (078H*D3) The LCD drive format can be selected with this switch. When "1" is written: Static drive When "0" is written: Dynamic drive Reading: Valid After an initial reset, this register is set to "0". 30 EPSON S1C60N11 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) Display memory (040H-06FH or C0H-EFH) The LCD segments are turned on or off according to this data. When "1" is written: On When "0" is written: Off Reading: Valid for 040H-06FH Undefined C0H-EFH By writing data into the display memory allocated to the LCD segment (on the panel), the segment can be turned on or off. After an initial reset, the contents of the display memory are undefined. 4.6.5 Programming notes (1) When 040H-06FH is selected for the display memory, the memory data and the display will not match until the area is initialized (through, for instance, memory clear processing by the CPU). Initialize the display memory by executing initial processing. (2) When 0C0H-0EFH is selected for the display memory, that area becomes write-only. Rewriting the contents with a logical operation instruction (e.g., AND, OR, etc.) which come with read-out operations is not possible. To perform bit operations, a buffer to hold the display data is required on the RAM. S1C60N11 TECHNICAL MANUAL EPSON 31 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer) 4.7 Clock Timer 4.7.1 Configuration of clock timer The S1C60N11 has a built-in clock timer that uses the oscillation circuit as the clock source. The clock timer is configured as a 7-bit binary counter that counts with a 256 Hz (when fCLK = 65,536 Hz) source clock from the divider. The high-order 4 bits of the counter data can be read by the software. Figure 4.7.1.1 is the block diagram of the clock timer. Data bus Oscillation circuit Divider 256 Hz* 128 Hz-32 Hz 16 Hz-2 Hz 32 Hz 8 Hz 2 Hz Clock timer reset signal Interrupt control Interrupt request When fCLK = 65,536 Hz. fCLK is controlled by the CLKFQ1-CLKFQ0 register. (fCLK = fOSC, fOSC/2, fOSC/3 or fOSC/4) Fig. 4.7.1.1 Block diagram of clock timer Normally, this clock timer is used for all kinds of timing purpose, such as clocks. 4.7.2 Interrupt function The clock timer can generate interrupts at the falling edge of the 32 Hz, 8 Hz, and 2 Hz signals (when fCLK = 65,536 Hz). The software can mask any of these interrupt signals. Figure 4.7.2.1 is the timing chart of the clock timer. Address Register bits D0 070H D1 D2 D3 Frequency fCLK 4,096 fCLK 8,192 fCLK 16,384 fCLK 32,768 Clock timer timing chart Hz Hz Hz Hz fCLK Hz interrupt request 2,048 fCLK Hz interrupt request 8,192 fCLK Hz interrupt request 32,768 Fig. 4.7.2.1 Timing chart of the clock timer As shown in Figure 4.7.2.1, an interrupt is generated at the falling edge of the 32 Hz, 8 Hz, and 2 Hz signals (when fCLK = 65,536 Hz). At this point, the corresponding interrupt factor flag (IT32, IT8, IT2) is set to "1". The interrupts can be masked individually with the interrupt mask register (EIT32, EIT8, EIT2). However, regardless of the interrupt mask register setting, the interrupt factor flags will be set to "1" at the falling edge of their corresponding signal (e.g. the falling edge of the 2 Hz signal sets the 2 Hz interrupt factor flag to "1"). 32 EPSON S1C60N11 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer) 4.7.3 I/O memory of clock timer Table 4.7.3.1 shows the clock timer control bits and their addresses. Table 4.7.3.1 Control bits of clock timer Address Register D3 D2 D1 D0 TM3 TM2 TM1 TM0 EIT8 EIT32 IT8 IT32 0 IOC0 070H R CSDC EIT2 078H R/W 0 IT2 079H R TMRST 0 07EH W R R/W 1 Initial value at initial reset 2 Not set in the circuit Comment 1 0 Name Init 1 Clock timer data (2 Hz) TM3 0 Clock timer data (4 Hz) TM2 0 When fCLK = 65,536 Hz Clock timer data (8 Hz) TM1 0 Clock timer data (16 Hz) TM0 0 CSDC 0 Static Dynamic LCD drive switch EIT2 0 Enable Mask Interrupt mask register (clock timer 2 Hz) When fCLK EIT8 0 Enable Mask Interrupt mask register (clock timer 8 Hz) = 65,536 Hz EIT32 0 Enable Mask Interrupt mask register (clock timer 32 Hz) 0 3 - 2 Unused - - IT2 4 0 Interrupt factor flag (clock timer 2 Hz) Yes No When fCLK IT8 4 0 Interrupt factor flag (clock timer 8 Hz) Yes No = 65,536 Hz 4 IT32 0 Interrupt factor flag (clock timer 32 Hz) Yes No TMRST Reset Reset Clock timer reset - 0 3 Unused - 2 - - 0 3 - 2 Unused - - IOC0 0 Output Input I/O control register 0 (P00-P03) 3 Always "0" being read 4 Reset (0) immediately after being read TM0-TM3: Timer data (070H) The l6 Hz to 2 Hz (when fCLK = 65,536 Hz) timer data of the clock timer can be read from this register. These four bits are read-only, and write operations are invalid. After an initial reset, the timer data is initialized to "0H". EIT32, EIT8, EIT2: Interrupt mask registers (078H*D0-D2) These registers are used to mask the clock timer interrupt. When "1" is written: Enabled When "0" is written: Masked Reading: Valid The interrupt mask registers (EIT32, EIT8, EIT2) mask the corresponding interrupt frequencies (32 Hz, 8 Hz, 2 Hz, when fCLK = 65,536 Hz). At initial reset, these registers are all set to "0". IT32, IT8, IT2: Interrupt factor flags (079H*D0-D2) These flags indicate the status of the clock timer interrupt. When "1" is read: Interrupt has occurred When "0" is read: Interrupt has not occurred Writing: Invalid The interrupt factor flags (IT32, IT8, IT2) correspond to the clock timer interrupts (32 Hz, 8 Hz, 2 Hz, when fCLK = 65,536 Hz). The software can determine from these flags whether there is a clock timer interrupt. However, even if the interrupt is masked, the flags are set to "1" at the falling edge of the signal. These flags can be reset when the register is read by the software. Reading of interrupt factor flags is available at EI, but be careful in the following cases. If the interrupt mask register value corresponding to the interrupt factor flag to be read is set to "1", an interrupt request will be generated by the interrupt factor flag set timing, or an interrupt request will not be generated. Be very careful when interrupt factor flags are in the same address. At initial reset, these flags are set to "0". S1C60N11 TECHNICAL MANUAL EPSON 33 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer) TMRST: Clock timer reset (07EH*D3) This bit resets the clock timer. When "1" is written: Clock timer reset When "0" is written: No operation Reading: Always "0" The clock timer is reset by writing "1" to TMRST. The clock timer starts immediately after this. No operation results when "0" is written to TMRST. This bit is write-only, and so is always "0" when read. 4.7.4 Programming notes (1) Note that the frequencies and times differ from the description in this section when the peripheral system clock frequency is not 65.536 kHz. (2) When the clock timer has been reset, the interrupt factor flag (IT) may sometimes be set to "1". Consequently, reset the flag by reading as necessary at reset. (3) Reading of interrupt factor flags is available at EI, but be careful in the following cases. If the interrupt mask register value corresponding to the interrupt factor flag to be read is set to 1, an interrupt request will be generated by the interrupt factor flag set timing, or an interrupt request will not be generated. Be very careful when interrupt factor flags are in the same address. 34 EPSON S1C60N11 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT/SLEEP) 4.8 Interrupt and HALT/SLEEP Interrupt types The S1C60N11 provides the following interrupt settings, each of which is maskable. External interrupt: Internal interrupt: Input port interrupt (one) Timer interrupt (one) To enable interrupts, the interrupt flag must be set to 1 (EI) and the necessary related interrupt mask registers must be set to 1 (enable). When an interrupt occurs, the interrupt flag is automatically reset to 0 (DI) and interrupts after that are inhibited. Figure 4.8.1 shows the configuration of the interrupt circuit. SLEEP cancellation RESET Interrupt vector (MSB) K00 EIK00 : K01 EIK01 Program counter of CPU (three low-order bits) : IK0 K02 (LSB) EIK02 K03 EIK03 IT2 EIT2 IT8 INT (Interrupt request) IT32 EIT32 Interrupt factor flag Interrupt mask register Interrupt flag EIT8 Fig. 4.8.1 Configuration of interrupt circuit S1C60N11 TECHNICAL MANUAL EPSON 35 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT/SLEEP) HALT and SLEEP modes When the HALT instruction is executed, the CPU stops operating and enters the HALT mode. The oscillation circuit and the peripheral circuits operate in the HALT mode. By an interrupt, the CPU exits the HALT mode and resumes operating. Executing the SLP instruction sets the IC in the SLEEP mode that stops operations of the CPU and oscillation circuit. The SLEEP mode will be canceled by an input interrupt request from the input port K00-K03 or a reset pulse input. Consequently, at least one input port (K00, K01, K02 or K03) interrupt must be enabled before shifting to the SLEEP status. When the SLEEP status is canceled by a K0n input interrupt, the CPU waits for oscillation to stabilize then restarts operating. Refer to the "S1C6200/6200A Core CPU Manual" for transition to the HALT/SLEEP status and timing of its cancellation. Figures 4.8.2 to 4.8.5 show the sequence to enter and cancel the SLEEP mode. Program counter PC PC+1 PC+2 PC+3 PC+4 USLP (controlled by software command "SLP") CLK K input Interrupt mask register Fig. 4.8.2 Entering SLEEP mode Interrupt service routine Key interrupt vector start address Program counter PC+4 PC+4 102H Interrupt service routine end address PC+4 PC+5 USLP (controlled by software command "SLP") CLK K input Interrupt mask register Waiting for clock stabilization Execute K-input interrupt service routine Fig. 4.8.3 Wakeup from SLEEP mode by K-port Interrupt service routine Key interrupt vector start address Program counter PC+4 PC+4 102H Interrupt service routine end address PC+4 PC+5 USLP (controlled by software command "SLP") CLK <1 ms RESET Interrupt mask register SR (internal initial reset) Waiting for clock stabilization Fig. 4.8.4 Wakeup from SLEEP mode by RESET pulse (<1 ms, for fCLK = 65 kHz) Program counter PC+4 100H 101H USLP (controlled by software command "SLP") CLK >1 ms (for fCLK = 65 kHz) RESET SR (internal initial reset) 1 ms 10 ms Waiting for clock stabilization Fig. 4.8.5 Wakeup from SLEEP mode by RESET pulse (>1 ms, for fCLK = 65 kHz) 36 EPSON S1C60N11 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT/SLEEP) 4.8.1 Interrupt factors Table 4.8.1.1 shows the factors that generate interrupt requests. The interrupt factor flags are set to 1 depending on the corresponding interrupt factors. The CPU is interrupted when the following two conditions occur and an interrupt factor flag is set to 1. * The corresponding mask register is 1 (enabled) * The interrupt flag is 1 (EI) The interrupt factor flag is a read-only register, but can be reset to 0 when the register data is read. At initial reset, the interrupt factor flags are reset to 0. Note: Reading of interrupt factor flag is available at EI, but be careful in the following cases. If the interrupt mask register value corresponding to the interrupt factor flag to be read is set to 1, an interrupt request will be generated by the interrupt factor flag set timing, or an interrupt request will not be generated. Be very careful when interrupt factor flags are in the same address. Table 4.8.1.1 Interrupt factors Interrupt factor Clock timer 2 Hz falling edge (fCLK = 65 kHz) Clock timer 8 Hz falling edge (fCLK = 65 kHz) Clock timer 32 Hz falling edge (fCLK = 65 kHz) Input (K00-K03) port rising edge Interrupt factor flag IT2 (079H*D2) IT8 (079H*D1) IT32 (079H*D0) IK0 (07AH*D2) 4.8.2 Specific masks for interrupt The interrupt factor flags can be masked by the corresponding interrupt mask registers. The interrupt mask registers are read/write registers. The interrupts are enabled when 1 is written to them, and masked (interrupt disabled) when 0 is written to them. At initial reset, the interrupt mask register is set to 0. Table 4.8.2.1 shows the correspondence between interrupt mask registers and interrupt factor flags. Table 4.8.2.1 Interrupt mask registers and interrupt factor flags Interrupt mask register EIT2 (078H*D2) EIT8 (078H*D1) EIT32 (078H*D0) EIK03* (075H*D3) EIK02* (075H*D2) EIK01* (075H*D1) EIK00* (075H*D0) Interrupt factor flag IT2 (079H*D2) IT8 (079H*D1) IT32 (079H*D0) IK0 (07AH*D2) There is an interrupt mask register for each input port pin. S1C60N11 TECHNICAL MANUAL EPSON 37 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT/SLEEP) 4.8.3 Interrupt vectors When an interrupt request is input to the CPU, the CPU starts interrupt processing. After the program being executed is suspended, interrupt processing is executed in the following order: The address data (value of the program counter) of the program step to be executed next is saved on the stack (RAM). The interrupt request causes the value of the interrupt vector (page 1, 01H-07H) to be loaded into the program counter. The program at the specified address is executed (execution of interrupt processing routine). Note: The processing in steps 1 and 2, above, takes 12 cycles of the CPU system clock. Table 4.8.3.1 Interrupt vector addresses Page 1 Step 00H 02H 04H 06H Interrupt vector Initial reset Input (K00-K03) interrupt Clock timer interrupt Clock timer & Input (K00-K03) interrupt 4.8.4 I/O memory of interrupt Table 4.8.4.1 shows the interrupt control bits and their addresses. Table 4.8.4.1 Control bits of interrupt Address Register D3 D2 D1 D0 EIK03 EIK02 EIK01 EIK00 075H R/W CSDC EIT2 EIT8 EIT32 078H R/W 0 IT2 IT8 IT32 079H R 0 IK0 0 07AH R 1 Initial value at initial reset 2 Not set in the circuit 0 Comment Name Init 1 1 0 EIK03 0 Enable Mask EIK02 0 Enable Mask Interrupt mask register (K00-K03) EIK01 0 Enable Mask EIK00 0 Enable Mask CSDC 0 Static Dynamic LCD drive switch EIT2 0 Enable Mask Interrupt mask register (clock timer 2 Hz) EIT8 0 Enable Mask Interrupt mask register (clock timer 8 Hz) EIT32 0 Enable Mask Interrupt mask register (clock timer 32 Hz) 0 3 - 2 Unused - - IT2 4 0 Interrupt factor flag (clock timer 2 Hz) Yes No IT8 4 0 Interrupt factor flag (clock timer 8 Hz) Yes No IT32 4 0 Interrupt factor flag (clock timer 32 Hz) Yes No 0 3 - 2 - Unused - IK0 4 0 Yes Interrupt factor flag (K00-K03) No 0 3 - 2 - Unused - 0 3 - 2 - Unused - 3 Always "0" being read 4 Reset (0) immediately after being read When fCLK = 65,536 Hz When fCLK = 65,536 Hz EIT32, EIT8, EIT2: Interrupt mask registers (078H*D0-D2) IT32, IT8, IT2: Interrupt factor flags (079H*D0-D2) ...See Section 4.7, "Clock Timer". EIK00-EIK03: Interrupt mask registers (075H) IK0: Interrupt factor flag (07AH*D2) ...See Section 4.3, "Input Ports". 38 EPSON S1C60N11 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT/SLEEP) 4.8.5 Programming notes (1) Restart from the HALT mode is performed by an interrupt. The return address after completion of the interrupt processing will be the address following the HALT instruction. (2) Restart from the SLEEP mode is performed by an input interrupt from the input port (K00-K03). The return address after completion of the interrupt processing will be the address following the SLP instruction. At least one input port interrupt must be enabled before shifting to the SLEEP mode. (3) When an interrupt occurs, the interrupt flag will be reset by the hardware and it will become DI status. After completion of the interrupt processing, set to the EI status through the software as needed. Moreover, the nesting level may be set to be programmable by setting to the EI state at the beginning of the interrupt processing routine. (4) The interrupt factor flags must always be reset before setting the EI status. When the interrupt mask register has been set to 1, the same interrupt will occur again if the EI status is set unless of resetting the interrupt factor flag. (5) The interrupt factor flag will be reset by reading through the software. Because of this, when multiple interrupt factor flags are to be assigned to the same address, perform the flag check after the contents of the address has been stored in the RAM. Direct checking with the FAN instruction will cause all the interrupt factor flag to be reset. (6) Reading of interrupt factor flag is available at EI, but be careful in the following cases. If the interrupt mask register value corresponding to the interrupt factor flag to be read is set to 1, an interrupt request will be generated by the interrupt factor flag set timing, or an interrupt request will not be generated. Be very careful when interrupt factor flags are in the same address. (7) Restart from SLEEP mode can be performed by an external reset signal. If the input reset pulse width is more than 1 ms (when fCLK = 65 kHz), the internal system reset signal goes high to reset the system. If the reset pulse width is less than 1 ms, the system will execute the input interrupt service routine. The return address after completion of the interrupt processing will be the address following the SLP instruction. S1C60N11 TECHNICAL MANUAL EPSON 39 CHAPTER 5: BASIC EXTERNAL WIRING DIAGRAM CHAPTER 5 BASIC EXTERNAL WIRING DIAGRAM Piezo Buzzer Single Terminal Driving O C1 CA C2 Connection depends on power supply and LCD panel specification. Please refer to Figure 2.1.1. VL2 P00 P01 P02 P03 P10 P11 P12 P13 VL3 S1C60N11 C3 VDD RESET R02 (FOUT) R03 (BZ) R00 (BZ) I/O CB VL1 R01 I COM3 K00 K01 K02 K03 SEG37 COM0 SEG0 LCD panel Lamp C1 C2 C3 CP Capacitor Capacitor Capacitor Capacitor TEST VSS + CP Piezo 0.1 F 0.1 F 0.1 F 3.3 F Note: The above table is simply an example, and is not guaranteed to work. Piezo Buzzer Direct Driving R03 (BZ) R00 (BZ) S1C60N11 RA1 RA2 Piezo RA1 Protection resistor RA2 Protection resistor 40 100 100 EPSON S1C60N11 TECHNICAL MANUAL CHAPTER 6: ELECTRICAL CHARACTERISTICS CHAPTER 6 ELECTRICAL CHARACTERISTICS 6.1 Absolute Maximum Rating Item Supply voltage Input voltage (1) Input voltage (2) Operating temperature Storage temperature Soldering temperature / time (VDD=0V) Unit V V V C C - Rated value -5.0 to 0.5 VSS - 0.3 to 0.5 VSS - 0.3 to 0.5 -20 to 70 -65 to 150 260C, 10sec (lead section) Symbol VSS VI VIOSC Topr Tstg Tsol 6.2 Recommended Operating Conditions Item Supply voltage Oscillation frequency Symbol VSS fOSC Booster capacitor C1 Condition VDD=0V CR oscillation CR oscillation CR oscillation CR oscillation Min. -1.8 Typ. -1.5 65 130 195 260 0.1 (Ta=-20 to 70C) Max. Unit -1.2 V kHz kHz kHz kHz F 6.3 DC Characteristics Unless otherwise specified: VDD=0V, VSS=-1.5V, fCLK=65kHz, Ta=25C, VL1-VL3 are internal voltage, C1-C3=0.1F Item Symbol Condition Min. High level input voltage (1) VIH1 K00-03, P00-03, P10-13 0.2*VSS High level input voltage (2) VIH2 0.1*VSS RESET, TEST Low level input voltage (1) VIL1 K00-03, P00-03, P10-13 VSS Low level input voltage (2) VIL2 VSS RESET, TEST High level input current (1) IIH1 VIH1=0V, No pull-down K00-03, P00-03, P10-13 0 High level input current (2) VIH2=0V, Pull-down 5 IIH2 K00-03 High level input current (3) 25 VIH3=0V, Pull-down IIH3 P00-03, P10-13 RESET, TEST Low level input current VIL=VSS IIL K00-03, P00-03, P10-13 -0.5 RESET, TEST High level output current (1) IOH1 VOH1=0.1*VSS R00, R03 High level output current (2) IOH2 VOH2=0.1*VSS R01, R02, P00-03, P10-13 Low level output current (1) IOL1 1400 VOL1=0.9*VSS R00, R03 Low level output current (2) IOL2 700 VOL2=0.9*VSS R01, R02, P00-03, P10-13 Common output current VOH3=-0.05V IOH3 COM0-3 3 VOL3=VL3+0.05V IOL3 Segment output current VOH4=-0.05V IOH4 SEG0-37 (during LCD output) 3 VOL4=VL3+0.05V IOL4 Segment output current VOH5=0.1*VSS IOH5 SEG0-37 (during DC output) 100 VOL5=0.9*VSS IOL5 S1C60N11 TECHNICAL MANUAL EPSON Typ. Max. 0 0 0.8*VSS 0.9*VSS 0.5 20 100 Unit V V V V A A A 0 A -300 -150 A A A A -3 -3 -100 A A A A A A 41 CHAPTER 6: ELECTRICAL CHARACTERISTICS 6.4 Analog Circuit Characteristics and Current Consumption LCD drive voltage * 4.5 V LCD panel, 1/4, 1/3, 1/2 duty, 1/3 bias (VL2 is shorted to VSS inside the IC) Unless otherwise specified: VDD=0V, VSS=-1.5V, fCLK=65kHz, Ta=25C, VL1-VL3 are internal voltage, C1-C3=0.1F, Internal CR oscillation circuit Condition Typ. Item Min. Max. Symbol Connect 1 M load resistor between VDD and VL1 VSS LCD drive voltage VL1 (without panel load) VL2 Connect 1 M load resistor between VDD and VL2 2*VL1 2*VL1 (without panel load) - 0.1 x0.9 Connect 1 M load resistor between VDD and VL3 VL3 3*VL1 3*VL1 - 0.1 x0.9 (without panel load) Unit V V V * 3 V LCD panel, 1/4, 1/3, 1/2 duty, 1/2 bias (VL3 is shorted to VSS inside the IC and VL1 is shorted to VL2 outside the IC) Unless otherwise specified: VDD=0V, VSS=-1.5V, fCLK=65kHz, Ta=25C, VL1-VL3 are internal voltage, C1-C3=0.1F, Internal CR oscillation circuit Condition Typ. Item Min. Max. Symbol Connect 1 M load resistor between VDD and VL1 VSS LCD drive voltage VL1 (without panel load) VL2 Connect 1 M load resistor between VDD and VL2 VSS (without panel load) VL3 Connect 1 M load resistor between VDD and VL3 2*VL1 2*VL1 (without panel load) - 0.1 x0.9 Unit V V V Current consumption Unless otherwise specified: VDD=0V, VSS=-1.5V, Ta=25C, VL1-VL3 are internal voltage, C1-C3=0.1F, RCR is internal resistor, fCLK=65kHz Item Condition Min. Typ. Max. Symbol Current consumption During HALT Without 4 6 IOP1 (fOSC=65kHz) During execution panel load 8 11 Current consumption During HALT Without 8 11 IOP2 (fOSC=130kHz) During execution panel load 15 21 During HALT Without 11 15 Current consumption IOP3 During execution panel load 20 26 (fOSC=195kHz) During HALT Without 14 19 Current consumption IOP4 During execution panel load 26 34 (fOSC=260kHz) During SLEEP Without 0.3 Current consumption IOP5 panel load 42 EPSON Unit A A A A A A A A A S1C60N11 TECHNICAL MANUAL CHAPTER 6: ELECTRICAL CHARACTERISTICS 6.5 Oscillation Caharacteristics Oscillation characteristics will vary according to different conditions (elements used, board pattern). Use the following characteristics are as reference values. Unless otherwise specified: VDD=0V, VSS=-1.5V, Ta=25C Item Oscillation frequency dispersion Oscillation start time Frequency v.s. voltage deviation Frequency v.s. temperature deviation Symbol fOSC1 tsta df1/dv df1/dta Condition VSS=-1.5V VSS=-1.5V VSS=-1.2 to -1.8V VSS=-1.5V, Ta=-25 to 75C Min. 42.3 Unless otherwise specified: VDD=0V, VSS=-1.5V, Ta=25C Item Oscillation frequency dispersion Oscillation start time Frequency v.s. voltage deviation Frequency v.s. temperature deviation Condition Symbol fOSC2 tsta VSS=-1.5V df2/dv VSS=-1.2 to -1.8V df2/dta VSS=-1.5V, Ta=-25 to 75C Min. 84.5 Unless otherwise specified: VDD=0V, VSS=-1.5V, Ta=25C Item Oscillation frequency dispersion Oscillation start time Frequency v.s. voltage deviation Frequency v.s. temperature deviation Symbol Condition fOSC3 tsta VSS=-1.5V df3/dv VSS=-1.2 to -1.8V df3/dta VSS=-1.5V, Ta=-25 to 75C Min. 136.5 Unless otherwise specified: VDD=0V, VSS=-1.5V, Ta=25C Item Oscillation frequency dispersion Oscillation start time Frequency v.s. voltage deviation Frequency v.s. temperature deviation Symbol fOSC4 tsta df4/dv df4/dta Min. 182 S1C60N11 TECHNICAL MANUAL Condition VSS=-1.5V VSS=-1.5V VSS=-1.2 to -1.8V VSS=-1.5V, Ta=-25 to 75C EPSON Typ. 65 Max. 87.8 3 30 15 Unit kHz mS % % Typ. 130 Max. 175.5 3 30 15 Unit kHz mS % % Typ. 195 Max. 253.5 3 30 15 Unit kHz mS % % Typ. 260 Max. 338 3 30 15 Unit kHz mS % % -30 -15 -30 -15 -30 -15 -30 -15 43 CHAPTER 7: PACKAGE CHAPTER 7 PACKAGE 7.1 Plastic Package QFP14-80pin (Unit: mm) 140.4 120.1 60 41 120.1 140.4 40 61 INDEX 21 80 1 20 +0.1 0.18 -0.05 +0.05 0.125 -0.025 0 10 0.2 0.5 0.1 1.7max 1.40.1 0.5 1 QFP5-80pin (Unit: mm) 25.60.4 200.1 64 41 65 INDEX 25 80 1 24 0.8 0.350.1 3.4max 2.70.1 19.60.4 140.1 40 0.26 0.150.05 0 12 1.5 2.8 44 EPSON S1C60N11 TECHNICAL MANUAL CHAPTER 7: PACKAGE 7.2 Ceramic Package for Test Samples 26.8 0.15 20.0 0.18 (Unit: mm) 80 25 0.35 0.05 24 0.95 0.08 0.05 0.76 0.08 0.80 0.8 0.4 0.08 1 0.15 40 20.9 65 0.14 41 14.0 64 Grass No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 S1C60N11 TECHNICAL MANUAL Name SEG35 N.C. N.C. SEG36 SEG37 K03 K02 K01 K00 P13 P12 P11 P10 P03 P02 P01 P00 R02 R01 R00 No. 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Name R03 N.C. N.C. N.C. VSS RESET N.C. N.C. N.C. VDD VL3 VL2 VL1 CB CA COM3 COM2 COM1 COM0 SEG0 No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 EPSON Name No. Name N.C. 61 N.C. N.C. 62 N.C. SEG1 63 N.C. SEG2 64 SEG19 SEG3 65 TEST SEG4 66 SEG20 SEG5 67 SEG21 SEG6 68 SEG22 SEG7 69 SEG23 SEG8 70 SEG24 SEG9 71 SEG25 SEG10 72 SEG26 SEG11 73 SEG27 SEG12 74 SEG28 SEG13 75 SEG29 SEG14 76 SEG30 SEG15 77 SEG31 SEG16 78 SEG32 SEG17 79 SEG33 SEG18 80 SEG34 N.C. : No Connection 45 CHAPTER 8: PAD LAYOUT CHAPTER 8 PAD LAYOUT 8.1 Pad Layout Diagram 15 10 1 70 5 20 25 30 X 60 Die No. (0, 0) 2.87 mm 65 55 35 40 45 50 2.90 mm Chip thickness: 400 m Pad opening: 95 m 8.2 Pad Coordinates (unit: m) No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 46 Pad name SEG37 K03 K02 K01 K00 P13 P12 P11 P10 P03 P02 P01 P00 R02 R01 R00 R03 VSS RESET N.C. N.C. N.C. VDD VL3 X 1,020 861 731 601 471 297 167 37 -93 -246 -376 -507 -637 -835 -969 -1,102 -1,236 -1,284 -1,284 -1,284 -1,284 -1,284 -1,284 -1,284 Y 1,268 1,268 1,268 1,268 1,268 1,268 1,268 1,268 1,268 1,268 1,268 1,268 1,268 1,268 1,268 1,268 1,268 965 835 705 575 445 286 156 No. 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Pad name VL2 VL1 CB CA COM3 COM2 COM1 COM0 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 X -1,284 -1,284 -1,284 -1,284 -1,284 -1,284 -1,284 -1,284 -1,284 -1,237 -1,107 -977 -795 -665 -535 -405 -275 -145 -15 115 245 375 505 635 EPSON Y 26 -104 -234 -364 -494 -624 -754 -884 -1,014 -1,268 -1,268 -1,268 -1,268 -1,268 -1,268 -1,268 -1,268 -1,268 -1,268 -1,268 -1,268 -1,268 -1,268 -1,268 No. 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 - - Pad name SEG16 SEG17 SEG18 SEG19 TEST SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 X 765 895 1,025 1,284 1,284 1,284 1,284 1,284 1,284 1,284 1,284 1,284 1,284 1,284 1,284 1,284 1,284 1,284 1,284 1,284 1,284 1,284 Y -1,268 -1,268 -1,268 -1,196 -1,037 -879 -749 -619 -489 -359 -229 -99 32 162 292 422 552 682 812 942 1,072 1,202 S1C60N11 TECHNICAL MANUAL CHAPTER 9: PRECAUTIONS ON MOUNTING CHAPTER 9 PRECAUTIONS ON MOUNTING <Reset Circuit> The power-on reset signal which is input to the RESET terminal changes depending on conditions (power rise time, components used, board pattern, etc.). Decide the time constant of the capacitor and resistor after enough tests have been completed with the application product. When the built-in pull-down resistor is added to the RESET terminal by mask option, take into consideration dispersion of the resistance for setting the constant. In order to prevent any occurrences of unnecessary resetting caused by noise during operating, components such as capacitors and resistors should be connected to the RESET terminal in the shortest line. <Power Supply Circuit> Sudden power supply variation due to noise may cause malfunction. Consider the following points to prevent this: (1) The power supply should be connected to the VDD and VSS terminal with patterns as short and large as possible. (2) When connecting between the VDD and VSS terminals with a bypass capacitor, the terminals should be connected as short as possible. Bypass capacitor connection example VDD VDD VSS VSS (3) Components which are connected to the VL1, VL2, VL3 terminals, such as a capacitor, should be connected in the shortest line. <Arrangement of Signal Lines> In order to prevent generation of electromagnetic induction noise caused by mutual inductance, do not arrange a large current signal line near the circuits that are sensitive to noise. <Precautions for Visible Radiation (when bare chip is mounted)> Visible radiation causes semiconductor devices to change the electrical characteristics. It may cause this IC to malfunction. When developing products which use this IC, consider the following precautions to prevent malfunctions caused by visible radiations. (1) Design the product and implement the IC on the board so that it is shielded from visible radiation in actual use. (2) The inspection process of the product needs an environment that shields the IC from visible radiation. (3) As well as the face of the IC, shield the back and side too. S1C60N11 TECHNICAL MANUAL EPSON 47 International Sales Operations AMERICA ASIA EPSON ELECTRONICS AMERICA, INC. EPSON (CHINA) CO., LTD. - HEADQUARTERS - 28F, Beijing Silver Tower 2# North RD DongSanHuan ChaoYang District, Beijing, CHINA Phone: 64106655 Fax: 64107319 1960 E. Grand Avenue EI Segundo, CA 90245, U.S.A. Phone: +1-310-955-5300 Fax: +1-310-955-5400 SHANGHAI BRANCH 4F, Bldg., 27, No. 69, Gui Jing Road Caohejing, Shanghai, CHINA Phone: 21-6485-5552 Fax: 21-6485-0775 - SALES OFFICES West 150 River Oaks Parkway San Jose, CA 95134, U.S.A. Phone: +1-408-922-0200 Fax: +1-408-922-0238 Central 101 Virginia Street, Suite 290 Crystal Lake, IL 60014, U.S.A. Phone: +1-815-455-7630 Fax: +1-815-455-7633 Northeast 301 Edgewater Place, Suite 120 Wakefield, MA 01880, U.S.A. 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FRENCH BRANCH OFFICE 1 Avenue de l' Atlantique, LP 915 Les Conquerants Z.A. de Courtaboeuf 2, F-91976 Les Ulis Cedex, FRANCE Phone: +33-(0)1-64862350 Fax: +33-(0)1-64862355 BARCELONA BRANCH OFFICE Barcelona Design Center Edificio Prima Sant Cugat Avda. Alcalde Barrils num. 64-68 E-08190 Sant Cugat del Valles, SPAIN Phone: +34-93-544-2490 Fax: +34-93-544-2491 421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN Phone: +81-(0)42-587-5812 Fax: +81-(0)42-587-5564 ED International Marketing Department Asia 421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN Phone: +81-(0)42-587-5814 Fax: +81-(0)42-587-5110 In pursuit of "Saving" Technology, Epson electronic devices. Our lineup of semiconductors, liquid crystal displays and quartz devices assists in creating the products of our customers' dreams. Epson IS energy savings. S1C60N11 Technical Manual ELECTRONIC DEVICES MARKETING DIVISION EPSON Electronic Devices Website http://www.epson.co.jp/device/ First issue April, 1999 Printed February, 2001 in Japan M A