AD7656A-1BSTZ-RL - Analog Devices

250 kSPS, 6-Channel, Simultaneous

Sampling, Bipolar, 16-Bit ADC

Data Sheet

AD7656A-1

FEATURES

Pin and software compatible with the AD7656A featuring

reduced decoupling requirements

6 independent analog-to-digital converters (ADCs)

True bipolar analog inputs

Pin-/software-selectable ranges: ±10 V or ±5 V

Fast throughput rate: 250 kSPS

iCMOS process technology

Low power: 140 mW at 250 kSPS with 5 V supplies

High noise performance with wide bandwidth

88 dB SNR at 10 kHz input frequency

On-chip reference and reference buffers

High speed parallel, serial, and daisy-chain interface modes

High speed serial interface

Serial peripheral interface (SPI)/QSPI™/MICROWIRE®/DSP

compatible

Power-down mode: 315 µW maximum

64-lead LQFP

Built-in power supply sequencing (PSS) robustness solution

APPLICATIONS

Power line monitoring and measuring systems

Instrumentation and control systems

Multiaxis positioning systems

FUNCTIONAL BLOCK DIAGRAM

VSS DGND

VDD

REF

CONVS T A CONVS T B CONVS T C

OUTPUT

DRIVERS

OUTPUT

DRIVERS

OUTPUT

DRIVERS

OUTPUT

DRIVERS

CONTROL

LOGIC

BUF

AGND

T/H

CLK

OSC

AVCC DVCC

SER/PAR SEL

VDRIVE

STBY

DB8/DO UT A

DB9/DO UT B

DB10/DO UT C

DB6/SCLK

WR/REFEN/DIS

DATA/

CONTROL

LINES

AD7656A-1

16-BIT SAR

11128-001

16-BIT SAR

Figure 1.

GENERAL DESCRIPTION

The AD7656A-11 is a reduced decoupling pin- and software-

compatible version of AD7656A. The AD7656A-1 contains six

16-bit, fast, low power successive approximation ADCs in a

package designed on the iCMOS® process (industrial CMOS).

iCMOS is a process combining high voltage silicon with submicron

CMOS and complementary bipolar technologies. It enables the

development of a wide range of high performance analog ICs,

capable of 33 V operation in a footprint that no previous

generation of high voltage devices could achieve. Unlike analog

ICs using conventional CMOS processes, iCMOS components

can accept bipolar input signals while providing increased

performance, which dramatically reduces power consumption

and package size.

The AD7656A-1 features throughput rates of to 250 kSPS. It

contains wide bandwidth (4.5 MHz), track-and-hold amplifiers

that can handle input frequencies up to 4.5 MHz.

The conversion process and data acquisition are controlled

using the CONVST x signals and an internal oscillator. Three

CONVST x pins (CONVST A, CONVST B, and CONVST C)

allow independent, simultaneous sampling of the three ADC

pairs. The AD7656A-1 has a high speed parallel and serial

interface, allowing the device to interface with microprocessors

or digital signal processors (DSPs). In serial interface mode, the

AD7656A-1 has a daisy-chain feature that allows multiple

ADCs to connect to a single serial interface. The AD7656A-1

can accommodate true bipolar input signals in the ±4 × VREF

range and the ±2 × VREF range. The AD7656A-1 also contains

an on-chip 2.5 V reference.

Multifunction pin names may be referenced by their relevant

function only.

PRODUCT HIGHLIGHTS

1. Six 16-bit, 250 kSPS ADCs on board.

2. Six true bipolar, high impedance analog inputs.

3. High speed parallel and serial interfaces.

4. Reduced decoupling requirements and reduced bill of

materials cost compared with the AD7656A.

1 Protected by U.S. Patent No. 6,731,232.

Rev. 0 Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Technical Support www.analog.com

AD7656A-1 Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Timing Specifications .................................................................. 5

Absolute Maximum Ratings ............................................................ 6

Power Supply Sequencing ........................................................... 6

Thermal Resistance ...................................................................... 6

ESD Caution .................................................................................. 6

Pin Configuration and Function Descriptions ............................. 7

Typical Performance Characteristics ........................................... 10

Terminology .................................................................................... 13

Theory of Operation ...................................................................... 15

Converter Details ....................................................................... 15

ADC Transfer Function ............................................................. 16

Internal/External Reference ...................................................... 16

Typical Connection Diagram ................................................... 16

Driving the Analog Inputs ........................................................ 17

Interface Options ........................................................................ 17

Software Selection of ADCs ...................................................... 19

Serial Read Operation ................................................................ 21

Daisy-Chain Mode (DCEN = 1, SER/PAR/SEL = 1) ............. 22

Application Hints ........................................................................... 24

Layout .......................................................................................... 24

Outline Dimensions ....................................................................... 25

Ordering Guide .......................................................................... 25

REVISION HISTORY

12/13—Revision 0: Initial Version

Rev. 0 | Page 2 of 28

Data Sheet AD7656A-1

SPECIFICATIONS

VREF = 2.5 V internal/external, AVCC = 4.75 V to 5.25 V, DVCC = 4.75 V to 5.25 V, and VDRIVE = 2.7 V to 5.25 V. For the ±4 × VREF range,

VDD = 11 V to 16.5 V, and VSS = −11 V to −16.5 V. For the ±2 × VREF range, VDD = 6 V to 16.5 V, and VSS = −6 V to −16.5 V. fSAMPLE =

250 kSPS, and TA = TMIN to TMAX, unless otherwise noted.

Table 1.

Parameter Min Typ Max Unit Test Conditions/Comments

DYNAMIC PERFORMANCE fIN = 10 kHz sine wave

Signal-to-Noise + Distortion (SINAD)1 88 dB

Signal-to-Noise Ratio (SNR)1 88 dB

Total Harmonic Distortion (THD)1 −90 dB

−105 dB VDD/VSS = ±6 V to ±16.5 V

Peak Harmonic or Spurious Noise (SFDR)1 −100 dB

Intermodulation Distortion (IMD)1 fa = 10.5 kHz, fb = 9.5 kHz

Second-Order Terms −112 dB

Third-Order Terms −107 dB

Aperture Delay 10 ns

Aperture Delay Matching 4 ns

Aperture Jitter 35 ps

Channel-to-Channel Isolation1 −100 dB fIN on unselected channels up to 100 kHz

Full-Power Bandwidth 4.5 MHz At −3 dB

2.2 MHz At −0.1 dB

DC ACCURACY

Resolution 16 Bits

No Missing Codes 15 Bits

Integral Nonlinearity1 ±3 LSB

±1 LSB

Positive Full-Scale Error1 ±0.381 ±0.8 % FSR

Positive Full-Scale Error Matching1 ±0.35 % FSR

Bipolar Zero-Scale Error1 ±0.0137% ±0.048 % FSR

Bipolar Zero-Scale Error Matching1 ±0.038 % FSR

Negative Full-Scale Error1 ±0.381 ±0.8 % FSR

Negative Full-Scale Error Matching1 ±0.35 % FSR

ANALOG INPUT See Table 6 for minimum VDD/VSS for each

range

Input Voltage Ranges −4 × VREF +4 × VREF V RNGx bits or RANGE pin = 0

−2 × VREF +2 × VREF V RNGx bits or RANGE pin = 1

DC Leakage Current ±1 µA

Input Capacitance2 10 pF ±4 × VREF range when in track mode

14 pF ±2 × VREF range when in track mode

REFERENCE INPUT/OUTPUT

Reference Input Voltage Range 2.5 3 V

DC Leakage Current ±1 µA

Input Capacitance2 18.5 pF REFEN/DIS = 13

Reference Output Voltage 2.49 2.51 V

Long-Term Stability 150 ppm 1000 hours

Reference Temperature Coefficient 25 ppm/°C

6 ppm/°C

Rev. 0 | Page 3 of 28

AD7656A-1 Data Sheet

Parameter Min Typ Max Unit Test Conditions/Comments

LOGIC INPUTS

Input High Voltage (VINH) 0.7 × VDRIVE V

Input Low Voltage (VINL) 0.3 × VDRIVE V

Input Current (IIN) ±10 µA Typically 10 nA, VIN = 0 V or VDRIVE

Input Capacitance (C

)

LOGIC OUTPUTS

Output High Voltage (VOH) VDRIVE − 0.2 V ISOURCE = 200 µA

Output Low Voltage (VOL) 0.2 V ISINK = 200 µA

Floating-State Leakage Current ±10 µA

Floating-State Output Capacitance2 10 pF

Output Coding Twos complement

CONVERSION RATE

Conversion Time 3.1 µs

Track-and-Hold Acquisition Time1, 2 550 ns

Throughput Rate 250 kSPS Parallel interface mode only

POWER REQUIREMENTS

VDD Range 6 16.5 V For the 4 × VREF range, VDD = 11 V to 16.5 V

VSS Range −6 −16.5 V For the 4 × VREF range, VSS= −11 V to −16.5 V

AVCC 4.75 5.25 V

DVCC 4.75 5.25 V

VDRIVE 2.7 5.25 V

ITOTAL 4 Digital inputs = 0 V or VDRIVE

Normal Mode (Static) 18 mA AVCC = DVCC = VDRIVE = 5.25 V, VDD = 16.5 V,

VSS = −16.5 V

Normal Mode (Operational) 26 mA fSAMPLE = 250 kSPS, AVCC = DVCC = VDRIVE = 5.25 V,

VDD = 16.5 V, VSS = −16.5 V

ISS (Operational) 0.25 mA VSS = −16.5 V, fSAMPLE = 250 kSPS

IDD (Operational) 0.25 mA VDD = 16.5 V, fSAMPLE = 250 kSPS

Partial Power-Down Mode 7 mA AVCC = DVCC = VDRIVE = 5.25 V, VDD = 16.5 V,

VSS = −16.5 V

Full Power-Down Mode (STBY Pin) 60 µA SCLK on or off, AVCC = DVCC = VDRIVE = 5.25 V,

VDD = 16.5 V, VSS = −16.5 V

Power Dissipation AVCC = DVCC = VDRIVE = 5.25 V, VDD = 16.5 V,

VSS = −16.5 V

Normal Mode (Static) 94 mW

Normal Mode (Operational)

140

SAMPLE

= 250 kSPS

Partial Power-Down Mode 40 mW

Full Power-Down Mode (STBY Pin) 315 µW

1 See the Terminology section.

2 Sample tested during initial release to ensure compliance.

3 Multifunction pin names may be referenced by their relevant function only.

4 Includes IAVCC, IVDD, IVSS, IVDRIVE, and IDVCC.

Rev. 0 | Page 4 of 28

Data Sheet AD7656A-1

TIMING SPECIFICATIONS

AVCC and DVCC = 4.75 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V, VREF = 2.5 V internal/external, TA = TMIN to TMAX, unless otherwise noted. For the

±4 × VREF range, VDD = 11 V to 16.5 V, and VSS = −11 V to −16.5 V. For the ±2 × VREF range, VDD = 6 V to 16.5 V, and VSS = −6 V to

−16.5 V. Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and

timed from a voltage level of 1.6 V.

Table 2.

Parameter

Limit at TMIN, TMAX

Unit Description1 VDRIVE < 4.75 V VDRIVE = 4.75 V to 5.25 V

PARALLEL INTERFACE MODE

tCONV 3 3 µs typ Conversion time, internal clock

tQUIET 150 150 ns min Minimum quiet time required between bus

relinquish and start of next conversion

tACQ 550 550 ns min Acquisition time

t10 25 25 ns min Minimum CONVST x low pulse

t1 60 60 ns max CONVST x high to BUSY high

tWAKE-UP 2 2 ms max STBY rising edge to CONVST x rising edge, not

shown in figures

µs max

Partial power-down mode

PARALLEL READ OPERATION

t2 0 0 ns min BUSY to RD delay

ns min

setup time

t4 0 0 ns min CS to RD hold time

t5 45 36 ns min RD pulse width

t6 45 36 ns max Data access time after RD falling edge

t7 10 10 ns min Data hold time after RD rising edge

t8 12 12 ns max Bus relinquish time after RD rising edge

t9 6 6 ns min Minimum time between reads

PARALLEL WRITE OPERATION

t11 15 15 ns min WR pulse width

t12 0 0 ns min CS to WR setup time

t13 5 5 ns min CS to WR hold time

t14 5 5 ns min Data setup time before WR rising edge

t15 5 5 ns min Data hold after WR rising edge

SERIAL INTERFACE MODE

fSCLK 18 18 MHz max Frequency of serial read clock

t16 12 12 ns max Delay from CS until DOUT x three-state disabled

t172 22 22 ns max Data access time after SCLK rising edge/CS

falling edge

t18 0.4 × tSCLK 0.4 × tSCLK ns min SCLK low pulse width

t19 0.4 × tSCLK 0.4 × tSCLK ns min SCLK high pulse width

t20 10 10 ns min SCLK to data valid hold time after SCLK falling edge

t21 18 18 ns max CS rising edge to DOUT x high impedance

1 Multifunction pin names may be referenced by their relevant function only.

2 A buffer is used on the DOUT x pins (Pin 5 to Pin 7) for this measurement.

200µA IOL

200µA IOH

1.6V

TO OUTPUT

PIN CL

25pF

11128-002

Figure 2. Load Circuit for Digital Output Timing Specifications

Rev. 0 | Page 5 of 28

AD7656A-1 Data Sheet

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

VDD to AGND, DGND 0 V to +16.5 V

VSS to AGND, DGND 0 V to −16.5 V

VDD to AVCC AVCC + 0.7 V to +16.5 V

AVCC to AGND, DGND −0.3 V to +7 V

DVCC to AVCC −0.3 V to AVCC + 0.3 V

DVCC to DGND, AGND −0.3 V to +7 V

AGND to DGND

−0.3 V to +0.3 V

VDRIVE to DGND −0.3 V to DVCC + 0.3 V

Analog Input Voltage to AGND VSS + 1 V to VDD − 1 V

Digital Input Voltage to DGND −0.3 V to VDRIVE + 0.3 V

Digital Output Voltage to DGND −0.3 V to VDRIVE + 0.3 V

REFIN/REFOUT to AGND −0.3 V to AVCC + 0.3 V

Input Current to Any Pin Except Supplies1 ±10 mA

Operating Temperature Range −40°C to +85°C

Storage Temperature Range −65°C to +150°C

Junction Temperature 150°C

Pb/Sn Temperature, Soldering

Reflow (10 sec to 30 sec) 240(0)°C

Pb-Free Temperature, Soldering Reflow 260(0)°C

ESD 1.5 kV

1 Transient currents of up to 100 mA do not cause SCR latch-up.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

POWER SUPPLY SEQUENCING

Simultaneous application of VDD and VSS is necessary to

guarantee reliability of the device. In cases where simultaneous

application cannot be guaranteed, VDD must power up before

VSS. When a negative voltage is applied to the analog inputs

before VDD and VSS are fully powered up, a 560 Ω resistor must

be placed on the analog inputs.

A number of sequencing combinations can lead to temporary

high current states; however, when all supplies are powered up,

the device returns to normal operating currents. The analog

input (AIN) coming before AV CC causes temporary high current

on the analog inputs. Digital inputs before DVCC, and DVCC

before other supplies, also cause temporary high current states.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device

soldered in a circuit board for surface-mount packages. These

specifications apply to a 4-layer board.

Table 4. Thermal Resistance

Package Type θJA θJC Unit

64-Lead LQFP

°C/W

ESD CAUTION

Rev. 0 | Page 6 of 28

Data Sheet AD7656A-1

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

DB15

WR/REF

EN/DIS

H/S SEL

SER/PAR SEL

AGND

REFCAPC

AGND

REFCAPB

AGND

REFCAPA

AGND

REFIN/REFOUT

AGND

DB13

DB12

DB11

DB8/DO UT A

DB9/DO UT B

DB10/DO UT C

DB14/REFBUF

EN/DIS

DGND

DRIVE

DB7/HBEN/DCEN

DB5/DCI N A

DB4/DCI N B

DB3/DCI N C

DB2/SE L C

DB1/SE L B

DB6/SCLK

DB0/SE L A

BUSY

CONVS T C

CONVS T B

CONVS T A

STBY

DGND

RANGE

RESET

W/B

AGND

PIN 1

AD7656A-1

TOP VIEW

(No t t o Scal e)

11128-003

Figure 3. Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description1

1 DB14/REFBUFEN/DIS Data Bit 14/Reference Buffer Enable and Disable. When SER/PAR/SEL = 0, this pin acts as a three-

state digital input/output pin.

2, 3, 64 DB13, DB12, DB15 Data Bit 12, Data Bit 13, and Data Bit 15. When SER/PAR/SEL = 0, these pins act as three-state parallel

digital input/output pins. When CS and RD are low, these pins are used to output the conversion

result. When CS and WR are low, these pins are used to write to the control register. When SER/PAR/SEL =

1, tie these pins to DGND.

4 DB11 Data Bit 11. When SER/PAR/SEL = 0, this pin acts as a three-state parallel digital output pin. When

SER/PAR/SEL = 1, tie this pin to DGND.

5 DB10/DOUT C Data Bit 10/Serial Data Output C. When SER/PAR/SEL = 0, this pin acts as a three-state parallel digital

output pin. When SER/PAR/SEL = 1 and SEL C = 1, this pin functions as DOUT C and outputs serial

conversion data. This pin configures the serial interface to have three DOUT x output lines.

6 DB9/DOUT B Data Bit 9/Serial Data Output B. When SER/PAR/SEL = 0, this pin acts as a three-state parallel digital

output pin. When SER/PAR/SEL = 1 and SEL B = 1, this pin functions as DOUT B and outputs serial

conversion data. This pin configures the serial interface to have two DOUT x output lines.

7 DB8/DOUT A Data Bit 8/Serial Data Output A. When SER/PAR/SEL = 0, this pin acts as a three-state parallel digital

output pin. When SER/PAR/SEL = 1 and SEL A = 1, this pin functions as DOUT A and outputs serial

conversion data.

8, 25 DGND Digital Ground. This is the ground reference point for all digital circuitry on the AD7656A-1. Connect

both DGND pins to the DGND plane of a system. The DGND and AGND voltages should ideally be at the

same potential and must not be more than 0.3 V apart, even on a transient basis.

9 VDRIVE Logic Power Supply Input. The voltage supplied at this pin determines the operating voltage of the

interface. This pin is nominally at the same supply as the supply of the host interface.

Rev. 0 | Page 7 of 28

AD7656A-1 Data Sheet

Pin No. Mnemonic Description1

10 DB7/HBEN/DCEN Data Bit 7/High Byte Enable/Daisy-Chain Enable. When the parallel interface is selected and the device is

used in word mode (SER/PAR/SEL = 0 and W/B = 0), Pin 10 functions as Data Bit 7. When the parallel

interface is selected and the device is used in byte mode (SER/PAR/SEL = 0 and W/B = 1), Pin 10 functions

as HBEN. If the HBEN is logic high, the data is output MSB byte first on DB15 to DB8. If HBEN is logic

low, the data is output LSB byte first on DB15 to DB8. When the serial interface is selected (SER/PAR/SEL =

1), Pin 10 functions as DCEN. If the DCEN is logic high, the AD7656A-1 operates in daisy-chain mode

with DB5 to DB3 functioning as DCIN A to DCIN C. When the serial interface is selected but the

device is not used in daisy-chain mode, tie DCEN to DGND.

11 DB6/SCLK Data Bit 6/Serial Clock. When SER/PAR/SEL = 0, this pin acts as a three-state parallel digital output

pin. When SER/PAR/SEL = 1, this pin functions as the SCLK input and is the read serial clock for the

serial transfer.

12 DB5/DCIN A Data Bit 5/Daisy-Chain Input A. When SER/PAR/SEL is low, this pin acts as a three-state parallel

digital output pin. When SER/PAR/SEL = 1 and DCEN = 1, this pin acts as Daisy-Chain Input A. When

the serial interface is selected, but the device is not used in daisy-chain mode, tie this pin to DGND.

13 DB4/DCIN B Data Bit 4/Daisy-Chain Input B. When SER/PAR/SEL = 0, this pin acts as a three-state parallel digital

output pin. When SER/PAR/SEL = 1 and DCEN = 1, this pin acts as Daisy-Chain Input B. When the serial

interface is selected, but the device is not used in daisy-chain mode, tie this pin to DGND.

14 DB3/DCIN C Data Bit 3/Daisy-Chain Input C. When SER/PAR/SEL = 0, this pin acts as a three-state parallel digital

output pin. When SER/PAR/SEL = 1 and DCEN = 1, this pin acts as Daisy-Chain Input C. When the serial

interface is selected, but the device is not used in daisy-chain mode, tie this pin to DGND.

15 DB2/SEL C Data Bit 2/Select DOUT C. When SER/PAR/SEL = 0, this pin acts as a three-state parallel digital output

pin. When SER/PAR/SEL = 1, this pin functions as SEL C and is used to configure the serial interface. If

this pin is 1, the serial interface operates with three DOUT x output pins and enables DOUT C as a

serial output. If this pin is 0, the DOUT C is not enabled to operate as a serial data output pin. Leave

unused serial DOUT x pins unconnected.

16 DB1/SEL B Data Bit 1/Select DOUT B. When SER/PAR/SEL = 0, this pin acts as a three-state parallel digital output

pin. When SER/PAR/SEL = 1, this pin functions as SEL B and is used to configure the serial interface. If

this pin is 1, the serial interface operates with two or three DOUT x output pins and enables DOUT B

as a serial output. If this pin is 0, DOUT B is not enabled to operate as a serial data output pin and

only one DOUT output pin, DOUT A, is used. Leave unused serial DOUT x pins unconnected.

17 DB0/SEL A Data Bit 0/Select DOUT A. When SER/PAR/SEL = 0, this pin acts as a three-state parallel digital output

pin. When SER/PAR/SEL = 1, this pin functions as SEL A and is used to configure the serial interface. If

this pin is 1, the serial interface operates with one, two, or three DOUT x output pins and enables

DOUT A as a serial output. When the serial interface is selected, always set this pin to 1.

18 BUSY Busy Output. This pin transitions to high when a conversion is started and remains high until the

conversion is complete and the conversion data is latched into the output data registers. A new

conversion cannot be initiated on the AD7656A-1 when the BUSY signal is high because any applied

CONVST edges are ignored.

19 CS Chip Select. This active low logic input frames the data transfer. If both CS and RD are logic low and

the parallel interface is selected, the output bus is enabled, and the conversion result is output on

the parallel data bus lines. If both CS and WR are logic low and the parallel interface is selected, DB15 to

DB8 are used to write data to the on-chip control register. When the serial interface is selected, the

CS is used to frame the serial read transfer and clock out the MSB of the serial output data.

20 RD Read Data. If both CS and RD are logic low and the parallel interface is selected, the output bus is

enabled. When the serial interface is selected, hold the RD line low.

21, 22, 23 CONVST C,

CONVST B, CONVST A

Conversion Start Input A, Conversion Start Input B, and Conversion Start Input C. These logic inputs

are used to initiate conversions on the ADC pairs. CONVST A is used to initiate simultaneous conversions

on V1 and V2. CONVST B is used to initiate simultaneous conversions on V3 and V4. CONVST C is

used to initiate simultaneous conversions on V5 and V6. When one of these pins switches from low

to high, the track-and-hold switch on the selected ADC pair switches from track to hold mode, and

the conversion is initiated. These inputs can also be used to place the ADC pairs into partial power-

down mode.

24 STBY Standby Mode Input. This pin is used to put all six on-chip ADCs into standby mode. The STBY pin is

high for normal operation and low for standby operation.

26 DVCC Digital Power, 4.75 V to 5.25 V. The DVCC and AVCC voltages should ideally be at the same potential

and must not be more than 0.3 V apart, even on a transient basis. Decouple this supply to DGND by

placing a 1 µF decoupling capacitor on the DVCC pin.

Rev. 0 | Page 8 of 28

Data Sheet AD7656A-1

Pin No. Mnemonic Description1

27 RANGE Analog Input Range Selection. Logic input. The logic level on this pin determines the input range of

the analog input channels. When this pin is Logic 1 at the falling edge of BUSY, the range for the

next conversion is ±2 × VREF. When this pin is Logic 0 at the falling edge of BUSY, the range for the

next conversion is ±4 × VREF. In hardware select mode, the RANGE pin is checked on the falling edge

of BUSY. In software mode (H/S SEL = 1), the RANGE pin can be tied to DGND, and the input range is

determined by the RNGA, RNGB, and RNGC bits in the control register (see Table 9).

28 RESET Reset Input. When set to logic high, this pin resets the AD7656A-1. In software mode, the current

conversion is aborted, and the internal register is set to all 0s. In hardware mode, the AD7656A-1 is

configured depending on the logic levels on the hardware select pins. In all modes, the AD7656A-1

should receive a RESET pulse after power-up. The RESET high pulse should be typically 100 ns wide.

The CONVST x pin may be held high during the RESET pulse. However, if the CONVST x pin is held low

during the RESET pulse, after the RESET pulse, the AD7656A-1 needs to receive a complete CONVST x

pulse to initiate the first conversion; this consists of a high-to-low CONVST x edge followed by a low-

to-high CONVST x edge. In hardware mode, the user can initiate a RESET pulse between conversion

cycles, that is, a 100 ns RESET pulse can be applied to the device after BUSY has transitioned from high

to low and the data has been read. The RESET can then be issued prior to the next complete CONVST x

pulse. Ensure that in such a case, RESET has returned to logic low prior to the next complete CONVST x

pulse.

29 W/B Word/Byte Input. When this pin is logic low, data can be transferred to and from the AD7656A-1 using

the parallel data lines DB15 to DB0. When this pin is logic high and the parallel interface is selected,

byte mode is enabled. In this mode, data is transferred using the DB15 to DB8 data lines, and DB7

functions as HBEN. To obtain the 16-bit conversion result, 2-byte reads are required. When the serial

interface is selected, tie this pin to DGND.

30 VSS Negative Power Supply Voltage. This is the negative supply voltage for the analog input section.

31 VDD Positive Power Supply Voltage. This is the positive supply voltage for the analog input section.

32, 37, 38, 43,

44, 49, 52, 53,

55, 57, 59

AGND Analog Ground. This pin is the ground reference point for all analog circuitry on the AD7656A-1. Refer

all analog input signals and external reference signals to this pin. Connect all AGND pins to the

AGND plane of the system. The AGND and DGND voltages should ideally be at the same potential

and must not be more than 0.3 V apart, even on a transient basis.

33, 36, 39,

42, 45, 48

V1 to V6 Analog Input 1 to Analog Input 6. These pins are single-ended analog inputs. In hardware mode,

the analog input range of these channels is determined by the RANGE pin. In software mode, it is

determined by the RNGC to RNGA bits of the control register (see Table 9).

34, 35, 40,

41, 46, 47,

50, 60

AVCC Analog Supply Voltage, 4.75 V to 5.25 V. This is the supply voltage for the ADC cores. The AVCC and

DVCC voltages should ideally be at the same potential and must not be more than 0.3 V apart, even

on a transient basis.

51 REFIN/REFOUT Reference Input/Reference Output. The on-chip reference is available via this pin. Alternatively, the

internal reference can be disabled, and an external reference can be applied to this input. See the

Internal/External Reference section. When the internal reference is enabled, decouple this pin using

at least a 1 µF decoupling capacitor.

54, 56, 58 REFCAPA, REFCAPB,

REFCAPC

Reference Capacitor A, Reference Capacitor B, and Reference Capacitor C. Decoupling capacitors are

connected to these pins to decouple the reference buffer for each ADC pair. Decouple each REFCAP x pin

to AGND using a 1 µF capacitor.

61 SER/PAR SEL Serial/Parallel Selection Input. When this pin is low, the parallel interface is selected. When this pin is high,

the serial interface is selected. When the serial interface is selected, DB10 to DB8 function as DOUT C to

DOUT A, DB0 to DB2 function as DOUT x, and DB7 functions as DCEN. When the serial interface is

selected, tie DB15 and DB13 to DB11 to DGND.

62 H/S SEL Hardware/Software Select Input. Logic input. When H/S SEL = 0, the AD7656A-1 is operated in

hardware select mode, and the ADC pairs to be simultaneously sampled are selected by the

CONVST pins. When H/S SEL = 1, the ADC pairs to be sampled simultaneously are selected by

writing to the control register. When the serial interface is selected, CONVST A is used to initiate

conversions on the selected ADC pairs.

63 WR/REFEN/

DIS Write Data/Reference Enable and Disable. When the H/S SEL pin is high and both CS and WR are

logic low, DB15 to DB8 are used to write data to the internal control register. When the H/S SEL pin is

low, this pin is used to enable or disable the internal reference. When H/S SEL = 0 and REFEN/DIS = 0, the

internal reference is disabled and an external reference should be applied to the REFIN/REFOUT pin.

When H/S SEL = 0 and REFEN/DIS = 1, the internal reference is enabled and the REFIN/REFOUT pin

should be decoupled. See the Internal/External Reference section.

1 Multifunction pin names may be referenced by their relevant function only.

Rev. 0 | Page 9 of 28

AD7656A-1 Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

–160

–180

FRE Q UE NCY ( kHz )

AMPLITUDE ( dB)

–20

–40

–60

–80

–100

–120

–140

40 60 80 100 120

200

= ±15V

/DV

DRIVE

= 5V

±10V RANG E

INTERNAL RE FERE NCE

= 25° C

SAMPLE

= 250kSPS

= 10kHz

SNR = 88. 44dB

SINAD = 88.43d B

THD = –111.66d B

11128-004

Figure 4. FFT for ±10 V Range (VDD/VSS = ±15 V)

–160

–180

FRE Q UE NCY ( kHz )

AMPLITUDE ( dB)

–20

–40

–60

–80

–100

–120

–140

40 60 80 100 120200

= ±12V

/DV

DRIVE

= 5V

±5V RANG E

INTERNAL RE FERE NCE

= 25° C

SAMPLE

= 250kSPS

= 10kHz

SNR = 88. 25dB

SINAD = 88.24d B

THD = –112.46d B

11128-005

Figure 5. FFT for ±5 V Range (VDD/VSS = ±12 V)

2.0

–2.0 010k 20k 30k 40k 50k 60k 65535

CODE

INL (LSB)

1.5

1.0

0.5

–0.5

–1.0

–1.5

= ±12V

/DV

DRIVE

= 5V

fSAMPLE

= 250kSPS

2 × V

REF

RANGE

= –40° C

INL WCP = 0.97L S B

INL WCN = –0.72L S B

11128-006

Figure 6. Typical INL

2.0

–2.0 010k 20k 30k 40k 50k 60k 65535

CODE

DNL ( LSB)

1.5

1.0

0.5

–0.5

–1.0

–1.5

= ±12V

/DV

DRIVE

= 5V

fSAMPLE

= 250kSPS

2 × V

REF

RANGE

= –40° C

DNL WCP = 0.61L S B

DNL WCN = –0. 82LSB

11128-007

Figure 7. Typical DNL

8310 100

ANALOG INPUT F RE QUENCY ( kHz )

SINAD (dB)

SAMPLE = 250kS P S

TA = 25° C

INTERNAL RE FERE NCE ±10V RANGE

VDD/VSS = ± 12V

AVCC/DVCC/VDRIVE = 5V

±5V RANG E

VDD/VSS = ± 12V

AVCC/DVCC/VDRIVE = 5V

11128-012

Figure 8. SINAD vs. Analog Input Frequency

–80

–11510 100

ANALOG INPUT F RE QUENCY ( kHz )

THD ( dB)

–85

–90

–95

–100

–105

–110

SAMPLE = 250kS P S

TA = 25° C

INTERNAL RE FERE NCE

±10V RANG E

VDD/VSS = ± 12V

AVCC/DVCC/VDRIVE = 5V

±5V RANG E

VDD/VSS = ± 12V

AVCC/DVCC/VDRIVE = 5V

11128-013

Figure 9. THD vs. Analog Input Frequency

Rev. 0 | Page 10 of 28

Data Sheet AD7656A-1

–80

–12010 100

ANALOG INPUT F RE QUENCY ( kHz )

THD ( dB)

–90

–100

–110

VDD/VSS = ± 16.5V

AVCC/DVCC/VDRIVE = 5.25V

TA = 25° C

INTERNAL RE FERE NCE

±4 × VREF RANGE

RSOURCE = 1000Ω

RSOURCE = 220Ω

RSOURCE = 50Ω

RSOURCE = 100Ω

RSOURCE = 10Ω

11128-014

Figure 10. THD vs. Analog Input Frequency for Various Source Impedances,

±4 × VREF Range

–80

–11510 100

ANALOG INPUT F RE QUENCY ( kHz )

THD ( dB)

–85

–90

–95

–100

–105

–110

VDD/VSS = ± 12V

AVCC/DVCC/VDRIVE = 5V

TA = 25° C

INTERNAL RE FERE NCE

±2 × VREF RANGE

RSOURCE = 1000Ω

RSOURCE = 220Ω RSOURCE = 100Ω

RSOURCE = 50Ω

RSOURCE = 10Ω

11128-015

Figure 11. THD vs. Analog Input Frequency for Various Source Impedances,

±2 × VREF Range

–55 125

TEMPERATURE (°C)

REFERENCE VOLTAGE (V)

–35 –15 525 45 65 85 105

2.492

2.494

2.496

2.498

2.500

2.502

2.504

2.506

2.508

2.510 AVCC/DVCC/VDRIVE = 5V

VDD/VSS = ± 12V

11128-016

Figure 12. Reference Voltage vs. Temperature

3.20

2.70

–55 125

TEMPERATURE (°C)

CONVERSION TIME (µs)

3.15

3.10

3.05

3.00

2.95

2.90

2.85

2.80

2.75

–35 –15 525 45 65 85 105

AVCC/DVCC/VDRIVE = 5V

VDD/VSS = ± 12V

11128-017

Figure 13. Conversion Time vs. Temperature

3500

–5

CODE

NUMBER O F O CCURRE NCE S

3000

2500

2000

1500

1000

500

–4 –3 –2 –1 0 1 2

= ±15V

/DV

DRIVE

= 5V

INTERNAL RE FERE NCE

8192 SAMP LES

168

1532

3212

2806

392

57 0

11128-018

Figure 14. Histogram of Codes

100

4030 530

SUPPLY RIPPLE FREQUENCY (kHz)

PSRR (dB)

80 130 180 230 280 330 380 430 480

VDD

VSS

fSAMPLE = 250kS P S

±2 × VREF RANGE

INTERNAL RE FERE NCE

TA = 25° C

fIN = 10kHz

100nF ON VDD AND VSS

11128-019

Figure 15. PSRR vs. Supply Ripple Frequency

Rev. 0 | Page 11 of 28

AD7656A-1 Data Sheet

–40 140

TEMPERATURE (°C)

SNR (dB)

–20 020 40 60 80 100 120

±10V RANG E

AVCC/DVCC/VDRIVE = 5.25V

VDD/VSS = ± 16.5V

±5V RANG E

AVCC/DVCC/VDRIVE = 5V

VDD/VSS = ± 12V

SAMPLE = 250kS P S

IN = 10kHz

INTERNAL RE FERE NCE

11128-020

Figure 16. SNR vs. Temperature

–90

–120

–60 140

TEMPERATURE (°C)

THD ( dB)

–95

–100

–105

–110

–115

–40 –20 04020 60 80 100 120

±10V RANG E

AVCC/DVCC/VDRIVE = 5.25V

VDD/VSS = ± 16.5V

±5V RANG E

AVCC/DVCC/VDRIVE = 5V

VDD/VSS = ± 12V

SAMPLE = 250kS P S

IN = 10kHz

INTERNAL RE FERE NCE

11128-021

Figure 17. THD vs. Temperature

120

600

FRE Q UE NCY OF INPUT NO ISE ( kHz )

CHANNEL - TO- CHANNE L I S OL ATION (dB)

AVCC/DVCC/VDRIVE = 5V

VDD/VSS = ± 12V

TA = 25° C

INTERNAL RE FERE NCE

±2 × VREF RANGE

30kHz O N SE LECTED CHANNE L

110

100

20 40 60 80 100 120 140

11128-022

Figure 18. Channel-to-Channel Isolation vs. Frequency of Input Noise

–40 –20 020 40 60 80 100 120

TEMPERATURE (°C)

DYNAMIC CURRENT ( mA)

±5V RANG E

±10V RANG E

/DV

DRIVE

= 5V

SAMPLE

= 250kSPS

FOR ±5V RANGE V

= ±12V

FOR ±10V RANGE V

= ±16. 5V

11128-023

Figure 19. Dynamic Current vs. Temperature

6030

SUPPLY RIPPLE FREQUENCY (kHz)

PSRR (dB)

70 110 150 190 230

fSAMPLE

= 250kSPS

±2 × V

REF

RANGE

INTERNAL RE FERE NCE

= 25° C

fIN

= 10kHz

1µF ON AV

SUPPLY PIN

±100mV SUPPLY RIPPLE AMPLI T UDE

11128-036

Figure 20. PSRR vs. Supply Ripple Frequency for AVCC Supply

Rev. 0 | Page 12 of 28

Data Sheet AD7656A-1

TERMINOLOGY

Integral Nonlinearity (INL)

The INL is the maximum deviation from a straight line passing

through the endpoints of the ADC transfer function. The

endpoints of the transfer function are zero scale at a ½ LSB below

the first code transition and full scale at ½ LSB above the last

code transition.

Differential Nonlinearity (DNL)

The DNL is the difference between the measured and the ideal

1 LSB change between any two adjacent codes in the ADC.

Bipolar Zero-Scale Error

The bipolar zero-scale error is the deviation of the midscale

transition (all 1s to all 0s) from the ideal VIN voltage, that is,

AGND − 1 LSB.

Bipolar Zero-Scale Error Matching

The bipolar zero-scale error matching is the difference in

bipolar zero-code error between any two input channels.

Positive Full-Scale Error

The positive full-scale error is the deviation of the last code

transition (011 … 110 to 011 … 111) from the ideal (4 × VREF −

1 LSB or 2 × VREF − 1 LSB) after adjusting for the bipolar zero-

scale error.

Positive Full-Scale Error Matching

The positive full-scale error matching is the difference in

positive full-scale error between any two input channels.

Negative Full-Scale Error

The negative full-scale error is the deviation of the first code

transition (10 … 000 to 10 … 001) from the ideal (−4 × VREF +

1 LSB or −2 × VREF + 1 LSB) after adjusting for the bipolar zero

scale error.

Negative Full-Scale Error Matching

The negative full-scale error matching is the difference in

negative full-scale error between any two input channels.

Track-and-Hold Acquisition Time

The track-and-hold amplifier returns to track mode at the end

of the conversion. The track-and-hold acquisition time is the

time required for the output of the track-and-hold amplifier to

reach its final value, within ±1 LSB, after the end of the conversion.

See the Track-and-Hold section for more details.

Signal-to-Noise Ratio (SNR)

SNR is the ratio of the rms value of the measured output signal

to the rms sum of all other spectral components below the

Nyquist frequency. The value for SNR is expressed in decibels.

Signal-to-Noise-and-Distortion (SINAD) Ratio

The SINAD ratio is the measured ratio of signal-to-noise-and-

distortion at the output of the ADC. The signal is the rms

amplitude of the fundamental. Noise is the sum of all

nonfundamental signals up to half the sampling frequency

(fSAMPLE/2, excluding dc).

The ratio depends on the number of quantization levels in the

digitization process: the more levels, the smaller the quantization

noise. The theoretical SINAD ratio for an ideal N-bit converter

with a sine wave input is given by

SINAD = (6.02 N + 1.76) dB

Therefore, SINAD is 98 dB for a 16-bit converter.

Total Harmonic Distortion (THD)

The THD is the ratio of the rms sum of the harmonics to the

fundamental. For the AD7656A-1, it is defined as

VVVVV

THD

22222

log20)dB(

++++

where:

V1 is the rms amplitude of the fundamental.

V2, V3, V4, V5, and V6 are the rms amplitudes of the second

through sixth harmonics.

Peak Harmonic or Spurious Noise

The peak harmonic or spurious noise is the ratio of the rms

value of the next largest component in the ADC output

spectrum (up to fSAMPLE/2, excluding dc) to the rms value of

the fundamental. Normally, the value of this specification is

determined by the largest harmonic in the spectrum, but for

ADCs where the harmonics are buried in the noise floor, it is

determined by a noise peak.

Intermodulation Distortion (IMD)

With inputs consisting of sine waves at two frequencies, fa and

fb, any active device with nonlinearities creates distortion

products at the sum and difference frequencies of mfa ± nfb,

where m, n = 0, 1, 2, 3. Intermodulation distortion terms are

those for which neither m nor n are equal to 0. For example, the

second-order terms include (fa + fb) and (fa − fb), and the

third-order terms include (2fa + fb), (2fa − fb), (fa + 2fb), and

(fa − 2fb).

The AD7656A-1 is tested using the CCIF standard in which two

input frequencies near the maximum input bandwidth are used.

In this case, the second-order terms are usually distanced in

frequency from the original sine waves, and the third-order

terms are usually at a frequency close to the input frequencies.

As a result, the second- and third-order terms are specified

separately. The calculation of the intermodulation distortion is

per the THD specification, where it is the ratio of the rms sum

of the individual distortion products to the rms amplitude of

the sum of the fundamentals and is expressed in decibels.

Channel-to-Channel Isolation

Channel-to-channel isolation is a measure of the level of crosstalk

between any two channels. It is measured by applying a full-scale,

100 kHz sine wave signal to all unselected input channels and

determining the degree to which the signal attenuates in the

selected channel with a 30 kHz signal.

Rev. 0 | Page 13 of 28

AD7656A-1 Data Sheet

Power Supply Rejection Ratio (PSRR)

Variations in power supply affect the full-scale transition but

not the linearity of the converter. Power supply rejection is the

maximum change in the full-scale transition point due to a change

in power supply voltage from the nominal value. See the Typical

Performance Characteristics section.

Figure 15 shows the power supply rejection ratio vs. supply ripple

frequency for the AD7656A-1. The power supply rejection ratio

is defined as the ratio of the power in the ADC output at full-scale

frequency, f, to the power of a 200 mV p-p sine wave applied to

the VDD and VSS supplies of the ADC at a frequency sampled,

fSAMPLE, as follows:

PSRR (dB) = 10 log(Pf/PfS)

where:

Pf is equal to the power at Frequency f in the ADC output.

PfS is equal to the power at Frequency fSAMPLE coupled onto the

VDD and VSS supplies.

Percent Full-Scale Ratio (% FSR)

%FSR is calculated using the full theoretical span of the ADC.

Rev. 0 | Page 14 of 28

Data Sheet AD7656A-1

THEORY OF OPERATION

CONVERTER DETAILS

The AD7656A-1 is a pin- and software-compatible, reduced

decoupling version of the AD7656A device. In addition, the

AD7656A-1 is a high speed, low power converter that allows the

simultaneous sampling of six on-chip analog-to-digital converters

(ADCs). The analog inputs on the AD7656A-1 can accept true

bipolar input signals. The RANGE pin or RNGx bits are used to

select either ±4 × VREF or ±2 × VREF as the input range for the

next conversion.

The AD7656A-1 contains six successive approximation (SAR)

ADCs, six track-and-hold amplifiers, an on-chip 2.5 V reference,

reference buffers, and high speed parallel and serial interfaces.

The device allows the simultaneous sampling of all six ADCs

when the three CONVST x pins (CONVST A, CONVST B, and

CONVST C) are tied together. Alternatively, the six ADCs can

be grouped into three pairs. Each pair has an associated CONVST x

signal used to initiate simultaneous sampling on each ADC pair,

on four ADCs, or on all six ADCs. CONVST A is used to initiate

simultaneous sampling on V1 and V2, CONVST B is used to

initiate simultaneous sampling on V3 and V4, and CONVST C

is used to initiate simultaneous sampling on V5 and V6.

A conversion is initiated on the AD7656A-1 by pulsing the

CONVST x input. On the rising edge of CONVST x, the track-

and-hold amplifier of the selected ADC pair is placed into hold

mode and the conversions are started. After the rising edge of

CONVST x, the BUSY signal goes high to indicate that the

conversion is taking place. The conversion clock for the

AD7656A-1 is internally generated, and the conversion time for

the device is 3 µs. Any further CONVST rising edges on either

CONVST A, CONVST B, or CONVST C are ignored as long as

BUSY is high. The BUSY signal returns low to indicate the end of

a conversion. On the falling edge of BUSY, the track-and-hold

amplifier returns to track mode. Data can be read from the output

Track-and-Hold Amplifiers

The track-and-hold amplifiers on the AD7656A-1 allow the ADCs

to accurately convert an input sine wave of full-scale amplitude

to 16-bit resolution. The input bandwidth of the track-and-hold

amplifiers is greater than the Nyquist rate of the ADC, even

when the AD7656A-1 is operating at the maximum throughput

rate. The device can handle input frequencies of up to 4.5 MHz.

The track-and-hold amplifiers sample their respective inputs

simultaneously on the rising edge of CONVST x. The aperture time

(that is, the delay time between the external CONVST x signal

actually entering hold) for the track-and-hold amplifier is 10 ns.

This is well matched across all six track-and-hold amplifiers on one

device and from device to device. This allows more than six ADCs

to be sampled simultaneously. The end of the conversion is signaled

by the falling edge of BUSY, and it is at this point that the track-

and-hold amplifiers return to track mode and the acquisition

time begins.

Analog Input

The AD7656A-1 can handle true bipolar input voltages. The

logic level on the RANGE pin or the value written to the RNGx

bits in the control register determines the analog input range on

the AD7656A-1 for the next conversion. When the RANGE pin or

RNGx bit is 1, the analog input range for the next conversion is

±2 × VREF. When the RANGE pin or RNGx bit is 0, the analog

input range for the next conversion is ±4 × VREF.

V1 C1

11128-024

DD_INTERNAL

SS_INTERNAL

Figure 21. Equivalent Analog Input Structure

Figure 21 shows an equivalent circuit of the analog input of

structure of the AD7656A-1. The two diodes, D1 and D2,

provide ESD protection for the analog inputs. Ensure that the

analog input signal never exceeds the VDD and VSS supply rail

limits by more than VSS + 1 V and VDD − 1 V. Signals exceeding

this value cause these diode to become forward-biased and to start

conducting into the substrate. The maximum current these diodes

can conduct without causing irreversible damage to the device is

10 mA. The C1 capacitor in Figure 21 is typically about 4 pF and

can be attributed primarily to pin capacitance. The R1 resistor is

a lumped component made up of the on resistance of a switch

(that is, a track-and-hold switch). This resistor is typically about

3.5 kΩ. The C2 capacitor is the ADC sampling capacitor and

has a capacitance of 10 pF typically.

The AD7656A-1 requires VDD and VSS dual supplies for the high

voltage analog input structures. These supplies must be greater

than the analog input range (see Table 6 for the requirements on

these supplies for each analog input range).

The AD7656A-1 requires a low voltage AVCC supply of 4.75 V to

5.25 V to power the ADC core, a DVCC supply of 4.75 V to 5.25 V

for the digital power, and a VDRIVE supply of 2.7 V to 5.25 V for

the interface power.

To meet the specified performance when using the minimum

supply voltage for the selected analog input range, it may be

necessary to reduce the throughput rate from the maximum

throughput rate.

Table 6. Minimum VDD/VSS Supply Voltage Requirements

Analog Input

Range (V)

Reference

Voltage (V)

Full-Scale

Input (V)

Minimum

VDD/VSS (V)

±4 × VREF 2.5 ±11 ±11

±2 × VREF 2.5 ±6 ±6

Rev. 0 | Page 15 of 28

AD7656A-1 Data Sheet

ADC TRANSFER FUNCTION

The output coding of the AD7656A-1 is twos complement. The

designed code transitions occur midway between successive

integer LSB values, that is, 1⁄2 LSB, 3⁄2 LSB. The LSB size is

FSR/65,536 for the AD7656A-1. The ideal transfer characteristic

is shown in Figure 22.

011 ... 111

011 ... 110

000 .. . 001

000 .. . 000

111 ... 111

–FSR/2 + 1/2L S B + FSR/2 – 3/2LSB

AGND – 1L S B

ANALO G I NP UT

ADC CODE

100 .. . 010

100 .. . 001

100 .. . 000

11128-025

Figure 22. Transfer Characteristic

The LSB size is dependent on the analog input range selected

(see Table 7).

Table 7. LSB Size for Each Analog Input Range

Input Range (V) LSB Size (mV) Full Scale Range

±10 0.305 20 V/65,536

±5 0.152 10 V/65,536

INTERNAL/EXTERNAL REFERENCE

The REFIN/REFOUT pin allows access to the 2.5 V reference of

the AD7656A-1, or it allows an external reference to be

connected, providing the reference source for conversion.

The AD7656A-1 can accommodate a 2.5 V external reference.

When applying an external reference via the REFIN/REFOUT

pin, the internal reference must be disabled, and the reference

buffers must be enabled. Alternatively, an external reference can be

applied via the REFCAPx pins, in which case, disable the internal

reference, and it is also recommended to disable the reference

buffers to save power and minimize crosstalk. After a reset, the

AD7656A-1 defaults to operating in external reference mode with

the internal reference disabled and the reference buffers

enabled.

The internal reference can be enabled in either hardware or

software mode. To enable the internal reference in hardware mode,

set the H/S SEL pin to 0 and the REFEN/DIS pin to 1. To enable the

internal reference in software mode, set H/S SEL to 1 and write to

the control register to set Bit DB9 of the register to 1. For the

internal reference mode, decouple the REFIN/REFOUT pin using a

1 µF capacitor.

The AD7656A-1 contains three on-chip reference buffers as

shown in Figure 23. Each of the three ADC pairs has an

associated reference buffer. These reference buffers require

external decoupling capacitors, using 1 µF capacitors, on the

REFCAPA, REFCAPB, and REFCAPC pins. The internal

reference buffers can be disabled in software mode by writing to

Bit DB8 in the internal control register. If a serial interface is

selected, the internal reference buffers can be disabled in hardware

mode by setting the DB14/REFBUFEN/DIS pin high. If the internal

reference and its buffers are disabled, apply an external buffered

reference to the REFCAPx pins.

BUF SAR

REF

SAR

BUF SAR

SAR

BUF SAR

SAR

REFCAPA

REFIN/

REFOUT

REFCAPB

REFCAPC

11128-127

Figure 23. Reference Circuit

TYPICAL CONNECTION DIAGRAM

Figure 24 shows the typical connection diagram for the

AD7656A-1, illustrating the reduction in the number and value

of decoupling capacitors that are required. There are eight AVCC

supply pins on each device. The AVCC supplies are the supplies

used for the AD7656A-1 conversion process; therefore, decouple

them well. The AVCC supply applied to the eight AVCC pins can

be decoupled using just one 1 µF capacitor. The AD7656A-1 can

operate with the internal reference or an externally applied

reference. In this configuration, the device is configured to

operate with the external reference. The REFIN/REFOUT pin is

decoupled with a 1 µF capacitor. The three internal reference

buffers are enabled. Each of the REFCAPx pins is decoupled

with a 1 µF capacitor.

If the same supply is being used for the AVCC and DVCC supplies,

place a ferrite or small RC filter between the supply pins.

The AGND pins are connected to the analog ground plane of

the system. The DGND pins are connected to the digital ground

plane in the system. Connect the AGND and DGND planes

together at one place in the system. Make this connection as

close as possible to the AD7656A-1 in the system.

Rev. 0 | Page 16 of 28

Data Sheet AD7656A-1

Rev. 0 | Page 17 of 28

AGND DGND V

DRIVE

DGND

AGND

REFCAPA, REFCAPB, REFCAPC

AGND

REFIN/OUT

AGND

D0 TO D15

RESET

BUSY

SER/PAR

H/S

W/B

RANGE

CONVST A, CONVST B, CONVST C

STBY V

DRIVE

AD7656A-1

1µF

DIGITAL SUPPLY

VOLTAGE +3V OR +5V

ANALOG SUPPLY

VOLTAGE 5V

11V TO +16.5

SUPPLY

2.5V

REF

SIX ANALOG

INPUTS

–11V TO –16.5V

SUPPLY

PARALLEL

INTERFACE

11128-026

MICROCONTROLLER/

MICROPROCESSOR/

DSP

SEE THE POWER SUPPLY SEQUENCING SECTION.

NOTES

Figure 24. Typical Connection Diagram

The VDRIVE supply is connected to the same supply as the

processor. The voltage on VDRIVE controls the voltage value of

the output logic signals.

Decouple the VDD and VSS signals with a minimum 1 μF decoupling

capacitor. These supplies are used for the high voltage analog

input structures on the AD7656A-1 analog inputs.

DRIVING THE ANALOG INPUTS

Together, the driver amplifier and the analog input circuit used

for the AD7656A-1 must settle for a full-scale step input to a 16-bit

level (0.0015%), which is within the specified 550 ns acquisition

time of the AD7656A-1. The noise generated by the driver

amplifier must be kept as low as possible to preserve the signal-

to-noise ratio (SNR) and transition noise performance of the

AD7656A-1. In addition, the driver also needs to have a THD

performance suitable for the AD7656A-1.

The AD8021 meets these requirements. The AD8021 needs an

external compensation capacitor of 10 pF. If a dual version of

the AD8021 is required, the AD8022 can be used. The AD8610

and the AD797 can also be used to drive the AD7656A-1.

INTERFACE OPTIONS

The AD7656A-1 provides two interface options: a high speed

parallel interface and a high speed serial interface. The required

interface mode is selected via the SER/PAR SEL pin. The parallel

interface can operate in word (W/B = 0) or byte (W/B = 1)

mode. When in serial mode, the AD7656A-1 can be configured

into daisy-chain mode.

When in parallel mode, a read operation only accesses the results

related to conversions that have just occurred. For example,

consider the case where CONVST A and CONVST C are toggled

simultaneously but CONVST B is not used. At the end of the

conversion process, when BUSY goes low, a read is implemented.

Four read pulses (in parallel mode) are applied and data from

V1, V2, V5, and V6 are output. Data from V3 and V4 is not

output because CONVST B was not toggled in this cycle.

However, when in serial mode, all zeros are output in place of

the ADC result for ADCs not included in the conversion cycle.

See the Serial Interface (SER//SEL = 1) section for more

information.

Parallel Interface (SER/PAR/SEL = 0)

The AD7656A-1 consists of six 16-bit ADCs. A simultaneous

sample of all six ADCs can be performed by connecting all

three CONVST x pins (CONVST A, CONVST B, and

CONVST C) together. The AD7656A-1 needs to see a CONVST x

pulse to initiate a conversion, consisting of a falling CONVST x

edge followed by a rising CONVST x edge. The rising edge of

CONVST x initiates simultaneous conversions on the selected

ADCs. The AD7656A-1 contains an on-chip oscillator that is

used to perform the conversions. The conversion time, tCONV, is

3 μs. The BUSY signal goes low to indicate the end of a

conversion. The falling edge of the BUSY signal is used to place

the track-and-hold amplifier into track mode.

The AD7656A-1 also allows the six ADCs to be converted

simultaneously in pairs by pulsing the three CONVST x pins

independently. CONVST A is used to initiate simultaneous

conversions on V1 and V2, CONVST B is used to initiate

simultaneous conversions on V3 and V4, and CONVST C is used

to initiate simultaneous conversions on V5 and V6. The conversion

results from the simultaneously sampled ADCs are stored in the

output data registers. Note that when a rising edge occurs on any

one CONVST x pin to initiate a conversion, any further CONVST

rising edges on any of the CONVST x pins are ignored while BUSY

is high.

AD7656A-1 Data Sheet

Data can be read from the AD7656A-1 via the parallel data bus

with standard CS and RD signals (W/B = 0). To read the data over

the parallel bus, tie SER/PA R SEL low. The CS and RD input

signals are internally gated to enable the conversion result onto

the data bus. The data lines, the DB0 to DB15 pins, leave their

high impedance state when both CS and RD are logic low.

The CS signal can be permanently tied low, and the RD signal

can be used to access the conversion results. A read operation

can take place after the BUSY signal goes low. The number of

required read operations depends on the number of ADCs that

are simultaneously sampled (see Figure 25). If CONVST A

and CONVST B are simultaneously brought low, four read

operations are required to obtain the conversion results from

V1, V2, V3, and V4. If CONVST A and CONVST C are

simultaneously brought low, four read operations are required

to obtain the conversion results from V1, V2, V5, and V6.

The conversion results are output in ascending order.

When using the three CONVST x signals to independently

initiate conversions on the three ADC pairs, when a rising edge

occurs on any one CONVST x pin to initiate a conversion, any

further CONVST rising edges on any of the CONVST x pins are

ignored while BUSY is high.

Although a conversion can be initiated during a read sequence,

it is not recommended practice, because doing so can affect the

performance of the conversion. For the specified performance,

it is recommended to perform the read after the conversion.

For unused input channel pairs, tie the associated CONVST x

pin to VDRIVE.

If there is only an 8-bit bus available, the parallel interface of the

AD7656A-1 can be configured to operate in byte mode (W/B = 1).

In this configuration, the DB7/HBEN/DCEN pin takes on its

HBEN function. Each channel conversion result from the

AD7656A-1 can be accessed in two read operations, with eight

bits of data provided on DB15 to DB8 for each of the read

operations (see Figure 26). The HBEN pin determines whether

the read operation first accesses the high byte or the low byte of

the 16-bit conversion result. To always access the low byte first

on DB15 to DB8, tie the HBEN pin low. To always access the

high byte first on DB15 to DB8, tie the HBEN pin high. In byte

mode when all three CONVST x pins are pulsed together to initiate

simultaneous conversions on all six ADCs, 12 read operations

are necessary to read back the six 16-bit conversion results.

Leave DB6 to DB0 unconnected in byte mode.

V1 V2 V3 V4 V5 V6

CONVS T A,

CONVS T B,

CONVS T C

BUSY

DATA

QUIET

ACQ

CONV

11128-027

Figure 25. Parallel Interface Timing Diagram (W/B = 0)

LOW BYTE HIG H BY TE

DB15 TO DB8

11128-028

Figure 26. Parallel Interface—Read Cycle for Byte Mode of Operation (W/B = 1, HBEN = 0)

Rev. 0 | Page 18 of 28

Data Sheet AD7656A-1

SOFTWARE SELECTION OF ADCS

The H/S SEL pin determines the source of the combination of ADCs

that are to be simultaneously sampled. When the H/S SEL pin is

logic low, the combination of channels to be simultaneously

sampled is determined by the CONVST A, CONVST B, and

CONVST C pins. When the H/S SEL pin is logic high, the

combination of channels selected for simultaneous sampling is

determined by the contents of the DB15 to DB13 bits in the

control registers. In this mode, a write to the control register is

necessary.

The control register is an 8-bit write-only register. Data is

written to this register using the CS and WR pins and the DB15

to DB8 data pins (see Figure 27). The control register is detailed

in Table 8 and Table 9. To select an ADC pair to be simultaneously

sampled, set the corresponding data line high during the write

operation.

DATA

DB15 TO DB8

11128-029

Figure 27. Parallel Interface—Write Cycle for Word Mode (W/B = 0)

The AD7656A-1 control register allows individual ranges to be

programmed on each ADC pair. DB12 to DB10 bits in the

control register are used to program the range on each ADC pair.

After a reset occurs on the AD7656A-1, the control register

contains all 0s. The CONVST A signal is used to initiate a

simultaneous conversion on the combination of channels

selected via the control register. The CONVST B and

CONVST C signals can be tied low when operating in software

mode (H/S SEL = 1). The number of read pulses required

depends on the number of ADCs selected in the control register

and on whether the devices are operating in word or byte mode.

The conversion results are output in ascending order.

During the write operation, Data Bus Bit DB15 to Data Bus Bit DB8

are bidirectional and become inputs to the control register when

RD is logic high and CS and WR are logic low. The logic state

on DB15 through DB8 is latched into the control register when

WR goes logic high.

Table 8. Control Register Bit Map (Default All Zeros)

DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8

VC VB VA RNGC RNGB RNGA REFEN REFBUF

Table 9. Control Register Bit Function Descriptions

Bit Mnemonic Description

DB15 VC This bit selects the V5 and V6 analog inputs for the next conversion. When this bit is set to 1, V5 and V6 are

simultaneously converted on the next CONVST A rising edge.

DB14

This bit selects the V3 and V4 analog inputs for the next conversion. When this bit is set to 1, V3 and V4 are

simultaneously converted on the next CONVST A rising edge.

DB13 VA This bit selects the V1 and V2 analog inputs for the next conversion. When this bit is set to 1, V1 and V2 are

simultaneously converted on the next CONVST A rising edge.

DB12 RNGC This bit selects the analog input range for the V5 and V6 analog inputs. When this bit is set to 1, the ±2 × VREF range is

selected for the next conversion. When this bit is set to 0, the ±4 × VREF range is selected for the next conversion.

DB11 RNGB This bit selects the analog input range for the V3 and V4 analog inputs. When this bit is set to 1, the ±2 × VREF range is

selected for the next conversion. When this bit is set to 0, the ±4 × V

REF

range is selected for the next conversion.

DB10 RNGA This bit selects the analog input range for the V1 and V2 analog inputs. When this bit is set to 1, the ±2 × VREF range is

selected for the next conversion. When this bit is set to 0, the ±4 × VREF range is selected for the next conversion.

DB9 REFEN This bit selects the internal reference or an external reference. When this bit is set to 0, the external reference mode is

selected. When this bit is set to 1, the internal reference is selected.

DB8 REFBUF This bit selects between using the internal reference buffers and choosing to bypass these reference buffers. When

this bit is set to 0, the internal reference buffers are enabled, and decoupling is required on the REFCAPx pins. When

this bit is set to 1, the internal reference buffers are disabled, and a buffered reference must be applied to the REFCAPx pins.

Rev. 0 | Page 19 of 28

AD7656A-1 Data Sheet

Changing the Analog Input Range (H/S SEL = 0)

The AD7656A-1 RANGE pin allows the user to select either ±2 ×

VREF or ±4 × VREF as the analog input range for the six analog

inputs. When the H/S SEL pin is low, the logic state of the

RANGE pin is sampled on the falling edge of the BUSY signal to

determine the range for the next simultaneous conversion. When

the RANGE pin is logic high at the falling edge of the BUSY

signal, the range for the next conversion is ±2 × VREF. When the

RANGE pin is logic low at the falling edge of the BUSY signal,

the range for the next conversion is ±4 × VREF. After a RESET

pulse, the range is updated on the first falling BUSY edge.

Changing the Analog Input Range (H/S SEL = 1)

When the H/S SEL pin is high, the range can be changed by

writing to the control register. Bits[DB12:DB10] in the control

conversion. Each analog input pair has an associated range bit,

allowing independent ranges to be programmed on each ADC

pair. When the RNGx bit is set to 1, the range for the next

conversion is ±2 × VREF. When the RNGx bit is set to 0, the range

for the next conversion is ±4 × VREF.

Serial Interface (SER/PAR/SEL = 1)

By pulsing one, two, or all three CONVST signals, the AD7656A-1

uses its on-chip trimmed oscillator to simultaneously convert

the selected channel pairs on the rising edge of CONVST x.

After the rising edge of CONVST x, the BUSY signal goes high to

indicate that the conversion has started. It returns low when the

conversion is complete, 3 µs later. Any further CONVST x rising

edges on either CONVST A, CONVST B, or CONVST C are

ignored as long as BUSY is high. The output register is loaded

with the new conversion results, and data can be read from the

AD7656A-1. To read the data back from the device over the

serial interface, tie SER/PA R SEL high. The CS and SCLK signals

are used to transfer data from the AD7656A-1. The device has

three DOUT x pins: DOUT A, DOUT B, and DOUT C. Data can

be read back from the AD7656A-1 using one, two, or all three

DOUT x lines.

Figure 28 shows six simultaneous conversions and the read

sequence using three DOUT x lines. Also in Figure 28, 32 SCLK

transfers are used to access data from the AD7656A-1; however,

two 16 SCLK individually framed transfers with the CS signal

can also be used to access the data on the three DOUT x lines.

Any additional SCLKs applied after this result in an output of

all zeros. When the serial interface is selected and conversion

data is clocking out on all three DOUT x lines, tie DB0/SEL A,

DB1/SEL B, and DB2/SEL C to VDRIVE. These pins are used to

enable the DOUT A to DOUT C lines, respectively.

If it is required to clock conversion data out on two data output

lines, use DOUT A and DOUT B. To enable DOUT A and

DOUT B, tie DB0/SEL A and DB1/SEL B to VDRIVE, and tie

DB2/SEL C tied low. When six simultaneous conversions are

performed and only two DOUT x lines are used, a 48 SCLK

transfer can be used to access the data from the AD7656A-1.

Any additional SCLKs applied after this result in an output of

all zeros. The read sequence is shown in Figure 29 for a

simultaneous conversion on all six ADCs using two DOUT x

lines. If a simultaneous conversion occurred on all six ADCs,

and only two DOUT x lines are used to read the results from

the AD7656A-1, DOUT A clocks out the result from V1, V2,

and V5, and DOUT B clocks out the results from V3, V4, and V6.

V1 V2

CONVS T A,

CONVS T B,

CONVS T C

BUSY

DOUT A

DOUT B

DOUT C

V3 V4

V5 V6

SCLK

QUIET

ACQ

CONV

11128-030

Figure 28. Serial Interface with Three DOUT x Lines

V1 V2 V5

DOUT A

DOUT B

V3 V4 V6

SCLK

11128-031

Figure 29. Serial Interface with Two DOUT x Lines

Rev. 0 | Page 20 of 28

Data Sheet AD7656A-1

BUSY

ACQUISITION CONVERSION ACQUISITION

SCLK

DOUT A,

DOUT B,

DOUT C DB15 DB14 DB13 DB1 DB0

ACQ

CONV

QUIET

CONVS T A,

CONVS T B,

CONVS T C

11128-032

Figure 30. Serial Read Operation

Data can also be clocked out using just one DOUT x line, in which

case, use DOUT A to access the conversion data. To configure

the AD7656A-1 to operate in this mode, tie DB0/SEL A to

VDRIVE, and tie DB1/SEL B and DB2/SEL C low. The disadvantage

of using only one DOUT x line is that the throughput rate is

reduced. Data can be accessed from the AD7656A-1 using one

96-SCLK transfer, three 32-SCLK individually framed transfers, or

six 16-SCLK individually framed transfers. Any additional SCLKs

applied after this result in an output of all zeros. When using the

serial interface, tie the RD signal low, and leave the unused

DOUT x line(s) unconnected.

Whether one, two, or three data output lines are used, if a

particular CONVST x pin is not used in the conversion cycle,

all zeros are output in place of the ADC result for the associated

ADCs even though they were not used in the conversion cycle.

This means that if, for example, only CONVST B is pulsed and

one data output pin is in use, 64 SCLKs are required to access

the results from V3 and V4; howe ver, only 32 SCLKs are required if

two or three data output lines are in use.

SERIAL READ OPERATION

Figure 30 shows the timing diagram for reading data from the

AD7656A-1 when the serial interface. The SCLK input signal

provides the clock source for the serial interface. The CS signal

goes low to access data from the AD7656A-1. The falling edge

of CS takes the bus out of three-state and clocks out the MSB of

the 16-bit conversion result. The ADCs output 16 bits for each

conversion result; the data stream of the AD7656A-1 consists of 16

bits of conversion data, provided MSB first.

The first bit of the conversion result is valid on the first SCLK

falling edge after the CS falling edge. The subsequent 15 data

bits are clocked out on the rising edge of the SCLK signal. Data

is valid on the SCLK falling edge. To access each conversion result,

16 clock pulses must be provided to the AD7656A-1. Figure 30

shows how a 16-SCLK read is used to access the conversion

results.

Rev. 0 | Page 21 of 28

AD7656A-1 Data Sheet

DIGITAL HOST

CONVERT

SCLK

AD7656A-1

CONVS T x

CS CS

SCLK SCLK

DATA I N1

DATA I N2

DOUT A

DOUT B

DOUT A

DOUT B

DCIN A

DCIN B

DCEN = 1

DEVICE 1

DCEN = 0

DEVICE 2

11128-033

AD7656A-1

Figure 31. Daisy-Chain Configuration

DEVI CE 1, DOUT A MSB V1 LSB V1 MSB V2 LSB V2 MSB V5 LSB V5 MSB V1 LSB V1 MSB V2 LSB V5

MSB V1 LSB V1 MSB V2 LSB V2 MSB V5 LSB V5

1 2 3

BUSY

SCLK

15 16 17 31 32 33 47 48 49 63 6564 94 95 96

DEVI CE 1, DOUT B MSB V3 LSB V3 MSB V4 LSB V4 MSB V6 LSB V6 MSB V3 LSB V3 MSB V4 LSB V6

DEVI CE 2, DOUT A

MSB V3 LSB V3 MSB V4 LSB V4 MSB V6 LSB V6

DEVI CE 2, DOUT B

CONVS T A,

CONVS T B,

CONVS T C

11128-034

Figure 32. Daisy-Chain Serial Interface Timing with Two DOUT Lines

DAISY-CHAIN MODE (DCEN = 1, SER/PAR/SEL = 1)

When reading conversion data back from the AD7656A-1 using

one, two, three DOUT x pins, it is possible to configure the

AD7656A-1 to operate in daisy-chain mode by using the DCEN

pin. This daisy-chain feature allows multiple AD7656A-1 devices

to be cascaded together and is useful for reducing the component

count and wiring connections. An example connection of two

devices is shown in Figure 31. This configuration shows two

DOUT x lines being used for each device. Simultaneous sampling

of the 12 analog inputs is possible by using a common CONVST x

signal. The DB5, DB4, and DB3 data pins are used as the

DCIN A to DCIN C data input pins for the daisy-chain mode.

The rising edge of CONVST is used to initiate a conversion on

the AD7656A-1. After the BUSY signal has gone low to indicate

that the conversion is complete, the user can begin to read the data

from the two devices. Figure 32 shows the serial timing diagram

when operating two AD7656A-1 devices in daisy-chain mode.

The CS falling edge is used to frame the serial transfer from the

AD7656A-1, to take the bus out of three-state, and to clock out

the MSB of the first conversion result. In the example shown in

Figure 32, all 12 ADC channels are simultaneously sampled.

Two DOUT x lines are used to read the conversion results in

this example. CS frames a 96-SCLK transfer. During the first

48 SCLKs, the conversion data is transferred from Device 2 to

Device 1. DOUT A on Device 2 transfers conversion data from

V1, V2, and V5 into DCIN A in Device 1; and DOUT B on

Device 2 transfers conversion results from V3, V4, and V6 to

DCIN B in Device 1. During the first 48 SCLKs, Device 1 transfers

data into the digital host. DOUT A on Device 1 transfers

conversion data from V1, V2, and V5; DOUT B on Device 1

transfers conversion data from V3, V4, and V6. During the last

48-SCLKs, Device 2 clocks out zeros, and Device 1 shifts the

data clocked in from Device 2 during the first 48-SCLKs into

the digital host. This example can also be implemented using

six 16-SCLK individually framed transfers if DCEN remains

high during the transfers.

Rev. 0 | Page 22 of 28

Data Sheet AD7656A-1

DEVI CE 1, DOUT A MSB V1 LSB V1 MSB V2 LSB V2 MSB V1 LSB V1 MSB V2 LSB V2

MSB V1 LSB V1 MSB V2 LSB V2

1 2 3

BUSY

SCLK

15 16 17 31 32 33 47 48 49 63 64

DEVI CE 2, DOUT A

MSB V3 LSB V3 MSB V4 LSB V4

DEVI CE 2, DOUT B

DEVI CE 1, DOUT B MSB V3 LSB V3 MSB V4 LSB V4 MSB V3 LSB V3 MSB V4 LSB V4

DEVI CE 1, DOUT C MSB V5 LSB V5 MSB V6 LSB V6 MSB V5 LSB V5 MSB V6 LSB V6

MSB V5 LSB V5 MSB V6 LSB V6

DEVI CE 2, DOUT C

CONVS T A,

CONVS T B,

CONVS T C

11128-035

Figure 33. Daisy-Chain Serial Interface Timing with Three DOUT x Lines

Figure 33 shows the timing if two AD7656A-1 devices are

configured in daisy-chain mode and are operating with three

DOUT x lines. Assuming that a simultaneous sampling of all

12 inputs occurs, the CS frames a 64-SCLK transfer during the

read operation. During the first 32 SCLKs of this transfer, the

conversion results from Device 1 are clocked into the digital

host and the conversion results from Device 2 are clocked into

Device 1. During the last 32 SCLKs of the transfer, the conversion

results from Device 2 are clocked out of Device 1 and into the

digital host, and Device 2 clocks out 0s.

The maximum number of devices in the chain is limited by the

throughput required per channel depending on the application

needs, the SCLK frequency used, and the number of serial data

lines used.

Standby/Partial Power-Down Modes of Operation

(SER/PAR/SEL = 0 or SER/PAR/SEL = 1)

Each ADC pair can be individually placed into partial power-

down mode at the end of their conversion by bringing the

associated CONVST x signal low before the falling edge of

BUSY. If a CONVST x pin is low when BUSY goes low, the

associated ADC pair only enters partial power-down mode if

they were actually converting within that cycle, that is, if that

particular CONVST x pin was used to trigger conversions. To

power an ADC pair back up, bring the CONVST x signal high

to tell the ADC pair to power up and place the track-and-hold

amplifier into track mode. After the power-up time from partial

power-down has elapsed, the CONVST x signal can receive a

rising edge to initiate a valid conversion. In partial power-down

mode, the reference buffers remain powered up. When an ADC

pair is in partial power-down mode, conversions can still occur

on the other fully powered ADCs. In Figure 34 at Point A, ADC 1

and ADC 2 enter partial power-down, and ADC 3 to ADC 6

remain fully powered. At Point B in Figure 34, ADC1 and ADC 2

begin to power up. When the required power-up time has

elapsed, a conversion can be initiated on the next CONVST x

rising edge as shown.

11128-135

CONVS T A

tWAKE-UP

BUSY

CONVS T B

CONVS T C

Figure 34. Entering and Exiting Partial Power-Down Mode

The AD7656A-1 has a standby mode whereby the device can be

placed into a low power consumption mode (315 µW maximum).

The AD7656A-1 is placed into standby mode by bringing the

input STBY logic low and can be powered up again for normal

operation by bringing STBY logic high. The output data buffers

are still operational when the AD7656A-1 is in standby mode,

meaning the user can continue to access the conversion results

of the device. This standby feature can be used to reduce the

average power consumed by the AD7656A-1 when operating at

lower throughput rates. The device can be placed into standby

at the end of each conversion when BUSY goes low and is taken

out of standby mode prior to the next conversion. The time for

the AD7656A-1 to come out of standby is called the wake-up

time. The wake-up time limits the maximum throughput rate at

which the AD7656A-1 can operate when powering down between

conversions. See the Specifications section for additional

information.

Rev. 0 | Page 23 of 28

AD7656A-1 Data Sheet

APPLICATION HINTS

LAYOUT

Design the printed circuit board (PCB) that houses the AD7656A-1

so that the analog and digital sections are separated and confined

to different areas of the board.

Use at least one ground plane. The ground plane can be

common or split between the digital and analog sections. In the

case of the split plane, join the digital and analog ground in only

one place, preferably underneath the AD7656A-1, or at least as

close as possible to the device.

If the AD7656A-1 is in a system where multiple devices require

analog-to-digital ground connections, still make the connection

at one point only, a star ground point, established as close as

possible to the AD7656A-1. Make good connections to the

ground plane. Avoid sharing one connection for multiple

ground pins. Use individual vias or multiple vias to the ground

plane for each ground pin.

Avoid running digital lines under the device because doing so

couples noise onto the die. Allow the analog ground plane to

run under the AD7656A-1 to avoid noise coupling. Shield fast

switching signals like CONVST x or clocks with digital ground

to avoid radiating noise to other sections of the board, and

never run the fast switching signals near the analog signal

paths. Avoid crossover of digital and analog signals. Run traces

on layers in close proximity on the board at right angles to each

other to reduce the effect of feedthrough through the board.

For the power supply lines to the AVCC, DVCC, VDRIVE, VDD, and VSS

pins on the AD7656A-1, use as large a trace as possible to

provide low impedance paths and to reduce the effect of glitches

on the power supply lines. Establish good connections between

the AD7656A-1 supply pins and the power tracks on the board;

this must involve the use of a single via or multiple vias for each

supply pin.

Good decoupling is also important to lower the supply impedance

presented to the AD7656A-1 and to reduce the magnitude of

the supply spikes. Place the decoupling capacitors near, but

ideally right up against, these pins and their corresponding

ground pins. Additionally, place low ESR 1 µF capacitors on each

of the supply pins, the REFIN/REFOUT pin, and each REFCAPx

pin. Avoid sharing these capacitors between pins, and use vias

to connect the capacitors to the power and ground planes. In

addition, use wide, short traces between each via and the

capacitor pad, or place the vias adjacent to the capacitor pad to

minimize parasitic inductances. The AD7656A-1 offers the user a

reduced decoupling solution that is pin and software compatible

with the AD7656A. The recommended reduced decoupling

required for AD7656A-1 is outlined in Figure 24.

Rev. 0 | Page 24 of 28

Data Sheet AD7656A-1

OUTLINE DIMENSIONS

COMPLIANT TO JE DE C S TANDARDS MS- 026- BCD

051706-A

TOP VIEW

(PINS DOW N)

17 33

4964

0.27

0.22

0.17

0.50

BSC

LEAD P IT CH

12.20

12.00 SQ

11.80

PIN 1

1.60

MAX

0.75

0.60

0.45

10.20

10.00 SQ

9.80

VIEW A

0.20

0.09

1.45

1.40

1.35

0.08

COPLANARITY

VIEW A

ROTAT E D 90° CCW

SEATING

PLANE

0.15

0.05

7°

3.5°

0°

Figure 35. 64-Lead Low Profile Quad Flat Package [LQFP]

(ST-64-2)

Dimensions shown in millimeters

ORDERING GUIDE

Model1 Temperature Range Package Description Package Option

AD7656A-1BSTZ −40°C to +85°C 64-Lead Low Profile Quad Flat Package [LQFP] ST-64-2

AD7656A-1BSTZ-RL −40°C to +85°C 64-Lead Low Profile Quad Flat Package [LQFP] ST-64-2

1 Z = RoHS Compliant Part.

Rev. 0 | Page 25 of 28

AD7656A-1 Data Sheet

Rev. 0 | Page 26 of 28

NOTES

Data Sheet AD7656A-1

NOTES

Rev. 0 | Page 27 of 28

AD7656A-1 Data Sheet

NOTES

registered trademarks are the property of their respective owners.

D11128-0-12/13(0)

Rev. 0 | Page 28 of 28