1
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IDT2309B
3.3V ZERO DELAY CLOCK BUFFER
AUGUST 2012
2012 Integrated Device Technology, Inc. DSC 6996/3c
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FEATURES:
• Phase-Lock Loop Clock Distribution
• 10MHz to 133MHz operating frequency
• Distributes one clock input to one bank of five and one bank of
four outputs
• Separate output enable for each output bank
• Output Skew < 250ps
• Low jitter <175 ps cycle-to-cycle
• 50ps typical cycle-to-cycle jitter (15pF, 66MHz)
• IDT2309B-1 for Standard Drive
• IDT2309B-1H for High Drive
• No external RC network required
• Operates at 3.3V VDD
• Available in SOIC and TSSOP packages
FUNCTIONAL BLOCK DIAGRAM
IDT2309B
3.3V ZERO DELAY
CLOCK BUFFER
DESCRIPTION:
The IDT2309B is a high-speed phase-lock loop (PLL) clock buffer,
designed to address high-speed clock distribution applications. The zero
delay is achieved by aligning the phase between the incoming clock and
the output clock, operable within the range of 10 to 133MHz.
The IDT2309B is a 16-pin version of the IDT2305B. The IDT2309B
accepts one reference input, and drives two banks of four low skew clocks.
The -1H version of this device operates at up to 133MHz frequency and
has higher drive than the -1 device. All parts have on-chip PLLs which lock
to an input clock on the REF pin. The PLL feedback is on-chip and is
obtained from the CLKOUT pad. In the absence of an input clock, the
IDT2309B enters power down, and the outputs are tri-stated. In this mode,
the device will draw less than 25µA.
The IDT2309B is characterized for both Industrial and Commercial
operation.
PLL
S1
CLKA1
CLKA2
CLKA3
CLKA4
CLKB1
CLKB2
CLKB3
CLKB4
Control
Logic
1
REF
S2
16 CLKOUT
8
9
2
3
14
15
6
7
10
11
2
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IDT2309B
3.3V ZERO DELAY CLOCK BUFFER
PIN CONFIGURATION
SOIC/ TSSOP
TOP VIEW
Symbol Rating Max. Unit
VDD Supply Voltage Range –0.5 to +4.6 V
VI (2) Input Voltage Range (REF) –0.5 to +5.5 V
VIInput Voltage Range –0.5 to V
(except REF) VDD+0.5
IIK (VI < 0) Input Clamp Current –50 mA
IO (VO = 0 to VDD) Continuous Output Current ±50 mA
VDD or G N D Continuous Current ±100 mA
TA = 55°C Maximum Power Dissipation 0 .7 W
(in still air)(3)
TSTG Storage Temperature Range –65 to +150 °C
Operating Commercial Temperature 0 to +70 °C
Temperature Range
Operating Industrial Temperature -40 to +85 °C
Temperature Range
NOTES:
1 . Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2 . The input and output negative-voltage ratings may be exceeded if the input and output
clamp-current ratings are observed.
3. The maximum package power dissipation is calculated using a junction temperature
of 150°C and a board trace length of 750 mils.
NOTES:
1. Weak pull down on all outputs.
2. Weak pull ups on these inputs.
PIN DESCRIPTION
ABSOLUTE MAXIMUM RATINGS(1)
Pin Name Pin Number Type Functional Description
REF 1 IN Input reference clock, 5 Volt tolerant input
CLKA1(1) 2 O u t Output clock for bank A
CLKA2(1) 3 O u t Output clock for bank A
VDD 4, 13 PWR 3.3V Supply
GND 5, 12 GND Ground
CLKB1(1) 6 O u t Output clock for bank B
CLKB2(1) 7 O u t Output clock for bank B
S2(2) 8 IN Select input Bit 2
S1(2) 9 IN Select input Bit 1
CLKB3(1) 10 O u t Output clock for bank B
CLKB4(1) 11 O u t Output clock for bank B
CLKA3(1) 14 O u t Output clock for bank A
CLKA4(1) 15 O u t Output clock for bank A
CLKOUT(1) 1 6 Out Output clock, internal feedback on this pin
APPLICATIONS:
•SDRAM
•Telecom
•Datacom
•PC Motherboards/Workstations
•Critical Path Delay Designs
REF
CLKA1
S2
2
3
4
5
6
7
89
10
11
12
13
14
15
161
CLKA2
GND
CLKB1
CLKOUT
CLKA4
GND
S1
VDD
VDD
CLKB2 CLKB3
CLKB4
CLKA3
3
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IDT2309B
3.3V ZERO DELAY CLOCK BUFFER
DC ELECTRICAL CHARACTERISTICS - COMMERCIAL
Symbol Parameter Conditions Min. Max. Unit
VIL Input LOW Voltage Level — 0.8 V
VIH Input HIGH Voltage Level 2 — V
IIL Input LOW Current VIN = 0V — 50 µ A
IIH Input HIGH Current VIN = VDD — 100 µA
VOL Output LOW Voltage Standard Drive IOL = 8mA — 0.4 V
High Drive IOL = 12mA (-1H)
VOH Output HIGH Voltage Standard Drive IOH = -8mA 2.4 — V
High Drive IOH = -12mA (-1H)
IDD_PD Power Down Current REF = 0MHz (S2 = S1 = H) — 12 µ A
IDD Supply Current Unloaded Outputs at 66.66MHz, SEL inputs at VDD or GND — 3 2 mA
SWITCHING CHARACTERISTICS (2309B-1) - COMMERCIAL(1,2)
Symbol Parameter Conditions Min. Typ. Max. Unit
t1Output Frequency 10pF Load 10 — 133 MHz
30pF Load 10 — 100
Duty Cycle = t2 ÷ t1Measured at 1.4V, FOUT = 66.66MHz 40 50 60 %
t3Rise Time Measured between 0.8V and 2V — — 2. 5 ns
t4Fall Time Measured between 0.8V and 2V — — 2. 5 ns
t5Output to Output Skew All outputs equally loaded — — 250 ps
t6A Delay, REF Rising Edge to CLKOUT Rising Edge(2) Measured at VDD/2 — 0 ±350 ps
t6B Delay, REF Rising Edge to CLKOUT Rising Edge(2) Measured at VDD/2 in PLL bypass mode (IDT2309B only) 1 5 8.7 ns
t7Device-to-Device Skew Measured at VDD/2 on the CLKOUT pins of devices — 0 7 0 0 p s
tJCycle-to-Cycle Jitter Measured at 66.66MHz, loaded outputs — 50 175 ps
tLOCK PLL Lock Time Stable power supply, valid clock presented on REF pin — — 1 ms
NOTES:
1. REF Input has a threshold voltage of VDD/2.
2. All parameters specified with loaded outputs.
Symbol Parameter Min. Max. Unit
VDD Supply Voltage 3 3.6 V
TAOperating Temperature (Ambient Temperature) 0 70 °C
CLLoad Capacitance < 100MHz — 3 0 pF
Load Capacitance 100MHz - 133MHz — 1 0
CIN Input Capacitance — 7 pF
OPERATING CONDITIONS - COMMERCIAL
FUNCTION TABLE(1)
S2 S1 CLKA CLKB CLKOUT(2) Output Source PLL Shut Down
L L Tri-State Tri-State Driven PLL N
L H Driven Tri-State Driven PLL N
H L Driven Driven Driven REF Y
H H Driven Driven Driven PLL N
NOTES:
1 . H = HIGH Voltage Level.
L = LOW Voltage Level
2. This output is driven and has an internal feedback for the PLL. The load on this ouput can be adjusted to change the skew between the REF and the output.
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COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IDT2309B
3.3V ZERO DELAY CLOCK BUFFER
SWITCHING CHARACTERISTICS (2309B-1H) - COMMERCIAL(1,2)
Symbol Parameter Conditions Min. Typ. Max. Unit
t1Output Frequency 10pF Load 10 — 133 MHz
30pF Load 10 — 100
Duty Cycle = t2 ÷ t1Measured at 1.4V, FOUT = 66.66MHz 40 50 60 %
Duty Cycle = t2 ÷ t1Measured at 1.4V, FOUT <50MHz 45 50 55 %
t3Rise Time Measured between 0.8V and 2V — — 1.5 ns
t4Fall Time Measured between 0.8V and 2V — — 1.5 ns
t5Output to Output Skew All outputs equally loaded — — 250 ps
t6A Delay, REF Rising Edge to CLKOUT Rising Edge Measured at VDD/2 — 0 ±350 ps
t6B Delay, REF Rising Edge to CLKOUT Rising Edge Measured at VDD/2 in PLL bypass mode (IDT2309 only) 1 5 8.7 ns
t7Device-to-Device Skew Measured at VDD/2 on the CLKOUT pins of devices — 0 7 0 0 p s
t8Output Slew Rate Measured between 0.8V and 2V using Test Circuit 2 1 — — V/ns
tJCycle-to-Cycle Jitter Measured at 66.66MHz, loaded outputs — — 175 ps
tLOCK PLL Lock Time Stable power supply, valid clock presented on REF pin — — 1 ms
NOTES:
1. REF Input has a threshold voltage of VDD/2.
2. All parameters specified with loaded outputs.
DC ELECTRICAL CHARACTERISTICS - INDUSTRIAL
Symbol Parameter Conditions Min. Max. Unit
VIL Input LOW Voltage Level — 0.8 V
VIH Input HIGH Voltage Level 2 — V
IIL Input LOW Current VIN = 0V — 50 µA
IIH Input HIGH Current VIN = VDD — 100 µA
VOL Output LOW Voltage Standard Drive IOL = 8mA — 0.4 V
High Drive IOL = 12mA (-1H)
VOH Output HIGH Voltage Standard Drive IOH = -8mA 2.4 — V
High Drive IOH = -12mA (-1H)
IDD_PD Power Down Current REF = 0MHz (S2 = S1 = H) — 25 µ A
IDD Supply Current Unloaded Outputs at 66.66MHz, SEL inputs at VDD or GND — 3 5 mA
Symbol Parameter Min. Max. Unit
VDD Supply Voltage 3 3.6 V
TAOperating Temperature (Ambient Temperature) -40 +85 °C
CLLoad Capacitance < 100MHz — 3 0 pF
Load Capacitance 100MHz - 133MHz — 1 0
CIN Input Capacitance — 7 pF
OPERATING CONDITIONS - INDUSTRIAL
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COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IDT2309B
3.3V ZERO DELAY CLOCK BUFFER
SWITCHING CHARACTERISTICS (2309B-1H) - INDUSTRIAL(1,2)
Symbol Parameter Conditions Min. Typ. Max. Unit
t1Output Frequency 10pF Load 10 — 133 MHz
30pF Load 10 — 100
Duty Cycle = t2 ÷ t1Measured at 1.4V, FOUT = 66.66MHz 40 50 60 %
Duty Cycle = t2 ÷ t1Measured at 1.4V, FOUT <50MHz 45 50 55 %
t3Rise Time Measured between 0.8V and 2V — — 1.5 ns
t4Fall Time Measured between 0.8V and 2V — — 1.5 ns
t5Output to Output Skew All outputs equally loaded — — 250 ps
t6A Delay, REF Rising Edge to CLKOUT Rising Edge Measured at VDD/2 — 0 ±350 ps
t6B Delay, REF Rising Edge to CLKOUT Rising Edge Measured at VDD/2 in PLL bypass mode (IDT2309B only) 1 5 8.7 ns
t7Device-to-Device Skew Measured at VDD/2 on the CLKOUT pins of devices — 0 7 0 0 p s
t8Output Slew Rate Measured between 0.8V and 2V using Test Circuit 2 1 — — V/ns
tJCycle-to-Cycle Jitter Measured at 66.66MHz, loaded outputs — — 1 75 ps
tLOCK PLL Lock Time Stable power supply, valid clock presented on REF pin — — 1 ms
NOTES:
1. REF Input has a threshold voltage of VDD/2.
2. All parameters specified with loaded outputs.
SWITCHING CHARACTERISTICS (2309B-1) - INDUSTRIAL(1,2)
Symbol Parameter Conditions Min. Typ. Max. Unit
t1Output Frequency 10pF Load 10 — 133 MHz
30pF Load 10 — 100
Duty Cycle = t2 ÷ t1Measured at 1.4V, FOUT = 66.66MHz 40 50 60 %
t3Rise Time Measured between 0.8V and 2V — — 2. 5 ns
t4Fall Time Measured between 0.8V and 2V — — 2. 5 ns
t5Output to Output Skew All outputs equally loaded — — 250 ps
t6A Delay, REF Rising Edge to CLKOUT Rising Edge Measured at VDD/2 — 0 ±350 ps
t6B Delay, REF Rising Edge to CLKOUT Rising Edge Measured at VDD/2 in PLL bypass mode (IDT2309B only) 1 5 8.7 ns
t7Device-to-Device Skew Measured at VDD/2 on the CLKOUT pins of devices — 0 7 0 0 p s
tJCycle-to-Cycle Jitter Measured at 66.66MHz, loaded outputs — 50 175 ps
tLOCK PLL Lock Time Stable power supply, valid clock presented on REF pin — — 1 ms
NOTES:
1. REF Input has a threshold voltage of VDD/2.
2. All parameters specified with loaded outputs.
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COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IDT2309B
3.3V ZERO DELAY CLOCK BUFFER
ZERO DELAY AND SKEW CONTROL
All outputs should be uniformly loaded in order to achieve Zero I/O Delay. Since the CLKOUT pin is the internal feedback for the PLL, its relative
loading can affect and adjust the input/output delay. The Output Load Difference diagram illustrates the PLL's relative loading with respect to the other
outputs that can adjust the Input-Output (I/O) Delay.
For designs utilizing zero I/O Delay, all outputs including CLKOUT must be equally loaded. Even if the output is not used, it must have a capacitive
load equal to that on the other outputs in order to obtain true zero I/O Delay. If I/O Delay adjustments are needed, use the Output Load Difference diagram
to calculate loading differences between the CLKOUT pin and other outputs. For zero output-to-output skew, all outputs must be loaded equally.
REF TO CLKA/CLKB RELAY vs. OUTPUT LOAD DIFFERENCE BETWEEN CLKOUT PIN AND CLKA/CLKB PINS
REF to CLKA/CLKB Delay (ps)
OUTPUT LOAD DIFFERENCE BETWEEN CLKOUT PIN AND CLKA/CLKB PINS (pF)
1500
1000
500
0
-500
-1000
-1500
-30 -25 -20 -15 -10 -5 0510 15 20 25 30
7
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IDT2309B
3.3V ZERO DELAY CLOCK BUFFER
VDD
OUTPUTS
CLKOUT
CLOAD
VDD
GND GND
0.1 F
0.1 F
VDD
OUTPUTS
10pF
VDD
GND GND
0.1 F
0.1 F
1K
1K CLKOUT
Output 1.4V
1.4V
t5
Output
REF VDD/2
t6
Output
CLKOUT
Device 1
t7
CLKOUT
Device 2
VDD/2
VDD/2
VDD/2
1.4V
1.4V
t2
t1
1.4V
2V
0.8V
t3 t4
0.8V 3.3V
0V
2V
Output
All Outputs Rise/Fall Time Input to Output Propagation Delay
Device to Device Skew
Output to Output Skew
Duty Cycle Timing
SWITCHING WAVEFORMS
Test Circuit 1 (all Parameters Except t8) Test Circuit 2 (t8, Output Slew Rate On -1H Devices)
TEST CIRCUITS
8
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IDT2309B
3.3V ZERO DELAY CLOCK BUFFER
TYPICAL DUTY CYCLE(1) AND IDD TRENDS(2) FOR IDT2309B-1
NOTES:
1. Duty Cycle is taken from typical chip measured at 1.4V.
2. IDD data is calculated from IDD = ICORE + nCVf, where ICORE is the unloaded current. (n = Number of outputs; C = Capacitance load per output (F);
V = Supply Voltage (V); f = Frequency (Hz))
33.1 3.2 3.3 3.4 3.5 3.6
VDD (V)
40
42
44
46
48
50
52
54
56
58
60
Duty Cycle vs VDD
(for 30pf loads over frequency - 3.3V, 25C)
33MHz
66MHz
100MHz
Duty Cycle (%)
33.1 3.2 3.3 3.4 3.5 3.6
VDD (V)
40
42
44
46
48
50
52
54
56
58
60
Duty Cycle vs VDD
(for 10pF loads over frequency - 3.3V, 25C)
33MHz
66MHz
100MHz
20 40 60 80 100 120 140
Frequency (MHz)
40
42
44
46
48
50
52
54
56
58
60
Duty Cycle vs Frequency
(for 30pf loads over temperature - 3.3V)
-40C
0C
25C
70C
85C
Duty Cycle (%)
Duty Cycle (%)
133MHz
20 40 60 80 100 120 140
Frequency (MHz)
40
42
44
46
48
50
52
54
56
58
60
Duty Cycle vs Frequency
(for 10pF loads over temperature - 3.3V)
-40C
0C
25C
70C
85C
Duty Cycle (%)
02
468
Number of Loaded Outputs
0
20
40
60
80
100
120
140
IDD vs Number of Loaded Outputs
(for 30pf loads over frequency - 3.3V, 25C)
33MHz
66MHz
100MHz
IDD (mA)
02
468
Number of Loaded Outputs
0
20
40
60
80
100
120
140
IDD vs Number of Loaded Outputs
(for 10pF loads over frequency - 3.3V, 25C)
33MHz
66MHz
100MHz
IDD (mA)
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COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IDT2309B
3.3V ZERO DELAY CLOCK BUFFER
TYPICAL DUTY CYCLE(1) AND IDD TRENDS(2) FOR IDT2309B-1H
NOTES:
1. Duty Cycle is taken from typical chip measured at 1.4V.
2. IDD data is calculated from IDD = ICORE + nCVf, where ICORE is the unloaded current. (n = Number of outputs; C = Capacitance load per output (F); V = Supply Voltage (V);
f = Frequency (Hz))
33.1 3.2 3.3 3.4 3.5 3.6
VDD (V)
40
42
44
46
48
50
52
54
56
58
60
Duty Cycle vs VDD
(for 30pf loads over frequency - 3.3V, 25C)
33MHz
66MHz
100MHz
Duty Cycle (%)
33.1 3.2 3.3 3.4 3.5 3.6
VDD (V)
40
42
44
46
48
50
52
54
56
58
60
Duty Cycle vs VDD
(for 10pF loads over frequency - 3.3V, 25C)
33MHz
66MHz
100MHz
20 40 60 80 100 120 140
Frequency (MHz)
40
42
44
46
48
50
52
54
56
58
60
Duty Cycle vs Frequency
(for 30pf loads over temperature - 3.3V)
-40C
0C
25C
70C
85C
Duty Cycle (%)
Duty Cycle (%)
133MHz
20 40 60 80 100 120 140
Frequency (MHz)
40
42
44
46
48
50
52
54
56
58
60
Duty Cycle vs Frequency
(for 10pF loads over temperature - 3.3V)
-40C
0C
25C
70C
85C
Duty Cycle (%)
02
468
Number of Loaded Outputs
0
20
40
60
80
100
120
140
IDD vs Number of Loaded Outputs
(for 30pf loads over frequency - 3.3V, 25C)
33MHz
66MHz
100MHz
IDD (mA)
02
468
Number of Loaded Outputs
0
20
40
60
80
100
120
140
IDD vs Number of Loaded Outputs
(for 10pF loads over frequency - 3.3V, 25C)
33MHz
66MHz
100MHz
IDD (mA)
160
160
10
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IDT2309B
3.3V ZERO DELAY CLOCK BUFFER
ORDERING INFORMATION
Ordering Code Package Type Operating Range
IDT2309B-1DCG 16-Pin SOIC Commercial
IDT2309B-1DCGI 16-Pin SOIC Industrial
IDT2309B-1HDCG 16-Pin SOIC Commercial
IDT2309B-1HDCGI 16-Pin SOIC Industrial
IDT2309B-1HPGGI 16-Pin TSSOP Industrial
IDT2309B-1HPGG 16-Pin TSSOP Commercial
IDT XXXXX XX X
Package Process
Device Type
Blank
I
2309B-1
2309B-1H
Commercial (0oC to +70oC)
Industrial (-40oC to +85oC)
Zero Delay Clock Buffer
High Drive Output
Small Outline
SOIC - Green
Thin Shrink Small Outline Package
DC
DCG
PG
CORPORATE HEADQUARTERS for SALES: for Tech Support:
6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 clockhelp@idt.com
San Jose, CA 95138 fax: 408-284-2775
www.idt.com
PGG TSSOP - Green
