Publication# 08140 Rev. HAmendment/0
Issue Date: May 1995
2-44
Advanced
Micro
Devices
Am27C512
512 Kilobit (65,536 x 8-Bit) CMOS EPROM
FINAL
DISTINCTIVE CHARACTERISTICS
■Fast access time
—55 ns
■Low power consumption
—20 µA typical CMOS standby current
■JEDEC-approved pinout
■Single +5 V power supply
■±10% power supply tolerance available
■100% Flashrite programming
— Typical programming time of 8 seconds
■Latch-up protected to 100 mA from –1 V to
VCC + 1 V
■High noise immunity
■Versatile features for simple interfacing
— Both CMOS and TTL input/output
compatibility
— Two line control functions
■Standard 28-pin DIP, PDIP, 32-pin TSOP, and
PLCC packages
GENERAL DESCRIPTION
The Am27C512 is a 512 K-bit ultraviolet erasable pro-
grammable read-only memory. It is organized as 64K
words by 8 bits per word, operates from a single +5 V
supply, has a static standby mode, and features fast sin-
gle address location programming. Products are avail-
able in windowed ceramic DIP packages as well as plas-
tic one time programmable (OTP) PDIP, TSOP, and
PLCC packages.
Typically, any byte can be accessed in less than 55 ns,
allowing operation with high-performance microproces-
sors without any WAIT states. The Am27C512 offers
separate Output Enable (OE) and Chip Enable (CE)
controls, thus eliminating bus contention in a multiple
bus microprocessor system.
AMD’s CMOS process technology provides high speed,
low power, and high noise immunity. Typical power con-
sumption is only 80 mW in active mode, and 100 µW in
standby mode.
All signals are TTL levels, including programming sig-
nals. Bit locations may be programmed singly, in blocks,
or at random. The Am27C512 supports AMD’s Flashrite
programming algorithm (100 µs pulses) resulting in a
typical programming time of 8 seconds.
BLOCK DIAGRAM
VSS
VCC
Output Enable
Chip Enable
and
Prog Logic
Y
Decoder
X
Decoder
CE
OE/VPP Output
Buffers
Y
Gating
524,288
Bit Cell
Matrix
A0–A15
Address
Inputs
Data Outputs
DQ0–DQ7
08140H-1
AMD
2-45
Am27C512
PRODUCT SELECTOR GUIDE
Family Part No. Am27C512
Ordering Part No:
VCC ± 5% -55 -255
VCC ± 10% -70 -90 -120 -150 -200
Max Access Time (ns) 55 70 90 120 150 200 250
CE (E) Access Time (ns) 55 70 90 120 150 200 250
OE (G) Access Time (ns) 55 40 40 50 50 75 75
CONNECTION DIAGRAMS
Top View DIP
Notes:
1. JEDEC nomenclature is in parentheses.
PLCC
A15 VCC
A9
A11
A12 A14
A8
DQ7
1
3
5
7
9
11
12
10
2
4
8
6
13
14
28
26
24
22
20
18
17
19
27
25
21
23
16
15
A7
A6
A5
A4
A3
A2
A1
A0
VSS
DQ2
DQ1
DQ0
OE (G)/VPP
A10
CE (E)
DQ6
DQ5
DQ4
DQ3
A13
08140H-2
08140H-3
13130234
5
6
7
8
9
10
11
12
13 17 18 19 20161514
29
28
27
26
25
24
23
22
21
32
A6
A5
A4
A3
A2
A1
A0
NC
DQ0
A8
A9
A11
NC
OE (G)
A10
CE (E)
DQ7
A7
A12
A15
DU
VCC
A14
A13
DQ1
DQ2
VSS
DU
DQ3
DQ4
DQ5
DQ6
/VPP
TSOP*
08140H-4
*Contact local AMD sales office for package availability.
1
16
2
3
4
5
6
7
8
9
10
11
12
13
14
15
32
17
31
30
29
28
27
26
25
24
23
22
21
20
19
18
OE/VPP
A11
A9
A8
A13
NC
A14
VCC
A15
NC
A12
A7
A6
A5
A4
A3
NC
A10
CE/PGM
O7
O6
O5
O4
O3
O2
VSS
O1
O0
NC
A0
A1
A2
Standard Pinout
AMD
2-46 Am27C512
LOGIC SYMBOLPIN DESIGNATIONS
A0–A15
CE (E)
OE (G)/VPP
8
DQ0–DQ7
A0–A15 = Address Inputs
CE (E) = Chip Enable Input
DQ0–DQ7 = Data Inputs/Outputs
DU = No External Connection
(Do Not Use)
NC = No Internal Connection
OE (G)/VPP = Output Enable Input/
Program Voltage Input
VCC =VCC Supply Voltage
VSS = Ground
08140H-5
16
AMD
2-47
Am27C512
ORDERING INFORMATION
UV EPROM Products
PACKAGE TYPE
D = 28-Pin Ceramic DIP (CDV028)
Valid Combinations
AMD Standard products are available in several packages and operating ranges. The order number (Valid Combination) is
formed by a combination of:
BCD-55AM27C512
OPTIONAL PROCESSING
Blank = Standard Processing
B = Burn-in
TEMPERATURE RANGE
C = Commercial (0°C to +70°C)
I = Industrial (–40°C to +85°C)
E = Extended Commercial (–55°C to +125°C)
SPEED OPTION
See Product Selector Guide and Valid Combinations
DEVICE NUMBER
Am27C512
512 Kilobit (65,536 x 8-Bit) CMOS UV EPROM
AM27C512-70 DC, DCB
AM27C512-90
AM27C512-120
AM27C512-150
AM27C512-200
AM27C512-250
AM27C512-255
DC, DCB, DI, DIB,
DE, DEB
Valid Combinations
Valid Combinations list configurations planned to be
supported in volume for this device. Consult the lo-
cal AMD sales office to confirm availability of specific
valid combinations and to check on newly released
combinations.
AM27C512-55 DC
DC, DCB, DI, DIB
AMD
2-48 Am27C512
ORDERING INFORMATION
OTP Products
DEVICE NUMBER
Am27C512
512 Kilobit (65,536 x 8-Bit) CMOS OTP EPROM
Valid Combinations list configurations planned to be
supported in volume for this device. Consult the lo-
cal AMD sales office to confirm availability of specific
valid combinations and to check on newly released
combinations.
Valid Combinations
AM27C512-70
AM27C512-90
AM27C512-120
AM27C512-150
AM27C512-200
AM27C512-255
PACKAGE TYPE
P = 28-Pin Plastic DIP (PD 028)
J = 32-Pin Rectangular Plastic Leaded Chip
Carrier (PL 032)
E = 32-Pin TSOP (TS 032)
AMD Standard products are available in several packages and operating ranges. The order number (Valid Combination) is
formed by a combination of:
Valid Combinations
CP-70AM27C512
OPTIONAL PROCESSING
Blank = Standard Processing
TEMPERATURE RANGE
C = Commercial (0°C to +70°C)
I = Industrial (–40°C to + 85°C)
SPEED OPTION
See Product Selector Guide and Valid Combinations
PC, JC, EC
PI, JI, EI
AMD
2-49
Am27C512
FUNCTIONAL DESCRIPTION
Erasing the Am27C512
In order to clear all locations of their programmed con-
tents, it is necessary to expose the Am27C512 to an
ultraviolet light source. A dosage of 15 W seconds/cm2
is required to completely erase an Am27C512. This
dosage can be obtained by exposure to an ultraviolet
lamp—wavelength of 2537 A
°—with intensity of
12,000 µW/cm2
for 15 to 20 minutes. The Am27C512
should be directly under and about one inch from the
source and all filters should be removed from the UV
light source prior to erasure.
It is important to note that the Am27C512 and similar
devices will erase with light sources having wavelengths
shorter than 4000 A
°. Although erasure times will be
much longer than with UV sources at 2537 A
°, exposure
to fluorescent light and sunlight will eventually erase the
Am27C512 and exposure to them should be prevented
to realize maximum system reliability. If used in such an
environment, the package window should be covered
by an opaque label or substance.
Programming the Am27C512
Upon delivery or after each erasure the Am27C512 has
all 524,288 bits in the “ONE” or HIGH state. “ZEROs”
are loaded into the Am27C512 through the procedure
of programming.
The programming mode is entered when 12.75 V ± 0.25
V is applied to the OE/VPP and CE is at VIL.
For programming, the data to be programmed is applied
8 bits in parallel to the data output pins.
The Flashrite algorithm reduces programming time by
using 100 µs programming pulses and by giving each
address only as many pulses as is necessary in order to
reliably program the data. After each pulse is applied to
a given address, the data in that address is verified. If
the data does not verify, additional pulses are given until
it verifies or the maximum is reached. This process is re-
peated while sequencing through each address of the
Am27C512. This part of the algorithm is done at
VCC = 6.25 V to assure that each EPROM bit is pro-
grammed to a sufficiently high threshold voltage. After
the final address is completed, the entire EPROM mem-
ory is verified at VCC = 5.25 V.
Please refer to Section 6 for programming flow chart
and characteristics.
Program Inhibit
Programming of multiple Am27C512 in parallel with dif-
ferent data is also easily accomplished. Except for CE,
all like inputs of the parallel Am27C512 may be com-
mon. A TTL low-level program pulse applied to an
Am27C512 CE input and OE/VPP = 12.75 V ± 0.25 V, will
program that Am27C512. A high-level CE input inhibits
the other Am27C512 devices from being programmed.
Program Verify
A verify should be performed on the programmed bits to
determine that they were correctly programmed. The
verify should be performed with CE at VIL and OE/VPP
at VIL. Data should be verified tDV after the falling edge
of CE.
Auto Select Mode
The auto select mode allows the reading out of a binary
code from an EPROM that will identify its manufacturer
and type. This mode is intended for use by programming
equipment for the purpose of automatically matching
the device to be programmed with its corresponding
programming algorithm. This mode is functional in the
25°C ± 5°C ambient temperature range that is required
when programming the Am27C512.
To activate this mode, the programming equipment
must force 12.0 ± 0.5 V on address line A9 of the
Am27C512. Two identifier bytes may then be se-
quenced from the device outputs by toggling address
line A0 from VIL to VIH. All other address lines must be
held at VIL during auto select mode.
Byte 0 (A0 = VIL) represents the manufacturer code, and
byte 1 (A0 = VIH), the device code. For the Am27C512,
these two identifier bytes are given in the Mode Select
Table. All identifiers for manufacturer and device codes
will possess odd parity, with the MSB (DQ7) defined as
the parity bit.
Read Mode
The Am27C512 has two control functions, both of which
must be logically satisfied in order to obtain data at the
outputs. Chip Enable (CE) is the power control and
should be used for device selection. Output Enable
(OE/VPP) is the output control and should be used to
gate data to the output pins, independent of device se-
lection. Assuming that addresses are stable, address
access time (tACC) is equal to the delay from CE to out-
put (tCE). Data is available at the outputs tOE after the fall-
ing edge of OE/VPP, assuming that CE has been LOW
and addresses have been stable for at least tACC–tOE.
Standby Mode
The Am27C512 has a CMOS standby mode which re-
duces the maximum VCC current to 100 µA. It is placed in
CMOS-standby when CE is at VCC ± 0.3 V. The
Am27C512 also has a TTL-standby mode which re-
duces the maximum VCC current to 1.0 mA. It is placed in
TTL-standby when CE is at VIH. When in standby mode,
the outputs are in a high-impedance state, independent
of the OE input.
AMD
2-50 Am27C512
Output OR-Tieing
To accommodate multiple memory connections, a two-
line control function is provided to allow for:
■Low memory power dissipation
■Assurance that output bus contention will not occur
It is recommended that CE be decoded and used as the
primary device-selecting function, while OE/VPP be
made a common connection to all devices in the array
and connected to the READ line from the system control
bus. This assures that all deselected memory devices
are in low-power standby mode and that the output pins
are only active when data is desired from a particular
memory device.
System Applications
During the switch between active and standby condi-
tions, transient current peaks are produced on the rising
and falling edges of Chip Enable. The magnitude of
these transient current peaks is dependent on the out-
put capacitance loading of the device. At a minimum, a
0.1-µF ceramic capacitor (high frequency, low inherent
inductance) should be used on each device between
VCC and VSS to minimize transient effects. In addition, to
overcome the voltage drop caused by the inductive ef-
fects of the printed circuit board traces on EPROM ar-
rays, a 4.7-µF bulk electrolytic capacitor should be used
between VCC and VSS for each eight devices. The loca-
tion of the capacitor should be close to where the power
supply is connected to the array.
MODE SELECT TABLE
CE OE/VPP A0 A9 Outputs
Read VIL VIL XXD
OUT
Output Disable X VIH X X Hi-Z
Standby (TTL) VIH X X X Hi-Z
Standby (CMOS) VCC ± 0.3 V X X X Hi-Z
Program VIL VPP XXD
IN
Program Verify VIL VIL XXD
OUT
Program Inhibit VIH VPP X X Hi-Z
Manufacturer
Code VIL VIL VIL VH01H
Device Code VIL VIL VIH VH91H
Auto Select
(Note 3)
Mode Pins
Notes:
1. VH = 12.0
±
0.5 V
2. X = Either VIH or VIL
3. A1–A8 = A10–A15 = VIL
4. See DC Programming Characteristics for VPP voltage during programming.
AMD
2-51
Am27C512
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
OTP Products –65°C to +125°C. . . . . . . . . . . . . . .
All Other Products –65°C to +150°C. . . . . . . . . . . .
Ambient Temperature
with Power Applied –55°C to +125°C. . . . . . . . . . . . .
Voltage with Respect To VSS
All pins except A9,
VPP,VCC –0.6 V to VCC + 0.5 V. . . . . . . . . . . . . . .
A9 and VPP –0.6 V to +13.5 V. . . . . . . . . . . . . . . .
VCC –0.6 V to +7.0 V. . . . . . . . . . . . . . . . . . . . . . .
Notes:
1. Minimum DC voltage on input or I/O pins is –0.5 V. During
transitions, the inputs may overshoot V
SS
to –2.0 V for pe-
riods of up to 20 ns. Maximum DC voltage on input and I/O
pins is V
CC
+ 0.5 V which may overshoot to V
CC
+ 2.0 V for
periods up to 20ns.
2. For A9 and V
PP
the minimum DC input is –0.5 V. During
transitions, A9 and V
PP
may overshoot V
SS
to –2.0 V for
periods of up to 20 ns. A9 and V
PP
must not exceed 13.5 V
for any period of time .
Stresses above those listed under “Absolute Maximum Rat-
ings” may cause permanent damage to the device. This is a
stress rating only; functional operation of the device at these
or any other conditions above those indicated in the opera-
tional sections of this specification is not implied. Exposure of
the device to absolute maximum rating conditions for ex-
tended periods may affect device reliability.
OPERATING RANGES
Commercial (C) Devices
Ambient Temperature (TA)0°C to +70°C. . . . . . .
Industrial (I) Devices
Ambient Temperature (TA) –40°C to +85°C. . . . .
Extended Commercial (E) Devices
Ambient Temperature (TA) –55°C to +125°C. . . .
Supply Read Voltages
VCC for Am27C512-XX5 +4.75 V to +5.25 V. . . . .
VCC for Am27C512-XX0 +4.50 V to +5.50 V. . . . .
VCC for Am27C512-55 +4.75 V to +5.25 V. . . . . .
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
AMD
2-52 Am27C512
DC CHARACTERISTICS over operating range unless otherwise specified.
(Notes 1, 2 and 4)
Parameter
Symbol Parameter Description Test Conditions Min Max Unit
VOH Output HIGH Voltage IOH = –400 µA 2.4 V
VOL Output LOW Voltage IOL = 2.1 mA 0.45 V
VIH Input HIGH Voltage 2.0 VCC + 0.5 V
VIL Input LOW Voltage –0.5 +0.8 V
1.0 µA
ICC1 VCC Active Current CE = VIL, f = 10 MHz, IOUT = 0 mA, 30 mA
(Note 3)
ICC2 VCC TTL Standby Current CE = VIH 1.0 mA
ICC3 VCC CMOS Standby Current CE = VCC ± 0.3 V 100 µA
C/I Devices
E Devices
1.0
5.0
ILI Input Load Current VIN = 0 V to +VCC
µA
ILO Output Leakage Current VOUT = 0 V to +VCC
Notes:
1. V
CC
must be applied simultaneously or before V
PP
, and removed simultaneously or after V
PP
.
2. Caution: The Am27C512 must not be removed from (or inserted into) a socket when V
CC
or V
PP
is applied.
3. I
CC1
is tested with
OE
/V
PP
= V
IH
to simulate open outputs.
4. Minimum DC Input Voltage is –0.5 V. During transitions, the inputs may overshoot to –2.0 V for periods less than 20 ns.
Maximum DC Voltage on output pins is V
CC
+ 0.5 V, which may overshoot to V
CC
+ 2.0 V for periods less than 20 ns.
–75 –50 –25 0 25 50 75 100 125 150
30
25
20
15
10
Frequency in MHz
12345678910
30
25
20
15
10
Supply Current
in mA
Supply Current
in mA
Temperature in °C
Figure 1. Typical Supply Current
vs. Frequency
VCC = 5.5 V, T = 25°C
Figure 2. Typical Supply Current
vs. Temperature
VCC = 5.5 V, f = 10 MHz
08140H-6 08140H-7
AMD
2-53
Am27C512
CAPACITANCE
Parameter Test
Symbol Parameter Description Conditions Typ Max Typ Max Typ Max Typ Max Unit
CIN Input Capacitance VIN = 0 10 12 10 12 9 12 6 10 pF
COUT Output Capacitance VOUT = 0 12 14 10 13 9 12 6 10 pF
Notes:
1. This parameter is only sampled and not 100% tested.
2. T
A
= +25
°
C, f = 1 MHz
CDV028 PL 032 PD 028TS 032
SWITCHING CHARACTERISTICS over operating range unless otherwise specified
(Notes 1, 3, 4 and 5)
Parameter Test
JEDEC Standard Description Conditions -55 -70 -90 -120 -150 -200 -255 Unit
tAVQV tACC Address to CE = OE = Min – – – – – – –
Output Delay VIL Max 55 70 90 120 150 200 250 ns
tELQV tCE Chip Enable to OE = VIL Min – – – – – – –
Output Delay Max 55 70 90 120 150 200 250 ns
tGLQV tOE Output Enable to CE = VIL Min – – – – – – –
Output Delay Max 35 40 40 50 50 75 75 ns
tEHQZ tDF Min – – – – – – –
tGHQZ (Note 2) Max 25 25 30 30 30 30 30 ns
tAXQX tOH Output Hold from Min 0 0 0 0 0 0 0
Addresses, CE, Max – – – – – – – ns
or OE, whichever
occurred first
Parameter
Symbols Am27C512
Notes:
1. V
CC
must be applied simultaneously or before V
PP
, and removed simultaneously or after V
PP
.
2. This parameter is only sampled and not 100% tested.
3. Caution: The Am27C512 must not be removed from (or inserted into) a socket or board when V
PP
or V
CC
is applied.
4. Output Load: 1 TTL gate and C
L
= 100 pF
Input Rise and Fall Times: 20 ns
Input Pulse Levels: 0.45 V to 2.4 V
Timing Measurement Reference Level: 0.8 V and 2 V inputs and outputs
For the Am27C512-55:
Output Load: 1 TTL gate and C
L
= 30 pF
Input Rise and Fall Times: 20 ns
Input Pulse Levels: 0 V to 3 V
Timing Measurement Reference Level: 1.5 V for inputs and outputs
Chip Enable HIGH or
Output Enable HIGH,
whichever comes
first, to Output Float
AMD
2-54 Am27C512
SWITCHING TEST CIRCUIT
Device
Under
Test
CL
+5.0 V
CL = 100 pF including jig capacitance (30 pF for -55)
6.2 kΩ
2.7 kΩ
Diodes = IN3064
or Equivalent
08140H-8
SWITCHING TEST WAVEFORM
2.4 V
0.45 V
2.0 V
0.8 V 2.0 V
0.8 V
Test Points
Input Output
3 V
0 V 1.5 V 1.5 V
Input Output
Test Points
AC Testing: Inputs are driven at 2.4 V for a logic “1”
and 0.45 V for a logic “0”. Input pulse
rise and fall times are ≤ 20 ns.
08140H-9
AC Testing: Inputs are driven at 3.0 V for a logic “1”
and 0 V for a logic “0”. Input pulse rise and
fall times are ≤ 20 ns for -55 device.
AMD
2-55
Am27C512
KEY TO SWITCHING WAVEFORMS
Must Be
Steady
May
Change
from H to L
May
Change
from L to H
Does Not
Apply
Don’t Care
Any Change
Permitted
Will Be
Steady
Will Be
Changing
from H to L
Will Be
Changing
from L to H
Changing
State
Unknown
Center
Line is High
Impedence
“Off” State
WAVEFORM INPUTS OUTPUTS
KS000010
SWITCHING WAVEFORMS
Notes:
1.
OE
/VPP may be delayed up to tACC–tOE after the falling edge of the addresses without impact on tACC.
2. tDF is specified from
OE
or
CE
, whichever occurs first.
08140H-10
Addresses
CE
OE/VPP
Output
Addresses Valid
High Z High Z
tCE
Valid Output
2.4
0.45
2.0
0.8 2.0
0.8
tACC
(Note 1)
tOE tDF
(Note 2)
tOH
