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Using the HI5721 Evaluation Module
Introduction
The HI5721 is a 10-bit 125MHz Digital to Analog Converter.
This current out DAC is designed for low glitch and high Spu-
rious Free Dynamic Range operation. This DAC is ideally
suited for Signal Reconstruction and DDS (Direct Digital
Synthesis) applications due to it’s inherent low noise design.
Architecture
The HI5721 DAC is designed with a split architecture to min-
imize glitch while maximizing linearity. Figure 1 shows the
functional architecture of the device. The 6 least significant
bits of the converter are derived by a traditional R/2R net-
work to binaurally weight the 1mA current sources. The
upper 4, most significant bits are implemented as seg-
mented or thermometer encoded current sources. The ther-
mometer encoder converts the incoming 4 bits to 15 control
lines to enable the most significant current sources.
As shown in Figure 2 the thermometer encoder translates the
4 bit binary input data into a decode that enables individual
current sources. For example a binary code of 0110 on the
data bits D6 thru D9 will enable current sources I1, I2, I3, I4,
I5, and I6. The thermometer encoding architecture ensures
good linearity without laser trimming. Also, compared to a
straight R/2R design, the worst case glitch is greatly reduced
since creating the MSB current is the sum of current sources
I1 thru I8. Overall glitch is reduced by a factor of 16. This also
reduces the theoretical switching skew from current source to
current source by using identically sized switches with identi-
cal gain, leakage, and transient responses.
FIGURE 1. BLOCK DIAGRAM
UPPER
10-BIT
REGISTER
REF IN
IOUT
CLK
-AVEE AGND -DVEE DGND
4-BIT
DECODER
R/2R
NETWORK
VCC
IOUT
QUADRATURE
LOGIC
DATA
BUFFER/
LEVEL
SHIFTER
+
-CTRL AMP
REF OUT RSET CTRL AMP IN
25Ω
6 LSB’S
CURRENT
CELLS
15
SWITCHED
CURRENT
CELLS
VOLTAGE
REFERENCE
(LSB) D0
D1
D2
D3
D4
D5
D6
(MSB) D9
INVERT
D7
D8
OUT
Application Note May 1995 AN9410.1
2
FIGURE 2. THERMOMETER ENCODER
Designing to Minimize Glitch
One cause of Glitch is the time skew between bits of the
incoming digital data. Typically the switching time of digital
inputs are asymmetrical meaning that the turn off time is
faster than the turn on time. Unequal delay paths through the
device can cause one current source to change before
another. To minimize this, the Intersil HI5721 employes an
internal register just prior to the current sources updated on
the rising clock edge. In traditional DACs the worst case glitch
usually happens at the major transition i.e. 01 1111 1111 to
10 0000 0000. But in the HI5721 the worst case glitch is
moved to the 00 0001 1111 to 11 1110 0000 transition. This is
achieved by the split R/2R segmented current source archi-
tecture. This decreases the amount of current switching at any
one time and reduces the glitch by a factor of 16.
Since the glitch is a transient event, this leads designers to
believe that a simple low pass filter can be used to eliminate or
reduce the size of the glitch. In effect low pass filtering a glitch
tends to “smear” the event and does little to remove the energy of
the transient.
FIGURE 3. GLITCH AREA
Input Timing/Logic Levels
The HI5721 has a maximum clock rate specification of
100MHz. The data setup time before the 50% point of the
rising edge of the clock is tS= 1.2ns (MIN) and the hold time
is tH= 0.5ns (MIN). Logic levels are 0.8V (MAX) for an input
low and 2.0V (MIN) for a logic high. The HI5721 is both TTL
and CMOS input compatible.
FIGURE 4. HI5721 DATA TIMING
INVERT Control Pin
The INVERT control pin is used to enable the internal
quadrature logic on the data bits. The internal quadrature
logic feature is used to reduce the amount of memory store
in a given Numerically Controlled Oscillator (NCO). The
NCO need only store one quadrant of the sine wave data
and use the invert pin to create the remaining 3 quadrants of
the sine wave.
FIGURE 5. USING THE INTERNAL QUADRATURE LOGIC
To use the internal quadrature logic simply connect the
INVERT pin to bit D9 of the HI5721 DAC. In normal opera-
tion INVERT should be connected to 0V or Digital Ground.
BIT 9
(MSB)
I1
I2
I3
I4
I5
I6
I7
I8
I9
I10
I11
I12
I13
I14
I15
I16
SUMMING
JUNCTION (IOUT)
4-BIT BINARY
TO
THERMOMETER
ENCODER
BIT 8
BIT 7
BIT 6
V
t(ps)
HEIGHT (H)
WIDTH (W)
GLITCH AREA = 1/2 (H X W)
tH
tS
CLK
D9 - D0
D0
D1
D2
D3
D4
D5
D6
D7
D8
INV
D9
1 QUADRANT
DATA
OF SINE WAVE
Application Note 9410
3
Integral Linearity
The HI5721 has a FSR range of 20.48mA. When driving an
equivalent 50Ωload the fullscale voltage swing is 0V to +1.024V.
Most video and communication applications use a 1VP-P voltage
swing which yields 20mA full scale current sink capability. With a
1VP-P voltage s wing on the HI5721 output an LSB is:
LSB = Full Scale Range/(2N-1)
where N is the number of bits and the Full Scale Range is 1VP-P.
The LSB size for this application is 977µV. To determine the Inte-
gral Linearity of the HI5721 the bit weights of each major transi-
tion is taken. The Best Fit Straight Line method is used to
calculate the overall INL. Measurements are taken at bits 0 thru 6
at each bit transition. Then all combinations of the upper 4 bits
are measured. Finally some worst case codes are measured
and the full scale is measured. Once this is completed a best fit
straight line is drawn through the data points and the worst case
de viation is determined.
The worst case integral linearity of the HI5721 is specified to be
less than 1.5 LSBs. The linearity of the HI5721 is worst in the
segmented current sources in the thermometer encoded sec-
tion. This is due to the errors of each current source being
biased in one direction and being additive with increasing data
values. The R/2R resistor matching need be to a 6-bit level to
ensure overall 10-bit linearity. Process control of resistor match-
ing in the BiCMOS process used is easily adequate to do the
job. For the overall transfer function the typical INL perfor-
mance is shown in Figure 6.
FIGURE 6A. INL TYPICAL PERFORMANCE CURVE
FIGURE 6B. TYPICAL PERFORMANCE CURVE
FIGURE 6.
Differential Linearity and Missing Codes
For a D/A Converter the differential linearity is the step size
difference throughout the entire code range. For the HI5721
the step to step maximum difference is 1.0 LSBs. For any
given D/A converter, to guarantee no missing codes the con-
verter must be monotonic.
The definition of monotonicity is; as the input code is
increased the output should increase. When an input code is
increased and the output of the DAC does not increase or
reverses direction, then this converter is assumed to be
missing codes.
FIGURE 7. DNL EXAMPLE
Shown in Figure 7, as the input code increases the output
voltage should increase. When an error of greater than 1.0
LSB is incurred, that bit can be assumed to be a missing
code since the output did not increase but rather remained
the same.
0.25
0.20
0.15
0.10
0.05
0.00
-0.05
-0.10
DNL
CODE
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
INL
CODE
00
01
10
11
INPUT CODE GREATER THAN ZERO
OUTPUT
VOLTAGE
-0.5 LSB ERROR
(MISSING CODE)
GREATER THAN
ERROR
-1.0 LSB
Application Note 9410
4
Adjusting Full Scale
The RSET pin is used to set the Full Scale Output Current.
The output current is a function of the reference voltage
applied to the CONTROL AMP IN pin and the value of the
RSET resistor. To calculate the IOUT Full Scale Current use
the following formula:
IOUT Full Scale = 32 x (CONTROL AMP IN/RSET)
So where CONTROL AMP IN = 1.25V
and RSET = 1960Ω
IOUT = 20.4mA
To adjust the output full scale current, use a potentiometer in
rheostat mode as shown in Figure 8.
FIGURE 8. FULL SCALE OUTPUT APPLICATION CIRCUIT
The Control Amplifier
The internal Control Amplifier is used to buffer the internal or
an external reference. The precision current cells require an
adequate amount of drive to bias. The Control Amplifier
frees the user from having to provide an external amplifier.
The Evaluation Board
The HI5721 Evaluation board is a 1/2 size daughter board
designed to interface to the HSP-EVAL board. When used
together these boards create a flexible and powerful DDS sys-
tem. The HSP45116 board is used to generate the high speed
digital sine wave patterns for the D/A module. The HI5721
board reconstructs the incoming digital data to an analog rep-
resentation that can be analyzed on a spectrum analyzer or
oscilloscope.
Plugging In
After setting-up the HSP45116 board and the HI5721 board;
power should be applied to the banana jacks. A +5V, and a -
5.2V supply will be needed. To reduce noise the power sup-
ply leads should be twisted pairs.
Connect the interface cable to an IBM PC or compatible’s
parallel port. Power should be applied to the board and then
run the software directly from floppy disk. To run the software
place the floppy disk into drive A: and type:
A: NCOMCTRL
the HSP45116 Control Panel will be loaded. To exercise the
board the following parameters should be set:
BINFMT# = 0
and then set the Center Frequency to:
CENTER FREQUENCY = 01000000HEX
where the center frequency is in hex. At this point the output
of the HI5721 DAC module should be converting a sine wave
at 48KHz. Connect the output of the HI5721 module to an
oscilloscope.
The HI5721 module has Jumper plug for selecting the
INVERT feature of the HI5721. When J2 is installed, the
quadrature logic is disabled. When J2 is removed, the
quadrature logic is enabled and the DAC data will be 1’s
complemented.
DDS Interface
The HSP45116 board is a TTL/CMOS compatible logic
board. The HI5721 is a TTL/CMOS compatible logic D/A
converter. The design of the DAC module is to interface to
the 10 Most Significant Bits of the NCO. The HI5721 module
should be plugged into P2 of the HSP-EVAL board.
Spurious Free Dynamic Range
The Spurious Free Dynamic Range of the HI5721 DACs is
the most important specification for communication applica-
tions. This specification shows how Integral Linearity, Glitch,
and Switching noise affect the spectral purity of the output
signal. Several important things must be noted first.
When a quantized signal is reconstructed, certain artifacts are
created. Let’s take the example of trying to recreate a 1MHz
sine wave with a 1VP-P output. In the frequency domain the
fundamental should appear at 1MHz as shown in Figure 9.
FIGURE 9. FREQUENCY PLOT OF 1MHz TONE
The fundamental of a pure 1MHz tone should appear as an
impulse in the frequency domain at 1MHz. In a sampled sys-
tem noise terms are produced near the sampling frequen-
cies called aliases. These aliases are related to the
fundamental in that they are located at ±fNaround the sam-
pling frequency as shown in Figure 10.
RSET (17)
5KΩ
1960Ω
f
AMPLITUDE
(dB)
1MHz
0
-85
-50
NOISE FLOOR
FUNDAMENTAL
(PURE TONE)
fN
Application Note 9410
5
FIGURE 10. SAMPLING ALIAS PRODUCTS
So for a 1MHz fundamental and a 5MHz sampling rate an
alias term is created at 4MHz and 6MHz. A (SIN)/X function
shaping is also induced by sampling a signal. Aliases con-
tinue up through the frequency spectrum repeating around
the sampling frequency and its harmonics (i.e. 2fS,3f
S,4f
S).
A reconstructed sine wave out of the HI5721 is not ideal and
as such has harmonics of the fundamental. The difference
between the magnitude of the fundamental and the highest
noise spur whether it is harmonically related to the funda-
mental or not, is the definition of Spurious Free Dynamic
Range. Figures 11, through 16 are sample plots taken of the
HI5721 at various frequencies. Included are the oscilloscope
plots.
f
AMPLITUDE
(dB)
1MHz
0
-85
-50
FUNDAMENTAL
fS
4MHz
ALIAS
(fS - 1MHz)
SAMPLING FUNCTION
(SIN X)/X
fN
FIGURE 11A. OSCILLOSCOPE PLOT FIGURE 11B. SAMPLE PLOT
FIGURE 11. A 1MHz FUNDAMENTAL TO fS UNFILTERED
FIGURE 12. A 1MHz FUNDAMENTAL ON A 1MHz SPAN UNFILTERED
fN= 1MHz UNFILTERED
fS = 40MHz
ATTEN 20dB
RL 0dB
∆MKR -65.50dBC
1.00MHz
START 0Hz
RBW 1.0kHz STOP 20.00MHz
SWP 50.0s
VBW 1.0kHz
10dB/
∆MKR
1.00MHz
-65.50dB
fN = 1MHz UNFILTERED LIMIT SPAN
fS = 40MHz
ATTEN 20dB
RL 0dB
∆MKR -81.50dBC
33kHz
CENTER 1.000MHz
RBW 300Hz SPAN 1.000MHz
SWP 28.0s
VBW 300Hz
10dB/
∆MKR
33kHz
-81.50dB
Application Note 9410
6
FIGURE 13A. OSCILLOSCOPE PLOT FIGURE 13B. A 1MHz FUNDAMENTAL TO NIQUIST WITH A
20MHz BANDPASS FILTER
FIGURE 13. A 1MHz FUNDAMENTAL TO NYQUIST WITH A 20MHz BANDPASS FILTER
FIGURE 14A. OSCILLOSCOPE PLOT FIGURE 14B. SAMPLE PLOT
FIGURE 14. A 5MHz FUNDAMENTAL TO fS UNFILTERED
FIGURE 15. A 5MHz FUNDAMENTAL ON A 1MHz SPAN UNFILTERED
fN = 1MHz FILTERED
fS= 40MHz
ATTEN 20dB
RL 0dB
∆MKR 64.16dBC
1.00MHz
START 0Hz
RBW 3.0kHz STOP 20.00MHz
SWP 5.60s
VBW 3.0kHz
10dB/
∆MKR
1.00MHz
-64.16dB
fN = 5MHz UNFILTERED
fS = 40MHz
ATTEN 20dB
RL 0dB
∆MKR -55.50dBC
10.00MHz
START 0Hz
RBW 1.0kHz STOP 20.00MHz
SWP 50.0s
VBW 1.0kHz
10dB/
∆MKR
-55.50dB
10.00MHz
fN = 5MHz UNFILTERED LIMIT SPAN
fS = 40MHz
ATTEN 20dB
RL 0dB
∆MKR -66.83dBC
5kHz
CENTER 5.000MHz
RBW 300Hz SPAN 1.000MHz
SWP 28.0s
VBW 300Hz
10dB/
∆MKR
-66.83dB
5kHz
Application Note 9410
7
FIGURE 16A. OSCILLOSCOPE PLOT FIGURE 16B. SAMPLE PLOT
FIGURE 16. A 5MHz FUNDAMENTAL TO fS WITH A BANDPASS FILTER
fN = 5MHz FILTERED
fS= 40MHz
ATTEN 20dB
RL 0dB
∆MKR -65.34dBC
5.00MHz
START 0Hz
RBW 3.0kHz STOP 20.00MHz
SWP 5.60s
VBW 3.0kHz
10dB/
PEAK
-80.6dBm
THRESHOLD
Application Note 9410
8
Using the HSP-EVAL Test Platform
The HSP-EVAL DDS platform allows quick testing of spectral
properties of a given DAC. The Numerically Controlled Oscil-
lator/Modulator (NCOM) generates digital sinewave patterns
that are loaded into the DAC. The analog output of the DAC
is the reconstructed sinewave pattern. The program NCOM-
CTRL allows downloading of the desired center frequency.
The clock or sampling frequency is 25MHz. To determine the
center frequency codeword the following formula is used:
Center FrequencyHEX = (Desired Frequency/25MHZ) x 232
This 32-bit hexadecimal word will create the fundamental. In
order to ensure zero phase offset the cursor should be
moved to the LOAD select. Pressing the spacebar the value
should be toggled from 1 to 0 and back to 1 again. This will
ensure that any previous values in the phase register are
cleared and the sinewave pattern is started at zero phase.
The HSP-EVAL setup is powered from the DAC module
power-supply banana jacks. The output of the setup can be
observed on an oscilloscope or a spectrum analyzer.
FIGURE 17. INTERSIL HI5721/DDS EVALUATION SYSTEM SETUP BLOCK DIAGRAM
PERSONAL COMPUTER SPECTRUM ANALYZER
HSP-EVAL/HPS45116
NCOM EVALUATION BOARD
HSP45116
NUMERICALLY
CONTROLLED
OSCILLATOR
50Ω
SMA
CABLE
HI5721
DAC
CLOCK
CIRCUIT
+5V -5.2V
HI5721
DAC MODULE
INCLUDED
SOFTWARE
PC INTERFACE
POWER
SUPPLY
Application Note 9410
9
Schematic Diagram
NOTES:
1. All passive components are SMT devices, except polarized capacitors and ferrite beads.
2. HI5721 is a 28 lead DIP. FIGURE 18.
12
34
56
78
910
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
P1
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB9
J3
SMA
D9 (MSB)
1D8
2D7
3D6
4D5
5D4
6D3
7
D0 (LSB)
10
INVERT
13 CLK
11 25
20
23
DVDD
14
DVSS
15 19
21
24
26
D2
8D1
9
DVEE
16 22
DVSS
28
DVEE
27
17
18
U1
HI5721
R1
50
R2
50
VCC
R6- R15
DB9
DB8
DB7
DB6
R17
50
1
J2
CON2
R5
22K
DB5
DB4
DB3
DB2
DB1
DB0
VCC
R16
50 R3
1960
C1
-AVEE
-5.2V
+5V VCC VCC
PLACE AS CLOSE TO PIN
C2
0.1µF
PLACE AS CLOSE TO PIN
22 AS POSSIBLE
-AVEE
L1
10µH
SYSTEM
BJ1
BJACK
ECL SUPPLY -AVEE
1
2
3
4
5
6
7
8
9
10
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
J1A
CON32
J1B
VCC
J1C
DB0
CLK
DB3
DB5
DB7
DB9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
CON32 CON32
DB1
DB2
DB4
DB6
DB8
11
20.1µFC9
10µF
+
C3
0.01µF
-5.2V
16 AS POSSIBLE
C10
10µFC4
0.1µFC5
0.01µF
R4
10
SPACE LIKE A
FERRITE BEAD
C8
0.1µFC11
0.01µF
+
+
-5.2V
BJ1
BJ1
BJACK
BJACK
GROUND
REF OUT
IOUT
REF IN
ARET
IOUT/
C AMP OUT
C AMP IN
AVEE
RSET
AVSS
+
Application Note 9410
10
Evaluation Board Layers
FIGURE 19A. HI5721 SILKSCREEN
FIGURE 19B. HI5721 LAYER 1
HI5721 EVAL.
BOARD
Application Note 9410
11
FIGURE 19C. HI5721 LAYER 2
FIGURE 19D. HI5721 LAYER 3
Evaluation Board Layers (Continued)
Application Note 9410
12
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
FIGURE 19E. HI5721 LAYER 4
Evaluation Board Layers (Continued)
Application Note 9410
