VBUS054CD-FHI
www.vishay.com Vishay Semiconductors
Rev. 1.4, 31-May-12 1Document Number: 81882
For technical questions, contact: ESDprotection@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
4-Line BUS-Port ESD-Protection - Flow Through Design
MARKING (example only)
Dot = pin 1 marking
YY = type code (see table below)
XX = date code
FEATURES
• Compact LLP2513-11L package
• Low package height < 0.6 mm
• 4-line ESD-protection
• Low leakage current IR < 0.1 μA
• Low load capacitance CD = 0.8 pF
• Ideal for high speed data line like
- HDMI, DisplayPort, eSATA
- USB, 1394/firewire
• ESD-protection acc. IEC 61000-4-2
± 15 kV contact discharge
± 15 kV air discharge
• Soldering can be checked by standard vision inspection.
No X-ray necessary
• e4 - precious metal (e.g. Ag, Au, NiPd, NiPdAu) (no Sn)
• Material categorization: For definitions of compliance
please see www.vishay.com/doc?99912
21324
21326
GND nc. nc.nc. nc.
GND D2 + D2 -D1 + D1 -
11
12345
10 9 876
YYXX
20720
ORDERING INFORMATION
DEVICE NAME ORDERING CODE TAPED UNITS PER REEL
(8 mm TAPE ON 7" REEL) MINIMUM ORDER QUANTITY
VBUS054CD-FHI VBUS054CD-FHI-GS08 3000 15 000
PACKAGE DATA
DEVICE NAME PACKAGE
NAME
TYPE
CODE WEIGHT MOLDING COMPOUND
FLAMMABILITY RATING
MOISTURE
SENSITIVITY LEVEL
SOLDERING
CONDITIONS
VBUS054CD-FHI LLP2513-11L 9X 5.5 mg UL 94 V-0 MSL level 1
(according J-STD-020) 260 °C/10 s at terminals
ABSOLUTE MAXIMUM RATINGS
PARAMETER TEST CONDITIONS SYMBOL VALUE UNIT
Peak pulse current Acc. IEC 61000-4-5; tP = 8/20 μs; single shot IPPM 3.5 A
Peak pulse power Acc. IEC 61000-4-5; tP = 8/20 μs; single shot PPP 45 W
ESD immunity Contact discharge acc. IEC 61000-4-2; 10 pulses VESD ± 15 kV
Air discharge acc. IEC 61000-4-2; 10 pulses VESD ± 15 kV
Operating temperature Junction temperature TJ- 40 to + 125 °C
Storage temperature TSTG - 55 to + 150 °C
VBUS054CD-FHI
www.vishay.com Vishay Semiconductors
Rev. 1.4, 31-May-12 2Document Number: 81882
For technical questions, contact: ESDprotection@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
APPLICATION NOTE
The VBUS054CD-FHI is a four-line ESD-protection device with the characteristic of a Z-diode with a high ESD-immunity and a
very low capacitance which makes it usable for high frequency applications like USB2.0 or HDMI.
With the VBUS054CD-FHI four high speed data lines can be protected against transient voltage signals like ESD (Electro Static
Discharge). Connected to the data line (pin 1, 2 and pin 4, 5) and to ground (pin 3, 8 and 11) negative transients will be clamped
close below the ground level while positive transients will be clamped close above the 5 V working range. The clamping
behaviour of the VBUS054CD-FHI is bidirectional but asymmetrical (BiAs) and so it offers the best protection for applications
running up to 5 V.
Pin configuration:
• Pin 3, 8 and 11 are internally shorted and have to be connected to ground
• Pin 1, 2 and 4, 5 are the inputs for the data lines D1+ and D1- and D2+ and D2-
• Pin 6, 7 and 9, 10 are not connected internally
FLOW THROUGH DESIGN
Modern digital transmission lines can be clocked up to 480 Mbit/s (USB2.0) or 1.65 Gbit/s (HDMI).
At such high data rates the transmission lines like cables or the line traces on the PCBs have to be very homogeneous regarding
their surge impedance. This requires well defined trace dimensions as trace width and distance which have to be calculated
depending on the requested surge impedance (e.g. 50 ) and the PCB material and layer dimensions. Any device connected
to the data lines - like ESD-protection devices - have to be connected with minimal changes in these trace dimensions and
distances.
With the package in the so called “Flow Through Design” this is possible. The lines are running straight along the PCB while the
VBUS054CD-FHI is placed on top without any vias or loops.
ELECTRICAL CHARACTERISTICS (pin 1, 2, 4 or 5 to pin 3)
(Tamb = 25 °C, unless otherwise specified)
PARAMETER TEST CONDITIONS/REMARKS SYMBOL MIN. TYP. MAX. UNIT
Protection paths Number of lines which can be protected Nchannel --4lines
Reverse stand-off voltage Max. reverse working voltage VRWM --5V
Reverse voltage at IR = 0.1 μA VR5--V
Reverse current at VRWM = 5 V IR- < 0.01 0.1 μA
Reverse breakdown voltage at IR = 1 mA VBR 6.9 7.9 8.7 V
Reverse clamping voltage at IPP = 1 A VC-9.111V
at IPP = IPPM = 3.5 A VC- 11.6 13 V
Forward clamping voltage at IPP = 1 A VF-1.62.4V
at IPP = 3.5 A VF-3.55 V
Capacitance at VR = 0 V; f = 1 MHz CD-0.81pF
21326
GND nc. nc.nc. nc.
GND D2 + D2 -D1 + D1 -
11
12345
10 9 876
matched pair
matched pair
GND D2 + D2 -D1 + D1 -
I/O Port Connector
USB/HDMI Interface
D1 + D1 - D2 + D2 -
21328
12345
10 9 8 7 6
11
VBUS054CD-FHI
www.vishay.com Vishay Semiconductors
Rev. 1.4, 31-May-12 3Document Number: 81882
For technical questions, contact: ESDprotection@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
TYPICAL CHARACTERISTICS (Tamb = 25 °C, unless otherwise specified)
Fig. 1 - ESD Discharge Current Wave Form
acc. IEC 61000-4-2 (330 /150 pF)
Fig. 2 - 8/20 μs Peak Pulse Current Wave Form
acc. IEC 61000-4-5
Fig. 3 - Typical Capacitance CD vs. Reverse Voltage VR
Fig. 4 - Typical Forward Current IF vs. Forward Voltage VF
Fig. 5 - Typical Reverse Voltage VR vs.
Reverse Current IR
Fig. 6 - Typical Peak Clamping Voltage VC vs.
Peak Pulse Current IPP
0 %
20 %
40 %
60 %
80 %
100 %
120 %
- 10 0 10 20 30 40 50 60 70 80 90 100
Time (ns)
Discharge Current IESD
Rise time = 0.7 ns to 1 ns
53 %
27 %
20557
0 %
20 %
40 %
60 %
80 %
100 %
010203040
Time (µs)
I
PPM
20 µs to 50 %
8 µs to 100 %
20548
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
012345
VR at Pin 1 and Pin 4 (V)
CD (pF)
22348
f = 1 MHz
VR at Pin 2 or Pin 3 = 0 V
VR at Pin 2 or Pin 3 = 3.3 V
0.001
0.01
0.1
1
10
100
0.5 0.6 0.7 0.8 0.9 1 1.1
Pin 3 to Pin 1, 2, 4 or 5
22349 VF (V)
IF (mA)
0
1
2
3
4
5
6
7
8
9
0.01 0.1 1 10 100 1000 10 000
Pin 1, 2, 4 or 5 to Pin 3
22350
IR (µA)
VR (V)
0
2
4
6
8
10
12
14
012345
Measured acc. IEC 61000-4-5 (8/20µs - wave form)
VC
Pin 1, 2, 4 or 5 to Pin 3
Pin 3 to Pin 1, 2, 4 or 5
21477
IPP (A)
VC (V)
VBUS054CD-FHI
www.vishay.com Vishay Semiconductors
Rev. 1.4, 31-May-12 4Document Number: 81882
For technical questions, contact: ESDprotection@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Fig. 7 - Typical Clamping Performance at + 8 kV
Contact Discharge (acc. IEC 61000-4-2)
Fig. 8 - Typical Clamping Performance at - 8 kV
Contact Discharge (acc. IEC 61000-4-2)
Fig. 9 - Typical Peak Clamping Voltage at ESD
Contact Discharge (acc. IEC 61000-4-2)
- 20
0
20
40
60
80
100
- 10 0 10 20 30 40 50 60 70 80 90
t (ns)
V
C-ESD
(V)
22352
Acc. IEC 61000-4-2
+ 8 kV
contact discharge
- 120
- 100
- 80
- 60
- 40
- 20
0
20
- 10 0 102030405060708090
t (ns)
V
C-ESD
(V)
22353
Acc. IEC 61000-4-2
- 8 kV
contact discharge
VBUS054CD-FHI
www.vishay.com Vishay Semiconductors
Rev. 1.4, 31-May-12 5Document Number: 81882
For technical questions, contact: ESDprotection@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
PACKAGE DIMENSIONS in millimeters (inches): LLP2513-11L
Solder
resist mask
Solder pad
0.5 (0.020) 0.25 (0.010)
4 x 0.5 = 2 (0.079)
0.15 (0.006)
0.37 (0.015)
0.22 (0.009)
2.55 (0.100)
2.45 (0.096)
Pin 1 marking
0.05 (0.002)
0 (0.000)
0.152 (0.006) ref.
2 (0.079) ref.
0.25 (0.010)
0.19 (0.007)
0.5 (0.020) bsc 0.28 (0.011)
0.22 (0.009)
1.4 (0.055)
1.3 (0.051)
0.6 (0.024)
0.5 (0.020)
0.4 (0.016)
0.4 (0.016)
21382
Created - Date: 15. April 2008
Document no.:S8-V-3906.04-009 (4)
Rev. 2 - Date: 09. Sep. 2008
Foot print recommendation:
VBUS054CD-FHI
www.vishay.com Vishay Semiconductors
Rev. 1.4, 31-May-12 6Document Number: 81882
For technical questions, contact: ESDprotection@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Pin 1 - Location
Top view Pad layout - view from top
seen at bottom side
LLP1713
LLP2513
LLP3313
Pin 1 - Location
Pin 1 - Location
Top view
Top view
Pad layout - view from top
seen at bottom side
Pad layout - view from top
seen at bottom side
Legal Disclaimer Notice
www.vishay.com Vishay
Revision: 02-Oct-12 1Document Number: 91000
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