A3282LLHLT-T - Allegro Microsystems

NOTE: For detailed information on purchasing options, contact your

local Allegro field applications engineer or sales representative.

Allegro MicroSystems, Inc. reserves the right to make, from time to time, revisions to the anticipated product life cycle plan

for a product to accommodate changes in production capabilities, alternative product availabilities, or market demand. The

information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no respon-

sibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use.

Recommended Substitutions:

Chopper-Stabilized Hall-Effect Latch

A3282

Our next generation recommended substitutes are:

• FortheA3282ELHLT-T,werecommendtheA1222ELHLX-T.

• FortheA3282LLHLT-T,werecommendtheA1222LLHLX-T.

• FortheA3282LUA-T,werecommendtheA1222LUA-T.

Date of status change: February 1, 2010

Deadline for receipt of LAST TIME BUY orders: July 30, 2010

These parts are in production but have been determined to be

LAST TIME BUY. This classification indicates that the product is

obsolete and notice has been given. Sale of this device is currently

restricted to existing customer applications. The device should not be

purchased for new design applications because of obsolescence in the

near future. Samples are no longer available.

Last Time Buy

Regulator

GND

VCC

VOUT

Control

Current Limit

<1Ω

Dynamic Offset

Cancellation

Sample and Hold

To All Subcircuits

Amp

Low-Pass

Filter

Description

The A3282 Hall-effect sensor IC is a temperature stable,

stress-resistant latch. Superior high-temperature performance

is made possible through an Allegro® patented dynamic

offset cancellation that utilizes chopper-stabilization. This

method reduces the offset voltage normally caused by device

overmolding, temperature dependencies, and thermal stress.

The A3282 complements the current Allegro family of chopper-

stabilized latching devices.

The A3282 includes the following on a single silicon chip:

voltage regulator, Hall-voltage generator, small-signal

amplifier, chopper stabilization, Schmitt trigger, and a short

circuit protected open-drain output. Advanced BiCMOS wafer

fabrication processing is used to take advantage of low-voltage

requirements, component matching, very low input-offset

errors, and small component geometries.

This device requires the presence of both south and north

polarity magnetic fields for operation. In the presence of a

south polarity field of sufficient strength, the device output

latches on, and only switches off when a north polarity field

of sufficient strength is present.

A3282-DS, Rev. 8

Features and Benefits

▪ Chopper stabilization

▫ Superior temperature stability

▫ Extremely low switchpoint drift

▫ Insensitive to physical stress

▪ Reverse battery protection

▪ Output short circuit protection

▪ Solid state reliability

▪ Small size

▪ Robust EMC capability

▪ High ESD ratings (HBM)

Chopper-Stabilized Hall-Ef fect Latch

Continued on the next page…

Functional Block Diagram

Not to scale

Packages: 3 pin SOT23W (suffix LH), and

3 pin SIP (suffix UA)

A3282

Chopper-Stabilized Hall Ef fect Latch

A3282

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Selection Guide

Part Number Packing1Mounting Ambient, TA

(°C) BRP(MIN)

(G) BOP(MAX)

(G)

A3282ELHLT-T27-in. reel, 3000 pieces/reel 3-pin SOT23W surface mount –40 to 85

–150 150A3282LLHLT-T27-in. reel, 3000 pieces/reel 3-pin SOT23W surface mount –40 to 150

A3282LUA-T2Bulk, 500 pieces/bag 3-pin SIP through hole

1Contact Allegro for additional packing options.

2Variant is in production but has been determined to be NOT FOR NEW DESIGN. This classification indicates that sale of the variant

is currently restricted to existing customer applications. The variant should not be purchased for new design applications because

obsolescence in the near future is probable. Samples are no longer available. Status change: August 12, 2009.

The A3282 is rated for operation between the ambient temperatures

–40°C and 85°C for the E temperature range, and –40°C to 150°C for

the L temperature range. The two package styles available provide

magnetically optimized solutions for most applications. Package

LH is an SOT23-W, a miniature low-profile surface-mount package,

while package UA is a three-lead ultramini SIP for through-hole

mounting. Each package is available in a lead (Pb) free version,

with 100% matte tin plated leadframes.

Description (continued)

Absolute Maximum Ratings

Characteristic Symbol Notes Rating Units

Supply Voltage VCC 28 V

Reverse-Supply Voltage VRCC –18 V

Output Off Voltage VOUT 28 V

Output Current IOUTSINK Internally Limited –

Reverse-Output Current IROUT –10 mA

Magnetic Flux Density B Unlimited G

Operating Ambient Temperature TA

Range E –40 to 85 ºC

Range L –40 to 150 ºC

Maximum Junction Temperature TJ(max) 165 ºC

Storage Temperature Tstg –65 to 170 ºC

Chopper-Stabilized Hall Ef fect Latch

A3282

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

OPERATING CHARACTERISTICS valid over full operating voltage and ambient temperature ranges, unless otherwise noted

Characteristic Symbol Test Conditions Min. Typ. Max. Units

Electrical Characteristics

Supply Voltage1VCC Operating, TJ < 165°C 3.6 – 24 V

Output Leakage Current IOUTOFF VOUT = 24 V, B < BRP ––10μA

Output On Voltage VOUT(SAT) IOUT = 20 mA, B > BOP – 250 500 mV

Output Current Limit IOM B > BOP 30 – 60 mA

Power-On Time tPO VCC > 3.6 V – 8 50 μs

Chopping Frequency fc– 200 – kHz

Output Rise Time2trRLOAD = 820 Ω, CS = 20 pF – 0.2 1 μs

Output Fall Time2tfRLOAD = 820 Ω, CS = 20 pF – 0.2 1 μs

Supply Current ICCON B > BOP – 1.6 3.5 mA

ICCOFF B < BRP – 1.6 3.5 mA

Reverse Battery Current IRCC VRCC = –18 V – – –2 mA

Supply Zener Clamp Voltage VZICC = 6.5 mA; TA = 25°C 28 – – V

Supply Zener Current3IZVS = 28 V – – 6.5 mA

Magnetic Characteristics4

Operate Point BOP South pole adjacent to branded face of device 70 110 150 G

Release Point BRP North pole adjacent to branded face of device –150 –110 –70 G

Hysteresis BHYS BOP – BRP 140 220 300 G

1 Maximum voltage must be adjusted for power dissipation and junction temperature, see Power Derating section.

2 CS = oscilloscope probe capacitance.

3 Maximum current limit is equal to the maximum ICC(MAX) + 3 mA.

4 Magnetic ﬂ ux density, B, is indicated as a negative value for north-polarity magnetic ﬁ elds, and as a positive value for south-polarity magnetic ﬁ elds.

This so-called algebraic convention supports arithmetic comparison of north and south polarity values, where the relative strength of the ﬁ eld is indicated

by the absolute value of B, and the sign indicates the polarity of the ﬁ eld (for example, a –100 G ﬁ eld and a 100 G ﬁ eld have equivalent strength, but

opposite polarity).

DEVICE QUALIFICATION PROGRAM

Contact Allegro for information.

EMC (Electromagnetic Compatibility) REQUIREMENTS

Contact Allegro for information.

Chopper-Stabilized Hall Ef fect Latch

A3282

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

TA (°C)

Supply Current (On) versus Ambient Temperature

(V)

ICCON (mA)

3.6

TA (°C)

Supply Current (Off) versus Ambient Temperature

(V)

ICCOFF (mA)

3.6

TA (°C)

Output Voltage (On) versus Ambient Temperature

(V)

VOUT(SAT) (mV)

3.6

Supply Current (On) versus Supply Voltage

(°C)

ICCON (mA)

VCC (V)

–40

150

Supply Current (Off) versus Supply Voltage

(°C)

ICCOFF (mA)

VCC (V)

–40

150

Output Voltage (On) versus Supply Voltage

(°C)

VOUT(SAT) (mV)

VCC (V)

–40

150

1.0

2.0

3.0

4.0

5.0

1.0

2.0

3.0

4.0

5.0

1.0

2.0

3.0

4.0

5.0

1.0

2.0

3.0

4.0

5.0

–50 0 50 100 150 0 5 10 15 20 25

200

250

100

150

300

350

400

450

500

200

250

100

150

300

350

400

450

500

Electrical Characteristic Data

Chopper-Stabilized Hall Ef fect Latch

A3282

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

(V)

3.8

TA (°C)

(V)

3.8

(V)

3.8

(°C)

–40

150

(°C)

–40

150

(°C)

–40

150

Operate Point versus Ambient Temperature

BOP (G)

TA (°C)

Release Point versus Ambient Temperature

BRP (G)

TA (°C)

Hysteresis versus Ambient Temperature

BHYS (G)

BOP (G)BRP (G)BHYS (G)

Operate Point versus Supply Voltage

Release Point versus Supply Voltage

VCC (V)

TA (°C) VCC (V)

Hysteresis versus Supply Voltage

–50 0 50 100 150 0 5 10 15 20 25

100

110

130

120

140

150

100

110

130

120

140

150

-150

-130

-140

-120

-90

-80

-100

-110

-70

-150

-130

-140

-120

-90

-80

-100

-110

-70

140

180

220

280

260

240

200

160

300

140

180

220

280

260

240

200

160

300

Magnetic Characteristic Data

Chopper-Stabilized Hall Ef fect Latch

A3282

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

THERMAL CHARACTERISTICS may require derating at maximum conditions, see application information

Characteristic Symbol Test Conditions* Value Units

Package Thermal Resistance RθJA

Package LH, 1-layer PCB with copper limited to solder pads 228 ºC/W

Package LH, 2-layer PCB with 0.463 in.2 of copper area each side

connected by thermal vias 110 ºC/W

Package UA, 1-layer PCB with copper limited to solder pads 165 ºC/W

*Additional thermal information available on Allegro Web site.

20 40 60 80 100 120 140 160 180

Temperature (ºC)

Maximum Allowable V

(V)

Power Derating Curve

θJA

= 228 ºC/W)

1-layer PCB, Package LH

θJA

= 110 ºC/W)

2-layer PCB, Package LH

θJA

= 165 ºC/W)

1-layer PCB, Package UA

VCC(min)

VCC(max)

100

200

300

400

500

600

700

800

900

1000

1100

1200

1300

1400

1500

1600

1700

1800

1900

20 40 60 80 100 120 140 160 180

Temperature (°C)

Power Dissipation, P

(mW)

Power Dissipation versus Ambient Temperature

θJA

= 165 ºC/W)

1-layer PCB, Package UA

(RθJA = 228 ºC/W)

1-layer PCB, Package LH

(RθJA = 110 ºC/W)

2-layer PCB, Package LH

Chopper-Stabilized Hall Ef fect Latch

A3282

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Functional Description

HYS

OUT

OUT(SAT)

Switch to Low

Switch to High

B+

B–

V+

VCC

Output

GND

VOUT

LOAD

A3282

0.1 µF

BYP

Operation

The output of these devices switches low (turns on) when a

magnetic ﬁ eld perpendicular to the Hall element exceeds the

operate point threshold, BOP. After turn-on, the output voltage

is VOUT(SAT). The output transistor is capable of sinking current

up to the short circuit current limit, IOM, which is a minimum of

30 mA. Note that the device latches, that is, a south pole of sufﬁ -

cient strength towards the branded surface of the device turns the

device on. The device remains on if the south pole is removed.

When the magnetic ﬁ eld is reduced below the release point, BRP

the device output turns off (goes high). The difference in the

magnetic operate and release points is the hysteresis, BHYS

, of

the device. This built-in hysteresis allows clean switching of the

output even in the presence of external mechanical vibration and

electrical noise.

Powering-on the device in the hysteresis region (less than BOP and

higher than BRP) allows an indeterminate output state. The correct

state is attained after the ﬁ rst excursion beyond BOP or BRP

Applications

It is strongly recommended that an external bypass capacitor be

connected (in close proximity to the Hall element) between the

supply and ground of the device to reduce both external noise

and noise generated by the chopper stabilization technique. As is

shown in Panel B of ﬁ gure 1, a 0.1μF capacitor is typical.

Extensive applications information on magnets and Hall-effect

devices is available in:

• Hall-Effect IC Applications Guide, AN27701,

• Hall-Effect Devices: Gluing, Potting, Encapsulating, Lead

Welding and Lead Forming, AN27703.1

• Soldering Methods for Allegro’s Products – SMT and Through-

Hole, AN26009

All are provided in Allegro Electronic Data Book, AMS-702 and

the Allegro Web site: www.allegromicro.com

Figure 1: Switching Behavior of Latches. In Panel A, on the horizontal axis, the B+ direction indicates increasing south polarity magnetic

ﬁ eld strength, and the B– direction indicates decreasing south polarity ﬁ eld strength (including the case of increasing north polarity). This

behavior can be exhibited when using a circuit such as that shown in panel B.

(A) (B)

Chopper-Stabilized Hall Ef fect Latch

A3282

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Figure 2. Chopper Stabilization Circuit (Dynamic Quadrature Offset Cancellation)

Amp

Regulator

Clock/Logic

Hall Element

Sample and

Hold

Low-Pass

Filter

Chopper Stabilization Technique

When using Hall-effect technology, a limiting factor for

switchpoint accuracy is the small signal voltage developed

across the Hall element. This voltage is disproportionally small

relative to the offset that can be produced at the output of the

Hall element. This makes it difﬁ cult to process the signal while

maintaining an accurate, reliable output over the speciﬁ ed oper-

ating temperature and voltage ranges.

Chopper stabilization is a unique approach used to minimize

Hall offset on the chip. The patented Allegro technique, namely

Dynamic Quadrature Offset Cancellation, removes key sources

of the output drift induced by thermal and mechanical stresses.

This offset reduction technique is based on a signal modulation-

demodulation process. The undesired offset signal is separated

from the magnetic-ﬁ eld-induced signal in the frequency domain,

through modulation. The subsequent demodulation acts as a

modulation process for the offset, causing the magnetic-ﬁ eld-

induced signal to recover its original spectrum at baseband,

while the dc offset becomes a high-frequency signal. The

magnetic-ﬁ eld-induced signal then can pass through a low-pass

ﬁ lter, while the modulated dc offset is suppressed. This conﬁ gu-

ration is illustrated in ﬁ gure 2.

The chopper stabilization technique uses a 200 kHz high-

frequency clock. For demodulation process, a sample and hold

technique is used, where the sampling is performed at twice the

chopper frequency (400 kHz). This high-frequency operation

allows a greater sampling rate, which results in higher accuracy

and faster signal-processing capability. This approach desensi-

tizes the chip to the effects of thermal and mechanical stresses,

and produces devices that have extremely stable quiescent Hall

output voltages and precise recoverability after temperature

cycling. This technique is made possible through the use of a

BiCMOS process, which allows the use of low-offset, low-noise

ampliﬁ ers in combination with high-density logic integration and

sample-and-hold circuits.

The repeatability of magnetic-ﬁ eld-induced switching is affected

slightly by a chopper technique. However, the Allegro high-

frequency chopping approach minimizes the affect of jitter and

makes it imperceptible in most applications. Applications that

are more likely to be sensitive to such degradation are those

requiring precise sensing of alternating magnetic ﬁ elds; for

example, speed sensing of ring-magnet targets. For such applica-

tions, Allegro recommends its digital device families with lower

sensitivity to jitter. For more information on those devices,

contact your Allegro sales representative.

Chopper-Stabilized Hall Ef fect Latch

A3282

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

The device must be operated below the maximum junction

temperature of the device, TJ(max). Under certain combinations of

peak conditions, reliable operation may require derating sup-

plied power or improving the heat dissipation properties of the

application. This section presents a procedure for correlating

factors affecting operating TJ. (Thermal data is also available on

the Allegro MicroSystems Web site.)

The Package Thermal Resistance, RJA, is a ﬁ gure of merit sum-

marizing the ability of the application and the device to dissipate

heat from the junction (die), through all paths to the ambient air.

Its primary component is the Effective Thermal Conductivity,

K, of the printed circuit board, including adjacent devices and

traces. Radiation from the die through the device case, RJC, is

relatively small component of RJA. Ambient air temperature,

TA, and air motion are signiﬁ cant external factors, damped by

overmolding.

The effect of varying power levels (Power Dissipation, PD), can

be estimated. The following formulas represent the fundamental

relationships used to estimate TJ, at PD.

PD = VIN × IIN (1)

 T = PD × RJA (2)

TJ = TA + ΔT (3)

For example, given common conditions such as: TA= 25°C,

VCC = 12 V, ICC = 1.5 mA, and RJA = 165 °C/W, then:

D = VCC × ICC = 12 V × 1.5 mA = 18 mW

T = PD × RJA = 18 mW × 165 °C/W = 3°C

J = TA + T = 25°C + 3°C = 28°C

A worst-case estimate, PD(max), represents the maximum allow-

able power level (VCC(max), ICC(max)), without exceeding TJ(max),

at a selected RJA and TA.

Example: Reliability for VCC at TA =

150°C, package LH, using a

low-K PCB.

Observe the worst-case ratings for the device, speciﬁ cally:

RJA

228 °C/W, TJ(max) =

165°C, VCC(max)

= 24 V, and

ICC(max) = 5 mA.

Calculate the maximum allowable power level, PD(max). First,

invert equation 3:

Tmax = TJ(max) – TA = 165

°C

–

150

°C = 15

°C

This provides the allowable increase to TJ resulting from internal

power dissipation. Then, invert equation 2:

PD(max) = Tmax ÷ RJA = 15°C ÷ 228 °C/W = 66 mW

Finally, invert equation 1 with respect to voltage:

VCC(est) = PD(max) ÷ ICC(max) = 66 mW ÷ 5 mA = 13 V

The result indicates that, at TA, the application and device can

dissipate adequate amounts of heat at voltages ≤VCC(est).

Compare VCC(est) to VCC(max). If VCC(est) ≤ VCC(max), then reli-

able operation between VCC(est) and VCC(max) requires enhanced

RJA. If VCC(est) ≥ VCC(max), then operation between VCC(est) and

VCC(max) is reliable under these conditions.

Power Derating

Chopper-Stabilized Hall Ef fect Latch

A3282

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

1 32

Package LH, 3-Pin SOT23-W

Package LH Package UA

Terminal List

Name Description Number

Package LH Package UA

VCC Connects power supply to chip 1 1

VOUT Output from circuit 2 3

GND Ground 3 2

Pin-out Drawings

0.55 REF

Gauge Plane

Seating Plane

0.25

0.95

1.00

0.70 2.40

AActive Area Depth, 0.28 mm REF

Reference land pattern layout

All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary

to meet application process requirements and PCB layout tolerances

Branding scale and appearance at supplier discretion

PCB Layout Reference View

Standard Branding Reference View

Branded Face

N = Last two digits of device part number

T = Temperature code

NNT

2.90 +0.10

–0.20

8X 10° REF

0.180+0.020

–0.053

0.05 +0.10

–0.05

0.25 MIN

1.91 +0.19

–0.06

2.98 +0.12

–0.08

1.00 ±0.13

0.40 ±0.10

4°±4°

For Reference Only; not for tooling use (reference dwg. 802840)

Dimensions in millimeters

Dimensions exclusive of mold flash, gate burrs, and dambar protrusions

Exact case and lead configuration at supplier discretion within limits shown

DHall element, not to scale

1.49

0.96

Chopper-Stabilized Hall Ef fect Latch

A3282

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Package UA, 3-Pin SIP

Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per-

mit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the

information being relied upon is current.

Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the

failure of that life support device or system, or to affect the safety or effectiveness of that device or system.

The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, Inc. assumes no re spon si bil i ty for its use;

nor for any in fringe ment of patents or other rights of third parties which may result from its use.

For the latest version of this document, visit our website:

www.allegromicro.com

231

1.27 NOM

2.16

MAX

0.51

REF

45°

0.79 REF

2.04

1.44

Gate burr area

Dambar removal protrusion (6X)

Branding scale and appearance at supplier discretion

Hall element, not to scale

Active Area Depth, 0.50 mm REF

For Reference Only; not for tooling use (reference DWG-9049)

Dimensions in millimeters

Dimensions exclusive of mold flash, gate burrs, and dambar protrusions

Exact case and lead configuration at supplier discretion within limits shown

Standard Branding Reference View

= Supplier emblem

N = Last two digits of device part number

T = Temperature code

NNT

Mold Ejector

Pin Indent

Branded

Face

4.09 +0.08

–0.05

0.41 +0.03

–0.06

3.02 +0.08

–0.05

0.43 +0.05

–0.07

15.75 ±0.51

1.52 ±0.5