DS90LV031A DS90LV031A 3V LVDS Quad CMOS Differential Line Driver Literature Number: SNLS020B DS90LV031A 3V LVDS Quad CMOS Differential Line Driver General Description Features The DS90LV031A is a quad CMOS differential line driver designed for applications requiring ultra low power dissipation and high data rates. The device is designed to support data rates in excess of 400 Mbps (200 MHz) utilizing Low Voltage Differential Signaling (LVDS) technology. The DS90LV031A accepts low voltage LVTTL/LVCMOS input levels and translates them to low voltage (350 mV) differential output signals. In addition the driver supports a TRISTATE(R) function that may be used to disable the output stage, disabling the load current, and thus dropping the device to an ultra low idle power state of 13 mW typical. The EN and EN* inputs allow active Low or active High control of the TRI-STATE outputs. The enables are common to all four drivers. The DS90LV031A and companion line receiver (DS90LV032A) provide a new alternative to high power psuedo-ECL devices for high speed point-to-point interface applications. Connection Diagram Functional Diagram >400 Mbps (200 MHz) switching rates 0.1 ns typical differential skew 0.4 ns maximum differential skew 2.0 ns maximum propagation delay 3.3V power supply design 350 mV differential signaling Low power dissipation (13mW at 3.3V static) Interoperable with existing 5V LVDS devices Compatible with IEEE 1596.3 SCI LVDS standard Compatible with TIA/EIA-644 LVDS standard Industrial operating temperature range Available in SOIC and TSSOP surface mount packaging Dual-In-Line 10009501 Order Number DS90LV031ATM or DS90LV031ATMTC See NS Package Number M16A or MTC16 10009502 Truth Table Enables Input Outputs EN EN* DIN DOUT+ L H X Z Z L L H H H L All other combinations of ENABLE inputs DOUT- TRI-STATE(R) is a registered trademark of National Semiconductor Corporation. (c) 2010 National Semiconductor Corporation 100095 www.national.com DS90LV031A 3V LVDS Quad CMOS Differential Line Driver October 27, 2010 DS90LV031A Storage Temperature Range Lead Temperature Range Soldering (4 sec.) Maximum Junction Temperature ESD Rating (Note 10) Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) -0.3V to +4V Input Voltage (DIN) -0.3V to (VCC + 0.3V) Enable Input Voltage (EN, EN*) -0.3V to (VCC + 0.3V) Output Voltage (DOUT+, DOUT-) -0.3V to +3.9V Short Circuit Duration (DOUT+, DOUT-) Continuous Maximum Package Power Dissipation @ +25C M Package 1088 mW MTC Package 866 mW Derate M Package 8.5 mW/C above +25C Derate MTC Package 6.9 mW/C above +25C -65C to +150C +260C +150C 6 kV (HBM, 1.5 k, 100 pF) Recommended Operating Conditions Supply Voltage (VCC) Operating Free Air Temperature (TA) Industrial Min +3.0 Typ +3.3 Max +3.6 Units V -40 +25 +85 C Electrical Characteristics Over supply voltage and operating temperature ranges, unless otherwise specified. (Note 2, Note 3, Note 4) Symbol Parameter Conditions RL = 100 (Figure 1) Pin Min Typ Max Units DOUT- DOUT+ 250 350 450 mV 4 35 |mV| 1.25 1.375 V 5 25 |mV| 1.38 1.6 V VOD1 Differential Output Voltage VOD1 Change in Magnitude of VOD1 for Complementary Output States VOS Offset Voltage VOS Change in Magnitude of VOS for Complementary Output States VOH Output Voltage High VOL Output Voltage Low VIH Input Voltage High VIL Input Voltage Low IIH Input Current VIN = VCC or 2.5V -10 1 IIL Input Current VIN = GND or 0.4V -10 1 +10 A VCL Input Clamp Voltage ICL = -18 mA -1.5 -0.8 IOS Output Short Circuit Current ENABLED, (Note 11) DIN = VCC, DOUT+ = 0V or DIN = GND, DOUT- = 0V IOSD Differential Output Short Circuit Current ENABLED, VOD = 0V (Note 11) IOFF Power-off Leakage VOUT = 0V or 3.6V, VCC = 0V or Open IOZ Output TRI-STATE Current EN = 0.8V and EN* = 2.0V VOUT = 0V or VCC ICC No Load Supply Current Drivers Enabled DIN = VCC or GND ICCL Loaded Supply Current Drivers Enabled ICCZ No Load Supply Current Drivers Disabled www.national.com 1.125 0.90 DIN, EN, EN* 1.03 2.0 GND V 0.8 V +10 A V -6.0 -9.0 mA -6.0 -9.0 mA -20 1 +20 A -10 1 +10 A 5.0 8.0 mA RL = 100 All Channels, DIN = VCC or GND (all inputs) 23 30 mA DIN = VCC or GND, EN = GND, EN* = VCC 2.6 6.0 mA 2 DOUT- DOUT+ V VCC VCC VCC = +3.3V 10%, TA = -40C to +85C (Note 3, Note 9, Note 12) Symbol Parameter Conditions Min Typ Max Units RL = 100, CL = 10 pF (Figure 2 and Figure 3) 0.8 1.18 2.0 ns 0.8 1.25 2.0 ns 0 0.07 0.4 ns Channel-to-Channel Skew (Note 6) 0 0.1 0.5 ns Differential Part to Part Skew (Note 7) 0 1.0 ns tSKD4 Differential Part to Part Skew (Note 8) 0 1.2 ns tTLH Rise Time 0.38 1.5 ns tTHL Fall Time 0.40 1.5 ns tPHZ Disable Time High to Z 5 ns tPLZ Disable Time Low to Z 5 ns tPZH Enable Time Z to High 7 ns tPZL Enable Time Z to Low fMAX Maximum Operating Frequency (Note 14) tPHLD Differential Propagation Delay High to Low tPLHD Differential Propagation Delay Low to High tSKD1 Differential Pulse Skew |tPHLD - tPLHD| (Note 5) tSKD2 tSKD3 RL = 100, CL = 10 pF (Figure 4 and Figure 5) 7 200 250 ns MHz Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" specifies conditions of device operation. Note 2: Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except: VOD1 and VOD1. Note 3: All typicals are given for: VCC = +3.3V, TA = +25C. Note 4: The DS90LV031A is a current mode device and only functions within datasheet specifications when a resistive load is applied to the driver outputs typical range is (90 to 110) Note 5: tSKD1, |tPHLD - tPLHD| is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of the same channel. Note 6: tSKD2 is the Differential Channel-to-Channel Skew of any event on the same device. Note 7: tSKD3, Differential Part to Part Skew, is defined as the difference between the minimum and maximum specified differential propagation delays. This specification applies to devices at the same VCC and within 5C of each other within the operating temperature range. Note 8: tSKD4, part to part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices over recommended operating temperature and voltage ranges, and across process distribution. tSKD4 is defined as |Max - Min| differential propagation delay. Note 9: Generator waveform for all tests unless otherwise specified: f = 1 MHz, ZO = 50, tr 1 ns, and tf 1 ns. Note 10: ESD Ratings: HBM (1.5 k, 100 pF) 6 kV Note 11: Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only. Note 12: CL includes probe and jig capacitance. Note 13: All input voltages are for one channel unless otherwise specified. Other inputs are set to GND. Note 14: fMAX generator input conditions: tr = tf < 1ns, (0% to 100%), 50% duty cycle, 0V to 3V. Output Criteria: duty cycle = 45%/55%, VOD > 250mV, all channels switching. 3 www.national.com DS90LV031A Switching Characteristics - Industrial DS90LV031A Parameter Measurement Information 10009503 FIGURE 1. Driver VOD and VOS Test Circuit 10009504 FIGURE 2. Driver Propagation Delay and Transition Time Test Circuit 10009505 FIGURE 3. Driver Propagation Delay and Transition Time Waveforms www.national.com 4 DS90LV031A 10009506 FIGURE 4. Driver TRI-STATE Delay Test Circuit 10009507 FIGURE 5. Driver TRI-STATE Delay Waveform 5 www.national.com DS90LV031A Applications Information Power Decoupling Recommendations: Bypass capacitors must be used on power pins. High frequency ceramic (surface mount is recommended) 0.1F in parallel with 0.01F, in parallel with 0.001F at the power supply pin as well as scattered capacitors over the printed circuit board. Multiple vias should be used to connect the decoupling capacitors to the power planes. A 10F (35V) or greater solid tantalum capacitor should be connected at the power entry point on the printed circuit board. General application guidelines and hints for LVDS drivers and receivers may be found in the following application notes: LVDS Owner's Manual (lit #550062-001), AN808, AN1035, AN977, AN971, AN916, AN805, AN903. LVDS drivers and receivers are intended to be primarily used in an uncomplicated point-to-point configuration as is shown in Figure 7. This configuration provides a clean signaling environment for the quick edge rates of the drivers. The receiver is connected to the driver through a balanced media which may be a standard twisted pair cable, a parallel pair cable, or simply PCB traces. Typically, the characteristic differential impedance of the media is in the range of 100. A termination resistor of 100 should be selected to match the media, and is located as close to the receiver input pins as possible. The termination resistor converts the current sourced by the driver into a voltage that is detected by the receiver. Other configurations are possible such as a multi-receiver configuration, but the effects of a mid-stream connector(s), cable stub(s), and other impedance discontinuities as well as ground shifting, noise margin limits, and total termination loading must be taken into account. The DS90LV031A differential line driver is a balanced current source design. A current mode driver, generally speaking has a high output impedance and supplies a constant current for a range of loads (a voltage mode driver on the other hand supplies a constant voltage for a range of loads). Current is switched through the load in one direction to produce a logic state and in the other direction to produce the other logic state. The output current is typically 3.5 mA, a minimum of 2.5 mA, and a maximum of 4.5 mA. The current mode requires (as discussed above) that a resistive termination be employed to terminate the signal and to complete the loop as shown in Figure 7. AC or unterminated configurations are not allowed. The 3.5 mA loop current will develop a differential voltage of 350 mV across the 100 termination resistor which the receiver detects with a 250 mV minimum differential noise margin neglecting resistive line losses (driven signal minus receiver threshold (350 mV - 100 mV = 250 mV)). The signal is centered around +1.2V (Driver Offset, VOS) with respect to ground as shown in Figure 6. Note that the steady-state voltage (VSS) peak-to-peak swing is twice the differential voltage (VOD) and is typically 700 mV. The current mode driver provides substantial benefits over voltage mode drivers, such as an RS-422 driver. Its quiescent current remains relatively flat versus switching frequency. Whereas the RS-422 voltage mode driver increases exponentially in most case between 20 MHz-50 MHz. This is due to the overlap current that flows between the rails of the device when the internal gates switch. Whereas the current mode driver switches a fixed current between its output without any substantial overlap current. This is similar to some ECL and PECL devices, but without the heavy static I CC requirements of the ECL/PECL designs. LVDS requires > 80% less current than similar PECL devices. AC specifications for the driver are a tenfold improvement over other existing RS-422 drivers. The TRI-STATE function allows the driver outputs to be disabled, thus obtaining an even lower power state when the transmission of data is not required. The footprint of the DS90LV031A is the same as the industry standard 26LS31 Quad Differential (RS-422) Driver and is a step down replacement for the 5V DS90C031 Quad Driver. www.national.com PC Board considerations: Use at least 4 PCB layers (top to bottom); LVDS signals, ground, power, TTL signals. Isolate TTL signals from LVDS signals, otherwise the TTL may couple onto the LVDS lines. It is best to put TTL and LVDS signals on different layers which are isolated by a power/ground plane(s). Keep drivers and receivers as close to the (LVDS port side) connectors as possible. Differential Traces: Use controlled impedance traces which match the differential impedance of your transmission medium (ie. cable) and termination resistor. Run the differential pair trace lines as close together as possible as soon as they leave the IC (stubs should be < 10mm long). This will help eliminate reflections and ensure noise is coupled as common-mode. Lab experiments show that differential signals which are 1mm apart radiate far less noise than traces 3mm apart since magnetic field cancellation is greater with the closer traces. Plus, noise induced on the differential lines is much more likely to appear as common-mode which is rejected by the receiver. Match electrical lengths between traces to reduce skew. Skew between the signals of a pair means a phase difference between signals which destroys the magnetic field cancellation benefits of differential signals and EMI will result. (Note the velocity of propagation, v = c/Er where c (the speed of light) = 0.2997mm/ps or 0.0118 in/ps). Do not rely solely on the auto-route function for differential traces. Carefully review dimensions to match differential impedance and provide isolation for the differential lines. Minimize the number of vias and other discontinuities on the line. Avoid 90 turns (these cause impedance discontinuities). Use arcs or 45 bevels. Within a pair of traces, the distance between the two traces should be minimized to maintain common-mode rejection of the receivers. On the printed circuit board, this distance should remain constant to avoid discontinuities in differential impedance. Minor violations at connection points are allowable. Termination: Use a resistor which best matches the differential impedance of your transmission line. The resistor should be between 90 and 130. Remember that the current mode outputs need the termination resistor to generate the differential voltage. LVDS will not work without resistor termination. Typically, connect a single resistor across the pair at the receiver end. Surface mount 1% to 2% resistors are best. PCB stubs, component lead, and the distance from the termination to the receiver inputs should be minimized. The distance between the termination resistor and the receiver should be < 10mm (12mm MAX). 6 Fail-safe of an LVDS Interface If the LVDS link as shown in Figure 7 needs to support the case where the Line Driver is disabled, powered off, or removed (un-plugged) and the Receiver device is powered on and enabled, the state of the LVDS bus is unknown and therefore the output state of the Receiver is also unknown. If this is of concern, please consult the respective LVDS Receiver data sheet for guidance on Failafe Biasing options for the LVDS interface to set a known state on the inputs for these conditions. 10009509 FIGURE 6. Driver Output Levels Typical Application 10009508 FIGURE 7. Point-to-Point Application 7 www.national.com DS90LV031A tial mode) noise which is rejected by the receiver. For cable distances < 0.5M, most cables can be made to work effectively. For distances 0.5M d 10M, CAT 3 (category 3) twisted pair cable works well, is readily available and relatively inexpensive. Probing LVDS Transmission Lines: Always use high impedance (> 100k), low capacitance (< 2pF) scope probes with a wide bandwidth (1GHz) scope. Improper probing will give deceiving results. Cables and Connectors, General Comments: When choosing cable and connectors for LVDS it is important to remember: Use controlled impedance media. The cables and connectors you use should have a matched differential impedance of about 100. They should not introduce major impedance discontinuities. Balanced cables (e.g. twisted pair) are usually better than unbalanced cables (ribbon cable, simple coax.) for noise reduction and signal quality. Balanced cables tend to generate less EMI due to field canceling effects and also tend to pick up electromagnetic radiation as common-mode (not differen- DS90LV031A Typical Performance Curves 10009510 FIGURE 8. Typical DS90LV031A, DOUT (single ended) vs RL, TA = 25C 10009511 FIGURE 9. Typical DS90LV031A, DOUT vs RL, VCC = 3.3V, TA = 25C Pin Descriptions Pin No. Name 1, 7, 9, 15 DIN Description 2, 6, 10, 14 DOUT+ Non-inverting driver output pin, LVDS levels 3, 5, 11, 13 DOUT- Inverting driver output pin, LVDS levels Driver input pin, TTL/CMOS compatible 4 EN Active high enable pin, OR-ed with EN* 12 EN* Active low enable pin, OR-ed with EN 16 VCC Power supply pin, +3.3V 0.3V 8 GND Ground pin Ordering Information Package Type www.national.com Package Number Order Number SOP M16A DS90LV031ATM TSSOP MTC16 DS90LV031ATMTC 8 DS90LV031A Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead (0.150 Wide) Molded Small Outline Package, JEDEC Order Number DS90LV031ATM NS Package Number M16A 16-Lead (0.100 Wide) Molded Thin Shrink Small Outline Package, JEDEC Order Number DS90LV031ATMTC NS Package Number MTC16 9 www.national.com DS90LV031A 3V LVDS Quad CMOS Differential Line Driver Notes For more National Semiconductor product information and proven design tools, visit the following Web sites at: www.national.com Products Design Support Amplifiers www.national.com/amplifiers WEBENCH(R) Tools www.national.com/webench Audio www.national.com/audio App Notes www.national.com/appnotes Clock and Timing www.national.com/timing Reference Designs www.national.com/refdesigns Data Converters www.national.com/adc Samples www.national.com/samples Interface www.national.com/interface Eval Boards www.national.com/evalboards LVDS www.national.com/lvds Packaging www.national.com/packaging Power Management www.national.com/power Green Compliance www.national.com/quality/green Switching Regulators www.national.com/switchers Distributors www.national.com/contacts LDOs www.national.com/ldo Quality and Reliability www.national.com/quality LED Lighting www.national.com/led Feedback/Support www.national.com/feedback Voltage References www.national.com/vref Design Made Easy www.national.com/easy www.national.com/powerwise Applications & Markets www.national.com/solutions Mil/Aero www.national.com/milaero PowerWise(R) Solutions Serial Digital Interface (SDI) www.national.com/sdi Temperature Sensors www.national.com/tempsensors SolarMagicTM www.national.com/solarmagic PLL/VCO www.national.com/wireless www.national.com/training PowerWise(R) Design University THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION ("NATIONAL") PRODUCTS. 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