1
4251b12f
LTC4251B/LTC4251B-1/
LTC4251B-2
+
LTC4251B
UV/OV
TIMER
GATE
SENSE
VIN
VEE
LOAD
–48RTN
–48RTN
(SHORT PIN)
DIN†
DDZ13B**
R1
402k
1%
RC
10Ω RS
0.02Ω
R2
32.4k
1%
–48V
CT
150nF
C1
10nF
CC
18nF
CIN
1μF
CL
100μF
RIN*
10k
500mW
VOUT
Q1
IRF530S
4251b12 TA01a
4
3
2
1
*TWO 0.25W RESISTORS IN SERIES FOR
R
IN ON THE PCB ARE RECOMMENDED.
**DIODES, INC.
†RECOMMENDED FOR HARSH ENVIRONMENTS
GATE
5V/DIV
SENSE
2.5A/DIV
VOUT
20V/DIV
4251b12 TA01b
1ms/DIV
TYPICAL APPLICATION
FEATURES DESCRIPTION
Negative Voltage
Hot Swap Controllers in SOT-23
APPLICATIONS
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
Hot Swap and ThinSOT are trademarks of Linear Technology Corporation. All other trademarks
are the property of their respective owners.
n Hot Board Insertion
n Electronic Circuit Breaker
n –48V Distributed Power Systems
n Negative Power Supply Control
n Central Office Switching
n Programmable Current Limiting Circuit
n High Availability Servers
n Disk Arrays
n Allows Safe Board Insertion and Removal from a
Live –48V Backplane
n Floating Topology Permits Very High Voltage
Operation
n Programmable Analog Current Limit with Circuit
Breaker Timer
n Fast Response Time Limits Peak Fault Current
n Improved Ruggedness Shunt Regulator
n Programmable Timer
n Programmable Undervoltage/Overvoltage Protection
n Low Profile 6-Lead SOT-23 (ThinSOT™) Package
The LTC
®
4251B/LTC4251B-1/LTC4251B-2 negative voltage
Hot Swap™ controllers allow a board to be safely inserted
and removed from a live backplane. Output current is con-
trolled by three stages of current limiting: a timed circuit
breaker, active current limiting and a fast feedforward path
that limits peak current under worst-case catastrophic
fault conditions.
Programmable undervoltage and overvoltage detectors
disconnect the load whenever the input supply exceeds
the desired operating range. The supply input is shunt
regulated, allowing safe operation with very high supply
voltages. A multifunction timer delays initial start-up and
controls the circuit breaker’s response time.
The LTC4251B UV/OV thresholds are designed to match
the standard telecom operating range of – 43V to –75V. The
LTC4251B-1 UV/OV thresholds extend the operating range
to encompass –36V to –72V. The LTC4251B-2 implements
a UV threshold of –43V only. The LTC4251B improves the
ruggedness of the LTC4251 shunt regulator.
–48V, 2.5A Hot Swap Controller Start-Up Behavior
2
4251b12f
LTC4251B/LTC4251B-1/
LTC4251B-2
PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS
SENSE 1
VEE 2
VIN 3
6 GATE
5 UV/OV*
4 TIMER
TOP VIEW
S6 PACKAGE
6-LEAD PLASTIC SOT-23
*UV FOR LTC4251B-2
TJMAX = 125°C, θJA = 192°C/W
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VZVIN to VEE Zener Voltage IIN = 2mA l11.5 13 14.5 V
rZVIN to VEE Zener Dynamic Impedance IIN = 2mA to 30mA 5 Ω
IIN VIN Supply Current UV/OV = 4V, VIN = (VZ – 0.3V) l0.8 2 mA
VLKO VIN Undervoltage Lockout Coming Out of UVLO (Rising VIN)l9.2 11.5 V
VLKH VIN Undervoltage Lockout Hysteresis 1 V
VCB Circuit Breaker Current Limit Voltage VCB = (VSENSE – VEE)l40 50 60 mV
VACL Analog Current Limit Voltage VACL = (VSENSE – VEE)l80 100 120 mV
VFCL Fast Current Limit Voltage VFCL = (VSENSE – VEE)l150 200 300 mV
IGATE GATE Pin Output Current UV/OV = 4V, VSENSE = VEE, VGATE = 0V (Sourcing)
UV/OV = 4V, VSENSE – VEE = 0.15V, VGATE = 3V (Sinking)
UV/OV = 4V, VSENSE – VEE = 0.3V, VGATE = 1V (Sinking)
l40 58
17
190
80 μA
mA
mA
VGATE External MOSFET Gate Drive VGATE – VEE, IIN = 2mA l10 12 VZV
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Notes 2, 3)
ORDER INFORMATION
Current into VIN (100μs Pulse) .............................100mA
Minimum VIN Voltage ............................................ –0.3V
Gate, UV/OV, Timer Voltage........................ –0.3V to 16V
Sense Voltage ............................................ –0.6V to 16V
Current Out of Sense Pin (20μs Pulse) .............. –200mA
Maximum Junction Temperature .......................... 125°C
Operating Temperature Range
LTC4251BC/LTC4251BC-1/LTC4251BC-2 ....0°C to 70°C
LTC4251BI/LTC4251BI-1/LTC4251BI-2 .. –40°C to 85°C
Storage Temperature Range .................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec) ................... 300°C
(Note 1), All Voltages are Referred to VEE
Lead Free Finish
TAPE AND REEL (MINI) TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC4251BCS6#TRMPBF LTC4251BCS6#TRPBF LTGCT 6-Lead Plastic SOT-23 0°C to 70°C
LTC4251BIS6#TRMPBF LTC4251BIS6#TRPBF LTGCT 6-Lead Plastic SOT-23 –40°C to 85°C
LTC4251BCS6-1#TRMPBF LTC4251BCS6-1#TRPBF LTGDV 6-Lead Plastic SOT-23 0°C to 70°C
LTC4251BIS6-1#TRMPBF LTC4251BIS6-1#TRPBF LTGDV 6-Lead Plastic SOT-23 –40°C to 85°C
LTC4251BCS6-2#TRMPBF LTC4251BCS6-2#TRPBF LTGDW 6-Lead Plastic SOT-23 0°C to 70°C
LTC4251BIS6-2#TRMPBF LTC4251BIS6-2#TRPBF LTGDW 6-Lead Plastic SOT-23 –40°C to 85°C
TRM = 500 pieces. *Temperature grades are identified by a label on the shipping container.
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
3
4251b12f
LTC4251B/LTC4251B-1/
LTC4251B-2
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VGATEL Gate Low Threshold (Before Gate Ramp-Up) 0.5 V
VUVHI UV Threshold High LTC4251B/LTC4251B-2
LTC4251B-1
l
l
3.075
2.300
3.225
2.420
3.375
2.540
V
V
VUVLO UV Threshold Low LTC4251B/LTC4251B-2
LTC4251B-1
l
l
2.775
2.050
2.925
2.160
3.075
2.270
V
V
VUVHST UV Hysteresis LTC4251B/LTC4251B-2
LTC4251B-1
0.30
0.26
V
V
VOVHI OV Threshold High LTC4251B
LTC4251B-1
l
l
5.85
5.86
6.15
6.17
6.45
6.48
V
V
VOVLO OV Threshold Low LTC4251B
LTC4251B-1
l
l
5.25
5.61
5.55
5.91
5.85
6.21
V
V
VOVHST OV Hysteresis LTC4251B
LTC4251B-1
0.60
0.26
V
V
ISENSE SENSE Input Current UV/OV = 4V, VSENSE = 50mV l–30 –15 μA
IINP UV/OV Input Current UV/OV = 4V l±0.1 ±1 μA
VTMRH Timer Voltage High Threshold 4V
VTMRL Timer Voltage Low Threshold 1V
ITMR Timer Current Timer On (Initial Cycle, Sourcing), VTMR = 2V
Timer Off (Initial Cycle, Sinking), VTMR = 2V
Timer On (Circuit Breaker, Sourcing), VTMR = 2V
Timer Off (Cooling Cycle, Sinking), VTMR = 2V
5.8
28
230
5.8
μA
mA
μA
μA
tPLLUG UV Low to GATE Low 0.7 μs
tPHLOG OV High to GATE Low LTC4251B/LTC4251B-1 1 μs
VIN (V)
024 6810121416182022
IIN (mA)
1000
100
10
1
0.1
4251b12 G02
TA = –40°C
TA = 125°C
TA = 25°C
TA = 85°C
IIN vs Temperature IIN vs VIN rZ vs Temperature
UV/OV = 4V refers to UV = 4V for the LTC4251B-2.
Note 2: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to VEE unless otherwise
specified.
Note 3: UV/OV = 4V refers to UV = 4V for the LTC4251B-2.
TYPICAL PERFORMANCE CHARACTERISTICS
TEMPERATURE (°C)
–55
IIN (μA)
2000
1800
1600
1400
1200
1000
800
600
400
200
0–15 25 45 125
4251b12 G01
–35 5 65 85 105
VIN = (VZ – 0.3V)
TEMPERATURE (°C)
–55
rZ (Ω)
10
9
8
7
6
5
4
3
2–15 25 45 125
4251b12 G03
–35 5 65 85 105
IIN = 2mA
4
4251b12f
LTC4251B/LTC4251B-1/
LTC4251B-2
TYPICAL PERFORMANCE CHARACTERISTICS
Circuit Breaker Current Limit
Voltage VCB vs Temperature
Analog Current Limit Voltage VACL
vs Temperature
Fast Current Limit Voltage VFCL
vs Temperature
IGATE (Source) vs Temperature IGATE (ACL, Sink) vs Temperature IGATE (FCL, Sink) vs Temperature
UV/OV = 4V refers to UV = 4V for the LTC4251B-2.
VZ vs Temperature
Undervoltage Lockout VLKO vs
Temperature
Undervoltage Lockout Hysteresis
VLKH vs Temperature
TEMPERATURE (°C)
–55
VZ (V)
14.5
14.0
13.5
13.0
12.5
12.0 –15 25 45 125
4251b12 G04
–35 5 65 85 105
IIN = 2mA
TEMPERATURE (°C)
–55
VLKO (V)
12.0
11.5
11.0
10.5
10.0
9.5
9.0
8.5
8.0 –15 25 45 125
4251b12 G05
–35 5 65 85 105
TEMPERATURE (°C)
–55
VLKH
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0–15 25 45 125
4251b12 G06
–35 5 65 85 105
TEMPERATURE (°C)
–55
VCB (mV)
60
58
56
54
52
50
48
46
44
42
40 –15 25 45 125
4251b12 G07
–35 5 65 85 105
TEMPERATURE (°C)
–55
VACL (V)
120
115
110
105
100
95
90
85
80 –15 25 45 125
4251b12 G08
–35 5 65 85 105
TEMPERATURE (°C)
–55
VFCL (mV)
300
275
250
225
200
175
150 –15 25 45 125
4251b12 G09
–35 5 65 85 105
TEMPERATURE (°C)
–55
IGATE (μA)
70
65
60
55
50
45
40 –15 25 45 125
4251b12 G10
–35 5 65 85 105
UV/0V = 4V
TIMER = 0V
VSENSE = VEE
VGATE = 0V
TEMPERATURE (°C)
–55
IGATE (mA)
30
25
20
15
10
5
0–15 25 45 125
4251b12 G11
–35 5 65 85 105
UV/0V = 4V
TIMER = 0V
VSENSE – VEE = 0.15V
VGATE = 3V
TEMPERATURE (°C)
–55
IGATE (mA)
400
350
300
250
200
150
100
50
0–15 25 45 125
4251b12 G12
–35 5 65 85 105
UV/0V = 4V
TIMER = 0V
VSENSE – VEE = 0.3V
VGATE = 1V
5
4251b12f
LTC4251B/LTC4251B-1/
LTC4251B-2
TYPICAL PERFORMANCE CHARACTERISTICS
OV Threshold vs Temperature
ISENSE vs Temperature ISENSE vs (VSENSE – VEE)TIMER Threshold vs Temperature
VGATE vs Temperature VGATEL vs Temperature UV Threshold vs Temperature
UV Threshold vs Temperature OV Threshold vs Temperature
UV/OV = 4V refers to UV = 4V for the LTC4251B-2.
TEMPERATURE (°C)
–55
UV THRESHOLD (V)
3.375
3.275
3.175
3.075
2.975
2.875
2.775 –15 25 45 125
4251b12 G15
–35 5 65 85 105
VUVH
LTC4251B/LTC4251B-2
VUVL
TEMPERATURE (°C)
–55
UV THRESHOLD (V)
2.55
2.50
2.45
2.40
2.35
2.30
2.25
2.20
2.15
2.10
2.05 –15 25 45 125
4251b12 G16
–35 5 65 85 105
VUVHI
LTC4251B-1
VUVLO
TEMPERATURE (°C)
–55
OV THRESHOLD (V)
6.45
6.25
6.05
5.85
5.65
5.45
5.25 –15 25 45 125
4251b12 G17
–35 5 65 85 105
VOVH
LTC4251B
VOVL
TEMPERATURE (°C)
–55
VGATEL (V)
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0–15 25 45 125
4251b12 G14
–35 5 65 85 105
UV/0V = 4V,
VTMR = 0V,
GATE THRESHOLD
BEFORE RAMP-UP
TEMPERATURE (°C)
–55
VGATE (V)
14.5
14.0
13.5
13.0
12.5
12.0
11.5
11.0
10.5
10.0 –15 25 45 125
4251b12 G13
–35 5 65 85 105
UV/0V = 4V
VTMR = 0V
VSENSE = VEE
TEMPERATURE (°C)
–55
ISENSE (μA)
–10
–12
–14
–16
–18
–20
–22
–24
–26
–28
–30 –15 25 45 125
4251b12 G19
–35 5 65 85 105
UV/0V = 4V
TIMER = 0V
GATE = HIGH
VSENSE – VEE = 50mV
(VSENSE – VEE) (V)
–1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0
–ISENSE (mA)
0.01
0.1
1.0
10
100
1000
4251b12 G20
UV/0V = 4V
TIMER = 0V
GATE = HIGH
TA = 25°C
TEMPERATURE (°C)
–55
TIMER THRESHOLD (V)
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0–15 25 45 125
4251b12 G21
–35 5 65 85 105
VTMRH
VTMRL
TEMPERATURE (°C)
–55
OV THRESHOLD (V)
6.51
6.41
6.31
6.21
6.11
6.01
5.91
5.81
5.71
5.61 –15 25 45 125
4251b12 G18
–35 5 65 85 105
VOVHI
VOVLO
LTC4251B-1
6
4251b12f
LTC4251B/LTC4251B-1/
LTC4251B-2
TYPICAL PERFORMANCE CHARACTERISTICS
ITMR (Cooling Cycle, Sinking)
vs Temperature tPLLUG and tPHLOG vs Temperature
ITMR (Initial Cycle, Sourcing) vs
Temperature
ITMR (Circuit Breaking, Sourcing)
vs Temperature
ITMR (Initial Cycle, Sinking) vs
Temperature
UV/OV = 4V refers to UV = 4V for the LTC4251B-2.
TEMPERATURE (°C)
–55
DELAY (μs)
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5 –15 25 45 125
4251b12 G26
–35 5 65 85 105
tPLLUG
tPHLOG (LTC4251B/LTC4251B-1)
TEMPERATURE (°C)
–55
ITMR (μA)
10
9
8
7
6
5
4
3
2
1
0–15 25 45 125
4251b12 G22
–35 5 65 85 105
TEMPERATURE (°C)
–55
ITMR (mA)
50
45
40
35
30
25
20
15
10 –15 25 45 125
4251b12 G23
–35 5 65 85 105
TEMPERATURE (°C)
–55
ITMR (μA)
280
260
240
220
200
180 –15 25 45 125
4251b12 G24
–35 5 65 85 105
TEMPERATURE (°C)
–55
ITMR (μA)
10
9
8
7
6
5
4
3
2
1
0–15 25 45 125
4251b12 G25
–35 5 65 85 105
7
4251b12f
LTC4251B/LTC4251B-1/
LTC4251B-2
PIN FUNCTIONS
SENSE (Pin 1): Circuit Breaker/Current Limit SENSE Pin.
Load current is monitored by sense resistor RS con-
nected between SENSE and VEE, and controlled in three
steps. If SENSE exceeds VCB (50mV), the circuit breaker
comparator activates a 230μA TIMER pin pull-up cur-
rent. The LTC4251B/LTC4251B-1/LTC4251B-2 latch off
when CT charges to 4V. If SENSE exceeds VACL (100mV),
the analog current limit amplifier pulls GATE down and
regulates the MOSFET current at VACL/RS. In the event
of a catastrophic short-circuit, SENSE may overshoot
100mV. If SENSE reaches VFCL (200mV), the fast current
limit comparator pulls GATE low with a strong pull-down.
To disable the circuit breaker and current limit functions,
connect SENSE to VEE.
Kelvin-sense connections between the sense resistor and
the VEE and SENSE pins are strongly recommended, see
Figure 6.
VEE (Pin 2): Negative Supply Voltage Input. Connect this
pin to the negative side of the power supply.
VIN (Pin 3): Positive Supply Input. Connect this pin to the
positive side of the supply through a dropping resistor.
A shunt regulator typically clamps VIN at 13V. An internal
undervoltage lockout (UVLO) circuit holds GATE low until
the VIN pin is greater than VLKO (9.2V), overriding UV/OV. If
UV is high, OV is low and VIN comes out of UVLO, TIMER
starts an initial timing cycle before initiating a GATE ramp
up. If VIN drops below approximately 8.2V, GATE pulls low
immediately.
TIMER (Pin 4): Timer Input. TIMER is used to generate
a delay at start-up, and to delay shutdown in the event of
an output overload. TIMER starts an initial timing cycle
when the following conditions are met: UV is high, OV is
low, VIN clears UVLO, TIMER pin is low, GATE is lower than
VGATEL and VSENSE – VEE < VCB. A pull-up current of 5.8μA
then charges CT, generating a time delay. If CT charges to
VTMRH (4V) the timing cycle terminates, TIMER quickly
pulls low and GATE is activated.
If SENSE exceeds 50mV while GATE is high, a 230μA
pull-up current charges CT. If SENSE drops below 50mV
before TIMER reaches 4V, a 5.8μA pull-down current slowly
discharges CT. In the event that CT eventually integrates
up to the 4V VTMRH threshold, TIMER latches high with
a 5.8μA pull-up source and GATE quickly pulls low. The
LTC4251B/LTC4251B-1/LTC4251B-2 fault latches may
be cleared by either pulling TIMER low with an external
device, or by pulling UV/OV below VUVLO.
UV/OV (Pin 5): Undervoltage/Overvoltage Input. This dual
function pin detects undervoltage as well as overvoltage.
The high threshold at the UV comparator is set at VUVHI
with VUVHST hysteresis. The high threshold at the OV
comparator is set at VOVHI with VOVHST hysteresis. If UV/
OV < VUVLO or UV/OV > VOVHI, GATE pulls low. If UV/OV
> VUVHI and UV/OV < VOVLO, the LTC4251B/LTC4251B-1/
LTC4251B-2 attempt to start-up. The internal UVLO at VIN
always overrides UV/OV. A low at UV resets an internal fault
latch. A high at OV pulls GATE low but does not reset the
fault latch. A 1nF to 10nF capacitor at UV/OV eliminates
transients and switching noise from affecting the UV/OV
thresholds and prevents glitches at the GATE pin.
GATE (Pin 6): N-Channel MOSFET Gate Drive Output.
This pin is pulled high by a 58μA current source. GATE is
pulled low by invalid conditions at VIN (UVLO), UV/OV, or
the fault latch. GATE is actively servoed to control fault
current as measured at SENSE. A compensation capacitor
at GATE stabilizes this loop. A comparator monitors GATE
to ensure that it is low before allowing an initial timing
cycle, GATE ramp up after an overvoltage event, or restart
after a current limit fault.
UV/OV refers to the UV pin for the LTC4251B-2. The OV comparator in the LTC4251B-2 is disabled. All
references in the text to overvoltage, OV, VOVHI and VOVLO do not apply to the LTC4251B-2.
8
4251b12f
LTC4251B/LTC4251B-1/
LTC4251B-2
BLOCK DIAGRAM
–
+
4251b12 BD
–
+
–
+
–
+
–
+
–
+
–
+
VIN VIN
VIN
VEE
VEE VEE
VEE
VEE
VEE
VEE
5.8μA
5.8μA
22μA
VIN
VIN
58μA
230μA
TIMER
VOVHI
VUVLO
4V
1V
LOGIC
+
–
+
–
VEE
VEE
VOS = 10mV
200mV
–
+
0.5V
UV/OV*
OV**
UV
GATE
SENSE
6
1
2
3
5
4
5k
CB
FCL
50mV
+
–
ACL
*UV FOR THE LTC4251B-2
** THE OV COMPARATOR IS DISABLED FOR LTC4251B-2
9
4251b12f
LTC4251B/LTC4251B-1/
LTC4251B-2
OPERATION
Hot Circuit Insertion
When circuit boards are inserted into a live backplane, the
supply bypass capacitors can draw huge transient currents
from the power bus as they charge. The flow of current
damages the connector pins and glitches the power bus,
causing other boards in the system to reset. The LTC4251B/
LTC4251B-1/LTC4251B-2 are designed to turn on a circuit
board supply in a controlled manner, allowing insertion or
removal without glitches or connector damage.
Initial Start-Up
The LTC4251B/LTC4251B-1/LTC4251B-2 reside on a re-
movable circuit board and control the path between the
connector and load or power conversion circuitry with an
external MOSFET switch (see Figure 1). Both inrush control
and short-circuit protection are provided by the MOSFET.
A detailed schematic is shown in Figure 2. –48V and
–48RTN receive power through the longest connector pins,
and are the first to connect when the board is inserted.
The GATE pin holds the MOSFET off during this time. UV/
OV determines whether or not the MOSFET should be
turned on based upon internal, high accuracy thresholds
and an external divider. UV/OV does double duty by also
monitoring whether or not the connector is seated. The top
of the divider detects –48RTN by way of a short connector
pin that is the last to mate during the insertion sequence.
Interlock Conditions
A start-up sequence commences once five initial “interlock”
conditions are met:
1. The input voltage VIN exceeds 9.2V (VLKO)
2. The voltage at UV/OV falls within the range of VUVHI to
VOVLO (UV > VUVHI, LTC4251B-2)
3. The (SENSE – VEE) voltage is <50mV (VCB)
4. The voltage on the timer capacitor (CT) is less than 1V
(VTMRL)
5. GATE is less than 0.5V (VGATEL)
The first two conditions are continuously monitored and
the latter three are checked prior to initial timing or GATE
ramp-up. Upon exiting an OV condition, the TIMER pin
voltage requirement is inhibited. Details are described in
the Applications Information, Timing Waveforms section.
TIMER begins the start-up sequence by sourcing 5.8μA
into CT. If VIN or UV/OV falls out of range, the start-up
cycle stops and TIMER discharges CT to less than 1V,
then waits until the aforementioned conditions are once
again met. If CT successfully charges to 4V, TIMER pulls
low and GATE is released. GATE sources 58μA (IGATE),
charging the MOSFET gate and associated capacitance.
Note that for simplicity, the following assumptions are made in the text. Firstly, UV/OV also means the UV
pin of the LTC4251B-2. Secondly, all overvoltage conditions and references to OV, VOVHI and VOVLO do not apply to the LTC4251B-2 as
the OV comparator in this part is disabled.
Figure 1. Basic LTC4251B Hot Swap Topology
Figure 2. –48V, 2.5A Hot Swap Controller
4251b12 F01
LTC4251B
CLOAD
ISOLATED
DC/DC
CONVERTER
MODULE
LOW
VOLTAGE
CIRCUITRY
++
––
PLUG-IN BOARD
BACKPLANE
–48RTN
–48V
+
34
12 4251b12 F02
–48RTN
–48V
UV/OV
TIMER
VEE
VIN
SENSE GATE
LTC4251B
R1
402k
1%
R2
32.4k
1% CT
150nF
CC
18nF
RS
20mΩ
Q1
IRF530S
RC
10Ω
RIN
10k
500mW
C1
10nF
CIN
1μF
DIN†
DDZ13B**
CL
100μF
TYP
LONG
LONG
SHORT
**DIODES, INC.
†RECOMMENDED FOR HARSH ENVIRONMENTS
+
10
4251b12f
LTC4251B/LTC4251B-1/
LTC4251B-2
Two modes of operation are possible during the time the
MOSFET is first turning on, depending on the values of
external components, MOSFET characteristics and nomi-
nal design current. One possibility is that the MOSFET
will turn on gradually so that the inrush into the load
capacitance remains a low value. The output will simply
ramp to –48V and the MOSFET will be fully enhanced.
A second possibility is that the load current exceeds the
current limit threshold of 100mV/RS. In this case, the
LTC4251B/LTC4251B-1/LTC4251B-2 will ramp the output
by sourcing 100mV/RS current into the load capacitance.
It is important to set the timer delay so that, regardless
of which start-up mode is used, the start-up time is less
than the TIMER delay time. If this condition is not met,
the LTC4251B/LTC4251B-1/LTC4251B-2 may shutdown
after one TIMER delay.
Board Removal
If the board is withdrawn from the card cage, the UV/OV
divider is the first to lose connection. This shuts off the
MOSFET and commutates the flow of current in the con-
nector. When the power pins subsequently separate, there
is no arcing.
Current Control
Three levels of protection handle short-circuit and over-
load conditions. Load current is monitored by SENSE and
resistor RS. There are three distinct thresholds at SENSE:
50mV for a timed circuit breaker function; 100mV for an
analog current limit loop; and 200mV for a fast, feedfor-
ward comparator which limits peak current in the event
of a catastrophic short-circuit.
If, owing to an output overload, the voltage drop across RS
exceeds 50mV, TIMER sources 230μA into CT. CT eventually
charges to a 4V threshold and the LTC4251B/LTC4251B-1/
LTC4251B-2 latchoff. If the overload goes away and SENSE
measures less than 50mV, CT slowly discharges (5.8μA).
OPERATION
In this way the circuit breaker function will also respond
to low duty cycle overloads, and accounts for fast heating
and slow cooling characteristic of the MOSFET.
Higher overloads are handled by an analog current limit
loop. If the drop across RS reaches 100mV, the current
limiting loop servos the MOSFET gate and maintains a
constant output current of 100mV/RS. Note that because
SENSE > 50mV, TIMER charges CT during this time and
the LTC4251B/LTC4251B-1/LTC4251B-2 will eventually
shut down.
Low impedance failures on the load side of the LTC4251B/
LTC4251B-1/LTC4251B-2 coupled with 48V or more driving
potential can produce current slew rates well in excess of
50A/μs. Under these conditions, overshoot is inevitable. A
fast SENSE comparator with a threshold of 200mV detects
overshoot and pulls GATE low much harder and hence
much faster than can the weaker current limit loop. The
100mV/RS current limit loop then takes over, and servos
the current as previously described. As before, TIMER
runs and latches the LTC4251B/LTC4251B-1/LTC4251B-2
off when CT reaches 4V.
The LTC4251B/LTC4251B-1/LTC4251B-2 circuit breaker
latch is reset by either pulling UV/OV momentarily low, or
dropping the input voltage VIN below the internal UVLO
threshold of 8.2V.
Although short-circuits are the most obvious fault type,
several operating conditions may invoke overcurrent
protection. Noise spikes from the backplane or load, input
steps caused by the connection of a second, higher voltage
supply, transient currents caused by faults on adjacent
circuit boards sharing the same power bus, or the inser-
tion of non-hot swappable products could cause higher
than anticipated input current and temporary detection
of an overcurrent condition. The action of TIMER and CT
rejects these events allowing the LTC4251B/LTC4251B-1/
LTC4251B-2 to “ride out” temporary overloads and distur-
bances that would trip a simple current comparator and
in some cases, blow a fuse.
11
4251b12f
LTC4251B/LTC4251B-1/
LTC4251B-2
SHUNT REGULATOR
A fast responding shunt regulator clamps the VIN pin to
13V (VZ). Power is derived from –48RTN by an external
current limiting resistor, RIN. A 1μF decoupling capacitor,
CIN filters supply transients and contributes a short delay
at start-up.
To meet creepage requirements RIN may be split into two
or more series connected units, such as two 5.1k or three
3.3k resistors. This introduces a wider total spacing than is
possible with a single component while at the same time
ballasting the potential across the gap under each resistor.
The LTC4251B is fundamentally a low voltage device that
operates with –48V as its reference ground. To further
protect against arc discharge into its pins, the area in
and around the LTC4251B and all associated components
should be free of any other planes such as chassis ground,
return, or secondary-side power and ground planes.
VIN is rated handle 30mA within the thermal limits of the
package, and is tested to survive a 100μs, 100mA pulse. To
protect VIN against damage from higher amplitude spikes,
clamp VIN to VEE with a 13V Zener diode. Star connect
VEE and all VEE referred components to the sense resistor
Kelvin terminal as illustrated in Figure 2, keeping trace
lengths between VIN, CIN, DIN and VEE as short as possible.
INTERNAL UNDERVOLTAGE LOCKOUT (UVLO)
Internal circuitry monitors VIN for undervoltage. The exact
thresholds are defined by VLKO and its hysteresis, VLKH.
When VIN rises above 9.2V (VLKO) the chip is enabled;
below 8.2V (VLKO-VLKH) it is disabled and GATE is pulled
low. The UVLO function at VIN should not be confused with
the UV/OV pin. These are completely separate functions.
UV/OV COMPARATORS
Two hysteretic comparators for detecting under- and
overvoltage conditions, with the following thresholds,
monitor the dual function UV/OV pin:
UV turning on at VUVHI
UV turning off at VUVLO
APPLICATIONS INFORMATION
OV turning off at VOVHI
OV turning on at VOVLO
The UV and OV trip point ratio for LTC4251B is designed to
match the standard telecom operating range of 43V to 75V.
The LTC4251B-2 implements a UV threshold of 43V only.
A divider (R1, R2) is used to scale the supply voltage. Using
R1 = 402k and R2 = 32.4k gives a typical operating range
of 43.2V to 74.4V. The under- and overvoltage shutdown
thresholds are then 39.2V and 82.5V. 1% divider resistors
are recommended to preserve threshold accuracy. The
same resistor values can be used for the LTC4251B-2.
The R1-R2 divider values shown in the Typical Application
set a standing current of slightly more than 100μA, and
define an impedance at UV/OV of 30k. In most applica-
tions, 30k impedance coupled with 300mV UV hysteresis
makes the LTC4251B/LTC4251B-1/LTC4251B-2 insensitive
to noise. If more noise immunity is desired, add a 1nF to
10nF filter capacitor from UV/OV to VEE.
The UV and OV trip point thresholds for the LTC4251B-1
are designed to encompass the standard telecom operating
range of –36V to –72V.
A divider (R1, R2) is used to scale the supply voltage.
Using R1 = 442k and R2 = 34.8k gives a typical operating
range of 33.2V to 81V. The typical under- and overvoltage
shutdown thresholds are then 29.6V and 84.5V. 1% divider
resistors are recommended to preserve threshold accuracy.
The R1-R2 divider values shown in the Typical Application
set a standing current of slightly more than 100μA, and
define an impedance at UV/OV of 32k. In most applica-
tions, 32k impedance coupled with 260mV UV hysteresis
makes the LTC4251B-1 insensitive to noise. If more noise
immunity is desired, add a 1nF to 10nF filter capacitor
from UV/OV to VEE.
UV/OV OPERATION
A low input to the UV comparator will reset the chip and
pull the GATE and TIMER pins low. A low-to-high UV
transition will initiate an initial timing sequence if the three
remaining interlock conditions are met.
12
4251b12f
LTC4251B/LTC4251B-1/
LTC4251B-2
Overvoltage conditions detected by the OV comparator
will also pull GATE low, thereby shutting down the load,
but it will not reset the circuit breaker latch. Returning the
supply voltage to an acceptable range restarts the GATE
pin provided all interlock conditions except TIMER are met.
TIMER
The operation of the TIMER pin is somewhat complex as
it handles several key functions. A capacitor, CT, is used at
TIMER to provide timing for the LTC4251B/LTC4251B-1/
LTC4251B-2. Four different charging and discharging
modes are available at TIMER:
1. 5.8μA slow charge; initial timing delay
2. 230μA fast charge; circuit breaker delay
3. 5.8μA slow discharge; circuit breaker “cool-off”
4. Low impedance switch; resets capacitor after initial
timing delay, in undervoltage lockout, and in overvoltage
For initial startup, the 5.8μA pull-up is used. The low im-
pedance switch is turned off and the 5.8μA current source
is enabled when the four interlock conditions are met. CT
charges to 4V in a time period given by:
t=4V • CT
5.8μA
(1)
When CT reaches 4V (VTMRH), the low impedance switch
turns on and discharges CT. The GATE output is enabled
and the load turns on.
CIRCUIT BREAKER TIMER OPERATION
If the SENSE pin detects more than 50mV across RS, the
TIMER pin charges CT with 230μA. If CT charges to 4V,
the GATE pin pulls low and the LTC4251B/LTC4251B-1/
LTC4251B-2 latch off. The part remains latched off until
either the UV/OV pin is momentarily pulsed low, or VIN
dips into UVLO and is then restored. The circuit breaker
timeout period is given by
t=4V • CT
230μA
(2)
Intermittent overloads may exceed the 50mV threshold at
SENSE, but if their duration is sufficiently short TIMER will
not reach 4V and the LTC4251B/LTC4251B-1/LTC4251B-2
will not latch off. To handle this situation, the TIMER
discharges CT slowly with a 5.8μA pull-down whenever
the SENSE voltage is less than 50mV. Therefore any inter-
mittent overload with an aggregate duty cycle of 2.5% or
more will eventually trip the circuit breaker and latch off
the LTC4251B/LTC4251B-1/LTC4251B-2. Figure 3 shows
the circuit breaker response time in seconds normalized
to 1μF. The asymmetric charging and discharging of CT is
a fair gauge of MOSFET heating.
APPLICATIONS INFORMATION
GATE
GATE is pulled low to VEE under any of the following
conditions: in UVLO, during the initial timing cycle, in an
overvoltage condition, or when the LTC4251B/LTC4251B-1/
LTC4251B-2 are latched off after a short-circuit. When GATE
turns on, a 58μA current source charges the MOSFET gate
and any associated external capacitance. VIN limits gate
drive to no more than 14.5V.
Gate-drain capacitance (CGD) feed through at the first
abrupt application of power can cause a gate-source
voltage sufficient to turn on the MOSFET. A unique circuit
pulls GATE low with practically no usable voltage at VIN,
and eliminates current spikes at insertion. A large external
gate-source capacitor is thus unnecessary for the purpose
of compensating CGD. Instead, a smaller value (≥10nF)
capacitor CC is adequate. CC also provides compensation
for the analog current limit loop.
Figure 3. Circuit Breaker Response Time
FAULT DUTY CYCLE, D (%)
20 40 60 800
NORMALIZED RESPONSE TIME (s/μF)
10
1
0.1
0.01 100
4251b12 F03
t
CT(μF)
4
t%o
=
13
4251b12f
LTC4251B/LTC4251B-1/
LTC4251B-2
SENSE
The SENSE pin is monitored by the circuit breaker (CB)
comparator, the analog current limit (ACL) amplifier, and
the fast current limit (FCL) comparator. Each of these
three measures the potential of SENSE relative to VEE. If
SENSE exceeds 50mV, the CB comparator activates the
230μA TIMER pull-up. At 100mV, the ACL amplifier servos
the MOSFET current, and at 200mV the FCL comparator
abruptly pulls GATE low in an attempt to bring the MOSFET
current under control. If any of these conditions persists
long enough for TIMER to charge CT to 4V (see Equa-
tion (2)), the LTC4251B/LTC4251B-1/LTC4251B-2 latch
off and pull GATE low.
If the SENSE pin encounters a voltage greater than 100mV,
the ACL amplifier will servo GATE downwards in an attempt
to control the MOSFET current. Since GATE overdrives the
MOSFET in normal operation, the ACL amplifier needs time
to discharge GATE to the threshold of the MOSFET. For a
mild overload, the ACL amplifier can control the MOSFET
current, but in the event of a severe overload the current
may overshoot. At SENSE = 200mV, the FCL comparator
takes over, quickly discharging the GATE pin to near VEE
potential. FCL then releases, and the ACL amplifier takes
over. All the while TIMER is running. The effect of FCL is
to add a nonlinear response to the control loop in favor
of reducing MOSFET current.
Owing to inductive effects in the system, FCL typically
overcorrects the current limit loop, and GATE undershoots.
A zero in the loop (resistor RC in series with the gate
capacitor) helps the ACL amplifier recover.
SHORT-CIRCUIT OPERATION
Circuit behavior arising from a load-side low impedance
short is shown in Figure 4. Initially, the current overshoots
the analog current limit level of VSENSE = 100mV (Trace 2)
as the GATE pin works to bring VGS under control (Trace3).
The overshoot glitches the backplane in the negative
direction, and when the current is reduced to 100mV/RS
the backplane responds by glitching in the positive
direction.
TIMER commences charging CT (Trace 4) while the
analog current limit loop maintains the fault current at
100mV/RS, which in this case is 5A (Trace 2). Note that
the backplane voltage (Trace 1) sags under load. When CT
reaches 4V,
GATE turns off, the load current drops to zero
and the backplane rings up to over 100V. The positive peak
is usually limited by avalanche breakdown in the MOSFET,
and can be further limited by adding a transient voltage
suppressor across the input from – 48V to –48RTN, such
as Diodes Inc. SMAT70A.
A low impedance short on one card may influence the
behavior of others sharing the same backplane. The initial
glitch and backplane sag as seen in Figure 4, Trace 1, can
rob charge from output capacitors on adjacent cards. When
the faulty card shuts down, current flows in to refresh the
capacitors. If LTC4251B, LTC4251B-1 or
LTC4251B-2s
are used throughout, they respond by limiting the inrush
current to a value of 100mV/RS. If CT is sized correctly, the
capacitors will recharge long before CT times out.
APPLICATIONS INFORMATION
MOSFET SELECTION
The external MOSFET switch must have adequate safe
operating area (SOA) to charge the load capacitance on
start-up and handle short-circuit conditions until TIMER
latchoff. These considerations take precedence over DC
current ratings. A MOSFET with adequate SOA for a given
application can always handle the required current, but
the opposite cannot be said. Consult the manufacturer’s
MOSFET data sheet for safe operating area and effective
transient thermal impedance curves.
Figure 4. Output Short-Circuit Behavior
(All Waveforms are Referenced to VEE)
GATE
10V/DIV
SENSE
200mV/DIV
–48RTN
50V/DIV
TIMER
5V/DIV
4251b12 F04
SUPPLY RING
OWING
TO CURRENT
OVERSHOOT
SUPPLY RING
OWING TO
MOSFET
TURN-OFF
ONSET OF OUTPUT
SHORT-CIRCUIT
FAST CURRENT
LIMIT
ANALOG
CURRENT LIMIT
CTIMER RAMP
LATCH OFF
TRACE 1
TRACE 2
TRACE 3
TRACE 4
2ms/DIV
14
4251b12f
LTC4251B/LTC4251B-1/
LTC4251B-2
MOSFET selection is a three-step process. First, RS is
calculated, and then the time required to charge the load
capacitance is determined. This timing, along with the
maximum short-circuit current and maximum input volt-
age defines an operating point that is checked against the
MOSFET’s SOA curve.
To begin a design, first specify the required load current
and load capacitance, IL and CL. The circuit breaker current
trip point (50mV/RS) should be set to accommodate the
maximum load current. Note that maximum input current
to a DC/DC converter is expected at VSUPPLY (MIN). RS is
given by:
RS=40mV
IL(MAX)
(3)
where 40mV represents the guaranteed minimum circuit
breaker threshold.
During the initial charging process, the LTC4251B/
LTC4251B-1/LTC4251B-2 may operate the MOSFET in
current limit, forcing 80mV to 120mV across RS. The
minimum inrush current is given by:
IINRUSH(MIN) =80mV
RS
(4)
Maximum short-circuit current limit is calculated using
maximum VSENSE, or:
ISHORT-CIRCUIT(MAX) =120mV
RS
(5)
The TIMER capacitor CT must be selected based on the
slowest expected charging rate; otherwise TIMER might
time out before the load capacitor is fully charged. A value
for CT is calculated based on the maximum time it takes
the load capacitor to charge. That time is given by:
tCL CHARGE =C•V
I=CL•V
SUPPLY(MAX)
IINRUSH(MIN)
(6)
Substituting Equation (4) for IINRUSH(MIN) and equating
(6) with (2) gives:
CT=CL•V
SUPPLY (MAX) •RS• 230μA
(4V • 80mV)
(7)
Returning to Equation (2), the TIMER period is calcu-
lated and used in conjunction with VSUPPLY(MAX) and
ISHORT-CIRCUIT(MAX) to check the SOA curves of a prospec-
tive MOSFET.
As a numerical design example, consider a 30W load,
which requires 1A input current at 36V. If VSUPPLY(MAX) =
72V and CL = 100μF, Equation (3) gives RSENSE = 40mΩ;
Equation (7) gives CT = 207nF. To account for errors in
RSENSE, CT, TIMER current (230μA) and TIMER threshold
(4V), the calculated value should be multiplied by 1.5,
giving a nearest standard value of CT = 330nF.
If a short-circuit occurs, a current of up to 120mV/40mΩ
= 3A will flow in the MOSFET for 5.7ms as dictated by
CT = 330nF in Equation (2). The MOSFET must be selected
based on this criterion. The IRF530S can handle 100V and
3A for 10ms, and is safe to use in this application.
SUMMARY OF DESIGN FLOW
To summarize the design flow, consider the application
shown in Figure 2, which was designed for 50W:
Calculate maximum load current: 50W/36V = 1.4A; allow-
ing 83% converter efficiency, IIN (MAX) = 1.7A.
Calculate RS: from Equation (3) RS = 20mΩ.
Calculate CT: from Equation (7) CT = 150nF (including
1.5X correction factor).
Calculate TIMER period: from Equation (2) the short-circuit
time-out period is t = 2.6ms.
Calculate maximum short-circuit current: from Equation
(5) maximum short-circuit current could be as high as
120mV/20mΩ = 6A.
Consult MOSFET SOA curves: the IRF530S can handle
6A at 72V for 5ms, so it is safe to use in this application.
APPLICATIONS INFORMATION
15
4251b12f
LTC4251B/LTC4251B-1/
LTC4251B-2
FREQUENCY COMPENSATION
The LTC4251B/LTC4251B-1/LTC4251B-2 typical frequency
compensation network for the analog current limit loop
is a series RC (10Ω) and CC connected to VEE. Figure 5
depicts the relationship between the compensation ca-
pacitor CC and the MOSFET’s CISS. The line in Figure 5
is used to select a starting value for CC based upon the
MOSFET’s CISS specification. Optimized values for CC are
shown for several popular MOSFETs. Differences in the
optimized value of CC versus the starting value are small.
Nevertheless, compensation values should be verified by
board level short-circuit testing.
As seen in Figure 4 previously, at the onset of a short-
circuit event, the input supply voltage can ring dramatically
owing to series inductance. If this voltage avalanches the
MOSFET, current continues to flow through the MOSFET
to the output. The analog current limit loop cannot control
this current flow and therefore the loop undershoots. This
effect cannot be eliminated by frequency compensation. A
zener diode is required to clamp the input supply voltage
and prevent MOSFET avalanche.
sense resistor. PCB layout should be balanced and sym-
metrical to minimize wiring errors. In addition, the PCB
layout for the sense resistor should include good thermal
management techniques for optimal sense resistor power
dissipation.
APPLICATIONS INFORMATION
SENSE RESISTOR CONSIDERATIONS
For proper circuit breaker operation, Kelvin-sense PCB
connections between the sense resistor and the VEE and
SENSE pins are strongly recommended. The drawing in
Figure 6 illustrates the correct way of making connections
between the LTC4251B/LTC4251B-1/LTC4251B-2 and the
TIMING WAVEFORMS
System Power-Up
Figure 7 details the timing waveforms for a typical
power-up sequence in the case where a board is already
installed in the backplane and system power is applied
abruptly. At time point 1, the supply ramps up, together
with UV/OV and VOUT. VIN follows at a slower rate as set
by the VIN bypass capacitor. At time point 2, VIN exceeds
VLKO and the internal logic checks for VUVHI < UV/OV <
VOVLO, TIMER < VTMRL, GATE < VGATEL and SENSE < VCB.
When all conditions are met, an initial timing cycle starts
and the TIMER capacitor is charged by a 5.8μA current
source pull-up. At time point 3, TIMER reaches the VTMRH
threshold and the initial timing cycle terminates. The
TIMER capacitor is then quickly discharged. At time point
4, the VTMRL threshold is reached and the conditions of
GATE < VGATEL and SENSE < VCB must be satisfied before
a start-up cycle is allowed to begin. GATE sources 58μA
into the external MOSFET gate and compensation network.
When the GATE voltage reaches the MOSFET’s threshold,
current begins flowing into the load capacitor. At time
point 5, the SENSE voltage (VSENSE – VEE ) reaches the VCB
threshold and activates the TIMER. The TIMER capacitor
Figure 5. Recommended Compensation
Capacitor CC vs MOSFET CISS
Figure 6. Making PCB Connections to the Sense Resistor
W
CURRENT FLOW
FROM LOAD
CURRENT FLOW
TO –48V BACKPLANE
SENSE RESISTOR
TRACK WIDTH W:
0.03" PER AMP
ON 1 OZ COPPER
TO
SENSE
TO
VEE
4251b12 F06
MOSFET CISS (pF)
COMPENSATION CAPACITOR CC (nF)
4251b12 F05
60
50
40
30
20
10
002000 4000 6000 8000
IRF530
IRF540
IRF740
IRF3710
MTY100N10E
16
4251b12f
LTC4251B/LTC4251B-1/
LTC4251B-2
is charged by a 230μA current-source pull-up. At time
point 6, the analog current limit loop activates. Between
time point 6 and time point 7, the GATE voltage is held
essentially constant and the sense voltage is regulated at
VACL. As the load capacitor nears full charge, its current
begins to decline. At point 7, the load current falls and
the sense voltage drops below VACL. The analog current
limit loop shuts off and the GATE pin ramps further. At
time point 8, the sense voltage drops below VCB and
TIMER now discharges through a 5.8μA current source
pull-down. At time point 9, GATE reaches its maximum
voltage as determined by VIN.
Live Insertion with Short Pin Control of UV/OV
In this example as shown in Figure 8, power is delivered
through long connector pins whereas the UV/OV divider
makes contact through a short pin. This ensures the power
connections are firmly established before the LTC4251B/
LTC4251B-1/LTC4251B-2 are activated. At time point 1,
the power pins make contact and VIN ramps through
VLKO. At time point2, the UV/OV divider makes contact
and its voltage exceeds VUVHI. In addition, the internal
logic checks for VUVHI < UV/OV < VOVHI, TIMER < VTMRL,
GATE < VGATEL and SENSE < VCB. When all conditions are
met, an initial timing cycle starts and the TIMER capaci-
tor is charged by a 5.8μA current source pull-up. At time
point 3, TIMER reaches the VTMRH threshold and the ini-
tial timing cycle terminates. The TIMER capacitor is then
quickly discharged. At time point 4, the VTMRL threshold
is reached and the conditions of GATE < VGATEL and
SENSE < VCB must be satisfied before a start-up cycle is
allowed to begin. GATE sources 58μA into the external
MOSFET gate and compensation network. When the
GATE voltage reaches the MOSFET’s threshold, current
begins flowing into the load capacitor. At time point 5, the
SENSE voltage (VSENSE – VEE ) reaches the VCB threshold
and activates the TIMER. The TIMER capacitor is charged
by a 230μA current source pull-up. At time point 6, the
analog current limit loop activates. Between time point
6 and time point 7, the GATE voltage is held essentially
constant and the sense voltage is regulated at VACL. As
the load capacitor nears full charge, its current begins to
APPLICATIONS INFORMATION
decline. At time point 7, the load current falls and the sense
voltage drops below VACL. The analog current limit loop
shuts off and the GATE pin ramps further. At time point
8, the sense voltage drops below VCB and TIMER now
discharges through a 5.8μA current source pull-down.
At time point 9, GATE reaches its maximum voltage as
determined by VIN.
Undervoltage Lockout Timing
In Figure 9, when UV/OV drops below VUVLO (time point 1),
TIMER and GATE pull low. If current has been flowing, the
SENSE pin voltage decreases to zero as GATE collapses.
When UV/OV recovers and clears VUVHI (time point 2),
an initial time cycle begins followed by a start-up cycle.
Undervoltage Timing with Overvoltage Glitch
In Figure 10, when UV/OV clears VUVHI (time point 1),
an initial timing cycle starts. If the system bus voltage
overshoots VOVHI as shown at time point 2, TIMER dis-
charges. At time point 3, the supply voltage recovers and
drops below the VOVLO threshold. The initial timing cycle
restarts followed by a start-up cycle.
Overvoltage Timing
During normal operation, if UV/OV exceeds VOVHI as
shown at time point 1 of Figure 11, the TIMER status is
unaffected. Nevertheless, GATE pulls down and discon-
nects the load. At time point 2, UV/OV recovers and drops
below the VOVLO threshold. A gate ramp up cycle ensues.
If the overvoltage glitch is long enough to deplete the
load capacitor, a full start-up cycle may occur as shown
between time points 3 through 6.
Timer Behavior
In Figure 12a, the TIMER capacitor charges at 230μA if
the SENSE pin exceeds VCB. It is discharged with 5.8μA
if the SENSE pin is less than VCB. In Figure 12b, when
TIMER exceeds VTMRH, TIMER is latched high by the 5.8μA
pull-up and GATE pulls down immediately. In Figure 12c,
multiple momentary faults cause the TIMER capacitor to
integrate until it latches.
17
4251b12f
LTC4251B/LTC4251B-1/
LTC4251B-2
APPLICATIONS INFORMATION
Figure 7. System Power-Up Timing (All Waveforms are Referenced to VEE)
Figure 8. Power-Up Timing with a Short-Pin (All Waveforms are Referenced to VEE)
132456789
VIN CLEARS VLKO, CHECK VUVHI <UV/0V < VOVLO, TIMER< VTMRL, GATE < VGATEL AND SENSE < VCB.
TIMER CLEARS VTMRL, CHECK GATE < VGATEL AND SENSE < VCB.
GND-VEE
UV/0V
VIN
TIMER
GATE
SENSE
VOUT
VLKO
VTMRH
VTMRL
VACL
VCB
5.8μA 5.8μA
5.8μA
INITIAL TIMING CYCLE START-UP CYCLE
4251b12 F07
230μA
58μA
58μA
132456789
UV/0V CLEARS VUVHI, CHECK VIN < VLKO – VLKH, TIMER < VTMRL, GATE < VGATEL AND SENSE < VCB.
TIMER CLEARS VTMRL, CHECK GATE < VGATEL AND SENSE < VCB.
GND-VEE
UV/0V
VIN
TIMER
GATE
SENSE
VOUT
VUVHI
VLKO
VTMRH
VTMRL
VACL
VCB
5.8μA 5.8μA
5.8μA
INITIAL TIMING CYCLE START-UP CYCLE
4251b12 F08
230μA
58μA
58μA
18
4251b12f
LTC4251B/LTC4251B-1/
LTC4251B-2
APPLICATIONS INFORMATION
Analog Current Limit and Fast Current Limit
In Figure 13a, when SENSE exceeds VACL, GATE is regulated
by the analog current limit amplifier loop. When SENSE
drops below VACL, GATE is allowed to pull up. In Figure
13b, when a severe fault occurs, SENSE exceeds VFCL
and GATE immediately pulls down until the analog current
amplifier can establish control. If TIMER reaches VTMRH,
GATE pulls low and latches off.
Resetting a Fault Latch
As shown in Figure 14, a latched fault is reset by either
pulling UV/OV below VUVLO or pulling TIMER below VTMRL.
An initial timing cycle is initiated if UV/OV is used for reset.
If TIMER is used for reset, the initial timing cycle is skipped.
Internal Soft-Start
An internal soft-start feature ramps the positive input of
the analog current limit amplifier during initial start-up.
The ramp duration is approximately 200μs. This feature
reduces load current dl/dt at start-up. As illustrated in
Figure15, soft-start is initiated by a TIMER transition from
VTMRH to VTMRL or when UV/OV falls below the VOVLO
threshold after an OV fault. After soft-start duration, load
current is limited by VACL/RS.
Figure 9. Undervoltage Lockout Timing (All Waveforms are Referenced to VEE)
132456789
VUV/0V CLEARS VUVHI, CHECK TIMER < VTMRL, GATE < VGATEL AND SENSE < VCB.
VUV/0V DROPS BELOW VUVLO. TIMER, GATE, AND SENSE ARE PULLED TO VEE.
TIMER CLEARS VTMRL, CHECK GATE < VGATEL AND SENSE < VCB.
VUVHI
VUVLO
VTMRH
VTMRL
VACL
VCB
5.8μA 230μA
58μA
58μA
5.8μA 5.8μA
INITIAL TIMING CYCLE START-UP CYCLE
4251b12 F09
UV/0V
TIMER
GATE
SENSE
19
4251b12f
LTC4251B/LTC4251B-1/
LTC4251B-2
APPLICATIONS INFORMATION
Figure 10. Undervoltage Timing with an Overvoltage Glitch (All Waveforms are Referenced to VEE)
Figure 11. Overvoltage Timing (All Waveforms are Referenced to VEE)
132456789
VUV/0V DROPS BELOW VOVLO AND TIMER RESTARTS INITIAL TIMING CYCLE.
VUV/0V CLEARS VUVHI. CHECK TIMER < VTMRL, GATE < VGATEL AND SENSE < VCB.
VUV/0V OVERSHOOTS VOVHI AND TIMER ABORTS INITIAL TIMING CYCLE.
TIMER CLEARS VTMRL, CHECK GATE < VGATEL AND SENSE < VCB.
VOVHI
VUVHI
VOVLO
VTMRH
VTMRL
VACL
VCB
5.8μA 230μA
58μA
58μA
5.8μA 5.8μA
INITIAL TIMING CYCLE START-UP CYCLE
4251b12 F10
UV/0V
TIMER
GATE
SENSE
10
1324567
UV/0V
TIMER
GATE
SENSE
VOVHI
VTMRH
VOVLO
VACL
VCB
5.8μA 5.8μA 5.8μA
5.8μA
4251b12 F11
230μA
58μA
58μA
VUV/0V DROPS BELOW VOVLO AND GATE RESTARTS.
VUV/0V OVERSHOOTS VOVHI AND GATE PULLS TO VEE. TIMER UNAFFECTED.
20
4251b12f
LTC4251B/LTC4251B-1/
LTC4251B-2
APPLICATIONS INFORMATION
(12a) Momentary Circuit-Breaker Fault (12b) Circuit-Breaker Time-Out
Figure 12. Timer Behavior (All Waveforms are Referenced to VEE)
(12c) Multiple Circuit-Breaker Faults
TIMER
GATE
SENSE
VOUT
VACL
VTMRL
VCB
5.8μA
5.8μA
CB FAULT
230μA
12
4251b12 F12a
TIMER
GATE
SENSE
VOUT
VACL
VTMRH
VCB
5.8μA
CB FAULT
230μA
12
TIMER LATCHES OFF
4251b12 F12b
TIMER
GATE
SENSE
VOUT
VACL
VTMRH
VCB
5.8μA
5.8μA 230μA
230μA
1432
TIMER LATCHES OFF
4251b12 F12c
21
4251b12f
LTC4251B/LTC4251B-1/
LTC4251B-2
Figure 13. Current Limit Behavior (All Waveforms are Referenced to VEE)
(13a) Analog Current Limit Fault (13b) Fast Current Limit Fault
Figure 14. Latched Fault Reset Timing (All Waveforms are Referenced to VEE)
APPLICATIONS INFORMATION
TIMER
GATE
SENSE
VOUT
VACL
VTMRH
VCB
58μA
5.8μA
5.8μA
1432
230μA
4251b12 F13a
TIMER
GATE
SENSE
VOUT
VFCL
VACL
VTMRH
VCB
5.8μA
230μA
12
TIMER LATCHES OFF
4251b12 F13b
TIMER
GATE
SENSE
VACL
VTMRH
VTMRL
VCB
5.8μA
5.8μA
5.8μA
156432
230μA
58μA
58μA
RESET LATCHED TIMER FAULT BY EXTERNAL LOW PULSE.
4251b12 F14
22
4251b12f
LTC4251B/LTC4251B-1/
LTC4251B-2
Figure 15. Internal Soft-Start Timing (All Waveforms are Referenced to VEE)
APPLICATIONS INFORMATION
TIMER
GATE
SENSE
VACL
VACL + 10mV
VTMRH
VTMRL
~VGS(th)
VCB
5.8μA
145 632
230μA
INTERNAL
SOFT-START
REFERENCE
58μA
10mV
END OF INITIAL TIMING CYCLE
4251b12 F15
23
4251b12f
LTC4251B/LTC4251B-1/
LTC4251B-2
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
S6 Package
6-Lead Plastic TSOT-23
(Reference LTC DWG # 05-08-1636)
1.50 – 1.75
(NOTE 4)
2.80 BSC
0.30 – 0.45
6 PLCS (NOTE 3)
DATUM ‘A’
0.09 – 0.20
(NOTE 3) S6 TSOT-23 0302 REV B
2.90 BSC
(NOTE 4)
0.95 BSC
1.90 BSC
0.80 – 0.90
1.00 MAX 0.01 – 0.10
0.20 BSC
0.30 – 0.50 REF
PIN ONE ID
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. JEDEC PACKAGE REFERENCE IS MO-193
3.85 MAX
0.62
MAX
0.95
REF
RECOMMENDED SOLDER PAD LAYOUT
PER IPC CALCULATOR
1.4 MIN
2.62 REF
1.22 REF
24
4251b12f
LTC4251B/LTC4251B-1/
LTC4251B-2
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2012
LT 0112 • PRINTED IN USA
+
LTC4251B
UV/OV
TIMER
GATE
SENSE
VIN
VEE
1
2
3
4
56
LOAD
–48RTN
–48RTN
(SHORT PIN)
R1
402k
1%
RC
10Ω RS
0.01Ω
R3
22Ω
R2
32.4k
1%
–48V
CT
82nF
C1
10nF
CC
22nF
CIN
1μF
CL
100μF
RIN
10k
500mW
Q1
IRF540
4251b12 TA02
PUSH-
RESET S1
4
3
2
1
**DIODES, INC.
†RECOMMENDED FOR HARSH ENVIRONMENTS
DIN†
DDZ13B**
+
LTC4251B-1
UV/OV
TIMER
GATE
SENSE
VIN
VEE
1
2
3
4
56
LOAD
–48RTN
–48RTN
(SHORT PIN)
R1
442k
1%
RC
10Ω RS
0.02Ω
R2
34.8k
1%
–48V
CT
220nF
C1
10nF
CC
22nF
CIN
1μF
D1
BZX84C36
CL
100μF
RIN
10k
500mW
R3
31.6k
R4
22Ω
VOUT
Q1
IRF540S
4251b12 TA03
4
3
2
1
**DIODES, INC.
†RECOMMENDED FOR HARSH ENVIRONMENTS
DIN†
DDZ13B**
RELATED PARTS
TYPICAL APPLICATIONS
PART NUMBER DESCRIPTION COMMENTS
LT1640AH/LT1640AL Negative High Voltage Hot Swap Controllers in SO-8 Negative High Voltage Supplies from –10V to –80V
LT1641-1/LT1641-2 Positive High Voltage Hot Swap Controllers in SO-8 Supplies from 9V to 80V, Latched Off/Autoretry
LTC1642 Fault Protected Hot Swap Controller 3V to 16.5V, Overvoltage Protection up to 33V
LTC1921 Dual –48V Supply and Fuse Monitor ±1V UV and ±1.5V OV Threshold Accuracy, ± 200V Transient
Protection, Drives Three Optoisolators for Status
LT4250 –48V Hot Swap Controller in SO-8 Active Current Limiting, Supplies from –20V to –80V
LTC4252B-1/
LTC4252B-2
Negative Voltage Hot Swap Controller in MSOP Fast Active Current Limiting with Drain Accelerated Response,
Supplies from –15V
LTC4253B Negative Voltage Hot Swap Controller with
3-Output Sequencer
Fast Active Current Limiting with Drain Accelerated Response,
Supplies from –15V
Figure 16. –48V/5A Application with Reverse SENSE Pin Limiting and Push-Reset at TIMER Pin
Figure 17. Power-Limited Circuit Breaker Application