©2002 Fairchild Semiconductor Corporation RFG75N05E Rev. B
RFG75N05E
75A, 50V, 0.008 Ohm, N-Channel Power
MOSFET
These are N-Channel enhancement mode silicon gate
power field effect transistors. They are advanced power
MOSFETs designed, tested, and guaranteed to withstand a
specified level of energy in the breakdown avalanche mode
of operation. All of these power MOSFETs are designed for
applications such as switching regulators, switching
convertors, motor drivers, relay drivers, and drivers for high
power bipolar switching transistors requiring high speed and
low gate drive power. These types can be operated directly
from integrated circuits.
Formerly developmental type TA09821.
Features
• 75A, 50V
•r
DS(ON)
= 0.008
Ω
• Electrostatic Discharge Rated
• UIS Rating Curve (Single Pulse)
• 175
o
C Operating Temperature
• Temperature Compensated PSPICE
®
Model Provided
Symbol
Packaging
JEDEC STYLE TO-247
Ordering Information
PART NUMBER PACKAGE BRAND
RFG75N05E TO-247 RFG75N05E
NOTE: When ordering, include the entire part number.
G
D
S
DRAIN
(BOTTOM
SIDE METAL)
SOURCE
DRAIN
GATE
January 2002Data Sheet
©2002 Fairchild Semiconductor Corporation RFG75N05E Rev. B
Absolute Maximum Ratings
T
C
= 25
o
C, Unless Otherwise Specified
RFG75N05E UNITS
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V
DSS
50 V
Drain to Gate Voltage (R
GS
= 20k
Ω)
(Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DGR
50 V
Continuous Drain Current (Current Limited by Package). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
D
75 A
Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
DM
200 A
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V
GS
±
20 V
Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .P
D
240 W
Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6 W/
o
C
Electrostatic Discharge Rating, MIL-STD-883, Category B(2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E
SD
2kV
Single Pulse Avalanche Rating (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Refer to UIS SOA
Curves
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
J
, T
STG
-55 to 175
o
C
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
L
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
pkg
300
260
o
C
o
C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. T
J
= 25
o
C to 125
o
C.
Electrical Specifications
T
C
= 25
o
C, Unless Otherwise Specified
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Drain to Source Breakdown Voltage BV
DSS
V
GS
= 0V, I
D
= 250
µ
A (Figure 9) 50 - - V
Gate Threshold Voltage V
GS(TH)
V
GS
= V
DS
, I
D
= 250
µ
A (Figure 8) 2.0 - 4.0 V
Zero Gate Voltage Drain Current I
DSS
V
DS
= Rated BV
DSS
, V
GS
= 0V - - 1
µ
A
V
DS
= 0.8 x Rated BV
DSS
, V
GS
= 0V, T
C
= 150
o
C- -25
µ
A
Gate to Source Leakage I
GSS
V
GS
=
±
20V - -
±
100 nA
Drain to Source on Resistance (Note 2) r
DS(ON)
V
GS
= 10V, I
D
= 75A (Figure 7) - - 0.008
Ω
Turn On Time t
(ON)
V
DD
= 25V, I
D
≈
37.5A,
R
L
= 0.67
Ω
, R
G
= 1.67
Ω,
V
GS
= 10V,
(Figure 11)
- - 125 ns
Turn On Delay Time t
d(ON)
-17- ns
Rise Time t
r
-75- ns
Turn Off Delay Time t
d(OFF)
-70- ns
Fall Time t
f
-17- ns
Turn Off Time t
(OFF)
- - 125 ns
Total Gate Charge
(Gate to Source + Gate to Drain)
Q
g(TOT)
V
GS
= 0, 20V V
DD
= 40V, I
D
= 75A,
R
L
= 0.53
Ω
I
G(REF)
= 3.44mA
(Figure 11)
- - 400 nC
Gate Charge at 10V Q
g(10)
V
GS
= 0, 10V - - 220 nC
Threshold Gate Charge Q
g(TH)
V
GS
= 0, 2V - - 15 nC
Junction to Case R
θ
JC
- - 0.625
o
C/W
Junction to Ambient R
θ
JA
--80
o
C/W
Source to Drain Diode Specifications
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Source to Drain Diode Voltage V
SD
I
SD
= 75A - - 1.5 V
Diode Reverse Recovery Time t
rr
I
SD
= 75A, dI
SD
/dt = 100A/
µ
s - - 125 ns
NOTES:
2. Pulse test: pulse width
≤
300
µ
s, duty cycle
≤
2%.
3. Repetitive pulse: pulse width is limited by maximum junction temperature.
4. Refer to Fairchild Application Notes AN9321 and AN9322. See Figure 4.
RFG75N05E
©2002 Fairchild Semiconductor Corporation RFG75N05E Rev. B
Typical Performance Curves
Unless Otherwise Specified
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
FIGURE 3. FORWARD BIAS SAFE OPERATING AREA FIGURE 4. UNCLAMPED INDUCTIVE SWITCHING SOA
(SINGLE PULSE UIS SOA)
FIGURE 5. SATURATION CHARACTERISTICS FIGURE 6. TRANSFER CHARACTERISTICS
TC, CASE TEMPERATURE (oC)
POWER DISSIPATION MULTIPLIER
0
0 25 50 75 100 175
0.2
0.4
0.6
0.8
1.0
1.2
125 150
25 50 75 100 125 150
TC, CASE TEMPERATURE (oC)
ID, DRAIN CURRENT (A)
80
70
60
50
40
30
20
10
0175
VDS, DRAIN TO SOURCE VOLTAGE (V)
10
1
100
1
ID, DRAIN CURRENT (A)
102
10
OPERATION IN THIS AREA
MAY BE LIMITED BY rDS(ON)
DC
ID MAX CONTINUOUS
TC = 25oC
TJ = MAX RATED
SINGLE PULSE
100
1000
10
IAS, AVALANCHE CURRENT (A)
tAV, TIME IN AVALANCHE (ms)
1100.01 0.10
tAV = (L)(IAS)/(1.3 RATED BVDSS - VDD)
If R = 0
If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3 RATED BVDSS - VDD) +1]
STARTING TJ = 25oC
STARTING TJ = 150oC
Idm
VDS, DRAIN TO SOURCE VOLTAGE (V)
1.5 3.0 4.5 6.00 7.5
200
160
120
0
80
ID, DRAIN CURRENT (A)
TC = 25oC
40
VGS = 10V
VGS = 5.0V
VGS = 6.0V
VGS = 4.0V
VGS = 7.0V
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
046102
0
80
120
200
IDS(ON), DRAIN TO SOURCE CURRENT (A)
VGS, GATE TO SOURCE VOLTAGE (V)
160
40
-55oC
8
175oC
VDD > ID x rDS(ON)
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX 25oC
RFG75N05E
©2002 Fairchild Semiconductor Corporation RFG75N05E Rev. B
FIGURE 7. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
FIGURE 8. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
FIGURE 9. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 10. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.
FIGURE 11. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT
Typical Performance Curves Unless Otherwise Specified (Continued)
3.0
2.0
1.0
-50
TJ, JUNCTION TEMPERATURE (oC)
NORMALIZED DRAIN TO SOURCE
2.5
1.5
0100
ON RESISTANCE
0 50 150 200
ID = 75A, VGS = 10V
0.5
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
2.0
1.2
0.4
-50
TJ, JUNCTION TEMPERATURE (oC)
NORMALIZED GATE
1.6
0.8
00 200
THRESHOLD VOLTAGE
50 100 150
ID = 250µA
VGS = VDS
2.0
1.0
0.5
50-50
TJ, JUNCTION TEMPERATURE (oC)
NORMALIZED DRAIN TO SOURCE
1.5
0100 200
BREAKDOWN VOLTAGE
0 150
ID = 250µA
0 10152025
C, CAPACITANCE (pF)
VDS, DRAIN TO SOURCE VOLTAGE (V)
6000
4000
2000
05
CRSS
CISS
COSS
VGS = 0V, f = 1MHz
CISS = CGS + CGD
CRSS = CGD
COSS ≈ CDS + CGD
GATE SOURCE
VOLTAGE
50
40
30
10
0
20
IG REF()
IG ACT()
-------------------------t, TIME (µs) 80
IG REF()
IG ACT()
-------------------------
10
8
6
2
0
VDS, DRAIN TO SOURCE VOLTAGE (V)
VGS , GATE TO SOURCE VOLTAGE (V)
VDD = 0.75 BVDSS
VDD = 0.50 BVDSS
VDD = 0.25 BVDSS
20
VDD = BVDSS VDD = BVDSS
4
DRAIN SOURCE VOLTAGE
RL = 0.667Ω
IG(REF) = 3.44mA
VGS = 10V
RFG75N05E
©2002 Fairchild Semiconductor Corporation RFG75N05E Rev. B
Test Circuits and Waveforms
FIGURE 12. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 13. UNCLAMPED ENERGY WAVEFORMS
FIGURE 14. SWITCHING TIME TEST CIRCUIT FIGURE 15. RESISTIVE SWITCHING WAVEFORMS
FIGURE 16. GATE CHARGE TEST CIRCUIT FIGURE 17. GATE CHARGE WAVEFORM
tP
VGS
0.01Ω
L
IAS
+
-
VDS
VDD
RG
DUT
VARY tP TO OBTAIN
REQUIRED PEAK IAS
0V
VDD
VDS
BVDSS
tP
IAS
tAV
0
VGS
RL
RGS
DUT
+
-
VDD
VDS
VGS
tON
td(ON)
tr
90%
10%
VDS 90%
10%
tf
td(OFF)
tOFF
90%
50%
50%
10% PULSE WIDTH
VGS
0
0
RL
VGS +
-
VDS
VDD
DUT
Ig(REF)
VDD
Qg(TH)
VGS = 2V
Qg(10)
VGS = 10V
Qg(TOT)
VGS = 20V
VDS
VGS
Ig(REF)
0
0
RFG75N05E
©2002 Fairchild Semiconductor Corporation RFG75N05E Rev. B
PSpice Electrical Model
.SUBCKT RFG75N05 2 1 3 ; rev 10/30/90
*Nominal Temperature = 25oC
CA 12 8 8.98e-9
CB 15 14 8.81e-9
Cin 6 8 4.48e-9
DPLCAP 10 5 DPLCAPMOD
Dbody 7 5 DBODYMOD
Dbreak 5 11 DBREAKMOD
Eds 14 8 5 8 1
Egs 13 8 6 8 1
Esg 6 10 6 8 1
Ebreak 11 7 17 18 58.4
EVTEMP 20 6 18 8 1
IT 8 17 1
Ldrain 2 5 e-10
Lgate 1 9 5e-9
Lsource 3 7 3e-9
Mos 16 6 8 8 MODMOD
Rbreak 17 18 RBREAKMOD 1
Rdrain 5 16 RSOURCEMOD 3.07e-3
Rgate 9 20 1.2
Rin 6 8 1e9
Rsource 8 7 RSOURCEMOD 2.e-3
RVTEMP 18 19 RVTONEGMOD 1
S1a 6 12 13 8 S1AMOD
S1b 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2b 13 15 14 13 S2AMOD
Vbat 8 19 DC 1
.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2.48 VOFF=-0.48)
.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=0.48 VOFF=-2.48)
.MODEL S2AMOD VSWITCH (RON=1e=5 ROFF=0.1 VON=-2.25 VOFF=2.75)
.MODEL S2ABMOD VSWITCH (RON=1e-5 ROFF=0.1 VON =2.75 VOFF=-2.25)
.MODEL DBODYMOD D (IS=2.23e-12 RS=249e-3 TRS1=2.5e-3 CJO=7.55e-9 TT=4e-8)
.MODEL DBREAKMOD D (RS=8e-2 TRS1=2.5e-3)
.MODEL DPLCAPMOD D (IS=1e-30 N=10 CJO=2.14e-9)
.MODEL RBREAKMOD RES (TC1=9.5e-4 TC2=-1.17e-6)
.MODEL RSOURCEMOD RES (TC1=5.2e-3 TC2=1.37e-5)
.MODEL RVTONEGMOD RES (TC1=-3.78e-3 TC2=-7.51e-7)
.MODEL MODMOD NMOS (VTO=3.48 N=10 IS=1e-30 KP=78.5 TOX=1 L=1u W1u)
.ENDS
1
GATE RGATE EVTO
18
22
9
+
12 13
8
14
13
13
15
S1A
S1B
S2A
S2B
CA CB
EGS EDS
CIN
DBREAK
EBREAK
DBODY
DRAIN
RSOURCE
SOURCE
RBREAK
RVTEMP
VBAT
IT
ESG
DPLCAP
6
6
8
10 5
16
11
17
18
8
14
5
8
6
8
7
3
17 18
19
2
+
+
+
+
+
MOS
LSOURCE
LDRAIN
LGATE
20
8
RDRAIN
RIN
RFG75N05E
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER
NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification Product Status Definition
Advance Information
Preliminary
No Identification Needed
Obsolete
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Formative or
In Design
First Production
Full Production
Not In Production
OPTOLOGIC™
OPTOPLANAR™
PACMAN™
POP™
Power247™
PowerTrench
QFET™
QS™
QT Optoelectronics™
Quiet Series™
SILENT SWITCHER
FAST
FASTr™
FRFET™
GlobalOptoisolator™
GTO™
HiSeC™
ISOPLANAR™
LittleFET™
MicroFET™
MicroPak™
MICROWIRE™
Rev. H4
ACEx™
Bottomless™
CoolFET™
CROSSVOLT™
DenseTrench™
DOME™
EcoSPARK™
E2CMOSTM
EnSignaTM
FACT™
FACT Quiet Series™
SMART START™
STAR*POWER™
Stealth™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
SyncFET™
TinyLogic™
TruTranslation™
UHC™
UltraFET
STAR*POWER is used under license
VCX™