2017 Microchip Technology Inc. DS20005851A-page 1
HV5530
Features
• 100 mA Minimum Sink Current
• 8 MHz Shift Register Speed
• Polarity and Blanking Inputs
• CMOS-compatible Inputs
• Forward and Reverse Shifting Options
• Diode to VPP allows Efficient Power Recovery
Applications
• Display Driver
• Inkjet Driver
• Print Head Driver
• Microelectromechanical Systems Applications
General Description
The HV5530 is a low-voltage to high-voltage
serial-to-parallel converter with open drain outputs.
This device is designed as a driver for
AC-electroluminescent displays. It can also be used in
any application requiring multiple-output high-voltage
current-sinking capabilities such as driving inkjet and
electrostatic print heads, plasma panels, vacuum
fluorescent and large matrix LCD displays.
The device consists of a 32-bit Shift register, 32 latches
and control logic to perform the polarity select and
blanking of the outputs. Data is shifted through the Shift
register on the high-to-low transition of the clock. The
HV5530 shifts in a counter-clockwise direction when
viewed from the top of the package. A data output
buffer is provided for cascading devices. This output
reflects the current status of the last bit of the Shift
register. The operation of the Shift register is not
affected by the latch enable (LE), blanking (BL) and
polarity (POL) inputs. Transfer of data from the Shift
register to the latch occurs when the LE input is high.
The data in the latch is stored when LE is low.
Package Types
See Table 2-1 and Table 2-2 for pin information.
44-lead PQFP
(Top view)
44-lead PLCC
(Top view)
1 44
6 40
1
44
32-Channel Serial-to-Parallel Converter With Open Drain Outputs
POL
BL
LE
DATA
IN
CLK
DATA
OUT
HVOUT1
(Outputs 3 to 30 not shown)
Latch
Latch
HVOUT2
HVOUT31
HVOUT32
Latch
Latch
32-Bit
Shift
Register
HV5530
DS20005851A-page 2 2017 Microchip Technology Inc.
Functional Block Diagram
2017 Microchip Technology Inc. DS20005851A-page 3
HV5530
Typical Application Circuit
Microcontroller
32-bit Shift Register
32 Latches and
output control
Level Translators and
Open Drain Output
32
-
bit Shi
f
t Re
g
iste
r
32
Latc
h
es and
o
ut
p
ut contro
l
Le
v
e
l Tr
a
n
s
l
a
t
o
r
s
a
n
d
O
p
en Drain Out
p
ut
To Data Input for cascading
Print Head
VDD
POL
BL
LE
Data
In
CLK
HVOUT1
HVOUT32
Data
Out
High Voltage
Amplifier Driver
HV5530
DS20005851A-page 4 2017 Microchip Technology Inc.
1.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings†
Supply Voltage, VDD (Note 1) .................................................................................................................. –0.5V to +15V
High-voltage Output Voltage, HVOUT (Note 1) ...................................................................................... –0.5V to +315V
Logic Input Levels (Note 1) .............................................................................................................. –0.5V to VDD+0.5V
Ground Current (Note 2) ......................................................................................................................................... 1.5A
Maximum Junction Temperature, TJ(MAX) ........................................................................................................... +125°C
Storage Temperature, TS .................................................................................................................... –65°C to +150°C
Continuous Total Power Dissipation:
44-lead PQFP (Note 3) ......................................................................................................................... 1200 mW
44-lead PLCC (Note 3) ......................................................................................................................... 1200 mW
† Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only, and functional operation of the device at those or any other conditions above those
indicated in the operational sections of this specification is not intended. Exposure to maximum rating conditions for
extended periods may affect device reliability.
Note 1: All voltages are referenced to VSS.
2: Duty cycle is limited by the total power dissipated in the package.
3: For operations above 25°C ambient, derate linearly to the maximum operating temperature at 20 mW/°C.
RECOMMENDED OPERATING CONDITIONS
Parameter Sym. Min. Typ. Max. Unit Conditions
Logic Supply Voltage VDD 10.8 —13.2 V
High-voltage Output Voltage HVOUT –0.3 —+300 V
High-level Input Voltage VIH VDD–2 —VDD V
Low-level Input Voltage VIL 0—2V
Clock Frequency fCLK ——8MHz
Operating Ambient Temperature TA–40 —+85 °C
DC ELECTRICAL CHARACTERISTICS
Electrical Specifications: Over recommended operating conditions unless otherwise stated
Parameter Sym. Min. Typ. Max. Unit Conditions
VDD Supply Current IDD — — 15 mA fCLK = 8 MHz,
fDATA = 4 MHz
Quiescent VDD Supply Current IDDQ — — 100 µA All VIN = 0
Off State Output Current IO(OFF) — — 10 µA All outputs high, all SWS
parallel
High-level Logic Input Current IIH — — 1µA VIH = VDD
Low-level Logic Input Current IIL — — –1 µA VIL = 0V
High-level Output Data Out VOH VDD–1V —— V IDOUT = –100 µA
Low-level Output Voltage HVOUT VOL
— — 15 V IHVOUT = 100 mA
Data Out — — 1VIDOUT = 100 µA
HVOUT Clamp Voltage VOC — — –1.5 V IOL = –100 mA
AC ELECTRICAL CHARACTERISTICS
Electrical Specifications: For VDD = 12V and TA = 25°C.
Parameter Sym. Min. Typ. Max. Unit Conditions
Clock Frequency fCLK — — 8 MHz
Clock Width High or Low tWL, tWH 62 — — ns
Data Set-up Time before Clock Falls tSU 25 — — ns
Data Hold Time after Clock Falls tH10 — — ns
Turn-on Time, HVOUT from Enable tON ——500 ns RL = 2 kΩ
to VPP maximum
Latch Enable Pulse Width tWLE 50 — — ns
Delay Time Clock to Latch Enable Low to
HightDLE 50 — — ns
Latch Enable Set-up Time before Clock
Falls tSLE 50 — — ns
Delay Time Clock to Data Low to High tDLH — — 100 ns CL = 15 pF
Delay Time Clock to Data High to Low tDHL — — 100 ns CL = 15 pF
TEMPERATURE SPECIFICATIONS
Parameter Sym. Min. Typ. Max. Unit Conditions
TEMPERATURE RANGE
Operating Ambient Temperature TA–40 —+85 °C
Maximum Junction Temperature TJ(MAX) — — +125 °C
Storage Temperature TS–65 —+150 °C
PACKAGE THERMAL RESISTANCE
44-lead PQFP JA —51 —°C/W
44-lead PLCC JA —37 —°C/W
2017 Microchip Technology Inc. DS20005851A-page 5
HV5530
HV5530
DS20005851A-page 6 2017 Microchip Technology Inc.
Timing Waveforms
LE
HV
OUT
w/ S/R HIGH
Data Valid 50% 50%
DATA
IN
CLK
DATA
OUT
50% 50% 50%
t
SU
t
H
t
WH
t
WL
50%
50%
t
DLH
t
DHL
50%
t
WLE
t
DLE
t
SLE
50% 50%
10%
t
ON
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
V
OH
V
OL
V
IH
V
IL
V
OH
V
OL
2017 Microchip Technology Inc. DS20005851A-page 7
HV5530
2.0 PIN DESCRIPTION
The details on the pins of HV5530 44-lead PQFP and
44-lead PLCC are in Table 2-1 and Table 2-2,
respectively. Refer to Package Types for the location
of pins.
TABLE 2-1: 44-LEAD PQFP PIN FUNCTION TABLE
Pin Number Pin Name Description
1HVOUT11 High-voltage output
2HVOUT12 High-voltage output
3HVOUT13 High-voltage output
4HVOUT14 High-voltage output
5HVOUT15 High-voltage output
6HVOUT16 High-voltage output
7HVOUT17 High-voltage output
8HVOUT18 High-voltage output
9HVOUT19 High-voltage output
10 HVOUT20 High-voltage output
11 HVOUT21 High-voltage output
12 HVOUT22 High-voltage output
13 HVOUT23 High-voltage output
14 HVOUT24 High-voltage output
15 HVOUT25 High-voltage output
16 HVOUT26 High-voltage output
17 HVOUT27 High-voltage output
18 HVOUT28 High-voltage output
19 HVOUT29 High-voltage output
20 HVOUT30 High-voltage output
21 HVOUT31 High-voltage output
22 HVOUT32 High-voltage output
23 DATA OUTPUT Data output pin
24 NC No connection
25 NC No connection
26 NC No connection
27 POL Inverts the polarity of the HVOUT pins
28 CLK Clock pin. Shift registers shift data on the falling edge of the input clock.
29 VSS Reference voltage (usually ground)
30 VDD Logic supply voltage
31 LE Latch enable pin. Data is shifted from the Shift register to the latches on logic
input high.
32 DATA INPUT Data input pin
33 BL This blanking pin sets all HVOUT pins low or high depending upon the state of
polarity. See Ta b l e 3-2.
34 NC No connection
HV5530
DS20005851A-page 8 2017 Microchip Technology Inc.
35 HVOUT1 High-voltage output
36 HVOUT2 High-voltage output
37 HVOUT3 High-voltage output
38 HVOUT4 High-voltage output
39 HVOUT5 High-voltage output
40 HVOUT6 High-voltage output
41 HVOUT7 High-voltage output
42 HVOUT8 High-voltage output
43 HVOUT9 High-voltage output
44 HVOUT10 High-voltage output
TABLE 2-1: 44-LEAD PQFP PIN FUNCTION TABLE (CONTINUED)
Pin Number Pin Name Description
TABLE 2-2: 44-LEAD PLCC PIN FUNCTION TABLE
Pin Number Pin Name Description
1HVOUT16 High-voltage output
2HVOUT17 High-voltage output
3HVOUT18 High-voltage output
4HVOUT19 High-voltage output
5HVOUT20 High-voltage output
6HVOUT21 High-voltage output
7HVOUT22 High-voltage output
8HVOUT23 High-voltage output
9HVOUT24 High-voltage output
10 HVOUT25 High-voltage output
11 HVOUT26 High-voltage output
12 HVOUT27 High-voltage output
13 HVOUT28 High-voltage output
14 HVOUT29 High-voltage output
15 HVOUT30 High-voltage output
16 HVOUT31 High-voltage output
17 HVOUT32 High-voltage output
18 DATA OUTPUT Data output pin
19 NC No connection
20 NC No connection
21 NC No connection
22 POL Inverts the polarity of the HVOUT pins
23 CLK Clock pin. Shift registers shift data on the falling edge of the input clock.
24 VSS Reference voltage (usually ground)
25 VDD Logic supply voltage
26 LE Latch enable pin. Data is shifted from the Shift register to the latches on logic
input high.
2017 Microchip Technology Inc. DS20005851A-page 9
HV5530
27 DATA INPUT Data input pin
28 BL This blanking pin sets all HVOUT pins low or high depending upon the state of
polarity. See Table 3-2.
29 NC No connection
30 HVOUT1 High-voltage output
31 HVOUT2 High-voltage output
32 HVOUT3 High-voltage output
33 HVOUT4 High-voltage output
34 HVOUT5 High-voltage output
35 HVOUT6 High-voltage output
36 HVOUT7 High-voltage output
37 HVOUT8 High-voltage output
38 HVOUT9 High-voltage output
39 HVOUT10 High-voltage output
40 HVOUT11 High-voltage output
41 HVOUT12 High-voltage output
42 HVOUT13 High-voltage output
43 HVOUT14 High-voltage output
44 HVOUT15 High-voltage output
TABLE 2-2: 44-LEAD PLCC PIN FUNCTION TABLE (CONTINUED)
Pin Number Pin Name Description
HV5530
DS20005851A-page 10 2017 Microchip Technology Inc.
3.0 FUNCTIONAL DESCRIPTION
Follow the steps in Ta b l e 3-1 to power up and power
down the HV5530.
TABLE 3-1: POWER-UP AND POWER-DOWN SEQUENCE
Power-up Power-down
Step Description Step Description
1Connect ground. 1Remove all inputs.
2Apply VDD. 2Remove VDD.
3Set all inputs to a known state. 3Disconnect ground.
TABLE 3-2:
Function
Inputs Outputs
Data CLK LE BL POL
Shift Register High-voltage Output Data Out
12...32 12...32 *
All On X X X L L * *...* On On...On *
All Off X X X L H * *...* Off Off...Off *
Invert Mode X X L H L * *...* * *...* *
Load S/R H or L ↓L H H H or L *...* **...* *
Load Latches XH or L ↑H H * *...* **...* *
XH or L ↑H L * *...* * *...* *
Transparent
Latch Mode
L↓H H H L *...* Off *...* *
H↓H H H H *...* On *...* *
Note: H = High-logic level
L = Low-logic level
X = Irrelevant
↓ = High-to-low transition
↑ = Low-to-high transition
* = Dependent on the previous stage’s state before the last CLK ↓ or last LE high
TRUTH FUNCTION TABLE
VDD
DATA
IN
HV
OUT
Logic Inputs
DATA
OUT
Logic Data Output High Voltage Outputs
VDD
HV
IN
VSS VSS
VSS
FIGURE 3-1: Input and Output Equivalent Circuits.
2017 Microchip Technology Inc. DS20005851A-page 11
HV5530
4.0 PACKAGE MARKING INFORMATION
4.1 Packaging Information
Legend: XX...X Product Code or Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for product code or customer-specific information. Package may or
not include the corporate logo.
3
e
3
e
44-lead PQFP Example
XXXXXXXXX
YYWWNNN
e3
HV5530PG
1729614
e3
44-lead PLCC Example
XXXXXXXXXX
YYWWNNN
e3
HV5530PJ
1731985
e3
44-Lead PQFP Package Outline (PG)
10.00x10.00mm body, 2.35mm height (max), 0.80mm pitch
Symbol A A1 A2 b D D1 E E1 e L L1 L2 ș
Dimension
(mm)
MIN 1.95* 0.00 1.95 0.30 13.65* 9.80* 13.65* 9.80*
0.80
BSC
0.73
1.95
REF
0.25
BSC
0O
NOM - - 2.00 - 13.90 10.00 13.90 10.00 0.88 3.5O
MAX 2.35 0.25 2.10 0.45 14.15* 10.20* 14.15* 10.20* 1.03 7O
JEDEC Registration MO-112, Variation AA-2, Issue B, Sep.1995.
7KLVGLPHQVLRQLVQRWVSHFL¿HGLQWKH-('(&GUDZLQJ
Drawings not to scale.
SD # DSPD 44PQFPPG V i C041309
1
44
Seating
Plane
Gauge
Plane
θ
L
L1
L2
View B
View B
Seating
Plane
Top View
D
D1
E
E1
be
Side View
A2
A
A1
Note 1
(Index Area
D1/4 x E1/4)
Note:
1. $3LQLGHQWL¿HUPXVWEHORFDWHGLQWKHLQGH[DUHDLQGLFDWHG7KH3LQLGHQWL¿HUFDQEHDPROGHGPDUNLGHQWL¿HUDQHPEHGGHGPHWDOPDUNHURU
a printed indicator.
Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging.Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging.
HV5530
DS20005851A-page 12 2017 Microchip Technology Inc.
44-Lead PLCC Package Outline (PJ)
.653x.653in body, .180in height (max), .050in pitch
Symbol A A1 A2 b b1 D D1 E E1 e R
Dimension
(inches)
MIN .165 .090 .062 .013 .026 .685 .650 .685 .650
.050
BSC
.025
NOM .172 .105 - - - .690 .653 .690 .653 .035
MAX .180 .120 .083 .021 .036†.695 .656 .695 .656 .045
JEDEC Registration MS-018, Variation AC, Issue A, June, 1993.
† This dimension differs from the JEDEC drawing.
Drawings not to scale.
.150 MAX
.048/.042 x 45O
1
.075 MAX
640
D
D1
E1 E
Top View
Horizontal Side View
View B
AA2
A1
Seating
Plane
e
b
Note 1
(Index Area)
.056/.042 x 45O
.020max
(3 Places)
.020 MIN
Vertical Side View
View B
Note 2
44
b1
Base
Plane
R
Notes:
1. $3LQLGHQWL¿HUPXVWEHORFDWHGLQWKHLQGH[DUHDLQGLFDWHG7KH3LQLGHQWL¿HUFDQEHDPROGHGPDUNLGHQWL¿HUDQHPEHGGHGPHWDOPDUNHURU
a printed indicator.
2. $FWXDOVKDSHRIWKLVIHDWXUHPD\YDU\
Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging.Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging.
2017 Microchip Technology Inc. DS20005851A-page 13
HV5530
HV5530
DS20005851A-page 14 2017 Microchip Technology Inc.
NOTES:
2017 Microchip Technology Inc. DS20005851A-page 15
HV5530
APPENDIX A: REVISION HISTORY
Revision A (October 2017)
• Converted Supertex Doc # DSFP-HV5530 to
Microchip DS20005851A
• Removed “Processed with HVCMOS® Technol-
ogy” in the Features section
• Changed the package marking format
• Removed the 44-lead PQFP PG M919 and
44-lead PLCC PJ M903 media types
• Made minor changes throughout the document
HV5530
DS20005851A-page 16 2017 Microchip Technology Inc.
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office.
Examples:
a) HV5530PG-G: 32-Channel Serial-to-Parallel
Converter with Open Drain
Outputs, 44-lead PQFP,
96/Tray
b) HV5530PJ-G: 32-Channel Serial-to-Parallel
Converter with Open Drain
Outputs, 44-lead PLCC,
27/Tube
PART NO.
Device
Device: HV5530 = 32-Channel Serial-to-Parallel Converter
with Open Drain Outputs
Packages: PG = 44-lead PQFP
PJ = 44-lead PLCC
Environmental: G = Lead (Pb)-free/RoHS-compliant Package
Media Types: (blank) = 96/Tray for a PG Package
(blank) = 27/Tube for a PJ Package
XX
Package
-
X - X
Environmental
Media Type
Options
2017 Microchip Technology Inc. DS20005851A-page 17
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, AnyRate, AVR,
AVR logo, AVR Freaks, BeaconThings, BitCloud, CryptoMemory,
CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KEELOQ,
KEELOQ logo, Kleer, LANCheck, LINK MD, maXStylus,
maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB,
OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip
Designer, QTouch, RightTouch, SAM-BA, SpyNIC, SST, SST
Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
and other countries.
ClockWorks, The Embedded Control Solutions Company,
EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS,
mTouch, Precision Edge, and Quiet-Wire are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo,
CodeGuard, CryptoAuthentication, CryptoCompanion,
CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average
Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial
Programming, ICSP, Inter-Chip Connectivity, JitterBlocker,
KleerNet, KleerNet logo, Mindi, MiWi, motorBench, MPASM, MPF,
MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,
Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,
PICtail, PureSilicon, QMatrix, RightTouch logo, REAL ICE, Ripple
Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI,
SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC,
USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and
ZENA are trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in
the U.S.A.
Silicon Storage Technology is a registered trademark of Microchip
Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip Technology
Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2017, Microchip Technology Incorporated, All Rights Reserved.
ISBN: 978-1-5224-2251-8
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
QUALITYMANAGEMENTS
YSTEM
CERTIFIEDBYDNV
== ISO/TS16949==
DS20005851A-page 18 2017 Microchip Technology Inc.
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India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4123
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
India - Pune
Tel: 91-20-3019-1500
Japan - Osaka
Tel: 81-6-6152-7160
Fax: 81-6-6152-9310
Japan - Tokyo
Tel: 81-3-6880- 3770
Fax: 81-3-6880-3771
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
Taiwan - Hsin Chu
Tel: 886-3-5778-366
Fax: 886-3-5770-955
Taiwan - Kaohsiung
Tel: 886-7-213-7830
Taiwan - Taipei
Tel: 886-2-2508-8600
Fax: 886-2-2508-0102
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
EUROPE
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
Finland - Espoo
Tel: 358-9-4520-820
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Germany - Garching
Tel: 49-8931-9700
Germany - Haan
Tel: 49-2129-3766400
Germany - Heilbronn
Tel: 49-7131-67-3636
Germany - Karlsruhe
Tel: 49-721-625370
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Germany - Rosenheim
Tel: 49-8031-354-560
Israel - Ra’anana
Tel: 972-9-744-7705
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Italy - Padova
Tel: 39-049-7625286
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Norway - Trondheim
Tel: 47-7289-7561
Poland - Warsaw
Tel: 48-22-3325737
Romania - Bucharest
Tel: 40-21-407-87-50
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
Sweden - Gothenberg
Tel: 46-31-704-60-40
Sweden - Stockholm
Tel: 46-8-5090-4654
UK - Wokingham
Tel: 44-118-921-5800
Fax: 44-118-921-5820
Worldwide Sales and Service
10/10/17
