© Semiconductor Components Industries, LLC, 2011
May, 2011 − Rev. 5
1Publication Order Number:
MC74VHCT00A/D
MC74VHCT00A
Quad 2-Input NAND Gate
The MC74VHCT00A is an advanced high speed CMOS 2−input
NAND gate fabricated with silicon gate CMOS technology. It
achieves high speed operation while maintaining CMOS low power
dissipation.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output.
The device input is compatible with TTL−type input thresholds and the
output has a full 5 V CMOS level output swing. The input protection
circuitry on this device allows overvoltage tolerance on the input,
allowing the device to be used as a logic−level translator from 3.0 V
CMOS logic to 5.0 V CMOS Logic or from 1.8 V CMOS logic to 3.0 V
CMOS Logic while operating at the high−voltage power supply.
The MC74VHCT00A input structure provides protection when
voltages up to 7 V are applied, regardless of the supply voltage. This
allows the MC74VHCT00A to be used to interface 5 V circuits to 3 V
circuits. The output structures also provide protection when VCC = 0 V.
These input and output structures help prevent device destruction caused
by supply voltage − input/output voltage mismatch, battery backup, hot
insertion, etc.
•High Speed: tPD = 5.0 ns (Typ) at VCC = 5 V
•Low Power Dissipation: ICC = 2 μA (Max) at TA = 25°C
•TTL−Compatible Inputs: VIL = 0.8 V; VIH = 2.0 V
•Power Down Protection Provided on Inputs and Outputs
•Balanced Propagation Delays
•Designed for 3.0 V to 5.5 V Operating Range
•Low Noise: VOLP = 0.8 V (Max)
•Pin and Function Compatible with Other Standard Logic Families
•Chip Complexity: 48 FETs or 12 Equivalent Gates
•These Devices are Pb−Free and are RoHS Compliant
TSSOP−14
DT SUFFIX
CASE 948G
14
1
SOIC−14
D SUFFIX
CASE 751A
MARKING DIAGRAMS
14
1
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or G= Pb−Free Package
VHCT00AG
AWLYWW
1
14
VHCT
00A
ALYWG
G
1
14
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the
dimensions section on page 6 of this data sheet.
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Figure 1. Pin Assignment
(Top View)
1314 12 11 10 9 8
21 34567
VCC B4 A4 Y4 B3 A3 Y3
A1 B1 Y1 A2 B2 Y2 GND
Figure 2. Logic Diagram
3Y1
1
A1
2
B1
6Y2
4
A2
5
B2
8Y3
9
A3
10
B3
11 Y4
12
A4
13
B4
Y = AB
L
L
H
H
L
H
L
H
FUNCTION TABLE
Inputs Output
AB
H
H
H
L
Y
Figure 3. IEC LOGIC DIAGRAM
3
A1
B1 &
6
8
11
1
2
A2
B2
4
5
A3
B3
9
10
A4
B4
12
13
Y1
Y2
Y3
Y4
PIN ASSIGNMENT
1
2
3 OUT Y1
IN A1
IN B1
4
5 IN B2
IN A2
6
7
8 OUT Y3
OUT Y2
GND
9
IN B3
IN A3
10
11
12 IN A4
OUT Y4
13
14 VCC
IN B4
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MAXIMUM RATINGS (Note 1)
Symbol Characteristics Value Unit
VCC DC Supply Voltage −0.5 to +7.0 V
VIN DC Input Voltage −0.5 to +7.0 V
VOUT DC Output Voltage VCC = 0
High or Low State
−0.5 to 7.0
−0.5 to VCC + 0.5
V
IIK Input Diode Current −20 mA
IOK Output Diode Current VOUT < GND; VOUT > VCC +20 mA
IOUT DC Output Current, per Pin +25 mA
ICC DC Supply Current, VCC and GND +50 mA
ÎÎÎÎ
ÎÎÎÎ
PD
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Power Dissipation in Still Air, SOIC Package (Note 2)
TSSOP Package (Note 2)
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
500
450
ÎÎÎ
ÎÎÎ
mW
TLLead temperature, 1 mm from case for 10 s 260 °C
Tstg Storage temperature −65 to +150 °C
VESD ESD Withstand Voltage Human Body Model (Note 3)
Machine Model (Note 4)
Charged Device Model (Note 5)
> 2000
> 200
> 3000
V
ILatch−Up Latch−Up Performance Above VCC and Below GND at 125°C
(Note 6)
±300 mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
* Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or
conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute−maximum−rated conditions
is not implied.
1. Maximum Ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those
indicated may adversely affect device reliability. Functional operation under absolute−maximum−rated conditions is not implied. Functional
operation should be restricted to the Recommended Operating Conditions.
2. Derating −SOIC Package: –7 mW/_C from 65_ to 125_C
−TSSOP Package: −6.1 mW/_C from 65_ to 125_C
3. Tested to EIA/JESD22−A114−A
4. Tested to EIA/JESD22−A115−A
5. Tested to JESD22−C101−A
6. Tested to EIA/JESD78
RECOMMENDED OPERATING CONDITIONS
Symbol Characteristics Min Max Unit
VCC DC Supply Voltage 3.0 5.5 V
VIN DC Input Voltage 0.0 5.5 V
VOUT DC Output Voltage VCC = 0
High or Low State
0.0
0.0
5.5
VCC
V
TAOperating Temperature Range −55 +125 °C
tr , tfInput Rise and Fall Time VCC = 3.3 V ± 0.3 V
VCC = 5.0 V ± 0.5 V
0
0
100
20
ns/V
This device contains
protection circuitry to guard
against damage due to high
static voltages or electric
fields. However, pre-
cautions must be taken to
avoid applications of any
voltage higher than maxi-
mum rated voltages to this
high−impedance circuit. For
proper operation, Vin and
Vout should be constrained
to the range GND v (Vin or
Vout) v VCC.
Unused inputs must al-
ways be tied to an appropri-
ate logic voltage level (e.g.,
either GND or VCC). Un-
used outputs must be left
open.
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The qJA of the package is equal to 1/Derating. Higher junction temperatures may affect the expected lifetime of the device per the table and
figure below.
DEVICE JUNCTION TEMPERATURE VERSUS
TIME TO 0.1% BOND FAILURES
Junction
Temperature °CTime, Hours Time, Years
80 1,032,200 117.8
90 419,300 47.9
100 178,700 20.4
110 79,600 9.4
120 37,000 4.2
130 17,800 2.0
140 8,900 1.0
1
1 10 100 1000
TIME, YEARS
NORMALIZED FAILURE RATE
TJ= 80 C°
TJ= 90 C°
TJ= 100 C°
TJ= 110 C°
TJ= 130 C°
TJ= 120 C°
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
Figure 4. Failure Rate vs. Time
Junction Temperature
DC ELECTRICAL CHARACTERISTICS
VCC TA = 25°C TA ≤ 85°C TA ≤ 125°C
Symbol Parameter Test Conditions (V) Min Typ Max Min Max Min Max Unit
VIH Minimum High−Level
Input Voltage
3.0
4.5
5.5
1.4
2.0
2.0
1.4
2.0
2.0
1.4
2.0
2.0
V
VIL Maximum Low−Level
Input Voltage
3.0
4.5
5.5
0.53
0.8
0.8
0.53
0.8
0.8
0.53
0.8
0.8
V
VOH Minimum High−Level
Output Voltage
VIN = VIH or VIL
VIN = VIH or VIL
IOH = −50 μA
3.0
4.5
2.9
4.4
3.0
4.5
2.9
4.4
2.9
4.4
V
VIN = VIH or VIL
IOH = −4 mA
IOH = −8 mA
3.0
4.5
2.58
3.94
2.48
3.80
2.34
3.66
V
VOL Maximum Low−Level
Output Voltage
VIN = VIH or VIL
VIN = VIH or VIL
IOL = 50 μA
3.0
4.5
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
V
VIN = VIH or VIL
IOL = 4 mA
IOL = 8 mA
3.0
4.5
0.36
0.36
0.44
0.44
0.52
0.52
V
IIN Maximum Input
Leakage Current
VIN = 5.5 V or GND 0 to
5.5
±0.1 ±1.0 ±1.0 μA
ICC Maximum Quiescent
Supply Current
VIN = VCC or GND 5.5 2.0 20 40 μA
ICCT Quiescent Supply
Current
Input: VIN = 3.4 V 5.5 1.35 1.50 1.65 mA
IOPD Output Leakage
Current
VOUT = 5.5 V 0.0 0.5 5.0 10 μA
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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
AC ELECTRICAL CHARACTERISTICS Cload = 50 pF, Input tr = tf = 3.0 ns
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
Symbol
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
Parameter
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
Test Conditions
TA = 25°C
ÎÎÎÎÎ
ÎÎÎÎÎ
TA ≤ 85°C
ÎÎÎÎÎ
ÎÎÎÎÎ
TA ≤ 125°C
ÎÎ
ÎÎ
ÎÎ
Unit
ÎÎ
ÎÎ
Min
ÎÎÎ
ÎÎÎ
Typ
ÎÎÎ
ÎÎÎ
Max
ÎÎÎ
ÎÎÎ
Min
ÎÎÎ
ÎÎÎ
Max
ÎÎÎ
ÎÎÎ
Min
ÎÎÎ
ÎÎÎ
Max
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
tPLH,
tPHL
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
Maximum
Propogation Delay,
Input A or B to Y
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
VCC = 3.3 ± 0.3 V CL = 15 pF
CL = 50 pF
ÎÎ
ÎÎ
ÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
4.1
5.5
ÎÎÎ
ÎÎÎ
ÎÎÎ
10.0
13.5
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
11.0
15.0
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
13.0
17.5
ÎÎ
ÎÎ
ÎÎ
ns
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
VCC = 5.0 ± 0.5 V CL = 15 pF
CL = 50 pF
ÎÎ
ÎÎ
ÎÎÎ
ÎÎÎ
3.1
3.6
ÎÎÎ
ÎÎÎ
6.9
7.9
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
8.0
9.0
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
9.5
10.5
ÎÎ
ÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
CIN
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
Maximum Input
Capacitance
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
5.5
ÎÎÎ
ÎÎÎ
ÎÎÎ
10
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
10
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
10
ÎÎ
ÎÎ
ÎÎ
pF
CPD Power Dissipation Capacitance (Note 7)
Typical @ 25°C, VCC = 5.0 V
pF
17
7. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC. CPD is used to determine the no−load dynamic
power consumption; PD = CPD VCC2 fin + ICC VCC.
NOISE CHARACTERISTICS (Input tr = tf = 3.0ns, CL = 50pF, VCC = 5.0V, Measured in SO Package)
Symbol Characteristic
TA = 25°C
Unit
Typ Max
VOLP Quiet Output Maximum Dynamic VOL 0.4 0.8 V
VOLV Quiet Output Minimum Dynamic VOL − 0.4 − 0.8 V
VIHD Minimum High Level Dynamic Input Voltage 2.0 V
VILD Maximum Low Level Dynamic Input Voltage 0.8 V
3.0 V
GND
50%
50% VCC
A or B
Y
tPHL
tPLH
*Includes all probe and jig capacitance
CL*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
VOH
VOL
Figure 5. Switching Waveforms Figure 6. Test Circuit
INPUT
Figure 7. Input Equivalent Circuit
OUTPUT
Figure 8. Output Equivalent Circuit
*
*Parastic Diode
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ORDERING INFORMATION
Device Package Shipping†
MC74VHCT00ADR2G SOIC−14
(Pb−Free)
2500 / Tape & Reel
MC74VHCT00ADTR2G TSSOP−14
(Pb−Free)
2000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specification Brochure, BRD8011/D.
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7
PACKAGE DIMENSIONS
SOIC−14
D SUFFIX
CASE 751A−03
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
−A−
−B−
G
P7 PL
14 8
7
1
M
0.25 (0.010) B M
S
B
M
0.25 (0.010) A S
T
−T−
F
RX 45
SEATING
PLANE D14 PL K
C
J
M
_DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A8.55 8.75 0.337 0.344
B3.80 4.00 0.150 0.157
C1.35 1.75 0.054 0.068
D0.35 0.49 0.014 0.019
F0.40 1.25 0.016 0.049
G1.27 BSC 0.050 BSC
J0.19 0.25 0.008 0.009
K0.10 0.25 0.004 0.009
M0 7 0 7
P5.80 6.20 0.228 0.244
R0.25 0.50 0.010 0.019
__ __
7.04
14X
0.58
14X
1.52
1.27
DIMENSIONS: MILLIMETERS
1
PITCH
SOLDERING FOOTPRINT
7X
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PACKAGE DIMENSIONS
TSSOP−14
DT SUFFIX
CASE 948G−01
ISSUE B
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A4.90 5.10 0.193 0.200
B4.30 4.50 0.169 0.177
C−−− 1.20 −−− 0.047
D0.05 0.15 0.002 0.006
F0.50 0.75 0.020 0.030
G0.65 BSC 0.026 BSC
H0.50 0.60 0.020 0.024
J0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L6.40 BSC 0.252 BSC
M0 8 0 8
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
____
S
U0.15 (0.006) T
2X L/2
S
U
M
0.10 (0.004) V S
T
L−U−
SEATING
PLANE
0.10 (0.004)
−T−
ÇÇÇ
ÇÇÇ
SECTION N−N
DETAIL E
JJ1
K
K1
ÉÉÉ
ÉÉÉ
DETAIL E
F
M
−W−
0.25 (0.010)
8
14
7
1
PIN 1
IDENT.
H
G
A
D
C
B
S
U0.15 (0.006) T
−V−
14X REFK
N
N
7.06
14X
0.36 14X
1.26
0.65
DIMENSIONS: MILLIMETERS
1
PITCH
SOLDERING FOOTPRINT
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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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MC74VHCT00A/D
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