3-141
80C86
CMOS 16-Bit Microprocessor
Features
• Compatible with NMOS 8086
• Completely Static CMOS Design
- DC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5MHz (80C86)
- DC . . . . . . . . . . . . . . . . . . . . . . . . . . . .8MHz (80C86-2)
• Low Power Operation
- lCCSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . .500µA Max
- ICCOP . . . . . . . . . . . . . . . . . . . . . . . . . 10mA/MHz Typ
• 1MByte of Direct Memory Addressing Capability
• 24 Operand Addressing Modes
• Bit, Byte, Word and Block Move Operations
• 8-Bit and 16-Bit Signed/Unsigned Arithmetic
- Binary, or Decimal
- Multiply and Divide
• Wide Operating Temperature Range
- C80C86 . . . . . . . . . . . . . . . . . . . . . . . . . .0oC to +70oC
- l80C86 . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC
- M80C86 . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC
Description
The Intersil 80C86 high performance 16-bit CMOS CPU is
manufactured using a self-aligned silicon gate CMOS pro-
cess (Scaled SAJI IV). Two modes of operation, minim um f or
small systems and maximum for larger applications such as
multiprocessing, allow user configuration to achieve the
highest performance level. Full TTL compatibility (with the
exception of CLOCK) and industr y standard operation allow
use of existing NMOS 8086 hardware and software designs.
Ordering Information
PACKAGE TEMP. RANGE 5MHz 8MHz PKG.
NO.
PDIP 0oC to +70oC CP80C86 CP80C86-2 E40.6
-40oC to +85oC lP80C86 IP80C86-2 E40.6
PLCC 0oC to +70oC CS80C86 CS80C86-2 N44.65
-40oC to +85oC lS80C86 IS80C86-2 N44.65
CERDIP 0oC to +70oC CD80C86 CD80C86-2 F40.6
-40oC to +85oC ID80C86 ID80C86-2 F40.6
-55oC to +125oC MD80C86/B MD80C86-
2/B F40.6
SMD# -55oC to +125oC 8405201QA 8405202QA F40.6
CLCC -55oC to +125oC MR80C86/B MR80C86-
2/B J44.A
SMD# -55oC to +125oC 8405201XA 8405202XA J44.A
March 1997
File Number 2957.1
[ /Title
(80C86
)
/Sub-
ject
(CMO
S 16-
Bit
Micro-
proces-
sor)
/Autho
r ()
/Key-
words
(Inter-
sil
Corpo-
ration,
Inter-
sil
Corpo-
ration,
16 Bit
uP,
micro-
proces-
sor,
8086,
PC)
/Cre-
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 |Copyright © Intersil Corporation 1999
3-142
Pinouts
80C86 (DIP)
TOP VIEW
80C86 (PLCC, CLCC)
TOP VIEW
13
1
2
3
4
5
6
7
8
9
10
11
12
14
15
16
17
18
19
20
GND
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
NMI
INTR
CLK
GND
28
40
39
38
37
36
35
34
33
32
31
30
29
27
26
25
24
23
22
21
VCC
AD15
A16/S3
A17/S4
A18/S5
A19/S6
BHE/S7
MN/MX
RD
RQ/GT0
RQ/GT1
LOCK
S2
S1
S0
QS0
QS1
TEST
READY
RESET
(INTA)
(ALE)
(DEN)
(DT/R))
(M/IO)
(WR)
(HLDA)
(HOLD)
MAX (MIN)
14
13
12
11
10
9
8
7
17
16
15
25
30
35
39
38
37
36
33
34
32
31
29
4
6 3 140414243
44
2827262524232221201918
A19/S6
BHE/S7
MN/MX
RD
HOLD
HLDA
WR
M/IO
DT/R
DEN
NC NC
A19/S6
BHE/S7
MN/MX
RD
RQ/GT0
RQ/GT1
LOCK
S2
S1
S0
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
AD10 AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
AD12
AD13
AD14
GND
NC
VCC
AD15
A16/S3
A17/S4
A18/S5
AD11 AD11
AD12
AD13
AD14
GND
NC
VCC
AD15
A16/S3
A17/S4
A18/S5
NMI
INTR
CLK
GND
NC
RESET
READY
TEST
QS1
QS0
NC NC
NMI
INTR
CLK
GND
NC
RESET
READY
TEST
INTA
ALE
MAX MODE
80C86
MIN MODE
80C86
MAX MODE
80C86
MIN MODE
80C86
80C8680C86
3-143
Functional Diagram
REGISTER FILE
EXECUTION UNIT
CONTROL AND TIMING
INSTRUCTION
QUEUE
6-BYTE
FLAGS
16-BIT ALU
BUS INTERFACE UNIT 16
4
QS0, QS1
S2, S1, S0
2
4
3
GND
VCC
CLK RESET READY
BUS INTERFACE UNIT
RELOCATION
REGISTER FILE
3
A19/S6
A16/S3
INTA, RD, WR
DT/R, DEN, ALE, M/IO
BHE/S7
2
SEGMENT REGISTERS
AND
INSTRUCTION POINTER
(5 WORDS)
DATA POINTER
AND
INDEX REGS
(8 WORDS)
TEST
INTR
NMI
HLDA
HOLD
RQ/GT0, 1
LOCK
MN/MX 3
ES
CS
SS
DS
IP
AH
BH
CH
DH
AL
BL
CL
DL
SP
BP
SI
DI
ARITHMETIC/
LOGIC UNIT
B-BUS
C-BUS
EXECUTION
UNIT
INTERFACE
UNIT
BUS
QUEUE
INSTRUCTION
STREAM BYTE
EXECUTION UNIT
CONTROL SYSTEM
FLAGS
MEMORY INTERFACE
A-BUS
AD15-AD0
80C86
3-144
Pin Description
The following pin function descriptions are for 80C86 systems in either minimum or maximum mode. The “Local Bus” in these description is
the direct multiplexed bus interface connection to the 80C86 (without regard to additional bus buffers).
SYMBOL PIN
NUMBER TYPE DESCRIPTION
AD15-AD0 2-16, 39 I/O ADDRESS D ATA BUS: These lines constitute the time multiple x ed memory/lO address (T1) and
data (T2, T3, TW, T4) bus. A0 is analogous to BHE for the lower byte of the data bus, pins D7-
D0. It is LOW during Ti when a byte is to be tr ansferred on the lower portion of the bus in memory
or I/O operations. Eight-bit oriented de vices tied to the low er half would normally use A0 to con-
dition chip select functions (See BHE). These lines are active HIGH and are held at high imped-
ance to the last valid logic level during interrupt acknowledge and local bus “hold acknowledge”
or “grant sequence”.
A19/S6
A18/S5
A17/S4
A16/S3
35-38 O ADDRESS/STATUS: During T1, these are the four most significant address lines f or memory op-
erations. During I/O operations these lines are LOW. During memory and I/O operations, status
information is available on these lines during T2, T3, TW, T4. S6 is always LOW. The status of
the interrupt enable FLAG bit (S5) is updated at the beginning of each clock cycle. S4 and S3
are encoded as shown.
This information indicates which segment register is presently being used for data accessing.
These lines are held at high impedance to the last valid logic level during local bus “hold ac-
knowledge” or “grant sequence”.
BHE/S7 34 O BUS HIGH ENABLE/STATUS: Dur ing T1 the bus high enable signal (BHE) should be used to
enable data onto the most significant half of the data bus, pins D15-D8. Eight bit oriented devices
tied to the upper half of the bus w ould normally use BHE to condition chip select functions. BHE
is LOW during T1 for read, wr ite, and interrupt acknowledge cycles when a byte is to be trans-
ferred on the high portion of the bus. The S7 status infor mation is available during T2, T3 and
T4. The signal is active LOW, and is held at high impedance to the last valid logic level during
interrupt acknowledge and local bus “hold acknowledge” or “grant sequence”, it is LOW during
T1 for the first interrupt acknowledge cycle.
RD 32 O READ: Read strobe indicates that the processor is performing a memory or I/O read cycle, de-
pending on the state of the M/IO or S2 pin. This signal is used to read devices which reside on
the 80C86 local bus . RD is active LOW during T2, T3 and TW of any read cycle , and is guar an-
teed to remain HIGH in T2 until the 80C86 local bus has floated.
This line is held at a high impedance logic one state during “hold acknowledge” or “grand se-
quence”.
READY 22 I READY : is the ackno wledgment from the addressed memory or I/O de vice that will complete the
data transf er. The RDY signal from memory or I/O is synchronized b y the 82C84A Cloc k Gener-
ator to form READY. This signal is active HIGH. The 80C86 READY input is not synchronized.
Correct operation is not guaranteed if the Setup and Hold Times are not met.
S4 S3 CHARACTERISTICS
0 0 Alternate Data
0 1 Stack
1 0 Code or None
1 1 Data
BHE A0 CHARACTERISTICS
0 0 Whole Word
0 1 Upper Byte From/to Odd Address
1 0 Lower Byte From/to Even address
1 1 None
80C86
3-145
INTR 18 I INTERRUPT REQUEST: is a level triggered input which is sampled during the last clock cycle
of each instruction to determine if the processor should enter into an interrupt ackno wledge op-
eration. A subroutine is vectored to via an interrupt vector lookup table located in system mem-
ory. It can be internally masked by software resetting the interrupt enable bit.
lNTR is internally synchronized. This signal is active HIGH.
TEST 23 I TEST : input is examined b y the “W ait” instruction. If the TEST input is LOW e xecution contin ues,
otherwise the processor waits in an “Idle”state. This input is synchroniz ed internally during each
clock cycle on the leading edge of CLK.
NMI 17 I NON-MASKABLE INTERRUPT: is an edge triggered input which causes a type 2 interrupt. A
subroutine is vectored to via an interrupt vector lookup table located in system memory. NMI is
not maskable internally by software. A transition from LOW to HIGH initiates the interrupt at the
end of the current instruction. This input is internally synchronized.
RESET 21 I RESET : causes the processor to immediately terminate its present activity. The signal must tran-
sition LOW to HIGH and remain active HIGH for at least four clock cycles. It restarts execution,
as described in the Instruction Set description, when RESET returns LOW. RESET is internally
synchronized.
CLK 19 I CLOCK: provides the basic timing for the processor and bus controller. It is asymmetr ic with a
33% duty cycle to provide optimized internal timing.
VCC 40 VCC: +5V power supply pin. A 0.1µF capacitor betw een pins 20 and 40 is recommended f or de-
coupling.
GND 1, 20 GND: Ground. Note: both must be connected. A 0.1µF capacitor between pins 1 and 20 is rec-
ommended for decoupling.
MN/MX 33 I MINIMUM/MAXIMUM: Indicates what mode the processor is to operate in. The two modes are
discussed in the following sections.
Minimum Mode System
The following pin function descriptions are for the 80C86 in minimum mode (i.e., MN/MX = VCC). Only the pin functions which are unique to
minimum mode are described; all other pin functions are as described below.
SYMBOL PIN
NUMBER TYPE DESCRIPTION
M/IO 28 O STATUS LINE: logically equivalent to S2 in the maximum mode. It is used to distinguish a mem-
ory access from an I/O access. M/lO becomes valid in the T4 preceding a bus cycle and remains
valid until the final T4 of the cycle (M = HIGH, I/O = LO W). M/lO is held to a high impedance logic
one during local bus “hold acknowledge”.
WR 29 O WRITE: indicates that the processor is performing a write memory or write I/O cycle, depending
on the state of the M/IO signal. WR is active for T2, T3 and TW of any write cycle. It is active
LOW, and is held to high impedance logic one during local bus “hold acknowledge”.
INTA 24 O INTERRUPT ACKNOWLEDGE: is used as a read strobe for interrupt acknowledge cycles. It is
active LOW during T2, T3 and TW of each interrupt ackno wledge cycle . Note that INTA is nev er
floated.
ALE 25 O ADDRESS LATCH ENABLE: is provided by the processor to latch the address into the
82C82/82C83 address latch. It is a HIGH pulse active during clock LOW of T1 of any bus cycle .
Note that ALE is never floated.
Pin Description
(Continued)
The following pin function descriptions are for 80C86 systems in either minimum or maximum mode. The “Local Bus” in these description is
the direct multiplexed bus interface connection to the 80C86 (without regard to additional bus buffers).
SYMBOL PIN
NUMBER TYPE DESCRIPTION
80C86
3-146
DT/R 27 O DATA TRANSMIT/RECEIVE: is needed in a minimum system that desires to use a data bus
transceiver. It is used to control the direction of data flow through the transceiver. Logically,
DT/R is equivalent to S1 in maximum mode, and its timing is the same as for M/IO (T = HIGH,
R = LOW). DT/R is held to a high impedance logic one during local bus “hold acknowledge”.
DEN 26 O DATA ENABLE: provided as an output enable for a bus transceiver in a minimum system which
uses the transceiver. DEN is active LOW during each memory and I/O access and for INTA cy-
cles. F or a read or INTA cycle it is active from the middle of T2 until the middle of T4, while for a
write cycle it is active from the beginning of T2 until the middle of T4. DEN is held to a high im-
pedance logic one during local bus “hold acknowledge”.
HOLD
HLDA 31, 30 I
OHOLD: indicates that another master is requesting a local bus “hold”. To be an acknowledged,
HOLD must be activ e HIGH. The processor receiving the “hold” will issue a “hold ac kno wledge”
(HLDA) in the middle of a T4 or TI clock cycle. Simultaneously with the issuance of HLDA, the
processor will float the local bus and control lines. After HOLD is detected as being LOW, the
processor will lower HLD A, and when the processor needs to run another cycle, it will again drive
the local bus and control lines.
HOLD is not an asynchronous input. External synchronization should be provided if the system
cannot otherwise guarantee the setup time.
Maximum Mode System
The following pin function descriptions are for the 80C86 system in maximum mode (i.e., MN/MX - GND). Only the pin functions which are
unique to maximum mode are described below.
SYMBOL PIN
NUMBER TYPE DESCRIPTION
S0
S1
S2
26
27
28
O
O
O
STATUS: is active during T4, T1 and T2 and is returned to the passive state (1, 1, 1) during T3
or during TW when READ Y is HIGH. This status is used by the 82C88 Bus Controller to gener ate
all memory and I/O access control signals. Any change by S2, S1 or S0 during T4 is used to
indicate the beginning of a bus cycle , and the return to the passive state in T3 or TW is used to
indicate the end of a bus cycle.
These signals are held at a high impedance logic one state during “grant sequence”.
Minimum Mode System (Continued)
The following pin function descriptions are for the 80C86 in minimum mode (i.e., MN/MX = VCC). Only the pin functions which are unique to
minimum mode are described; all other pin functions are as described below.
SYMBOL PIN
NUMBER TYPE DESCRIPTION
S2 S1 S0 CHARACTERISTICS
0 0 0 Interrupt Acknowledge
0 0 1 Read I/O Port
0 1 0 Write I/O Port
0 1 1 Halt
1 0 0 Code Access
1 0 1 Read Memory
1 1 0 Write Memory
1 1 1 Passive
80C86
3-147
RQ/GT0
RQ/GT1 31, 30 I/O REQUEST/GRANT: pins are used by other local bus masters to force the processor to release
the local bus at the end of the processor’s current bus cycle. Each pin is bidirectional with
RQ/GTO having higher priority than RQ/GT1. RQ/GT has an internal pull-up bus hold device so
it may be left unconnected. The request/grant sequence is as follows (see RQ/GT Sequence
Timing)
1. A pulse of 1 CLK wide from another local bus master indicates a local bus request (“hold”)
to the 80C86 (pulse 1).
2. During a T4 or TI clock cycle, a pulse 1 CLK wide from the 80C86 to the requesting master
(pulse 2) indicates that the 80C86 has allowed the local bus to float and that it will enter the
“grant sequence” state at the next CLK. The CPU’s bus interface unit is disconnected logi-
cally from the local bus during “grant sequence”.
3. A pulse 1 CLK wide from the requesting master indicates to the 80C86 (pulse 3) that the
“hold” request is about to end and that the 80C86 can reclaim the local bus at the next CLK.
The CPU then enters T4 (or TI if no bus cycles pending).
Each Master-Master exchange of the local b us is a sequence of 3 pulses. There must be one
idle CLK cycle after each bus exchange. Pulses are active low.
If the request is made while the CPU is performing a memor y cycle, it will release the local
bus during T4 of the cycle when all the following conditions are met:
1. Request occurs on or before T2.
2. Current cycle is not the low byte of a word (on an odd address).
3. Current cycle is not the first acknowledge of an interrupt acknowledge sequence.
4. A locked instruction is not currently executing.
If the local bus is idle when the request is made the two possible events will follow:
1. Local bus will be released during the next cycle.
2. A memory cycle will start within three clocks. Now the f our rules for a currently activ e memory
cycle apply with condition number 1 already satisfied.
LOCK 29 O LOCK: output indicates that other system bus masters are not to gain control of the system b us
while LOCK is active LOW. The LOCK signal is activated by the “LOCK” prefix instruction and
remains active until the completion of the ne xt instruction. This signal is activ e LO W, and is held
at a high impedance logic one state during “grant sequence”. In MAX mode, LOCK is automat-
ically generated during T2 of the first INTA cycle and removed during T2 of the second INTA
cycle.
QS1, QSO 24, 25 O QUEUE STATUS: The queue status is valid during the CLK cycle after which the queue opera-
tion is performed.
QS1 and QS0 provide status to allow external tracking of the internal 80C86 instruction queue.
Note that QS1, QS0 never become high impedance.
Maximum Mode System (Continued)
The following pin function descriptions are for the 80C86 system in maximum mode (i.e., MN/MX - GND). Only the pin functions which are
unique to maximum mode are described below.
SYMBOL PIN
NUMBER TYPE DESCRIPTION
QSI QSO
0 0 No Operation
0 1 First byte of op code from queue
1 0 Empty the queue
1 1 Subsequent byte from queue
80C86
3-148
Functional Description
Static Operation
All 80C86 circuitry is of static design. Internal registers,
counters and latches are static and require no refresh as
with dynamic circuit design. This eliminates the minimum
operating frequency restriction placed on other microproces-
sors. The CMOS 80C86 can operate from DC to the speci-
fied upper frequency limit. The processor clock may be
stopped in either state (HIGH/LOW) and held there indefi-
nitely. This type of operation is especially useful for system
debug or power critical applications.
The 80C86 can be single stepped using only the CPU clock.
This state can be maintained as long as is necessary. Single
step clock operation allows simple interface circuitry to pro-
vide critical information for bringing up your system.
Static design also allows very low frequency operation
(down to DC). In a power critical situation, this can provide
extremely low power operation since 80C86 power dissipa-
tion is directly related to operating frequency. As the system
frequency is reduced, so is the operating power until, ulti-
mately, at a DC input frequency, the 80C86 power require-
ment is the standby current, (500µA maximum).
Internal Architecture
The internal functions of the 80C86 processor are parti-
tioned logically into two processing units. The first is the Bus
Interface Unit (BlU) and the second is the Execution Unit
(EU) as shown in the CPU functional diagram.
These units can interact directly, but for the most part perform
as separate asynchronous operational processors. The bus
interface unit provides the functions related to instruction
fetching and queuing, operand fetch and store, and address
relocation. This unit also provides the basic bus control. The
over lap of instr uction pre-fetching provided by this unit serves
to increase processor performance through improved bus
bandwidth utilization. Up to 6 bytes of the instruction stream
can be queued while waiting for decoding and execution.
The instruction stream queuing mechanism allows the BIU
to keep the memory utilized ver y efficiently. Whenever there
is space f or at least 2 b ytes in the queue , the BlU will attempt
a word f etch memory cycle. This greatly reduces “dead-time”
on the memory bus. The queue acts as a First-In-First-Out
(FIFO) buffer, from which the EU extracts instruction bytes
as required. If the queue is empty (following a branch
instruction, for example), the first byte into the queue imme-
diately becomes available to the EU.
The execution unit receives pre-fetched instructions from the
BlU queue and provides un-relocated operand addresses to
the BlU . Memory operands are passed through the BIU for pro-
cessing by the EU, which passes results to the BIU f or storage .
Memory Organization
The processor provides a 20-bit address to memory, which
locates the byte being referenced. The memory is organized
as a linear array of up to 1 million bytes, addressed as
00000(H) to FFFFF(H). The memor y is logically divided into
code, data, extra and stack segments of up to 64K bytes
each, with each segment f alling on 16-b yte boundaries. (See
Figure 1).
All memor y references are made relative to base addresses
contained in high speed segment registers. The segment
types were chosen based on the addressing needs of pro-
grams. The segment register to be selected is automatically
chosen according to the specific rules of Table 1. All inf orma-
tion in one segment type share the same logical attributes
(e.g. code or data). By structuring memor y into re-locatable
areas of similar characteristics and by automatically select-
ing segment registers, programs are shorter, faster and
more structured. (See Table 1).
Word (16-bit) operands can be located on even or odd
address boundaries and are thus, not constrained to even
boundaries as is the case in many 16-bit computers. For
address and data operands, the least significant byte of the
word is stored in the lower valued address location and the
most significant byte in the next higher address location. The
BIU automatically performs the proper number of memory
TABLE 1.
TYPE OF
MEMORY
REFERENCE
DEFAULT
SEGMENT
BASE
ALTERNATE
SEGMENT
BASE OFFSET
Instruction Fetch CS None IP
Stack Operation SS None SP
Variable (except
following) DS CS, ES, SS Effective
Address
String Source DS CS, ES, SS SI
String Destination ES None DI
BP Used As Base
Register SS CS, DS, ES Effective
Address
SEGMENT
REGISTER FILE
CS
SS
DS
ES
64K-BIT
+ OFFSET
FFFFFH
CODE SEGMENT
XXXXOH
STACK SEGMENT
DATA SEGMENT
EXTRA SEGMENT
00000H
FIGURE 1. 80C86 MEMORY ORGANIZATION
80C86
3-149
accesses; one, if the word operand is on an even byte
boundary and two, if it is on an odd byte boundary. Except
for the performance penalty,this double access is transpar-
ent to the software. The performance penalty does not occur
for instruction fetches; only word operands.
Physically, the memory is organized as a high bank (D15-
D8) and a low bank (D7-D0) of 512K b ytes addressed in par-
allel by the processor’s address lines.
Byte data with even addresses is transferred on the D7-D0
bus lines , while odd addressed byte data (A0 HIGH) is trans-
ferred on the D15-D8 bus lines. The processor provides two
enable signals, BHE and A0, to selectively allow reading
from or writing into either an odd byte location, even byte
location, or both. The instruction stream is fetched from
memory as words and is addressed internally by the proces-
sor at the byte level as necessary.
In ref erencing word data, the BlU requires one or tw o memory
cycles depending on whether the star ting byte of the word is
on an even or odd address, respectively. Consequently, in ref-
erencing word operands performance can be optimized by
locating data on even address boundaries. This is an espe-
cially useful technique for using the stack, since odd address
references to the stack may adversely affect the context
s witching time for interrupt processing or task multiplexing.
Certain locations in memory are reserved for specific CPU
operations (See Figure 2). Locations from address FFFF0H
through FFFFFH are reserved for operations including a jump
to the initial program loading routine. Following RESET, the
CPU will always begin execution at location FFFF0H where
the jump must be located. Locations 00000H through 003FFH
are reserv ed f or interrupt operations . Each of the 256 possib le
interrupt ser vice routines is accessed thru its own pair of 16-
bit pointers (segment address pointer and offset address
pointer). The first pointer, used as the offset address, is
loaded into the lP and the second pointer, which designates
the base address is loaded into the CS. At this point program
control is transferred to the interr upt routine. The pointer ele-
ments are assumed to have been stored at the respective
places in reserved memory prior to occurrence of interrupts .
Minimum and Maximum Operation Modes
The requirements for supporting minimum and maximum
80C86 systems are sufficiently different that they cannot be
met efficiently using 40 uniquely defined pins. Consequently,
the 80C86 is equipped with a strap pin (MN/MX) which
defines the system configuration. The definition of a certain
subset of the pins changes, dependent on the condition of the
strap pin. When the MN/MX pin is strapped to GND, the
80C86 defines pins 24 through 31 and 34 in maximum mode.
When the MN/MX pin is strapped to VCC, the 80C86 gener-
ates bus control signals itself on pins 24 through 31 and 34.
The minimum mode 80C86 can be used with either a multi-
plexed or demultiplexed bus. This architecture provides the
80C86 processing power in a highly integrated form.
The demultiplexed mode requires two 82C82 latches (for 64K
addressability) or three 82C82 latches (for a full megabyte of
addressing). An 82C86 or 82C87 transceiver can also be
used if data bus buffering is required. (See Figure 6A.) The
80C86 provides DEN and DT/R to control the transceiver, and
ALE to latch the addresses. This configuration of the minim um
mode provides the standard demultiplexed bus str ucture with
heavy bus buff ering and relax ed bus timing requirements.
The maximum mode employs the 82C88 bus controller (See
Figure 6B). The 82C88 decodes status lines S0, S1 and S2,
and provides the system with all bus control signals.
Moving the bus control to the 82C88 provides better source
and sink current capability to the control lines, and frees the
80C86 pins for extended large system features. Hardware
lock, queue status, and two request/grant interfaces are pro-
vided by the 80C86 in maxim um mode . These features allow
coprocessors in local bus and remote bus configurations.
Bus Operation
The 80C86 has a combined address and data bus com-
monly referred to as a time multiplexed bus. This technique
provides the most efficient use of pins on the processor
while permitting the use of a standard 40 lead package. This
“local bus” can be buffered directly and used throughout the
system with address latching provided on memory and I/O
modules. In addition, the bus can also be demultiplexed at
the processor with a single set of 82C82 address latches if a
standard non-multiplexed bus is desired for the system.
Each processor bus cycle consists of at least four CLK
cycles. These are referred to as T1, T2, T3 and T4 (see Fig-
ure 3). The address is emitted from the processor during T1
and data transfer occurs on the bus during T3 and T4. T2 is
used primarily for changing the direction of the bus during
read operations. In the event that a “NOT READY” indication
is given by the addressed device, “Wait” states (TW) are
inser ted between T3 and T4. Each inser ted wait state is the
same duration as a CLK cycle. Periods can occur between
80C86 driven bus cycles. These are referred to as idle”
states (TI) or inactive CLK cycles. The processor uses these
cycles for internal housekeeping and processing.
During T1 of any bus cycle, the ALE (Address Latch Enable)
signal is emitted (by either the processor or the 82C88 bus
controller, depending on the MN/MX strap). At the trailing
edge of this pulse, a valid address and certain status infor-
mation for the cycle may be latched.
Status bits S0, S1 and S2 are used by the bus controller, in
maximum mode, to identify the type of bus transaction
according to Table 2.
TABLE 2.
S2 S1 S0 CHARACTERISTICS
0 0 0 Interrupt
0 0 1 Read I/O
0 1 0 Write I/O
0 1 1 Halt
1 0 0 Instruction Fetch
1 0 1 Read Data from Memory
1 1 0 Write Data to Memory
1 1 1 Passive (No Bus Cycle)
80C86
3-150
Status bits S3 through S7 are time multiplexed with high
order address bits and the BHE signal, and are therefore
valid during T2 through T4. S3 and S4 indicate which seg-
ment register (see Instruction Set Descr iption) was used for
this bus cycle in forming the address, according to Table 3.
S5 is a reflection of the PSW interrupt enable bit. S3 is
always zero and S7 is a spare status bit.
I/O Addressing
In the 80C86, I/O operations can address up to a maximum
of 64K I/O byte registers or 32K I/O word registers. The I/O
address appears in the same f ormat as the memory address
on bus lines A15-A0. The address lines A19-A16 are zero in
I/O operations. The variable I/O instructions which use regis-
ter DX as a pointer have full address capability while the
direct I/O instructions directly address one or two of the 256
I/O byte locations in page 0 of the I/O address space.
I/O ports are addressed in the same manner as memory loca-
tions. Even addressed bytes are transferred on the D7-D0 bus
lines and odd addressed bytes on D15-D8. Care must be taken
to ensure that each register within an 8-bit peripheral located on
the lower portion of the bus be addressed as even.
TABLE 3.
S4 S3 CHARACTERISTICS
0 0 Alternate Data (Extra Segment)
0 1 Stack
1 0 Code or None
1 1 Data
TYPE 225 POINTER
(AVAILABLE)
RESET BOOTSTRAP
PROGRAM JUMP
TYPE 33 POINTER
(AVAILABLE)
TYPE 32 POINTER
(AVAILABLE)
TYPE 31 POINTER
(AVAILABLE)
TYPE 5 POINTER
(RESERVED)
TYPE 4 POINTER
OVERFLOW
TYPE 3 POINTER
1 BYTE INT INSTRUCTION
TYPE 2 POINTER
NON MASKABLE
TYPE 1 POINTER
SINGLE STEP
TYPE 0 POINTER
DIVIDE ERROR
16 BITS
CS BASE ADDRESS
IP OFFSET
014H
010H
00CH
008H
004H
000H
07FH
080H
084H
FFFF0H
FFFFFH
3FFH
3FCH
AVAILABLE
INTERRUPT
POINTERS
(224)
DEDICATED
INTERRUPT
POINTERS
(5)
RESERVED
INTERRUPT
POINTERS
(27)
FIGURE 2. RESERVED MEMORY LOCATIONS
80C86
3-151
(4 + NWAIT) = TCY
T1 T2 T3 T4TWAIT T1 T2 T3 T4TWAIT
(4 + NWAIT) = TCY
GOES INACTIVE IN THE STATE
JUST PRIOR TO T4
BHE,
A19-A16 S7-S3
A15-A0 D15-D0
VALID A15-A0 DATA OUT (D15-D0)
READYREADY
WAIT WAIT
MEMORY ACCESS TIME
ADDR/
STATUS
CLK
ALE
S2-S0
ADDR/DATA
RD, INTA
READY
DT/R
DEN
WR
BHE
A19-A16 S7-S3
BUS RESERVED
FOR DATA IN
FIGURE 3. BASIC SYSTEM TIMING
80C86
3-152
External Interface
Processor RESET and Initialization
Processor initialization or star t up is accomplished with activa-
tion (HIGH) of the RESET pin. The 80C86 RESET is required to
be HIGH for greater than 4 CLK cycles. The 80C86 will termi-
nate operations on the high-going edge of RESET and will
remain dormant as long as RESET is HIGH. The low-going
transition of RESET triggers an internal reset sequence for
approximately 7 clock cycles. After this interval, the 80C86
operates normally beginning with the instruction in absolute
location FFFF0H. (See Figure 2). The RESET input is internally
synchronized to the processor clock. At initialization, the HIGH-
to-LOW transition of RESET must occur no sooner than 50µs
(or 4 CLK cycles, whichever is greater) after power-up, to allow
complete initialization of the 80C86.
NMl will not be recognized prior to the second CLK cycle follo w-
ing the end of RESET. If NMl is asserted sooner than nine clock
cycles after the end of RESET, the processor may execute one
instruction before responding to the interrupt.
Bus Hold Circuitry
To avoid high current conditions caused by floating inputs to
CMOS de vices and to eliminate need f or pull-up/down resistors ,
“bus-hold” circuitry has been used on the 80C86 pins 2-16, 26-
32 and 34-39. (See Figure 4A and Figure 4B). These circuits
will maintain the last valid logic state if no driving source is
present (i.e., an unconnected pin or a driving source which
goes to a high impedance state). To overdriv e the “bus hold” cir-
cuits, an exter nal driver must be capable of supplying approxi-
mately 400µA minimum sink or source current at valid input
voltage levels. Since this “bus hold” circuitry is active and not a
“resistive” type element, the associated power supply current is
negligible and power dissipation is significantly reduced when
compared to the use of passive pull-up resistors.
Interrupt Operations
Interrupt operations fall into two classes: software or hard-
ware initiated. The software initiated interrupts and software
aspects of hardware interrupts are specified in the Instruc-
tion Set Description. Hardware interrupts can be classified
as non-maskable or maskable.
Interrupts result in a transfer of control to a new program loca-
tion. A 256-element table containing address pointers to the
interrupt service program locations resides in absolute loca-
tions 0 through 3FFH, which are reserved for this purpose.
Each element in the table is 4 bytes in size and corresponds
to an interrupt “type”. An interr upting device supplies an 8-bit
type number during the interrupt acknowledge sequence,
which is used to “vector” through the appropriate element to
the new interrupt service program location. All flags and both
the Code Segment and Instruction Pointer register are saved
as par t of the lNTA sequence. These are restored upon exe-
cution of an Interrupt Return (IRET) instruction.
Non-Maskable Interrupt (NMI)
The processor provides a single non-maskable interr upt pin
(NMI) which has higher priority than the maskable interrupt
request pin (INTR). A typical use would be to activate a
power failure routine. The NMI is edge-triggered on a LOW-
to-HIGH transition. The activation of this pin causes a type 2
interrupt.
NMl is required to have a duration in the HIGH state of
greater than two CLK cycles, but is not required to be syn-
chronized to the clock. Any positive transition of NMI is
latched on-chip and will be serviced at the end of the current
instruction or between whole moves of a block-type instruc-
tion. Worst case response to NMI would be for multiply,
divide, and variable shift instructions. There is no specifica-
tion on the occurrence of the low-going edge; it may occur
before, during or after the ser vicing of NMI. Another positive
edge triggers another response if it occurs after the star t of
the NMI procedure. The signal must be free of logical spikes
in general and be free of bounces on the low-going edge to
avoid triggering extraneous responses.
Maskable Interrupt (INTR)
The 80C86 provides a single interrupt request input (lNTR)
which can be masked internally by software with the reset-
ting of the interrupt enable flag (IF) status bit. The interrupt
request signal is level triggered. It is internally synchronized
during each clock cycle on the high-going edge of CLK. To
be responded to, lNTR must be present (HIGH) during the
clock period preceding the end of the current instruction or
the end of a whole move for a block type instruction. lNTR
may be removed anytime after the falling edge of the first
INTA signal. Dur ing the interrupt response sequence fur ther
interrupts are disabled. The enable bit is reset as part of the
response to any interrupt (lNTR, NMI, software interrupt or
single-step), although the FLAGS register which is automati-
cally pushed onto the stack reflects the state of the proces-
sor prior to the interrupt. Until the old FLAGS register is
restored, the enable bit will be zero unless specifically set by
an instruction.
FIGURE 4A. BUS HOLD CIRCUITRY PIN 2-16, 34-39
FIGURE 4B. BUS HOLD CIRCUITRY PIN 26-32
OUTPUT
DRIVER
INPUT
BUFFER INPUT
PROTECTION
CIRCUITRY
BOND
PAD EXTERNAL
PIN
OUTPUT
DRIVER
INPUT
BUFFER INPUT
PROTECTION
CIRCUITRY
EXTERNAL
PIN
PVCC
BOND
PAD
80C86
3-153
During the response sequence (Figure 5) the processor exe-
cutes two successive (back-to-back) interrupt acknowledge
cycles. The 80C86 emits the LOCK signal (Max mode only)
from T2 of the first bus cycle until T2 of the second. A local
bus “hold” request will not be honored until the end of the
second bus cycle . In the second b us cycle, a b yte is supplied
to the 80C86 by the 82C59A Interrupt Controller, which iden-
tifies the source (type) of the interrupt. This byte is multiplied
by four and used as a pointer into the interrupt vector lookup
table . An INTR signal left HIGH will be continually responded
to within the limitations of the enable bit and sample period.
The INTERRUPT RETURN instruction includes a FLAGS
pop which returns the status of the original interrupt enable
bit when it restores the FLAGS.
Halt
When a software “HALT” instruction is executed the proces-
sor indicates that it is entering the “HALT” state in one of two
ways depending upon which mode is strapped. In minimum
mode, the processor issues one ALE with no qualifying bus
control signals. In maximum mode the processor issues
appropriate HALT status on S2, S1, S0 and the 82C88 bus
controller issues one ALE. The 80C86 will not leave the
“HALT” state when a local bus “hold” is entered while in
“HALT”. In this case, the processor reissues the HALT indi-
cator at the end of the local bus hold. An NMI or interrupt
request (when interrupts enabled) or RESET will force the
80C86 out of the “HALT” state.
Read/Modify/Write (Semaphore)
Operations Via Lock
The LOCK status information is provided by the processor
when consecutive bus cycles are required during the execution
of an instruction. This gives the processor the capability of per-
forming read/modify/write operations on memory (via the
Exchange Register With Memory instruction, f or e xample) with-
out another system bus master receiving intervening memory
cycles. This is useful in multiprocessor system configur ations to
accomplish “test and set lock” operations. The LOCK signal is
activated (forced LOW) in the clock cycle following decoding of
the software “LOCK” prefix instruction. It is deactivated at the
end of the last bus cycle of the instruction follo wing the “LOCK”
prefix instruction. While LOCK is active a request on a RQ/GT
pin will be recorded and then honored at the end of the LOCK.
External Synchronization Via TEST
As an alternative to interrupts, the 80C86 provides a single
software-testable input pin (TEST). This input is utilized by
executing a WAIT instr uction. The single WAIT instruction is
repeatedly e xecuted until the TEST input goes active (LO W).
The execution of WAIT does not consume bus cycles once
the queue is full.
If a local bus request occurs during WAIT execution, the
80C86 three-states all output drivers while inputs and I/O
pins are held at valid logic levels b y internal bus-hold circuits.
If interrupts are enabled, the 80C86 will recognize interrupts
and process them when it regains control of the bus. The
WAIT instruction is then refetched, and re-executed.
TABLE 4. 80C86 REGISTER
Basic System Timing
Typical system configurations for the processor operating in
minimum mode and in maximum mode are shown in Figures
6A and 6B, respectively. In minimum mode, the MN/MX pin
is strapped to VCC and the processor emits bus control sig-
nals (e.g. RD, WR, etc.) directly. In maximum mode, the
MN/MX pin is strapped to GND and the processor emits
coded status information which the 82C88 bus controller
uses to generate MULTIBUS compatible bus control signals.
Figure 3 shows the signal timing relationships.
System Timing - Minimum System
The read cycle begins in T1 with the assertion of the
Address Latch Enable (ALE) signal. The trailing (low-going)
edge of this signal is used to latch the address information,
which is valid on the address/data bus (AD0-AD15) at this
time, into the 82C82/82C83 latch. The BHE and A0 signals
address the low, high or both bytes. From T1 to T4 the M/lO
signal indicates a memory or I/O operation. At T2, the
address is removed from the address/data bus and the bus
is held at the last valid logic state by internal bus hold
ALE
LOCK
INTA
AD0- FLOAT TYPE
AD15
T1 T2 T3 T4 TI T1 T2 T3 T4
VECTOR
FIGURE 5. INTERRUPT ACKNOWLEDGE SEQUENCE
AH AL
BH
CH
DH
BL
CL
DL
SP
BP
SI
DI
IP
FLAGSHFLAGSL
CS
DS
SS
ES
AX
BX
CX
DX
ACCUMULATOR
BASE
COUNT
DATA
STACK POINTER
BASE POINTER
SOURCE INDEX
DESTINATION INDEX
INSTRUCTION POINTER
STATUS FLAG
CODE SEGMENT
DATA SEGMENT
STACK SEGMENT
EXTRA SEGMENT
80C86
3-154
devices. The read control signal is also asser ted at T2. The
read (RD) signal causes the addressed device to enable its
data bus drivers to the local bus. Some time later, valid data
will be available on the bus and the addressed device will
drive the READY line HIGH.When the processor returns the
read signal to a HIGH level, the addressed device will again
three-state its bus drivers. If a transceiver (82C86/82C87) is
required to buffer the 80C86 local bus, signals DT/R and
DEN are provided by the 80C86.
A write cycle also begins with the asser tion of ALE and the
emission of the address. The M/IO signal is again asserted
to indicate a memory or I/O write operation. In T2, immedi-
ately following the address emission, the processor emits
the data to be written into the addressed location. This data
remains valid until at least the middle of T4. During T2, T3
and TW, the processor asser ts the write control signal. The
write (WR) signal becomes active at the beginning of T2 as
opposed to the read which is delayed somewhat into T2 to
provide time for output drivers to become inactive.
The BHE and A0 signals are used to select the proper
byte(s) of the memor y/lO word to be read or written accord-
ing to Table 5.
I/O ports are addressed in the same manner as memory
location. Even addressed b ytes are tr ansf erred on the D7-D0
bus lines and odd address bytes on D15-D8.
The basic difference between the interrupt acknowledge
cycle and a read cycle is that the interrupt acknowledge sig-
nal (INTA) is asserted in place of the read (RD) signal and
the address bus is held at the last v alid logic state b y internal
bus hold devices. (See Figure 4). In the second of two suc-
cessive INTA cycles a byte of information is read from the
data bus (D7-D0) as supplied by the interrupt system logic
(i.e., 82C59A Priority Interrupt Controller). This byte identi-
fies the source (type) of the interrupt. It is multiplied by four
and used as a pointer into an interrupt vector lookup table,
as described earlier.
Bus Timing - Medium Size Systems
For medium complexity systems the MN/MX pin is con-
nected to GND and the 82C88 Bus Controller is added to the
system as well as an 82C82/82C83 latch for latching the
system address, and an 82C86/82C87 transceiver to allow
for bus loading greater than the 80C86 is capable of han-
dling. Signals ALE, DEN, and DT/R are generated by the
82C88 instead of the processor in this configuration,
although their timing remains relatively the same. The
80C86 status outputs (S2, S1 and S0) provide type-of-cycle
information and become 82C88 inputs. This bus cycle infor-
mation specifies read (code, data or I/O), write (data or I/O),
interrupt acknowledge, or software halt. The 82C88 issues
control signals specifying memor y read or write, I/O read or
write, or interrupt acknowledge. The 82C88 provides two
types of write strobes, normal and advanced, to be applied
as required. The normal wr ite strobes have data valid at the
leading edge of write. The advanced write strobes have the
same timing as read strobes, and hence, data is not valid at
the leading edge of write. The 82C86/82C87 transceiver
receives the usual T and OE inputs from the 82C88 DT/R
and DEN signals.
The pointer into the interrupt vector table, which is passed
during the second INTA cycle, can be derived from an
82C59A located on either the local bus or the system bus. If
the master 82C59A Prior ity Interrupt Controller is positioned
on the local bus, the 82C86/82C87 transceiver must be dis-
abled when reading from the master 82C59A during the
interrupt acknowledge sequence and software “poll”.
TABLE 5.
BHE A0 CHARACTERISTICS
0 0 Whole word
0 1 Upper Byte From/To Odd Address
1 0 Lower Byte From/To Even Address
1 1 None
80C86
3-155
FIGURE 6A. MINIMUM MODE 80C86 TYPICAL CONFIGURATION
FIGURE 6B. MAXIMUM MODE 80C86 TYPICAL CONFIGURATION
GND
82C8A/85
CLOCK
BHE
A16-A19
AD0-AD15
ALE
80C86
CPU
DT/R
WR
RD
MN/MX
RESET
READY
CLK
VCC C1
C2
GND
GND
1
20
40
C1 = C2 = 0.1µF
VCC
VCC
STB
OE
82C82
T
OE82C86
TRANSCEIVER
(2) BHE
ADDR
DATA
A0
E G
HM-6616
CMOS PROM (2)
2K x 8 2K x 8
CS RDWR
CMOS
82CXX
PERIPHERALS
HM-6516
CMOS RAM
2K x 8
W G
GND
VCC
WAIT
STATE
GENERATOR
GENERATOR
RES RDY
M/IO
INTA
DEN
LATCH
2 OR 3
EHEL
2K x 8
ADDR/DATA
OPTIONAL
FOR INCREASED
DATA BUS DRIVE
GND
82C84A/85
CLOCK
GENERATOR/
BHE
A16-A19
AD0-AD15
LOCK
80C86
CPU
S2
S1
S0
MN/MX
RESET
READY
CLK
VCC C1
C2
GND
GND
1
20
40
C1 = C2 = 0.1µF
GND
VCC
CLK
S0
S1
S2
DEN
DT/R
ALE
MRDC
MWTC
AMWC
IORC
IOWC
AIOWC
INTA
82C88
BUS
CTRLR
STB
OE
82C82
(2 OR 3)
T
OE82C86
TRANSCEIVER
(2) BHE
NC
NC
ADDR
DATA
A0
E G
HM-6616
CMOS PROM (2)
2K x 8 2K x 8
CS RDWR
CMOS
82CXX
PERIPHERALS
HM-65162
CMOS RAM
2K x 8
EH
GND
VCC
NC
ADDR/DATA
WAIT
STATE
GENERATOR
ELW G
2K x 8
RES RDY
80C86
3-156
Absolute Maximum Ratings Thermal Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+8.0V
Input, Output or I/O Voltage . . . . . . . . . . . .GND -0.5V to VCC +0.5V
Storage Temperature Range . . . . . . . . . . . . . . . . . -65oC to +150oC
Junction Temperature
Ceramic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
Plastic Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150oC
Lead Temperature (Soldering 10s). . . . . . . . . . . . . . . . . . . . +300oC
(Lead tips only for surface mount packages)
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Resistance (Typical, Note 1) θJA (oC/W) θJC (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . 50 N/A
PLCC Package . . . . . . . . . . . . . . . . . . 46 N/A
SBDIP Package. . . . . . . . . . . . . . . . . . 30 6
CLCC Package . . . . . . . . . . . . . . . . . . 40 6
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9750 Gates
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause per manent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Operating Conditions
Operating Supply Voltage. . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
M80C86-2 ONLY. . . . . . . . . . . . . . . . . . . . . . . . +4.75V to +5.25V Operating Temperature Range: C80C86/-2 . . . . . . . . 0oC to +70oC
I80C86/-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40oC to +85oC
M80C86/-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55oC to +125oC
DC Electrical Specifications VCC = 5.0V, ±10%; TA = 0oC to +70oC (C80C86, C80C86-2)
VCC = 5.0V, ±10%; TA = -40oC to +85oC (l80C86, I80C86-2)
VCC = 5.0V, ±10%; TA = -55oC to +125oC (M80C86)
VCC = 5.0V, ±5%; TA = -55oC to +125oC (M80C86-2)
SYMBOL PARAMETER MIN MAX UNITS TEST CONDITION
VlH Logical One
Input Voltage 2.0
2.2 V
VC80C86, I80C86 (Note 5)
M80C86 (Note 5)
VIL Logical Zero Input Voltage 0.8 V
VIHC CLK Logical One Input Voltage VCC -0.8 V
VILC CLK Logical Zero Input Voltage 0.8 V
VOH Output High Voltage 3.0
VCC -0.4 V
VlOH = -2.5mA
lOH = -100µA
VOL Output Low Voltage 0.4 V lOL = +2.5mA
IIInput Leakage Current -1.0 1.0 µAV
IN = GND or VCC DIP
Pins 17-19, 21-23, 33
lBHH Input Current-Bus Hold High -40 -400 µAV
IN = - 3.0V (Note 1)
lBHL Input Current-Bus Hold Low 40 400 µAV
IN = - 0.8V (Note 2)
IOOutput Leakage Current - -10.0 µAV
OUT = GND (Note 4)
ICCSB Standby Power Supply Current - 500 µAV
CC = - 5.5V (Note 3)
ICCOP Operating Power Supply Current - 10 mA/MHz FREQ = Max, VIN = VCC or GND,
Outputs Open
Capacitance TA = 25oC
SYMBOL PARAMETER TYPICAL UNITS TEST CONDITIONS
CIN Input Capacitance 25 pF FREQ = 1MHz. All measurements are referenced to device GND
COUT Output Capacitance 25 pF FREQ = 1MHz. All measurements are referenced to device GND
CI/O I/O Capacitance 25 pF FREQ = 1MHz. All measurements are referenced to device GND
NOTES:
2. lBHH should be measured after raising VIN to VCC and then lowering to 3.0V on the following pins 2-16, 26-32, 34-39.
3. IBHL should be measured after lowering VIN to GND and then raising to 0.8V on the following pins: 2-16, 34-39.
4. lCCSB tested during clock high time after halt instruction executed. VIN = VCC or GND, VCC = 5.5V, Outputs unloaded.
5. IO should be measured by putting the pin in a high impedance state and then driving VOUT to GND on the following pins: 26-29 and 32.
6. MN/MX is a strap option and should be held to VCC or GND.
80C86
3-157
AC Electrical Specifications VCC = 5.0V ±10%; TA = 0oC to +70oC (C80C86, C80C86-2)
VCC = 5.0V ±100%; TA = -40oC to +85oC (I80C86, I80C86-2)
VCC = 5.0V ±100%; TA = -55oC to +125oC (M80C86)
VCC = 5.0V ±5%; TA = -55oC to +125oC (M80C86-2)
MINIMUM COMPLEXITY SYSTEM
SYMBOL PARAMETER
80C86 80C86-2
UNITS TEST
CONDITIONSMIN MAX MIN MAX
TIMING REQUIREMENTS
(1) TCLCL Cycle Period 200 125 ns
(2) TCLCH CLK Low Time 118 68 ns
(3) TCHCL CLK High Time 69 44 ns
(4) TCH1CH2 CLK Rise Time 10 10 ns From 1.0V to 3.5V
(5) TCL2C1 CLK FaIl Time 10 10 ns F rom 3.5V to 1.0V
(6) TDVCL Data In Setup Time 30 20 ns
(7) TCLDX1 Data In Hold Time 10 10 ns
(8) TR1VCL RDY Setup Time into 82C84A
(Notes 7, 8) 35 35 ns
(9) TCLR1X RDY Hold Time into 82C84A
(Notes 7, 8) 00ns
(10) TRYHCH READY Setup Time into 80C86 118 68 ns
(11) TCHRYX READY Hold Time into 80C86 30 20 ns
(12) TRYLCL READY Inactive to CLK (Note 9) -8 -8 ns
(13) THVCH HOLD Setup Time 35 20 ns
(14) TINVCH lNTR, NMI, TEST Setup Time
(Note 8) 30 15 ns
(15) TILIH Input Rise Time (Except CLK) 15 15 ns From 0.8V to 2.0V
(16) TIHIL Input FaIl Time (Except CLK) 15 15 ns From 2.0V to 0.8V
TIMING RESPONSES
(17) TCLAV Address Valid Delay 10 110 10 60 ns CL = 100pF
(18) TCLAX Address Hold Time 10 10 ns CL = 100pF
(19) TCLAZ Address Float Delay TCLAX 80 TCLAX 50 ns CL = 100pF
(20) TCHSZ Status Float Delay 80 50 ns CL = 100pF
(21) TCHSV Status Active Delay 10 110 10 60 ns CL = 100pF
(22) TLHLL ALE Width TCLCH-20 TCLCH-10 ns CL = 100pF
(23) TCLLH ALE Active Delay 80 50 ns CL = 100pF
(24) TCHLL ALE Inactive Delay 85 55 ns CL = 100pF
80C86
3-158
(25) TLLAX Address Hold Time to ALE Inactive TCHCL-10 TCHCL-10 ns CL = 100pF
(26) TCLDV Data Valid Delay 10 110 10 60 ns CL = 100pF
(27) TCLDX2 Data Hold Time 10 10 ns CL = 100pF
(28) TWHDX Data Hold Time After WR TCLCL-30 TCLCL-30 ns CL = 100pF
(29) TCVCTV Control Active Delay 1 10 110 10 70 ns CL = 100pF
(30) TCHCTV Control Active Delay 2 10 110 10 60 ns CL = 100pF
(31) TCVCTX Control Inactive Delay 10 110 10 70 ns CL = 100pF
(32) TAZRL Address Float to READ Active 0 0 ns CL = 100pF
(33) TCLRL RD Active Delay 10 165 10 100 ns CL = 100pF
(34) TCLRH RD Inactive Delay 10 150 10 80 ns CL = 100pF
(35) TRHAV RD Inactive to Next Address Active TCLCL-45 TCLCL-40 ns CL = 100pF
(36) TCLHAV HLDA Valid Delay 10 160 10 100 ns CL = 100pF
(37) TRLRH RD Width 2TCLCL-75 2TCLCL-50 ns CL = 100pF
(38) TWLWH WR Width 2TCLCL-60 2TCLCL-40 ns CL = 100pF
(39) TAVAL Address Valid to ALE Low TCLCH-60 TCLCH-40 ns CL = 100pF
(40) TOLOH Output Rise Time 20 15 ns F rom 0.8V to 2.0V
(41) TOHOL Output Fall Time 20 15 ns F rom 2.0V to 0.8V
NOTES:
7. Signal at 82C84A shown for reference only.
8. Setup requirement for asynchronous signal only to guarantee recognition at next CLK.
9. Applies only to T2 state (8ns into T3).
AC Electrical Specifications VCC = 5.0V ±10%; TA = 0oC to +70oC (C80C86, C80C86-2)
VCC = 5.0V ±100%; TA = -40oC to +85oC (I80C86, I80C86-2)
VCC = 5.0V ±100%; TA = -55oC to +125oC (M80C86)
VCC = 5.0V ±5%; TA = -55oC to +125oC (M80C86-2) (Continued)
MINIMUM COMPLEXITY SYSTEM
SYMBOL PARAMETER
80C86 80C86-2
UNITS TEST
CONDITIONSMIN MAX MIN MAX
80C86
3-159
Waveforms
FIGURE 7A. BUS TIMING - MINIMUM MODE SYSTEM
NO TE: Signals at 82C84A are shown f or reference only. RDY is sampled near the end of T2, T3, TW to determine if TW machine states are
to be inserted.
TCVCTX
(31)
(29) TCVCTV
DEN
DT/R
(30)
TCHCTV TCLRL
(33)
(30)
TCHCTV
READ CYCLE
(35)
(34) TCLRH
RD
DATA IN
(7)
TCLDX1
(10)
TRYHCH
AD15-AD0
(24)
(17)
TCLAV
READY (80C86 INPUT)
RDY (82C84A INPUT)
SEE NOTE
ALE
BHE/S7, A19/S6-A16/S3
(17)
TCLAV
M/IO
(30) TCHCTV
CLK (82C84A OUTPUT)
(3) TCHCL
TCH1CH2
(4)
(2)
TCLCH TCHCTV
(30)
(5)
TCL2CL1
T1 T2 T3
TW
T4
(WR, INTA = VOH)
(1)
TCLCL
(26) TCLDV
(18) TCLAX
BHE, A19-A16
(23) TCLLH TLHLL
(22) TLLAX
(25)
TCHLL
TAVAL
(39) VIL
VIH
(12)
TRYLCL
(11)
TCHRYX
(19)
TCLAZ (16)
TDVCL
AD15-AD0
TRHAV
(32) TAZRL
TRLRH
(37)
TCLR1X (9)
TR1VCL (8)
S7-S3
80C86
3-160
FIGURE 7B. BUS TIMING - MINIMUM MODE SYSTEM
NOTE: Two INTA cycles run bac k-to-back. The 80C86 local ADDR/DATA bus is floating during both INTA cycles. Control signals are shown
for the second INTA cycle.
Waveforms
(Continued)
T4T3T2T1
TW
TDVCL TCLDX1 (7)
TWHDX
TCVCTX
TCHCTV (30)
TCLAV
TCLAZ
TCHCTV
(31) TCVCTX
TCVCTV
(17) (26) (27)
(29) TCVCTV
DATA OUT
AD15-AD0
INVALID ADDRESS
CLK (82C84A OUTPUT)
WRITE CYCLE
(RD, INTA,
DT/R = VOH)
AD15-AD0
DEN
WR
INTA CYCLE
(SEE NOTE)
(RD, WR = VOH
BHE = VOL)
AD15-AD0
DT/R
INTA
DEN
AD15-AD0
SOFTWARE
HALT -
DEN, RD,
WR, INTA = VOH
DT/R = INDETERMINATE
SOFTWARE HALT
(29) TCVCTV
POINTER
TCL2CL1
(5)
TW
TCLAV TCLDV
TCLAX (18) TCLDX2
(29) (28)
TWLWH
(38)
(29) TCVCTV
(19) TCVCTX (31)
(6)
(30)
(31)
(17)
TCH1CH2
(4)
80C86
3-161
AC Electrical Specifications VCC = 5.0V ±10% TA = 0oC to +70oC (C80C86, C80C86-2)
VCC = 5.0V ±10%; TA = -40oC to +85oC (I80C86, I80C86-2)
VCC = 5.0V ±10%; TA = -55oC to +125oC (M80C86)
VCC = 5.0V ±5%; TA = -55oC to +125oC (M80C86-2)
MAX MODE SYSTEM (USING 82C88 BUS CONTROLLER)
TIMING REQUIREMENTS 80C86 80C86-2
UNITS TEST CONDITIONSSYMBOL PARAMETER MIN MAX MIN MAX
(1) TCLCL CLK Cycle Period 200 125 ns
(2) TCLCH CLK Low Time 118 68 ns
(3) TCHCL CLK High Time 69 44 ns
(4) TCH1CH2 CLK Rise Time 10 10 ns From 1.0V to 3.5V
(5) TCL2CL1 CLK Fall Time 10 10 ns From 3.5V to 1.0V
(6) TDVCL Data in Setup Time 30 20 ns
(7) TCLDX1 Data In Hold Time 10 10 ns
(8) TR1VCL RDY Setup Time into 82C84A
(Notes 10, 11) 35 35 ns
(9) TCLR1X RDY Hold Time into 82C84A
(Notes 10, 11) 00ns
(10) TRYHCH READY Setup Time into 80C86 118 68 ns
(11) TCHRYX READY Hold Time into 80C86 30 20 ns
(12) TRYLCL READY Inactive to CLK (Note 12) -8 -8 ns
(13) TlNVCH Setup Time for Recognition (lNTR,
NMl, TEST) (Note 11) 30 15 ns
(14) TGVCH RQ/GT Setup Time 30 15 ns
(15) TCHGX RQ Hold Time into 80C86 (Note 13) 40 TCHCL+
10 30 TCHCL+
10 ns
(16) TILlH Input Rise Time (Except CLK) 15 15 ns From 0.8V to 2.0V
(17) TIHIL Input Fall Time (Except CLK) 15 15 ns From 2.0V to 0.8V
TIMING RESPONSES
(18) TCLML Command Active Delay (Note 10) 5 35 5 35 ns CL = 100pF for All
80C86 Outputs (In
Addition to 80C86
Self Load)
(19) TCLMH Command Inactive (Note 10) 5 35 5 35 ns CL = 100pF for All
80C86 Outputs (In
Addition to 80C86
Self Load)
(20) TRYHSH READY Active to Status Passive
(Notes 12, 14) 110 65 ns CL = 100pF for All
80C86 Outputs (In
Addition to 80C86
Self Load)
(21) TCHSV Status Active Delay 10 110 10 60 ns CL = 100pF for All
80C86 Outputs (In
Addition to 80C86
Self Load)
(22) TCLSH Status Inactive Delay (Note 14) 10 130 10 70 ns CL = 100pF for All
80C86 Outputs (In
Addition to 80C86
Self Load)
80C86
3-162
(23) TCLAV Address Valid Delay 10 110 10 60 ns CL = 100pF for All
80C86 Outputs (In
Addition to 80C86
Self Load)
(24) TCLAX Address Hold Time 10 10 ns CL = 100pF for All
80C86 Outputs (In
Addition to 80C86
Self Load)
(25) TCLAZ Address Float Delay TCLAX 80 TCLAX 50 ns CL = 100pF for All
80C86 Outputs (In
Addition to 80C86
Self Load)
(26) TCHSZ Status Float Delay 80 50 ns CL = 100pF for All
80C86 Outputs (In
Addition to 80C86
Self Load)
(27) TSVLH Status Valid to ALE High (Note 10) 20 20 ns CL = 100pF for All
80C86 Outputs (In
Addition to 80C86
Self Load)
(28) TSVMCH Status Valid to MCE High (Note 10) 30 30 ns CL = 100pF for All
80C86 Outputs (In
Addition to 80C86
Self Load)
(29) TCLLH CLK low to ALE Valid (Note 10) 20 20 ns CL = 100pF for All
80C86 Outputs (In
Addition to 80C86
Self Load)
(30) TCLMCH CLK low to MCE High (Note 10) 25 25 ns CL = 100pF for All
80C86 Outputs (In
Addition to 80C86
Self Load)
(31) TCHLL ALE Inactive Delay (Note 10) 4 18 4 18 ns CL = 100pF for All
80C86 Outputs (In
Addition to 80C86
Self Load)
(32) TCLMCL MCE Inactive Delay (Note 10) 15 15 ns CL = 100pF for All
80C86 Outputs (In
Addition to 80C86
Self Load)
(33) TCLDV Data Valid Delay 10 110 10 60 ns CL = 100pF for All
80C86 Outputs (In
Addition to 80C86
Self Load)
(34) TCLDX2 Data Hold Time 10 10 ns CL = 100pF for All
80C86 Outputs (In
Addition to 80C86
Self Load)
AC Electrical Specifications VCC = 5.0V ±10% TA = 0oC to +70oC (C80C86, C80C86-2)
VCC = 5.0V ±10%; TA = -40oC to +85oC (I80C86, I80C86-2)
VCC = 5.0V ±10%; TA = -55oC to +125oC (M80C86)
VCC = 5.0V ±5%; TA = -55oC to +125oC (M80C86-2) (Continued)
MAX MODE SYSTEM (USING 82C88 BUS CONTROLLER)
TIMING REQUIREMENTS 80C86 80C86-2
UNITS TEST CONDITIONSSYMBOL PARAMETER MIN MAX MIN MAX
80C86
3-163
(35) TCVNV Control Active Delay (Note 10) 5 45 5 45 ns CL = 100pF for All
80C86 Outputs (In
Addition to 80C86
Self Load)
(36) TCVNX Control Inactive Delay (Note 10) 10 45 10 45 ns CL = 100pF
(37) TAZRL Address Float to Read Active 0 0 ns CL = 100pF
(38) TCLRL RD Active Delay 10 165 10 100 ns CL = 100pF
(39) TCLRH RD Inactive Delay 10 150 10 80 ns CL = 100pF
(40) TRHAV RD Inactive to Next Address Active TCLCL
-45 TCLCL
-40 ns CL = 100pF
(41) TCHDTL Direction Control Active Delay
(Note 10) 50 50 ns CL = 100pF
(42) TCHDTH Direction Control Inactive Delay
(Note 10) 30 30 ns CL = 100pF
(43) TCLGL GT Active Delay 10 85 0 50 ns CL = 100pF
(44) TCLGH GT Inactive Delay 10 85 0 50 ns CL = 100pF
(45) TRLRH RD Width 2TCLC
L -75 2TCLC
L -50 ns CL = 100pF
(46) TOLOH Output Rise Time 20 15 ns From 0.8V to 2.0V
(47) TOHOL Output Fall Time 20 15 ns From 2.0V to 0.8V
NOTES:
10. Signal at 82C84A or 82C88 shown for reference only.
11. Setup requirement for asynchronous signal only to guarantee recognition at next CLK.
12. Applies only to T2 state (8ns into T3).
13. The 80C86 actively pulls the RQ/GT pin to a logic one on the following clock low time.
14. Status lines return to their inactive (logic one) state after CLK goes low and READY goes high.
AC Electrical Specifications VCC = 5.0V ±10% TA = 0oC to +70oC (C80C86, C80C86-2)
VCC = 5.0V ±10%; TA = -40oC to +85oC (I80C86, I80C86-2)
VCC = 5.0V ±10%; TA = -55oC to +125oC (M80C86)
VCC = 5.0V ±5%; TA = -55oC to +125oC (M80C86-2) (Continued)
MAX MODE SYSTEM (USING 82C88 BUS CONTROLLER)
TIMING REQUIREMENTS 80C86 80C86-2
UNITS TEST CONDITIONSSYMBOL PARAMETER MIN MAX MIN MAX
80C86
3-164
Waveforms
FIGURE 8A. BUS TIMING - MAXIMUM MODE (USING 82C88)
NOTES:
15. Signals at 82C84A or 82C88 are shown for reference only. RDY is sampled near the end of T2, T3, TW to determine if TW machine states
are to be inserted.
16. The issuance of the 82C88 command and control signals (MRDC, MWTC, AMWC, IORC, IOWC,AIOWC,INTA, and DEN) lags the active
high 82C88 CEN.
17. Status inactive in state just prior to T4.
T1T2T3T4
TCLCL
TCH1CH2
TCL2CL1 TW
TCHCL (3)
(21) TCHSV
(SEE NOTE 17)
TCLDV
TCLAX
(23) TCLAV TCLAV
BHE, A19-A16
TSVLH
TCLLH
TR1VCL
TCHLL
TCLR1X
TCLAV TDVCL TCLDX1
TCLAX
AD15-AD0 DATA IN
TRYHSH
(39) TCLRH TRHAV
(41) TCHDTL
TCLRL TRLRH TCHDTH
(37) TAZRL
TCLML TCLMH
(35) TCVNV
TCVNX
CLK
QS0, QS1
S2, S1, S0 (EXCEPT HALT)
BHE/S7, A19/S6-A16/S3
ALE (82C88 OUTPUT)
RDY (82C84 INPUT)
NOTE
READY 80C86 INPUT)
READ CYCLE
82C88
OUTPUTS
SEE NOTES
15, 16
MRDC OR IORC
DEN
S7-S3
AD15-AD0
RD
DT/R
TCLAV
(1)
(4)
(23) TCLCH
(2)
TCLSH (22)
(24) (23)
(27)
(29)
(31)
(8)
(9)
TCHRYX
(11)
(20)
(12) TRYLCL
(24)
TRYHCH (10)
(6) (7)
(23)
(40)
(42)
(45)
(38)
(18) (19)
(36)
(33)
TCLAZ
(25)
(5)
80C86
3-165
FIGURE 8B. BUS TIMING - MAXIMUM MODE (USING 82C88)
NOTES:
18. Signals at 82C84A or 82C86 are shown for reference only.
19. The issuance of the 82C88 command and control signals (MRDC, MWTC, AMWC, IORC, IOWC,AIO WC, INTA and DEN) lags the active
high 82C88 CEN.
20. Status inactive in state just prior to T4.
21. Cascade address is valid between first and second INTA cycles.
22. Two INTA cycles run back-to-back. The 80C86 local ADDR/DATA bus is floating during both INTA cycles. Control for pointer address is
shown for second INTA cycle.
Waveforms
(Continued)
T1 T2 T3 T4
TW
TCLSH
(SEE NOTE 20))
TCLDX2
TCLDV
TCLAX
TCLMH
(18) TCLML
TCHDTH
(19) TCLMH
TCVNX
TCLAV
TCHSV TCLSH
CLK
S2, S1, S0 (EXCEPT HALT)
WRITE CYCLE
AD15-AD0
DEN
AMWC OR AIOWC
MWTC OR IOWC
82C88
OUTPUTS
SEE NOTES
18, 19
INTA CYCLE
AD15-AD0
(SEE NOTES 21, 22)
AD15-AD0
MCE/PDEN
DT/R
INTA
DEN
82C88 OUTPUTS
SEE NOTES 18, 19
RESERVED FOR
CASCADE ADDR
(25) TCLAZ
(30) TCLMCH
TCVNV
SOFTWARE
HALT - RD, MRDC, IORC, MWTC, AMWC, IOWC, AIOWC, INTA, S0, S1 = VOH
(18) TCLML
TCLMH (19)
TCLDX1 (7)
(18)TCLML
POINTER
INVALID ADDRESS
AD15-AD0
S2
TCHDTL
TCHSV (21)
(34)
(22)
(33)
(24)
DATA
TCVNX (36)
(19)
(6) TDVCL
TCLMCL (32)
(41)
(42)
(35)
(36)
(23)
(21) (22)
TCLAV
(23)
TCVNV
(35)
(28) TSVMCH
80C86
3-166
NOTE: The coprocessor may not drive the busses outside the region shown without risking contention.
FIGURE 9. REQUEST/GRANT SEQUENCE TIMING (MAXIMUM MODE ONLY)
FIGURE 10. HOLD/HOLD ACKNOWLEDGE TIMING (MINIMUM MODE ONLY)
NOTE: Setup requirements for asynchronous signals only to guar-
antee recognition at next CLK.
FIGURE 11. ASYNCHRONOUS SIGNAL RECOGNITION FIGURE 12. BUS LOCK SIGNAL TIMING (MAXIMUM MODE
ONLY)
Waveforms
(Continued)
CLK
TCLGH
RQ/GT
PREVIOUS GRANT
AD15-AD0
RD, LOCK
BHE/S7, A19/S0-A16/S3
S2, S1, S0
TCLCL
ANY
CLK
CYCLE
>0-CLK
CYCLES
PULSE 2
80C86
TGVCH (14)
TCHGX (15) TCLGH (44)
PULSE 1
COPROCESSOR
RQ TCLAZ (25)
80C86 GT
PULSE 3
COPROCESSOR
RELEASE
(SEE NOTE)TCHSZ (26)
(1) TCLGL
(43)
COPROCESSOR
TCHSV (21)
(44)
CLK
HOLD
HLDA
AD15-AD0
BHE/S7, A19/S6-A16/S3
RD, WR, M/IO, DT/R, DEN
80C86
THVCH (13)
TCLHAV (36)
≥1CLK 1 OR 2
CYCLES
TCLAZ (19)
COPROCESSOR 80C86
TCLHAV (36)
CYCLE
TCHSZ (20)
THVCH (13)
TCHSV (21)
NMI
INTR
TEST
CLK
SIGNAL
TINVCH (SEE NOTE)
(13)
ANY CLK CYCLE
CLK
LOCK
TCLAV
ANY CLK CYCLE
(23) TCLAV
(23)
80C86
3-167
FIGURE 13. RESET TIMING
Waveforms
(Continued)
VCC
CLK
RESET
≥50µs
≥4 CLK CYCLES
(7) TCLDX1
(6) TDVCL
AC Test Circuit
NOTE: Includes stay and jig capacitance.
AC Testing Input, Output Waveform
NO TE: A C Testing: All input signals (other than CLK) must switch between VILMAX -50% VIL and VIHMIN +20% VIH. CLK m ust switch between
0.4V and VCC.-0.4 Input rise and fall times are driven at 1ns/V.
OUTPUT FROM
DEVICE UNDER TEST TEST POINT
CL (SEE NOTE)
INPUT
VIH + 20% VIH
VIL - 50% VIL
OUTPUT
VOH
VOL
1.5V 1.5V
80C86
3-168
Burn-In Circuits
MD80C86 CERDIP
NOTES:
VCC = 5.5V ±0.5V, GND = 0V.
Input voltage limits (except clock):
VIL (maximum) = 0.4V
VIH (minimum) = 2.6V, VIH (clock) = (VCC -0.4V) minimum.
VCC/2 is external supply set to 2.7V ±10%.
VCL is generated on program card (VCC - 0.65V).
Pins 13 - 16 input sequenced instructions from internal hold de vices.
F0 = 100kHz ±10%.
Node = a 40µs pulse every 2.56ms.
COMPONENTS:
1. RI = 10kΩ±5%, 1/4W
2. RO = 1.2kΩ±5%, 1/4W
3. RIO = 2.7kΩ±5%, 1/4W
4. RC = 1kΩ±5%, 1/4W
5. C = 0.01µF (Minimum)
33
34
35
36
37
38
40
32
31
30
29
24
25
26
27
28
21
22
23
13
2
3
4
5
6
7
8
9
10
11
12
14
15
16
17
18
19
20
39
GND
GND
NMI
INTR
CLK
GND
1
RIO
RIO
RIO
RIO
RIO
RIO
RIO
RIO
RIO
RIO
RIO
RC
RI
RI
VCC/2
VCL
VCL
VCC/2
GND
VCC/2
VCC/2
RI
VCC/2
VCC/2
VCC/2
VCL
VCC
GND
RIO
RO
RO
RO
VCC/2
VCC/2
VCC/2
VCC/2
VCC/2
GND
VCL
NODE
FROM
PROGRAM
CARD
GND
GND
VCL
GND
GND
VCL
GND
GND
GND
VCL
VCL
VCL
OPEN
OPEN
OPEN
OPEN
GND
GND
F0
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
A
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
VCC
QS2
TEST
READY
RESET
AD15
AD16
AD17
AD18
AD19
BHE
MX
RD
RQ0
RQ1
LOCK
S2
S1
S0
QS0
C
A
80C86
3-169
MR80C86 CLCC
NOTES:
VCC = 5.5V ±0.5V, GND = 0V.
Input voltage limits (except clock):
VIL (maximum) = 0.4V
VIH (minimum) = 2.6V, VIH (clock) = (VCC -0.4V) minimum.
VCC/2 is external supply set to 2.7V ±10%.
VCL is generated on program card (VCC - 0.65V).
Pins 13 - 16 input sequenced instructions from internal hold de vices.
F0 = 100kHz ±10%.
Node = a 40µs pulse every 2.56ms.
COMPONENTS:
1. RI = 10kΩ±5%, 1/4W
2. RO = 1.2kΩ±5%, 1/4W
3. RIO = 2.7kΩ±5%, 1/4W
4. RC = 1kΩ±5%, 1/4W
5. C = 0.01µF (Minimum)
Burn-In Circuits
(Continued)
14
13
12
11
10
9
8
7
17
16
15
25
30
35
39
38
37
36
33
34
32
31
29
4
6 3 140414243
44
2827262524232221201918
RIO
RIO
RIO
RIO
RIO
RIO
RIO
RIO
RIO
RIO
RIO
RO
RO
RO
RO
RO
RO
RI
RI
RO
RO
RO
RO
RC
RI
RI
RO
RO
RIO
VCC
VCL
VCC/2
C
F0(FROM PROGRAM CARD)A
GND
A
80C86
3-170
Metallization Topology
DIE DIMENSIONS:
249.2 x 290.9 x 19
METALLIZATION:
Type: Silicon - Aluminum
Thickness: 11kű2kÅ
GLASSIVATION:
Type: Nitrox
Thickness: 10kű2kÅ
WORST CASE CURRENT DENSITY:
1.5 x 105 A/cm2
Metallization Mask Layout
80C86
AD11 AD12 AD13 AD14 A17/S4 A18/S5GND A16/S3VCC AD15
A19/S6
BHE/S7
MN/MX
RD
RQ/GT0
RQ/GT1
LOCK
S2
S1
S0
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
NMI INTR CLK GND RESET READY TEST QS1 QS0
80C86
3-171
Instruction Set Summary
MNEMONIC AND DESCRIPTION
INSTRUCTION CODE
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
DATA TRANSFER
MOV = MOVE:
Register/Memory to/from Register 1 0 0 0 1 0 d w mod reg r/m
Immediate to Register/Memory 1 1 0 0 0 1 1 w mod 0 0 0 r/m data data if w 1
Immediate to Register 1 0 1 1 w reg data data if w 1
Memory to Accumulator 1 0 1 0 0 0 0 w addr-low addr-high
Accumulator to Memory 1 0 1 0 0 0 1 w addr-low addr-high
Register/Memory to Segment Register †† 1 0 0 0 1 1 1 0 mod 0 reg r/m
Segment Register to Register/Memory 1 0 0 0 1 1 0 0 mod 0 reg r/m
PUSH = Push:
Register/Memory 1 1 1 1 1 1 1 1 mod 1 1 0 r/m
Register 0 1 0 1 0 reg
Segment Register 0 0 0 reg 1 1 0
POP = Pop:
Register/Memory 1 0 0 0 1 1 1 1 mod 0 0 0 r/m
Register 0 1 0 1 1 reg
Segment Register 0 0 0 reg 1 1 1
XCHG = Exchange:
Register/Memory with Register 1 0 0 0 0 1 1 w mod reg r/m
Register with Accumulator 1 0 0 1 0 reg
IN = Input from:
Fixed Port 1 1 1 0 0 1 0 w port
Variable Port 1 1 1 0 1 1 0 w
OUT = Output to:
Fixed Port 1 1 1 0 0 1 1 w port
Variable Port 1 1 1 0 1 1 1 w
XLAT = Translate Byte to AL 1 1 0 1 0 1 1 1
LEA = Load EA to Register2 1 0 0 0 1 1 0 1 mod reg r/m
LDS = Load Pointer to DS 1 1 0 0 0 1 0 1 mod reg r/m
LES = Load Pointer to ES 1 1 0 0 0 1 0 0 mod reg r/m
LAHF = Load AH with Flags 1 0 0 1 1 1 1 1
SAHF = Store AH into Flags 1 0 0 1 1 1 1 0
PUSHF = Push Flags 1 0 0 1 1 1 0 0
POPF = Pop Flags 1 0 0 1 1 1 0 1
ARITHMETIC
ADD = Add:
Register/Memory with Register to Either 0 0 0 0 0 0 d w mod reg r/m
Immediate to Register/Memory 1 0 0 0 0 0 s w mod 0 0 0 r/m data data if s:w = 01
Immediate to Accumulator 0 0 0 0 0 1 0 w data data if w = 1
ADC = Add with Carry:
Register/Memory with Register to Either 0 0 0 1 0 0 d w mod reg r/m
80C86
3-172
Immediate to Register/Memory 1 0 0 0 0 0 s w mod 0 1 0 r/m data data if s:w = 01
Immediate to Accumulator 0 0 0 1 0 1 0 w data data if w = 1
INC = Increment:
Register/Memory 1 1 1 1 1 1 1 w mod 0 0 0 r/m
Register 0 1 0 0 0 reg
AAA = ASCll Adjust for Add 0 0 1 1 0 1 1 1
DAA = Decimal Adjust for Add 0 0 1 0 0 1 1 1
SUB = Subtract:
Register/Memory and Register to Either 0 0 1 0 1 0 d w mod reg r/m
Immediate from Register/Memory 1 0 0 0 0 0 s w mod 1 0 1 r/m data data if s:w = 01
Immediate from Accumulator 0 0 1 0 1 1 0 w data data if w = 1
SBB = Subtract with Borrow
Register/Memory and Register to Either 0 0 0 1 1 0 d w mod reg r/m
Immediate from Register/Memory 1 0 0 0 0 0 s w mod 0 1 1 r/m data data if s:w = 01
Immediate from Accumulator 0 0 0 1 1 1 0 w data data if w = 1
DEC = Decrement:
Register/Memory 1 1 1 1 1 1 1 w mod 0 0 1 r/m
Register 0 1 0 0 1 reg
NEG = Change Sign 1 1 1 1 0 1 1 w mod 0 1 1 r/m
CMP = Compare:
Register/Memory and Register 0 0 1 1 1 0 d w mod reg r/m
Immediate with Register/Memory 1 0 0 0 0 0 s w mod 1 1 1 r/m data data if s:w = 01
Immediate with Accumulator 0 0 1 1 1 1 0 w data data if w = 1
AAS = ASCll Adjust for Subtract 0 0 1 1 1 1 1 1
DAS = Decimal Adjust for Subtract 0 0 1 0 1 1 1 1
MUL = Multiply (Unsigned) 1 1 1 1 0 1 1 w mod 1 0 0 r/m
IMUL = Integer Multiply (Signed) 1 1 1 1 0 1 1 w mod 1 0 1 r/m
AAM = ASCll Adjust for Multiply 1 1 0 1 0 1 0 0 0 0 0 0 1 0 1 0
DlV = Divide (Unsigned) 1 1 1 1 0 1 1 w mod 1 1 0 r/m
IDlV = Integer Divide (Signed) 1 1 1 1 0 1 1 w mod 1 1 1 r/m
AAD = ASClI Adjust for Divide 1 1 0 1 0 1 0 1 0 0 0 0 1 0 1 0
CBW = Convert Byte to Word 1 0 0 1 1 0 0 0
CWD = Convert Word to Double Word 1 0 0 1 1 0 0 1
LOGIC
NOT = Invert 1 1 1 1 0 1 1 w mod 0 1 0 r/m
SHL/SAL = Shift Logical/Arithmetic Left 1 1 0 1 0 0 v w mod 1 0 0 r/m
SHR = Shift Logical Right 1 1 0 1 0 0 v w mod 1 0 1 r/m
SAR = Shift Arithmetic Right 1 1 0 1 0 0 v w mod 1 1 1 r/m
ROL = Rotate Left 1 1 0 1 0 0 v w mod 0 0 0 r/m
ROR = Rotate Right 1 1 0 1 0 0 v w mod 0 0 1 r/m
RCL = Rotate Through Carry Flag Left 1 1 0 1 0 0 v w mod 0 1 0 r/m
Instruction Set Summary
(Continued)
MNEMONIC AND DESCRIPTION
INSTRUCTION CODE
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
80C86
3-173
RCR = Rotate Through Carry Right 1 1 0 1 0 0 v w mod 0 1 1 r/m
AND = And:
Reg./Memory and Register to Either 0 0 1 0 0 0 0 d w mod reg r/m
Immediate to Register/Memory 1 0 0 0 0 0 0 w mod 1 0 0 r/m data data if w = 1
Immediate to Accumulator 0 0 1 0 0 1 0 w data data if w = 1
TEST = And Function to Flags, No Result:
Register/Memory and Register 1 0 0 0 0 1 0 w mod reg r/m
Immediate Data and Register/Memory 1 1 1 1 0 1 1 w mod 0 0 0 r/m data data if w = 1
Immediate Data and Accumulator 1 0 1 0 1 0 0 w data data if w = 1
OR = Or:
Register/Memory and Register to Either 0 0 0 0 1 0 d w mod reg r/m
Immediate to Register/Memory 1 0 0 0 0 0 0 w mod 1 0 1 r/m data data if w = 1
Immediate to Accumulator 0 0 0 0 1 1 0 w data data if w = 1
XOR = Exclusive or:
Register/Memory and Register to Either 0 0 1 1 0 0 d w mod reg r/m
Immediate to Register/Memory 1 0 0 0 0 0 0 w mod 1 1 0 r/m data data if w = 1
Immediate to Accumulator 0 0 1 1 0 1 0 w data data if w = 1
STRING MANIPULATION
REP = Repeat 1 1 1 1 0 0 1 z
MOVS = Move Byte/Word 1 0 1 0 0 1 0 w
CMPS = Compare Byte/Word 1 0 1 0 0 1 1 w
SCAS = Scan Byte/Word 1 0 1 0 1 1 1 w
LODS = Load Byte/Word to AL/AX 1 0 1 0 1 1 0 w
STOS = Stor Byte/Word from AL/A 1 0 1 0 1 0 1 w
CONTROL TRANSFER
CALL = Call:
Direct Within Segment 1 1 1 0 1 0 0 0 disp-low disp-high
Indirect Within Segment 1 1 1 1 1 1 1 1 mod 0 1 0 r/m
Direct Intersegment 1 0 0 1 1 0 1 0 offset-low offset-high
seg-low seg-high
Indirect Intersegment 1 1 1 1 1 1 1 1 mod 0 1 1 r/m
JMP = Unconditional Jump:
Direct Within Segment 1 1 1 0 1 0 0 1 disp-low disp-high
Direct Within Segment-Short 1 1 1 0 1 0 1 1 disp
Indirect Within Segment 1 1 1 1 1 1 1 1 mod 1 0 0 r/m
Direct Intersegment 1 1 1 0 1 0 1 0 offset-low offset-high
seg-low seg-high
Indirect Intersegment 1 1 1 1 1 1 1 1 mod 1 0 1 r/m
RET = Return from CALL:
Within Segment 1 1 0 0 0 0 1 1
Within Seg Adding lmmed to SP 1 1 0 0 0 0 1 0 data-low data-high
Instruction Set Summary
(Continued)
MNEMONIC AND DESCRIPTION
INSTRUCTION CODE
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
80C86
3-174
Intersegment 1 1 0 0 1 0 1 1
Intersegment Adding Immediate to SP 1 1 0 0 1 0 1 0 data-low data-high
JE/JZ = Jump on Equal/Zero 0 1 1 1 0 1 0 0 disp
JL/JNGE = Jump on Less/Not Greater or Equal 0 1 1 1 1 1 0 0 disp
JLE/JNG = Jump on Less or Equal/ Not Greater 0 1 1 1 1 1 1 0 disp
JB/JNAE = Jump on Below/Not Above or Equal 0 1 1 1 0 0 1 0 disp
JBE/JNA = Jump on Below or Equal/Not Above 0 1 1 1 0 1 1 0 disp
JP/JPE = Jump on Parity/Parity Even 0 1 1 1 1 0 1 0 disp
JO = Jump on Overflow 0 1 1 1 0 0 0 0 disp
JS = Jump on Sign 0 1 1 1 1 0 0 0 disp
JNE/JNZ = Jump on Not Equal/Not Zero 0 1 1 1 0 1 0 1 disp
JNL/JGE = Jump on Not Less/Greater or Equal 0 1 1 1 1 1 0 1 disp
JNLE/JG = Jump on Not Less or Equal/Greater 0 1 1 1 1 1 1 1 disp
JNB/JAE = Jump on Not Below/Above or Equal 0 1 1 1 0 0 1 1 disp
JNBE/JA = Jump on Not Below or Equal/Above 0 1 1 1 0 1 1 1 disp
JNP/JPO = Jump on Not Par/Par Odd 0 1 1 1 1 0 1 1 disp
JNO = Jump on Not Overflow 0 1 1 1 0 0 0 1 disp
JNS = Jump on Not Sign 0 1 1 1 1 0 0 1 disp
LOOP = Loop CX Times 1 1 1 0 0 0 1 0 disp
LOOPZ/LOOPE = Loop While Zero/Equal 1 1 1 0 0 0 0 1 disp
LOOPNZ/LOOPNE = Loop While Not Zero/Equal 1 1 1 0 0 0 0 0 disp
JCXZ = Jump on CX Zero 1 1 1 0 0 0 1 1 disp
INT = Interrupt
Type Specified 1 1 0 0 1 1 0 1 type
Type 3 1 1 0 0 1 1 0 0
INTO = Interrupt on Overflow 1 1 0 0 1 1 1 0
IRET = Interrupt Return 1 1 0 0 1 1 1 1
PROCESSOR CONTROL
CLC = Clear Carry 1 1 1 1 1 0 0 0
CMC = Complement Carry 1 1 1 1 0 1 0 1
STC = Set Carry 1 1 1 1 1 0 0 1
CLD = Clear Direction 1 1 1 1 1 1 0 0
STD = Set Direction 1 1 1 1 1 1 0 1
CLl = Clear Interrupt 1 1 1 1 1 0 1 0
ST = Set Interrupt 1 1 1 1 1 0 1 1
HLT = Halt 1 1 1 1 0 1 0 0
WAIT = Wait 1 0 0 1 1 0 1 1
ESC = Escape (to External Device) 1 1 0 1 1 x x x mod x x x r/m
LOCK = Bus Lock Prefix 1 1 1 1 0 0 0 0
Instruction Set Summary
(Continued)
MNEMONIC AND DESCRIPTION
INSTRUCTION CODE
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
80C86
3-175
NOTES:
AL = 8-bit accumulator
AX = 16-bit accumulator
CX = Count register
DS= Data segment
ES = Extra segment
Above/below refers to unsigned value.
Greater = more positive;
Less = less positive (more negative) signed values
if d = 1 then “to” reg; if d = 0 then “from” reg
if w = 1 then word instruction; if w = 0 then byte
instruction
if mod = 11 then r/m is treated as a REG field
if mod = 00 then DISP = O†, disp-low and disp-high
are absent
if mod = 01 then DISP = disp-low sign-extended
16-bits, disp-high is absent
if mod = 10 then DISP = disp-high:disp-low
if r/m = 000 then EA = (BX) + (SI) + DISP
if r/m = 001 then EA = (BX) + (DI) + DISP
if r/m = 010 then EA = (BP) + (SI) + DISP
if r/m = 011 then EA = (BP) + (DI) + DISP
if r/m = 100 then EA = (SI) + DISP
if r/m = 101 then EA = (DI) + DISP
if r/m = 110 then EA = (BP) + DISP †
if r/m = 111 then EA = (BX) + DISP
DISP follows 2nd byte of instruction (before data
if required)
†except if mod = 00 and r/m = 110 then
EA = disp-high: disp-low.
†† MOV CS, REG/MEMORY not allowed.
if s:w = 01 then 16-bits of immediate data form the operand.
if s:w. = 11 then an immediate data byte is sign extended
to form the 16-bit operand.
if v = 0 then “count” = 1; if v = 1 then “count” in (CL)
x = don't care
z is used for string primitives for comparison with ZF FLAG.
SEGMENT OVERRIDE PREFIX
001 reg 11 0
REG is assigned according to the following table:
16-BIT (w = 1) 8-BIT (w = 0) SEGMENT
000 AX 000 AL 00 ES
001 CX 001 CL 01 CS
010 DX 010 DL 10 SS
011 BX 011 BL 11 DS
100 SP 100 AH 00 ES
101 BP 101 CH 00 ES
110 SI 110 DH 00 ES
111 DI 111 BH 00 ES
Instructions which reference the flag register file as a 16-bit
object use the symbol FLAGS to represent the file:
FLAGS =
X:X:X:X:(OF):(DF):(IF):(TF):(SF):(ZF):X:(AF):X:(PF):X:(CF)
Mnemonics Intel, 1978
Instruction Set Summary
(Continued)
MNEMONIC AND DESCRIPTION
INSTRUCTION CODE
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
80C86
