24FC1026-I/SN - Microchip Technology

 2011 Microchip Technology Inc. DS22270A-page 1

24AA1026/24LC1026/24FC1026

Device Selection Table:

Features:

• Low-Power CMOS Technology:

- Read current 450 A, maximum

- Standby current 5 A, maximum

• 2-Wire Serial Inte rfac e, I2C™ Compatible

• Cascadable up to Four Devices

• Schmitt Trigger Inputs for Noise Suppression

• Output Slop e Control t o El im ina te Gro und Bounc e

• 100 kHz and 400 kHz Clock Compatibility

• 1 MHz Clock f or FC Versions

• Page Write Time 3 ms, typical

• Self-Timed Erase/Write Cycle

• 128-Byte Page Write Buffer

• Hardware Write-Protect

• ESD Protection >400V

• More than 1 Million Erase/Write Cycles

• Data Retention >200 Years

• Factory Programming Available

• Packages include 8-lead PDIP, SOIJ and SOIC

• Pb-Free and RoHS Compliant

• Temperature Ranges:

- Industrial (I): -40C to +85C

Description:

The Microchip Technology Inc. 24AA1026/24LC1026/

24FC1026 (24XX1026*) is a 128K x 8 (1024K bit)

Serial Electrically Erasable PROM, capable of

operatio n ac ros s a broa d vo ltage ra nge (1.7 V to 5. 5V).

It has been developed for advanced, low-power

applications such as personal communications or data

acquisition. This device has both byte write and page

write capability of up to 128 bytes of data.

This device is c apable of bo th rand om and se quenti al

reads. Reads may be sequential within address

boundaries 0000h to FFFFh and 10000h to 1FFFFh.

Functio nal address lines al low up t o four de vices on the

same data bus. This allows for up to 4 Mbits total

system EEPROM memory. This device is available in

the standard 8-pin PDIP, SOIC and SOIJ packages.

Package Type

Block Diagram

*24XX1026 is used in this document as a generic part number

for the 24AA1026/24LC1026/24FC1026 devices.

Part

Number VCC

Range Max. Clock

Frequency Temp.

Ranges

24AA1026 1.7-5.5V 400 kHz†I

24LC1026 2.5-5.5V 400 kHz I

24FC1026 1.8-5.5V 1 MHz‡I

†100 kHz for VCC < 2.5V

‡400 kHz for VCC < 2.5V

VSS

VCC

SCL

SDA

PDIP

SOIJ/SOICNC

VSS

VCC

SCL

SDA

HV Generator

EEPROM

Array

Page Latches

YDEC

XDEC

Sens e A MP

R/W Control

Memory

Control

Logic

I/O

Control

Logic

I/O

A1A2

SDA

SCL

1024K I2C™ CMOS Serial EEPROM

24AA1026/24LC1026/24FC1026

DS22270A-page 2  2011 Microchip Technology Inc.

1.0 ELECTRICAL CHARAC TERISTICS

Absolute Maximum Ratings(†)

VCC.............................................................................................................................................................................6.5V

All inputs and outputs w.r.t. VSS ................ ..... ...... ..... ................. ...... ...... ................ ...... ................. ..... . -0.6V to VCC+1.0V

Storage temperature ...............................................................................................................................-65°C to +150°C

Ambient temperature with power applied..................................................................................................-40°C to +85°C

ESD protection on all pins 4kV

TABLE 1-1: DC CHARACTERISTICS

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device . This is a stres s ratin g o nly and fun ctional ope ration of the devic e at th ose o r any other c onditi ons a bove those

indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for

extended periods may affect device reliability.

DC CHARACTERISTICS Industri al (I): VCC = +1.7V to 5.5V TA = -40°C to +85°C

Param.

No. Sym. Characteristic Min. Max. Units Conditions

— A1, A2, SCL, SDA and

WP pins: ———

D1 VIH High-level input voltage 0.7 VCC —V

D2 VIL Low-level input voltage — 0.3 VCC

0.2 VCC V

VVCC 2.5V

VCC < 2.5V

D3 VHYS Hysteresis of Schmitt

Trigger inputs

(SDA, SCL pins)

0.05 VCC —VVCC  2.5V (Note)

D4 VOL Low-level output voltage — 0.40 V IOL = 3.0 mA @ VCC = 4.5V

IOL = 2.1 mA @ VCC = 2.5V

D5 ILI Input leakage current — ±1 AVIN = VSS or VCC

VIN = VSS or VCC

D6 ILO Output leaka ge curre nt — ±1 AVOUT = VSS or VCC

D7 CIN,

COUT Pin capacitance

(all inputs/ou tpu t s) —10pFVCC = 5.0V (Note)

TA = 25°C, FCLK = 1 MHz

D8 ICC Read Operating current — 450 AVCC = 5.5V, SCL = 400 kHz

ICC Write — 5 mA VCC = 5.5V

D9 ICCS Standby current — 5

A SCL, SDA, VCC = 5.5V

A1, A2, WP = VSS

Note: This parameter is periodically sampled and not 100% tested.

 2011 Microchip Technology Inc. DS22270A-page 3

24AA1026/24LC1026/24FC1026

TABLE 1-2: AC CHARACTERISTICS

AC CHARACTERISTICS Industrial (I): VCC = +1.7V to 5.5V TA = -40°C to +85°C

Param.

No. Sym. Characteristic Min. Max. Units Conditions

CLK Clock frequency —

—

100

400

1000

kHz 1.7V  VCC  2.5V

2.5V  VCC  5.5V

1.8V  VCC  2.5V (24FC1026 only)

2.5V  VCC  5.5V (24FC1026 only)

HIGH Clock high time 4000

600

500

—

ns 1.7V  VCC  2.5V

2.5V  VCC  5.5V

1.8V  VCC  2.5V (24FC1026 only)

2.5V  VCC  5.5V (24FC1026 only)

LOW Clock low time 4700

1300

500

—

ns 1.7V  VCC  2.5V

2.5V  VCC  5.5V

1.8V  VCC  2.5V (24FC1026 only)

2.5V  VCC  5.5V (24FC1026 only)

RSDA and SCL rise time

(Note 1)—

—

1000

300

ns 1.7V  VCC  2.5V

2.5V  VCC  5.5V

1.8V  VCC  2.5V (24FC1026 only)

2.5V  VCC  5.5V (24FC1026 only)

FSDA and SCL fall time

(Note 1)—

—300

100 ns All except 24FC1026

1.8V  VCC  5.5V (24FC1026 only)

HD:STA Start condition hold time 4000

600

250

—

ns 1.7V  VCC  2.5V

2.5V  VCC  5.5V

1.8V  VCC  2.5V (24FC1026 only)

2.5V  VCC  5.5V (24FC1026 only)

SU:STA Start condition setup time 4700

600

250

—

ns 1.7V  VCC  2.5V

2.5V  VCC  5.5V

1.8V  VCC  2.5V (24FC1026 only)

2.5V  VCC  5.5V (24FC1026 only)

HD:DAT Data input hold time 0 — ns (Note 2)

SU:DAT Data input setup time 250

100

—

ns 1.7V  VCC  2.5V

2.5V  VCC  5.5V

1.8V  VCC  2.5V (24FC1026 only)

2.5V  VCC  5.5V (24FC1026 only)

10 TSU:STO Stop condition setup time 4000

600

250

—

ns 1.7V  VCC  2.5V

2.5V  VCC  5.5V

1.8V  VCC  2.5V (24FC1026 only)

2.5V  VCC  5.5V (24FC1026 only)

11 TSU:WP WP setup time 4000

600

—

ns 1.7V  VCC  2.5V

2.5V  VCC  5.5V

1.8V  VCC  2.5V (24FC1026 only)

2.5V  VCC  5.5V (24FC1026 only)

12 THD:WP WP hold time 4700

1300

—

ns 1.7V  VCC  2.5V

2.5V  VCC  5.5V

1.8V  VCC  2.5V (24FC1026 only)

2.5V  VCC  5.5V (24FC1026 only)

13 TAA Output valid from clock

(Note 2)—

—

3500

900

400

ns 1.7V  VCC  2.5V

2.5V  VCC  5.5V

1.8V  VCC  2.5V (24FC1026 only)

2.5V  VCC  5.5V (24FC1026 only)

Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.

2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum

300 ns) of the falling edge of SCL to avoid unintended generation of St art or Stop conditions.

3: The combined TSP and VHYS specifications are due to new Schm itt Trigger inputs which provide improved noise spike

suppression. This eliminates the need for a TI specification for standard operation.

4: This parameter is not tested but established by characterization. For endurance estimates in a specific application,

please consult the Total Endurance™ Model which can be obtained from Microchip’s web site at www.microchip. com.

24AA1026/24LC1026/24FC1026

DS22270A-page 4  2011 Microchip Technology Inc.

FIGURE 1-1: BUS TIMING DATA

14 TBUF Bus free time: Time the bus

must be free before a new

transmission can start

4700

1300

500

—

ns 1.7V  VCC  2.5V

2.5V  VCC  5.5V

1.8V  VCC  2.5V (24FC1026 only)

2.5V  VCC  5.5V (24FC1026 only)

15 TSP Input filter spike suppression

(SDA and SCL pins) — 50 ns All except 24FC1026 (Note 1 and Note 3)

16 TWC Write cycle time (byte or page) — 5 ms —

17 Endurance 1,000,000 — cycles P age mode, 25°C, VCC = 5.5V (Note 4)

AC CHARACTERISTICS (Continued) Industrial (I): VCC = +1.7V to 5.5V TA = -40°C to +85°C

Param.

No. Sym. Characteristic Min. Max. Units Conditions

Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.

2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum

300 ns) of the falling edge of SCL to avoid unintended generation of St art or Stop conditions.

3: The combined TSP and VHYS specifications are due to new Schm itt Trigger inputs which provide improved noise spike

suppression. This eliminates the need for a TI specification for standard operation.

4: This parameter is not tested but established by characterization. For endurance estimates in a specific application,

please consult the Total Endurance™ Model which can be obtained from Microchip’s web site at www.microchip. com.

(unprotected)

(protected)

SCL

SDA

OUT

D3 4

11 12

 2011 Microchip Technology Inc. DS22270A-page 5

24AA1026/24LC1026/24FC1026

2.0 PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 2-1.

TABLE 2-1: PIN FUNCTION TABLE

2.1 A1, A2 Chip Address Inputs

The A1 and A2 inputs are used by the 24XX1026 for

multiple device operations. The levels on these inputs

are compared with the corresponding bits in the slave

address. The chip is selected if the comparison is true.

Up to four devices may be connected to the same bus

by usin g diffe rent Chip Select bit c ombinations . In most

applications, the chip address inputs A1 and A2 are

hard-wired to logic ‘0’ or logic ‘1’. For applications in

whic h t h es e pin s ar e c o nt ro ll ed b y a m ic rocont r ol l er o r

other programmable device, the chip address pins

must be driven to logic ‘0’ or logic ‘1’ before normal

device operation can proceed.

2.2 Serial Data (SDA)

This is a bidirectional pin used to transfer addresses

and data into and data out of the device. It is an open-

drain terminal, therefore, the SDA bus requires a pull-

up resistor to VCC (typic al 10 k  for 100 kHz, 2 kfor

400kHz and 1MHz).

For norma l data trans fer SDA is all owed to change only

during SCL low. Changes during SCL high are

reserved for indi cating the Start and Stop co nditions.

2.3 Serial Clock (SCL)

This i nput is u sed t o sy nchron ize the d ata trans fer fro m

and to the device.

2.4 Write-Protect (WP)

This pin must be conn ected to eith er VSS or VCC. If tied

to VSS, write operations are enabled. If tied to VCC,

write operations are inhibited, but read operations are

not affected.

Name PDIP SOIJ SOIC Function

NC 1 1 1 Not Connected

A1 2 2 2 User Configurable Chip

Select

A2 3 3 3 User Configurable Chip

Select

VSS 444Ground

SDA 5 5 5 Serial Data

SCL 6 6 6 Serial Clock

WP 7 7 7 Write-Protect Input

VCC 8 8 8 +1.7 to 5.5V ( 24AA1026)

+2.5 to 5. 5V ( 24LC1026)

+1.8 to 5. 5V ( 24FC1026)

24AA1026/24LC1026/24FC1026

DS22270A-page 6  2011 Microchip Technology Inc.

3.0 FUNCTIONAL DESCRIPTION

The 24XX1026 supports a bidirectional 2-wire bus and

data transmission protocol. A device that sends data

onto the bus is defined as a transmitter and a device

receiving data as a receiver. The bus must be

controlled by a master device which generates the

Serial Clock (SCL), controls the bus access, and

generates the Start and Stop conditions while the

24XX1026 works as a slave. Both master and slave

can opera te as a transm itter or recei ver , but the master

device determines which mode is activated.

 2011 Microchip Technology Inc. DS22270A-page 7

24AA1026/24LC1026/24FC1026

4.0 BUS CHARACTERISTICS

The following bus protocol has been defined:

• Data transfer may be initiated only when the bus

is not busy.

• During data transfer, the data line must remain

stab le when ever th e clock lin e is high . Change s in

the data line while the clock line is high will be

interpreted as a Start or Stop condition.

Accordingly, the following bus conditions have been

defined (Figure 4-1).

4.1 Bus Not Busy (A)

Both data and clock lines remain high.

4.2 Start Data Transfer (B)

A high-to-low transition of the SDA line while the clock

(SCL) is high determines a Start condition. All

commands must be preceded by a Start condition.

4.3 S top Data Transfer (C)

A low-to-high transition of the SDA line while the clock

(SCL) is high determines a Stop condition. All

operations must end with a Stop condition.

4.4 Data Valid (D)

The state of the data line represents valid data when,

after a Start condition, the data line is stable for the

duration of the high period of the cl ock s ignal.

The data on the line must be changed during the low

period of the clock signal. There is one bit of data per

clock pulse.

Each dat a transf er is initiated w ith a S tart condition an d

terminated with a Stop condition. The number of the

data bytes transferred between the Start and Stop

conditions is determined by the master device.

4.5 Acknowledge

Each receiving device, when addressed, is obliged to

generate an Acknowledge signal after the reception of

each byte. The master device must generate an extra

clock pulse which is associated with this Acknowledge

bit.

A device that acknowledges must pull-down the SDA

line during the Acknowledge clock pulse in such a way

that the SD A line is sta ble low d uring the high pe riod of

the acknowledge related clock pulse. Of course, setup

and hold times must be taken into account. During

reads, a maste r mus t sign al an e nd of dat a to the sl ave

by NOT gene rating an Acknowl edge bit on the las t byte

that has been cl ocke d out o f the slave . In th is ca se , the

slave (24XX1026) will leave the data line high to en able

the master to generate the Stop condition.

FIGURE 4-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS

FIGURE 4-2: ACKNOWLEDGE TIMING

Note: The 24XX1026 does not generate any

Acknowledge bits if an internal program-

ming cycle is in progress, however, the

control byte that is being polled must

match the control byte used to initiate the

write cycle.

Address or

Acknowledge

Valid

Data

Allowed

To Change

Stop

Condition

Start

Condition

SCL

SDA

(A) (B) (D) (D) (C) (A)

SCL 987654321123

The transmitter m ust release the SDA line at this

point allowing the receiver to pull the SDA line low

to acknowledge the previous eight bits of data.

The receiver must release the SDA line at this

point so the transmitter can continue sending

data.

Dat a fr om tra nsmi tter Data from transmitter

SDA

Acknowledge

Bit

24AA1026/24LC1026/24FC1026

DS22270A-page 8  2011 Microchip Technology Inc.

5.0 DEVICE ADDRESSING

A control byte is the first byte received following the

Start condition from the master device (Figure 5-1).

The con trol b yte c onsis ts of a 4-bit con trol c ode; fo r the

24XX1026, this is set as ‘1010’ binary for read and

write operations. The next two bits of the control byte

are the Chip Select bits (A2, A1). The Chip Select bits

allow the use of up to four 24XX1026 devices on the

same bus and are used to select which device is

accessed. The Chip Select bits in the control byte must

corresp ond to the logi c le ve ls on the corre sp ond ing A2

and A1 p ins for th e devic e to resp ond. Thes e bits are in

effect the two Most Significant bits (MSb) of the word

address. The next bit of the control byte is the block

select bit (B0). This bit acts as the A16 address bit for

accessing the entire array.

The last bit of the control byte defines the operation to

be performed. When set to a one, a read operation is

selected, and when set to a zero, a write operation is

selected. The next two bytes received define the

address of the first data byte (Figure 5-2). The upper

address bits are transferred first, followed by the Least

Significant bits (LSb).

Following the Start condition, the 24XX1026 monitors

the SDA bus checking the device type identifier being

transmitted. Upon receiving a ‘1010’ code and

appropri ate dev ice s elect b its , the s lave d evice output s

an Ackn owle dge si gnal on the SDA li ne. Dependi ng on

the state of the R/W bit, the 24XX1026 will select a read

or write operation.

This device has an internal addressing boundary

limit ation that is d ivided into tw o segments o f 512K bits.

Block select bit ‘B0’ is used to control access to each

segment.

FIGURE 5-1: CONTROL BYTE

FORMAT

5.1 Contiguous Addressing Across

Multi ple Devices

The Chip Select b its A2 and A1 can be used to exp and

the contiguous address space for up to 4 Mbit by add-

ing up to four 24XX1026’s on the same bus. In this

case, software can use A1 of the control byte as

address bit A16 and A2 as address bit A17. It is not

possible to sequentially read across device boundar-

ies.

Each device has internal addressing boundary

limitation s. This d ivi de s each p a r t in to t w o s egm en t s of

512K bits. The block select bit ‘B0’ controls access to

each “half”.

Sequential read operations are limited to 512K blocks.

To read through four devices on the same bus, eight

random Read commands must be given.

FIGURE 5-2: ADDRESS SEQUENCE BIT ASSIGNMENTS

1010A2 A1 B0SACKR/W

Control Code

Chip

Bits

Slave Address

Acknowledge Bit

Start Bit

Read/Write Bit

Select Block

Select

Bit

1010A

0R/W A

11 A

10 A

8••••••

Control Byte Address High Byte Address Low Byte

Control

Code Chip

Select

Bits

Block

Select

Bit

 2011 Microchip Technology Inc. DS22270A-page 9

24AA1026/24LC1026/24FC1026

6.0 WRITE OPERATIONS

6.1 Byte Write

Following the Start condition from the master, the

control code (four bits), the Chip Select (two bits), the

block select (one bit), and the R/W bit (which is a logic

low) are clocked onto the bus by the mast er transmitter .

This i n di ca tes t o th e ad d res se d s l av e re ce i ve r t ha t t he

address high byte will follow after it has generated an

Acknowledge bit during the ninth clock cycle.

Therefore, the next byte transmitted by the master is

the high-order byte of the word address and will be

written into the Address Pointer of the 24XX1026. The

next byte is the Least Significant Address Byte. After

receiving another Acknowledge signal from the

24XX1026, the master device will transmit the data

word to be wr itten into the addressed mem ory locatio n.

The 24XX1026 acknowledges again and the master

generates a Stop condition. This initiates the internal

write cycle and during this time, the 24XX1026 will not

generate Acknowledge signals as long as the control

byte being polled matches the control byte that was

used to initiate the write (Figure 6-1). If an attempt is

made to write to the array with the WP pin held high, the

device will acknowledge the command, but no write

cycle will occur, no data will be written and the device

will immediately accept a new command. After a byte

Write command, the internal address counter will point

to the address location following the one that was just

written.

6.2 Page Write

The write control byte, word address and the first data

byte are transmitted to the 24XX1026 in the same way

as in a byte write. But instead of generating a Stop

condition, the master transmits up to 127 additional

bytes, w hich are temporari ly stored in the on- chip pag e

buffer and will be written into memory after the master

has transmitted a Stop condition. After receipt of each

word, the seven lower Address Pointer bits are

internally incremented by one. If the master should

transmit more than 128 bytes prior to generating the

Stop condition, the address counter will roll over and

the previ ously received data will be overwritten . As with

the byte write operation, once the Stop condition is

received, an internal write cycle will begin (Figure 6-2).

If an attempt is made to write to the array with the WP

pin held high, the device will acknowledge the

command, but no write cycle will occur, no data will be

written and the device will immediately accept a new

command.

6.3 Write Protection

The W P pin a llows th e user t o writ e-prote ct the entire

array (0000 0-1FFFF) when th e pin is tie d to VCC. If tied

to VSS the write protection is disabled. The WP pin is

sampled at the Stop bit for every Write command

(Figure 1-1). Toggling the WP pin after the Stop bit will

have no effect on the execution of the write cycle.

Note: When doing a write o f less t han 128 bytes

the data in the rest of the page is

refreshed along with the data bytes being

written. This will force the entire page to

endure a write cycle, for this reason

endurance is specified per page.

Note: Page write operations are limited to writ-

ing bytes within a single physical page,

regardless of the number of bytes actually

being written. Physical page boundaries

start at addresses that are integer

multiples of the page buffer size (or ‘page

size’) and end at addresses that are

integer multiples of [page size – 1]. If a

Page Write command attempts to write

across a physical page boundary, the

result is that the data wraps around to the

beginni ng o f th e cu rren t p a ge (o ve rw riti ng

data previously stored there), instead of

being w ritten to th e next p age as migh t be

expecte d. It is the refo re nec es sa ry for the

application so ftwa re to p reve nt page write

operations that would attempt to cross a

page boundary.

24AA1026/24LC1026/24FC1026

DS22270A-page 10  2011 Microchip Technology Inc.

FIGURE 6-1: BYTE WRITE

FIGURE 6-2: PAGE WRITE

BUS ACT IV IT Y

MASTER

SDA LINE

BUS ACT IV IT Y

Control

Byte Address

High Byte Address

Low Byte Data

S1010 0

BUS ACTIVITY

MASTER

SDA LINE

BUS ACTIVITY

Control

Byte Address

High Byte Address

Low Byte Data Byte 0

Data Byte 127

S1010 0

 2011 Microchip Technology Inc. DS22270A-page 11

24AA1026/24LC1026/24FC1026

7.0 ACKNOWLEDGE POLLING

Since the device will not acknowledge during a write

cycle, this can be used to determine when the cycle is

complete. (This feature can be used to maximize bus

throughput.) Once the Stop condition for a Write

comma nd has been is sued from the master , the device

initiates the internally timed write cycle. ACK polling

can be initiated immediately. This involves the master

sending a Start condition, followed by the control byte

for a Write command (R/W = 0). If the device is still

busy with the write cycle, then no ACK will be returned.

If no AC K is retu rned, then the S t art b it and cont rol byte

must be resent. I f the cyc le is compl ete, then th e device

will return the ACK and the master can then proceed

with the next Read or Write command. See Figure 7-1

for flow diagram.

FIGURE 7-1: ACKNOWLEDGE

POLLING FLOW

Note: Care must be taken when polling the

24XX1026. The control byte that was

used to initiate the write needs to match

the control byte used for polling.

Send

Write Command

Send Stop

Condition to

Initiate Write Cycle

Send Start

Send Control Byte

with R/W = 0

Did Device

Acknowledge

(ACK = 0)?

Operation

Yes

24AA1026/24LC1026/24FC1026

DS22270A-page 12  2011 Microchip Technology Inc.

8.0 READ OPERATION

Read operations are initiated in the same way as write

operations with the exception that the R/W bit of the

control byte is set to one. There are three basic types

of read operat ions: current add ress read , rand om rea d

and sequential read.

8.1 Current Address Read

The 24XX1026 contains an address counter that

maintains the address of the last word accessed,

internally incremented by one. Therefore, if the

previous read access was to address n (n is any legal

address), the next current address read operation

would access data from address n + 1.

Upon re ceipt of th e control b yte with R/ W bit set to on e,

the 24XX1026 issues an acknowledge and transmits

the 8-bit data word. The master will not acknowledge

the transfer , but do es generate a S top condition and the

24XX1026 dis co nti nue s trans m is sio n (Figure 8-1).

FIGURE 8-1: CURRENT ADDRESS

READ

8.2 Random Read

Random read operations allow the master to access

any memory location in a random manner. To perform

this typ e of re ad o peration, fi rst the w o rd ad dres s m us t

be set. This is done b y sending the word address to the

24XX1026 as part of a write operation (R/W bit set to

0). After the word address is sent, the master

generates a Start condit ion fo llo w ing the ac kn ow le dg e.

This terminates the write operation, but not before the

internal Address Pointer is set. Then, the master issues

the control byte again, but wit h the R/W bit set to a one.

The 24XX1026 will then issue an acknowledge and

transmit the 8-bit data word. The master will not

acknowledge the transfer, but does generate a Stop

condition which causes the 24XX1026 to discontinue

transmission (Figure 8-2). After a random Read

command, the interna l address counte r wil l point to the

address location following the one that was just read.

8.3 Sequentia l Read

Sequential reads are initiated in the same way as a

random read except that after the 24XX1026 transmits

the first data byte, the master issues an acknowledge

as opposed to the Stop condition used in a random

read. This acknowledge directs the 24XX1026 to

transmit the next sequentially addressed 8-bit word

(Figure 8-3). Following the final byte transmitted to the

master, the m aster w ill NOT generate an ackn owledg e,

but will generate a Stop condition. To provide

sequential reads, the 24XX1026 contains an internal

Address Pointer which is incremented by one at the

completion of each operation. This Address Pointer

allows half the memory contents to be serially read

during one operation. Sequential read address

boundaries are 0000h to FFFFh and 10000h to

1FFFFh. The internal Address Pointer will

automatically roll over from address FFFF to address

0000 if the master acknowledges the byte received

from the array address, 1FFFF. The internal address

counter will automatically roll over from address

1FFFFh to address 10000h if the m aster acknowledges

the byte received from the array address, 1FFFFh.

BUS ACTIVITY

MASTER

SDA LINE

BUS ACTIVITY

Control

Byte

Data

1100

AAB1

Byte

210

 2011 Microchip Technology Inc. DS22270A-page 13

24AA1026/24LC1026/24FC1026

FIGURE 8-2: RANDOM READ

FIGURE 8-3: SEQUENTIAL READ

BUS ACTIVITY

MASTER

SDA LINE

BUS ACTIVITY A

Control

Byte Address

High Byte Address

Low Byte Control

Byte Data

Byte

S1010AAB0

210 S1010AAB1

210 P

BUS ACTIVITY

MASTER

SDA LINE

BUS ACTIVITY

Control

Byte Data n Da ta n + 1 Data n + 2 Data n + X

24AA1026/24LC1026/24FC1026

DS22270A-page 14  2011 Microchip Technology Inc.

9.0 PACKAGING INFORMATION

9.1 Package Marking Information

XXXXXXXX

TXXXXNNN

YYWW

8-Lead PDIP (300 mil) Example:

*Standard marking consists of Microchip part number, year code, week code, traceability code (facility

code, mask rev#, and assembly code). For marking beyond this, certain price adders apply. Please

check with your Microchip Sales Office.

24LC1026

I/P 13F

1028

8-Lead SOIJ (5.28 mm) Example

XXXXXXXX

YYWWNNN

TXXXXXXX 24LC1026

1028 13F

I/SM

Legend: XX...X Part number or part number code

T Temperature (I, E)

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week ‘01’)

NNN Alphanumeric traceability code (2 characters for small packages)

Pb-free JEDEC designator for Matte Tin (Sn)

Note: For very small packages with no room for the Pb-free JEDEC designator

, the marking will only appear on the outer carton or reel label.

Note: In the event the full Mi croch ip p art numb er ca nnot be mark ed on one l ine, it w ill

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

8-Lead SOIC (3.90 mm) Example

XXXXXXXT

NNN

XXXXYYWW 24L1026I

1028

13F

 2011 Microchip Technology Inc. DS22270A-page 15

24AA1026/24LC1026/24FC1026





 

 

 

 



 



 

   

  

  

    

    

    

    

    

    

    

    

    

    

    

NOTE 1

123

   

24AA1026/24LC1026/24FC1026

DS22270A-page 16  2011 Microchip Technology Inc.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

 2011 Microchip Technology Inc. DS22270A-page 17

24AA1026/24LC1026/24FC1026

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

24AA1026/24LC1026/24FC1026

DS22270A-page 18  2011 Microchip Technology Inc.

 ! ""#$%& !'



 2011 Microchip Technology Inc. DS22270A-page 19

24AA1026/24LC1026/24FC1026

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

24AA1026/24LC1026/24FC1026

DS22270A-page 20  2011 Microchip Technology Inc.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

 2011 Microchip Technology Inc. DS22270A-page 21

24AA1026/24LC1026/24FC1026

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

24AA1026/24LC1026/24FC1026

DS22270A-page 22  2011 Microchip Technology Inc.

APPENDIX A: REVISION HISTORY

Revision A

Original release (01/2011)

 2011 Microchip Technology Inc. DS22270A-page 23

24AA1026/24LC1026/24FC1026

THE MICROCHIP WEB SITE

Microc hip pro vides onl ine s upport v ia our W WW site at

www.microchi p.c om . Thi s web si te i s us ed as a m ean s

to make files and information easily available to

customers. Accessible by using your favorite Internet

browser, the web site contains the following

information:

•Product Support – Data sheets and errata,

application notes and sample programs, design

resources, user’s guides and hardware support

documents, latest software releases and archived

software

•General Technical Support – Frequently Asked

Questions (FAQ), technical support requests,

online dis cu ss io n gr oups, Microchip con sultant

program member listing

•Business of Microchip – Product selector and

ordering guides, latest Microchip press releases,

listing of seminars and even ts, listings of

Microchip sales offices, distributors and factory

representatives

CUSTOMER CHANGE NOTIFICATION

SERVICE

Microchip’s customer notification service helps keep

customers current on Microchip products. Subscribers

will receive e-mail notification whenever there are

changes, updates, revisions or errata related to a

specif ied produ ct family or develo pment tool of interes t.

To register, access the Microchip web site at

www.microchip.com, click on Customer Change

Notification and follow the registration instructions.

CUSTOMER SUPP ORT

Users of Microchip products can receive assistance

through several channels:

• Distributor or Representative

• Local Sales Office

• Field Application Engineer (FAE)

• Technical Support

• Development Systems Information Line

Customers should contact their distributor,

representative or field application engineer (FAE) for

support. Local sales offices are also available to help

customers. A listing of sales offices and locations is

included in the back of this document.

Technical s upport is a vailable through the web si te

at: http://support.microchip.com

24AA1026/24LC1026/24FC1026

DS22270A-page 24  2011 Microchip Technology Inc.

READER RESP ONSE

It is ou r intentio n to provide you w it h th e b es t do cument ation po ss ib le to ensure suc c es sfu l u se of y ou r M ic roc hip prod-

uct. If you wi sh to prov ide you r comment s on org aniza tion, clar ity, subj ect matte r , and ways i n which o ur docum entatio n

can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.

Please list the following information, and use this outline to provide us with your comments about this document.

To: Technical Publications Manager

RE: Reader Response Total Pages Sent ________

From: Name

Company

Address

City / State / ZIP / Country

Telephone: (_______) _________ - _________

Application (optional):

Would you like a reply? Y N

Device: Literature Number:

Questions:

FAX: (______) _________ - _________

DS22270A24AA1026/24LC1026/24FC1026

1. What are the best featu res of this document ?

2. How does this document meet your hardware and software development needs?

3. Do you find the organization of this document easy to follow? If not, why?

4. What additions to the document do you think would enhance the structure and subject?

5. What deletions from the document could be made without affecting the overall usefulness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?

 2011 Microchip Technology Inc. DS22270A-page 25

24AA1026/24LC1026/24FC1026

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

PART NO. X/XX

PackageTemperature

Range

Device

Device: 24AA1026 = 1024K Bit 1.7V I2C CMOS Serial EEPROM

24AA1026T = 1024K Bit 1.7V I2C CMOS Serial EEPROM

(Tape and Reel)

24LC1026 = 1024K Bit 2.5V I2C CMOS Serial EEPROM

24LC1026T = 1024K Bit 2.5V I2C CMOS Serial EEPROM

(Tape and Reel)

24FC1026 = 1024K Bit 1.8V I2C CMOS Serial EEPROM

24FC1026T = 1024K Bit 1.8V I2C CMOS Serial EEPROM

(Tape and Reel)

Temperature

Range:I = -40°C to +85°C

Package: P = Plastic DIP (300 mil Body), 8-lead

SM = Plastic SOIJ (5.28 mm Body), 8-lead

SN = Plastic SOIC (3.90 mm Body), 8-lead

Examples:

a) 24AA1026T-I/SM: Tape and Reel, Industrial

Temperature, 1.7V, SOIJ package.

b) 24LC1026-I/P: Industrial Temperature,

2.5V, PDIP package.

c) 24LC1026T-I/SM: Tape and Reel, Industrial

Temperature, 2.5V, SOIJ package.

d) 24FC1026-I/SN: Tape and Reel, Industrial

Temperature , 1.8V, SOIC package.

24AA1026/24LC1026/24FC1026

DS22270A-page 26  2011 Microchip Technology Inc.

NOTES:

 2011 Microchip Technology Inc. DS22270A-page 27

Information contained in this publication regarding device

applications a nd the lik e is p rovided on ly for your c on ve nience

and may be supers eded by updat es . I t is y our responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC,

KEELOQ, KEELOQ logo, MPL AB, PIC , PI Cmi cro, PI CSTART,

PIC32 logo, rfPIC and UNI/O are registered trademarks of

Microchip Technology In corporated in the U.S.A. and other

countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,

MXDEV, MXLAB, SEEVAL and The Embedded Contr ol

Solutions Company are registered trademarks of Microchip

Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,

dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,

ECONOMONIT OR, FanSense, HI- TIDE , In - Circuit Seria l

Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified

logo, MPLIB, MPLINK, mTouch, Omniscient Code

Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,

PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance,

TSHARC, UniWinDriver, WiperLock and ZENA are

trademarks of Microchip Tec hnology Incorporat ed in the

U.S.A. and other countries.

SQTP is a service mark of Microchip T echnology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

ISBN: 978-1-60932-810-8

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure famili es of its kind on the market today, when used in the

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is c onstantly evolving. We a t Microc hip are co m mitted to continuously improving the code prot ect ion featur es of our

products. Attempts to break Microchip’ s code protection feature may be a violation of the Digital Millennium Copyright Act. If such act s

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping

devices, Serial EEPROMs, microperiph erals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

DS22270A-page 28  2011 Microchip Technology Inc.

AMERICAS

Corporate Office

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Fax: 480-792-7277

Technic al Support:

http://support.microchip.com

Web Address:

www.microchip.com

Atlanta

Duluth, GA

Tel: 678-957-9614

Fax: 678-957-1455

Boston

Westborough, MA

Tel: 774-760-0087

Fax: 774-760-0088

Chicago

Itasc a , IL

Tel: 630-285-0071

Fax: 630-285-0075

Cleveland

Independence, OH

Tel: 216-447-0464

Fax: 216-447-0643

Dallas

Addison, TX

Tel: 972-818-7423

Fax: 972-818-2924

Detroit

Farmington Hills, MI

Tel: 248-538-2250

Fax: 248-538-2260

Kokomo

Kokomo, IN

Tel: 765-864-8360

Fax: 765-864-8387

Los A n ge les

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

Santa Clara

Santa Clara, CA

Tel: 408-961-6444

Fax: 408-961-6445

Toronto

Mississauga, Ontario,

Canada

Tel: 905-673-0699

Fax: 905-673-6509

ASIA/PACIFIC

Asia Pacific Office

Suites 3707-14, 37th Floor

Tower 6, The Gateway

Harbour City, Kowloon

Hong Kong

Tel: 852-2401-1200

Fax: 852-2401-3431

Australia - Sydney

Tel: 61-2-9868-67 33

Fax: 61-2-9868-6755

China - Beijing

Tel: 86-10-8528-2 100

Fax: 86-10-8528-2104

China - Chengdu

Tel: 86-28-8665-5 511

Fax: 86-28-8665-7889

China - Chongqing

Tel: 86-23-8980-9 588

Fax: 86-23-8980-9500

China - Hong Kong SAR

Tel: 852-2401-1200

Fax: 852-2401-3431

China - Nanjing

Tel: 86-25-8473-2 460

Fax: 86-25-8473-2470

China - Qingdao

Tel: 86-532-8502-7355

Fax: 86-532-8502-7205

China - Shanghai

Tel: 86-21-5407-5 533

Fax: 86-21-5407-5066

China - Shenyang

Tel: 86-24-2334-2 829

Fax: 86-24-2334-2393

China - Shenzhen

Tel: 86-755-8203-2660

Fax: 86-755-8203-1760

China - Wuhan

Tel: 86-27-5980-5 300

Fax: 86-27-5980-5118

China - Xian

Tel: 86-29-8833-7 252

Fax: 86-29-8833-7256

China - Xiamen

Tel: 86-592-2388138

Fax: 86-592-2388130

China - Zhuhai

Tel: 86-756-3210040

Fax: 86-756-3210049

ASIA/PACIFIC

India - Bangalore

Tel: 91-80-3090-4444

Fax: 91-80-3090-4123

India - New Delhi

Tel: 91-11-4160-8631

Fax: 91-11-4160-8632

India - Pune

Tel: 91-20-2566-1512

Fax: 91-20-2566-1513

Japan - Yokohama

Tel: 81-45-471- 6166

Fax: 81-45-471-6122

Korea - Daegu

Tel: 82-53-744-4301

Fax: 82-53-744-4302

Korea - Seoul

Tel: 82-2-554-7200

Fax: 82-2-558-5932 or

82-2-558-5934

Malaysia - Kuala Lumpur

Tel: 60-3-6201-9857

Fax: 60-3-6201-9859

Malaysia - Penang

Tel: 60-4-227-8870

Fax: 60-4-227-4068

Philippines - Manila

Tel: 63-2-634-9065

Fax: 63-2-634-9069

Singapore

Tel: 65-6334-8870

Fax: 65-6334-8850

Taiwan - Hsin Chu

Tel: 886-3-6578-300

Fax: 886-3-6578-370

Taiwan - Kaohsiung

Tel: 886-7-213-7830

Fax: 886-7-330-9305

Taiwan - Taipei

Tel: 886-2-2500-6610

Fax: 886-2-2508-0102

Thailand - Bangko k

Tel: 66-2-694-1351

Fax: 66-2-694-1350

EUROPE

Austria - Wels

Tel: 43-7242-2244-39

Fax: 43-7242-2244-393

Denmark - Cop e nha gen

Tel: 45-4450-2828

Fax: 45-4485-2829

France - Paris

Tel: 33-1-69-53 -63-20

Fax: 33-1-69-30-90-79

Germany - Munich

Tel: 49-89-627-144-0

Fax: 49-89-627-14 4-44

Italy - Milan

Tel: 39-0331-742611

Fax: 39-0331-466781

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

Spain - Madrid

Tel: 34-91-708-08-90

Fax: 34-91-708-08 -91

UK - Wokingham

Tel: 44-118-921-5869

Fax: 44-118-921-5820

Worldwide Sales and Service

08/04/10