Philips Semiconductors Product specification
PowerMOS transistor BUK583-60A
Logic level FET
GENERAL DESCRIPTION QUICK REFERENCE DATA
N-channel enhancement mode SYMBOL PARAMETER MAX. UNIT
logic level field-effect power
transistor in a plastic envelope VDS Drain-source voltage 60 V
suitable for surface mount IDDrain current (DC) 3.2 A
applications. Ptot Total power dissipation 1.8 W
The device is intended for use in TjJunction temperature 150 ˚C
automotive and general purpose RDS(ON) Drain-source on-state 0.10 Ω
switching applications. resistance; VGS = 5 V
PINNING - SOT223 PIN CONFIGURATION SYMBOL
PIN DESCRIPTION
1 gate
2 drain
3 source
4 drain (tab)
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VDS Drain-source voltage - - 60 V
VDGR Drain-gate voltage RGS = 20 kΩ-60V
±V
GS Gate-source voltage - - 15 V
IDDrain current (DC) Tamb = 25 ˚C - 3.2 A
IDDrain current (DC) Tamb = 100 ˚C - 2.0 A
IDM Drain current (pulse peak value) Tamb = 25 ˚C - 13 A
Ptot Total power dissipation Tamb = 25 ˚C - 1.8 W
Tstg Storage temperature - - 55 150 ˚C
TjJunction temperature - - 150 ˚C
THERMAL RESISTANCES
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Rth j-sp From junction to solder point1Mounted on any PCB - 12 15 K/W
Rth j-amb From junction to ambient Mounted on PCB of fig.18 - - 70 K/W
4
123
d
g
s
1 Temperature measured at solder joint on drain tab.
September 1995 1 Rev 1.200
Philips Semiconductors Product specification
PowerMOS transistor BUK583-60A
Logic level FET
STATIC CHARACTERISTICS
Tj = 25 ˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V(BR)DSS Drain-source breakdown VGS = 0 V; ID = 0.25 mA 60 70 - V
voltage
VGS(TO) Gate threshold voltage VDS = VGS; ID = 1 mA 1.0 1.5 2.0 V
IDSS Zero gate voltage drain current VDS = 60 V; VGS = 0 V; - 1 10 µA
IDSS Zero gate voltage drain current VDS = 60 V; VGS = 0 V; Tj = 125 ˚C - 0.1 1.0 mA
IGSS Gate source leakage current VGS = ±15 V; VDS = 0 V - 10 100 nA
RDS(ON) Drain-source on-state VGS = 5 V; ID = 3.2 A - 0.08 0.10 Ω
resistance
DYNAMIC CHARACTERISTICS
Tj = 25 ˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
gfs Forward transconductance VDS = 25 V; ID = 3.2 A - 6.0 - S
Ciss Input capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 650 825 pF
Coss Output capacitance - 240 350 pF
Crss Feedback capacitance - 120 160 pF
td on Turn-on delay time VDD = 30 V; ID = 3 A; - 10 20 ns
trTurn-on rise time VGS = 5 V; RGS = 50 Ω; - 35 55 ns
td off Turn-off delay time Rgen = 50 Ω- 6090ns
t
fTurn-off fall time - 55 80 ns
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = 25 ˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
IDR Continuous reverse drain - - - 3.2 A
current
IDRM Pulsed reverse drain current - - - 13 A
VSD Diode forward voltage IF = 3.2 A; VGS = 0 V - 0.85 1.1 V
trr Reverse recovery time IF = 3.2 A; -dIF/dt = 100 A/µs; - 70 - ns
Qrr Reverse recovery charge VGS = -10 V; VR = 30 V - 0.25 - µC
AVALANCHE LIMITING VALUE
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
WDSS Drain-source non-repetitive ID = 3.2 A; VDD ≤ 25 V; - - 45 mJ
unclamped inductive turn-off VGS = 5 V; RGS = 50 Ω; Tamb = 25 ˚C
energy
September 1995 2 Rev 1.200
Philips Semiconductors Product specification
PowerMOS transistor BUK583-60A
Logic level FET
Fig.1. Normalised power dissipation.
PD% = 100
⋅
P
D
/P
D 25 ˚C
= f(T
amb
)
Fig.2. Normalised continuous drain current.
ID% = 100
⋅
I
D
/I
D 25 ˚C
= f(T
amb
); conditions: V
GS
≥
5 V
Fig.3. Transient thermal impedance.
Z
th j-amb
= f(t); parameter D = t
p
/T
Fig.4. Safe operating area T
amb
= 25 ˚C
I
D
& I
DM
= f(V
DS
); I
DM
single pulse; parameter t
p
Fig.5. Typical output characteristics, T
j
= 25 ˚C
.
I
D
= f(V
DS
); parameter V
GS
Fig.6. Typical on-state resistance, T
j
= 25 ˚C
.
R
DS(ON)
= f(I
D
); parameter V
GS
0 20 40 60 80 100 120 140
PD% Normalised Power Derating
120
110
100
90
80
70
60
50
40
30
20
10
0
Tamb / C
0.1 1 10 100
VDS / V
ID / A
100
10
1
0.1
0.01
BUK583-60A
100 us
1 ms
10 ms
100 ms
1 s
RDS(ON) = VDS/ID
10 s
DC
tp = 10 us
0 20 40 60 80 100 120 140
ID% Normalised Current Derating
120
110
100
90
80
70
60
50
40
30
20
10
0
Tamb / C
0 1 2
10
9
8
7
6
5
4
3
2
1
0 0.5 1.5
ID / A
VDS / V
2.5
VGS / V = 3.0
3.5
4.0
4.5
5.0
1E-07 1E-05 1E-03 1E-01 1E+01 1E+03
BUKX83
t / s
Zth j-amb / (K/W)
1E+02
1E+01
1E+00
1E-01
1E-02 0
0.5
0.2
0.1
0.05
0.02
D =
D =
t
p
t
p
T
T
P
t
D
0 2 4 6 8 10
1.2
1
0.8
0.6
0.4
0.2
0
ID / A
RDS(ON) / Ohm
VGS / V = 2.5
3
3.5
September 1995 3 Rev 1.200
Philips Semiconductors Product specification
PowerMOS transistor BUK583-60A
Logic level FET
Fig.7. Typical transfer characteristics.
I
D
= f(V
GS
)
; conditions: V
DS
= 25 V; parameter T
j
Fig.8. Typical transconductance, T
j
= 25 ˚C
.
g
fs
= f(I
D
); conditions: V
DS
= 25 V
Fig.9. Normalised drain-source on-state resistance.
a = R
DS(ON)
/R
DS(ON)25 ˚C
= f(T
j
); I
D
= 3.2 A; V
GS
= 5 V
Fig.10. Gate threshold voltage.
V
GS(TO)
= f(T
j
); conditions: I
D
= 1 mA; V
DS
= V
GS
Fig.11. Sub-threshold drain current.
I
D
= f(V
GS)
; conditions: T
j
= 25 ˚C; V
DS
= V
GS
Fig.12. Typical capacitances, C
iss
, C
oss
, C
rss
.
C = f(V
DS
); conditions: V
GS
= 0 V; f = 1 MHz
0 2 4
10
9
8
7
6
5
4
3
2
1
0
Tj / C = 150
25
135
ID / A
VGS / V
-60 -40 -20 0 20 40 60 80 100 120 140
Tj / C
VGS(TO) / V
2
1
0
max.
typ.
min.
0 2 4 6 8 10
15
10
5
0
gfs / S
ID / A
0 0.4 0.8 1.2 1.6 2 2.4
VGS / V
ID / A
1E-01
1E-02
1E-03
1E-04
1E-05
1E-06
SUB-THRESHOLD CONDUCTION
2 % typ 98 %
-60 -40 -20 0 20 40 60 80 100 120 140
Tj / C
aNormalised RDS(ON) = f(Tj)
1.5
1.0
0.5
0
0 20 40
VDS / V
C / pF
Ciss
Coss
Crss
10
100
1000
10000 BUK5y3-50
September 1995 4 Rev 1.200
Philips Semiconductors Product specification
PowerMOS transistor BUK583-60A
Logic level FET
Fig.13. Typical turn-on gate-charge characteristics.
V
GS
= f(Q
G
); conditions: I
D
= 3.2 A; parameter V
DS
Fig.14. Typical reverse diode current.
I
F
= f(V
SDS
); conditions: V
GS
= 0 V; parameter T
j
Fig.15. Normalised avalanche energy rating.
W
DSS
% = f(T
amb
); conditions: I
D
= 3.2 A
Fig.16. Avalanche energy test circuit.
0QG / nC
VGS / V
10
9
8
7
6
5
4
3
2
1
0
VDS / V =12
48
51015
20 40 60 80 100 120 140
Tamb/ C
120
110
100
90
80
70
60
50
40
30
20
10
0
WDSS% Normalised Avalanche Energy
0 1
10
9
8
7
6
5
4
3
2
1
0 1.50.5
ID / A
VGS / V
Tj / C = 150 25
L
T.U.T.
VDD
RGS R 01
VDS
-ID/100
+
-
shunt
VGS
0
WDSS =0.5 ⋅LID
2⋅BVDSS/(BVDSS −VDD)
September 1995 5 Rev 1.200
Philips Semiconductors Product specification
PowerMOS transistor BUK583-60A
Logic level FET
MOUNTING INSTRUCTIONS
Dimensions in mm.
Fig.17. soldering pattern for surface mounting
SOT223.
PRINTED CIRCUIT BOARD
Dimensions in mm.
Fig.18. PCB for thermal resistance and power rating
for SOT223.
PCB: FR4 epoxy glass (1.6 mm thick), copper
laminate (35
µ
m thick).
36
60
9
10
4.6
18
4.5
7
15
50
3.8
min
6.3
2.3
4.6
1.5
min
1.5
min
1.5
min
(3x)
September 1995 6 Rev 1.200
Philips Semiconductors Product specification
PowerMOS transistor BUK583-60A
Logic level FET
MECHANICAL DATA
Dimensions in mm
Net Mass: 0.11 g
Fig.19. SOT223 surface mounting package.
Notes
1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent
damage to MOS gate oxide.
2. Refer to surface mounting instructions for SOT223 envelope.
3. Epoxy meets UL94 V0 at 1/8".
6.7
6.3
3.1
2.9
4
123
2.3
1.05
0.85 0.80
0.60
4.6
3.7
3.3 7.3
6.7
B
A
0.10
0.02
13
16
max
1.8
max
10
max
0.32
0.24
(4x) B
M
0.1
AM0.2
September 1995 7 Rev 1.200
Philips Semiconductors Product specification
PowerMOS transistor BUK583-60A
Logic level FET
DEFINITIONS
Data sheet status
Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
Philips Electronics N.V. 1996
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.
September 1995 8 Rev 1.200
