DW OR NT PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
OEA
A1
A2
A3
A4
A5
A6
A7
A8
ERR
CLR
GND
VCC
B1
B2
B3
B4
B5
B6
B7
B8
PARITY
OEB
LE
SCBS257 − SEPTEMBER 1987 − REVISED NOVEMBER 1993
Copyright 1993, Texas Instruments Incorporated
2−1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
•BiCMOS Process With TTL Inputs and
Outputs
•State-of-the-Art BiCMOS Design
Significantly Reduces Standby Current
•Flow-Through Pinout (All Inputs on
Opposite Side From Outputs)
•Functionally Equivalent to AMD Am29854
•High-Speed Bus Transceiver With Parity
Generator/Checker
•Parity-Error Flag With Open-Collector
Output
•Latch for Storage of the Parity-Error Flag
•Package Options Include Plastic
Small-Outline (DW) Packages and Standard
Plastic 300-mil DIPs (NT)
description
The SN74BCT29854 is an 8-bit to 9-bit parity transceiver designed for asynchronous communication between
data buses. When data is transmitted from the A to B bus, a parity bit is generated. When data is transmitted
from the B to A bus with its corresponding parity bit, the parity-error (ERR) output will indicate whether or not
an error in the B data has occurred. The output-enable (OEA, OEB) inputs can be used to disable the device
so that the buses are effectively isolated.
A 9-bit parity generator/checker generates a parity-odd (PARITY) output and monitors the parity of the I/O ports
with an open-collector parity-error (ERR) flag. ERR can be either passed, sampled, stored, or cleared from the
latch using the latch-enable (LE) and clear (CLR) control inputs. When both OEA and OEB are low, data is
transferred from the A bus to the B bus and inverted parity is generated. Inverted parity is a forced error condition
which gives the designer more system diagnostic capability. The SN74BCT29854 provides inverting logic.
The SN74BCT29854 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
INPUTS OUTPUT AND I/O
OEB OEA CLR LE Ai
∑of H’s Bi†
∑ of L’s A B PARITY ERR‡FUNCTION
L H X X Odd
Even NA NA A H
LNA A data to B bus and generate parity
H L X L NA Odd
Even B NA NA H
LB data to A bus and check parity
H L H H NA X X NA NA N−1 Store error flag
X X L H X X X NA NA H Clear error-flag register
H H
H
L
X
X
H
H
L
L
X
X
L Odd
H Even
X Z Z Z
NC
H
L
H
Isolation§
L L X X Odd
Even NA NA A L
HNA A data to B bus and generate inverted
parity
NA = not applicable, NC = no change, X = don’t care
†Summation of low-level inputs includes PARITY along with Bi inputs.
‡Output states shown assume the ERR output was previously high.
§In this mode, the ERR output, when enabled, shows noninverted parity of the A bus.
! " #$%! " &$'(#! )!%*
)$#!" # ! "&%##!" &% !+% !%" %," "!$%!"
"!)) -!.* )$#! &#%""/ )%" ! %#%""(. #($)%
!%"!/ (( &%!%"*
SCBS257 − SEPTEMBER 1987 − REVISED NOVEMBER 1993
2−2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
logic diagram (positive logic)
8x
EN
A1−A8
OEA
OEB
LE
CLR
G1
1
1
1
1MUX
2k
EN
8x B1−B8
PARIT
Y
ERR
88
8
8
8
9P
SCBS257 − SEPTEMBER 1987 − REVISED NOVEMBER 1993
2−3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
error-flag waveforms
Sample
Clear
StorePass
ERR
CLR
LE
Bi + PARITY
OEA
OEB
Even
H
Odd
L
H
L
H
L
H
L
H
L
ERROR-FLAG FUNCTION TABLE
INPUTS INTERNAL
TO DEVICE OUTPUT
PRESTATE OUTPUT
FUNCTION
LE CLR POINT P ERRn−1†ERR
FUNCTION
L L L
HXL
HPass
L H L
X
H
X
L
H
L
L
HSample
H L X X H Clear
H H X L
HL
HStore
†ERRn−1 represents the state of the ERR output before any changes at CLR, L E ,
or point P.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡
Supply voltage, VCC 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, VI7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage applied to a disabled I/O port 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
‡Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
SCBS257 − SEPTEMBER 1987 − REVISED NOVEMBER 1993
2−4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
recommended operating conditions
MIN NOM MAX UNIT
VCC Supply voltage 4.5 5 5.5 V
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
VOH High-level output voltage ERR 2.4 V
IOH High-level output current −24 mA
IOL Low-level output current 48 mA
TAOperating free-air temperature 0 70 °C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
VIK VCC = 4.5 V, II = −18 mA −1.2 V
VOH
All inputs/outputs except ERR
VCC = 4.5 V
IOH = −15 mA 2.4
V
VOH
All inputs/outputs except ERR
VCC = 4.5 V IOH = −24 mA 2V
IOH ERR VCC = 4.5 V, VOH = 2.4 V 20 µA
VOL VCC = 4.5 V, IOL = 48 mA 0.35 0.5 V
IIVCC = 5.5 V, VI = 5.5 V 0.1 mA
IIH‡VCC = 5.5 V, VI = 2.7 V 20 µA
IIL‡
Data
VCC = 5.5 V,
VI = 0.4 V
−0.2
mA
IIL
‡
Control VCC = 5.5 V, VI = 0.4 V −0.75 mA
IOS§VCC = 5.5 V, VO = 0 −75 −250 mA
ICCL VCC = 5.5 V, Outputs open 55 80 mA
ICCZ VCC = 5.5 V, Outputs open 30 45 mA
†All typical values are at VCC = 5 V, TA = 25°C.
‡These parameters include off-state output current for I/O ports only.
§Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
MIN MAX UNIT
tw
Pulse duration
LE low 10
ns
twPulse duration CLR low 10 ns
tsu Setup time before LE↓Bi and PARITY 18 ns
thHold time after LE↓Bi and PARITY 8 ns
SCBS257 − SEPTEMBER 1987 − REVISED NOVEMBER 1993
2−5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 50 pF (unless otherwise noted) (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 5 V,
TA = 25°C
MIN
MAX
UNIT
PARAMETER
(INPUT)
(OUTPUT)
MIN TYP MAX
MIN
MAX
UNIT
tPLH
A or B
B or A
1 5 7 1 8
ns
tPHL A or B B or A 1 5 7 1 8 ns
tPLH
A
PARITY
1.5 10 13 1.5 15
ns
tPHL A PARITY 1.5 10 13 1.5 15 ns
tPZH
OEA or OEB
A or B
2 12 15 2 17
ns
tPZL
OEA or OEB
A or B 2 13 16 2 19 ns
tPHZ
OEA or OEB
A or B
2 8 11 2 15
ns
tPLZ
OEA or OEB
A or B 2 10 14 2 17 ns
tPLH CLR
ERR
1.5 11 13 1.5 15
ns
tPHL LE ERR 1.5 5 7 1.5 9 ns
tPLH
OEA
PARITY
1.5 10 13 1.5 15
ns
tPHL
OEA
PARITY 1.5 10 13 1.5 16 ns
tPLH
Bi/PARITY
ERR
1.5 15 18 1.5 20
ns
tPHL
Bi/PARITY
ERR
1.5 10 13 1.5 15
ns
NOTE 1: Load circuits and voltage waveforms are shown in Section 1.
SCBS257 − SEPTEMBER 1987 − REVISED NOVEMBER 1993
2−6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
PACKAGE OPTION ADDENDUM
www.ti.com 18-Aug-2011
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
SN74BCT29854DW ACTIVE SOIC DW 24 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74BCT29854NT ACTIVE PDIP NT 24 15 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
SN74BCT29854NT ACTIVE PDIP NT 24 15 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
SN74BCT29854NTE4 ACTIVE PDIP NT 24 15 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
SN74BCT29854NTE4 ACTIVE PDIP NT 24 15 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
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