@ ECL 100K input and output levels @ Dual units with separate inputs and outputs @ Delays stable and precise @ 12-pin DIP package (.325 high) @ Available in delays from 2 to 20ns @ Output isolated and with 70 ECL DC fan-out capacity @ Rise time Ins nominal design notes The DIP Series Dual Logic Delay Lines developed by Engineered Components Company have been designed to provide precise delays with required driving and pick-off circuitry con- tained in a 12-pin DIP package compatible with ECL 100K Series ar 10,000 Series circuitry. The design includes com- pensatian for propagation delays and incorporates internal term- ination at the output; mo additional external campanents are needed to obtain the desired delay. These modules accept either logic 1" of logic O" inputs and reproduce the logic at the output without inversian, The delay lines are intended primarily for use with positive going pulses and are calibrated ta the tolerances shown in the table on rising edge delay; where best accuracy is desired in applications using falling edge timing, it is recarmmended that a special unit be calibrated for the specific application. All modules can be driven from a standard ECL gate with an external pull-down resistor of 50 or 100 ohms to -2V or 470 ohms to 4.5V. Qutput is standard ECL 100K open emitter. Each module has the capability of driving up ta 70 ECL DC loads. 2 Z engineered components company low profile ECL 100K COMPATIBLE _ DUAL LOGIC DELAY LINE The DECLDL is offered in 32 delays from 2? to 20ns, Each madule includes two (2) separate delay lines, each isolated and fully buffered, Delay tolerances are maintained as shawn in the accompanying Part Number Table, when tested under the Test Conditions shown, Delay time is measured at the -1.3V level on the leading edge; rise time is 2ns maximum, when measured fram 20% to 80% pulse amplitude. Temperature coefficient of delay is less than 150 pprn/"C over the operating ternperature range of O to +85C. These modules are of hybrid construction utilizing the proven technologies of active integrated circuitry and of passive networks Utilizing capacitive, inductive and resistive elements. The ICs utilized in these modules are burned-in to Level B of MIL-STD- 883 to ensure a high MTBF. The MTBF on these modules, when calculated per MIL-HDBK-217 for a 50C ground fixed environ- rent, is in excess of 1 million hours, The DIP Series Logic Delay Lines are packaged in a 12-pin DIP housing, molded of flame-proof Diallyl Phthalate per MIL-M- 14, Type SOG-F, and are fully encapsulated in epoxy resin. Leads meet the solderability requirements of MIL-STD-202, Methad 208, Corner standoffs on the housing provide positive standoff fram the printed circuit board to permit solder-fillet formation and flush cleaning of solder-flux residues for improved reliability. Marking consists of manufacturer's name, logo (EC2}, part number, terminal identification and date code of manufacture. All marking is applied by silk screen process using white epoxy paint in accordance with MIL-STD-130 to meet the permanency of identification required by MIL-STD-202, Method 215. 3580 Sacramento Drive, P. 0. Box 8121, San Luis Obispo, CA 93403-8121 Phone: (805) 544-3800BLOCK DIAGRAM IS SHOWN BELOW IN4 Vee OUT, OUT 4 12 Q 8 7 c aa a aa Neer asa x Y : x | ECL 100K ECL 100K l INPUT Bae: OUTRUT | BUFFER BUFFER | | xy xy | ECL100K ECL 100K | INPUT ee RL ouTPUT | | BUFFER BUFFER | Y 1 4 5 6 IN9 Veo OUT OUT? MECHANICAL DETAIL IS SHOWN BELOW perro INy V_OUT, OUT, B75 @DECLDL-2-__ iN> VOUTZOUT, 1 7 | 8432 30 325 MADE IN SLO USA I ij , | L 160+.030 LN OO ced) Lge lL I TYP, 020 DIA. TYP, 100 TYP, = bay Tee | (** TYP. ! * Supply valtage: + + = OPERATING SPECIFICATIONS Logic 1 Input at 25C: Voltage - Current + Lagic O Input at25 C: Voltage Current Logic 1 Output at 25 C: Logic O Qutput at 25C: + +-- Operating temperature range: Storage temperature: = + 155ma typical - 1.165 min. 350ua max. .5Ua min. = 1.025 min. Hae = 1.620 max. Oto +85C -55 to +125 C * Delays increase ar decrease less than .5% for a respective increase or decrease of 5% in supply voltage. PART NUMBER TABLE # DELAYS AND TOLERANCES (in ns) [ o 8 o o oa Sg ae | FOO o 250 TYP.+| TEST CONDITONS 1. All measurements are made at 25C. | 2. Vee supply voltage is maintained at 4.6V DC. 3. All units are tested using a positive input pulse provided by a standard open emitter ECL 100K gate. The input and output utilizes a 50 ohm pull-down resistor to - 2; the output is alsa loaded with ane ECL 100K gate. m4, module under test; spacing between pulses [falling edge to rising edge) is three times the pulse width used, Input pulse width used ig 5 to 10ns longer than full delay of -4.5V 45% to Vee - 1475 max. PART NO. OUTPUT || PART NO. OUTPUT DECLDL- 2-2 2t.2 DECGLDL- 2-10 10+1 DECLDL-?2- 2.5 2.54.2 DECLDL-2- 10.5 10.521 DECLDOL-2-3 34.3 DECLDBL-2-11 1144 DECLDL=2-3.5 3.54.3 DECLDBL-2-11.5 11.541 DECLDL-2-4 4.4 DECLBL- 2-12 1241 DECLDL=2-4,5 4.52.4 DECLDOL-2- 12.5 12.541 DECLDL- 2-5 61.5 DECLOL-2- 13 1321 DECLDL-2-5.5 5.54.5 DECLDL=2- 13.5 13.521 DECLDL- 2-6 64.6 DECLDL- 2-14 1441 DECLDL-2- 6.5 6.54.6 DECLDL-2- 14.5 14.541 DECLDL-2-7 TtF |] DECLDL- 2-15 1541 DECLDL-2- 7.5 7.54.7 |/DECLDL- 2-16 1641 DECLDL-2-8 6+.8 DECLDL- 2-17 +1 DECLDL-2- 8.5 8.54.8 DECLDL-2- 18 18+1 DECLDL-2-9 O+,9 DECLDL-=2- 19 1921 DECLDL-2-9.5 9,5+,9 DECLBOL- 2-20 20% 1 All modules can be operated with a minimum input pulse width of 100% of full delay and pulse period approaching square wave; since delay accuracies may be somewhat degraded, it is suggested that the module be evaluated under the intended specific oper- ating conditions. Special modules can be readily manufactured to improve accuracies and/or provide customer specified random delay times for specific applications, Catalog No. C/012580