
4White Paper
1743A–04/01
memory blocks (both on- and off-chip). The AMBA Bridge links this to a lower-speed
APB, which minimizes power consumption in data transfers to and from the peripherals.
The AT91 series surrounds the ARM core with an SRAM workspace, External Bus Inter-
face and a set of general-purpose peripherals. These include an Advanced Interrupt
Controller, USARTs, Timer/Counters, SPI, Watchdog Timer, Real Time Clock, etc. Fig-
ure 1 shows the peripherals for the entry-level AT91R40807. The modular design
enables power consumption to be minimized in every aspect of the operation of the
device, under all scenarios of use.
Fully Static Operation All AT91 devices are fully static, driven by a single system clock. The operational power
consumption is proportional to the clock frequency. Power can be saved at device level
by stopping the clock externally, or running it at the slowest rate required to complete a
task in the time interval available. A common practice is to accomplish each task at full
clock speed, and then stop the clock until the device is next required. With the external
clock disabled, an AT91 device consumes between 30 and 60 µA.
Low Voltage
Operation
The AT91 devices normally operate at 3.3V, but they can be powered down to 1.8V and
still deliver the performance required for most power-sensitive applications. The I/Os
continue to operate at 3.3V – all internal level shifting is transparent to the environment
of the system. This gives a power saving of around 35%.
Power-saving SRAM The large on-chip SRAM (up to 136K bytes in the case of the AT91R40807) significantly
reduces system power consumption compared with a two-ship solution. For example,
an AT91M40800 operating at 40 MHz with an external 12 ns SRAM consumes 120 mA.
The AT91R40807 under the same conditions consumes only 50 mA.
Power Reduction
during Interrupts and
Data Transfer
Two architectural features play significant roles in reducing power consumption during
operation: the Advanced Interrupt Controller and the Peripheral Data Controller chan-
nels associated with the on-chip peripherals.
The 8-level priority Advanced Interrupt Controller intercepts all internal and external
interrupt requests, prioritizes them, associates them with the corresponding interrupt
vector and passes them to the core when they are scheduled for handling. It reduces the
number of core instructions required to reach the interrupt handler to only one. In real-
time interrupt driven systems (the majority of hand-held devices are in this category) this
represents a major saving of processor cycles, and hence of power.
The integral Peripheral Data Controller provides a direct memory access (DMA) function
between on-chip peripherals such as the USART, SPI or DAC and the system memory
(on- or off-chip). The PDC does not use any processor resources, allowing the proces-
sor to be put into idle mode during data transfers. With a capacity of up to 64K
contiguous bytes from the same start address, it significantly reduces power consump-
tion during data transfer.