D−14
N−14
RSA−16
1
FEATURES
DESCRIPTION
1
2
3
4
5
6
7
14
13
12
11
10
9
8
NC
R
RE
DE
D
GND
GND
VCC
VCC
A
B
Z
Y
NC
DORNPACKAGE
(TOP VIEW)
NC − Nointernalconnection
logic diagram(positivelogic)
R
RE
D
DE
B
A
Z
Y
11
12
10
9
2
3
5
4
16 15 14 13
5678
1
2
3
4
12
11
10
9
A
B
Z
Y
NC
R
RE
DE
NC
NC
GND
NC
V
V
D
GND
RSA PACKAGE
(TOP VIEW)
CC
CC
Pins6and7areconnectedtogetherinternally
Pins13and14areconnectedtogetherinternally
SN55LBC180
SN65LBC180
SN75LBC180
www.ti.com
................................................................................................................................................... SLLS174G – FEBRUARY 1994 – REVISED APRIL 2009
LOW-POWER RS-485 LINE DRIVER AND RECEIVER PAIRS
2
•Designed for High-Speed Multipoint DataTransmission Over Long Cables•Operate With Pulse Durations as Low as 30 ns•Low Supply Current . . . 5 mA Max•Meet or Exceed the Requirements of ANSIStandard RS-485 and ISO 8482:1987(E)•3-State Outputs for Party-Line Buses•Common-Mode Voltage Range of – 7 V to 12 V•Thermal Shutdown Protection PreventsDriver Damage From Bus Contention•Positive and Negative Output CurrentLimiting
•Pin Compatible With the SN75ALS180
The SN55LBC180, SN65LBC180 and SN75LBC180differential driver and receiver pairs are monolithicintegrated circuits designed for bidirectional datacommunication over long cables that take on thecharacteristics of transmission lines. They arebalanced, or differential, voltage mode devices thatmeet or exceed the requirements of industrystandards ANSI RS-485 and ISO 8482:1987(E).These devices are designed using TI ' s proprietaryLinBiCMOS™ with the low-power consumption ofCMOS and the precision and robustness of bipolartransistors in the same circuit.
this deviceinfo section is for space between the para and table
ORDERING INFORMATION
T
A
PACKAGE PART NUMBER PART MARKING
PDIP SN75LBC180N SN75LBC180N0 ° C to 70 ° C SOIC SN75LBC180D 7LB180QFN SN75LBC180RSA LB180PDIP SN65LBC180N 65LBC180N– 40 ° C to 85 ° C SOIC SN65LBC180D 6LB180QFN SN65LBC180RSA BL180– 55 ° C to 125 ° C QFN SN55LBC180RSA SN55LBC180
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2LinBiCMOS is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 1994 – 2009, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
DESCRIPTION (CONTINUED)
SN55LBC180
SN65LBC180
SN75LBC180
SLLS174G – FEBRUARY 1994 – REVISED APRIL 2009 ...................................................................................................................................................
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.
The SN55LBC180, SN65LBC180 and SN75LBC180 combine a differential line driver and receiver with 3-stateoutputs and operate from a single 5-V supply. The driver and receiver have active-high and active-low enables,respectively, which can be externally connected to function as a direction control. The driver differential outputsand the receiver differential inputs are connected to separate terminals for full-duplex operation and are designedto present minimum loading to the bus whether disabled or powered off (V
CC
= 0). These parts feature a widecommon-mode voltage range making them suitable for point-to-point or multipoint data-bus applications.
The devices also provide positive and negative output-current limiting and thermal shutdown for protection fromline fault conditions. The line driver shuts down at a junction temperature of approximately 172 ° C.
The SN75LBC180 is characterized for operation over the commercial temperature range of 0 ° C to 70 ° C. TheSN65LBC180 is characterized over the industrial temperature range of – 40 ° C to 85 ° C.
The SN55LBC180 is characterized for operation over the military temperature range of – 55 ° C to 125 ° C.
FUNCTION TABLES
(1)
DRIVER
INPUT ENABLE OUTPUTSD DE
Y Z
H H H LL H L HX L Z Z
RECEIVER
DIFFERENTIAL INPUTS ENABLE OUTPUTA – B RE R
V
ID
≥0.2 V L H– 0.2 V < V
ID
< 0.2 V L ?V
ID
≤– 0.2 V L LX H ZOpen circuit L H
(1) H = high level, L = low level, ? = Indeterminate, X = irrelevant,Z = high impedance (off)
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Product Folder Link(s): SN55LBC180 SN65LBC180 SN75LBC180
ABSOLUTE MAXIMUM RATINGS
(1)
DISSIPATION RATING TABLE
RECOMMENDED OPERATING CONDITIONS
SN55LBC180
SN65LBC180
SN75LBC180
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................................................................................................................................................... SLLS174G – FEBRUARY 1994 – REVISED APRIL 2009
UNIT
V
CC
Supply voltage range
(2)
– 0.3 to 7 VV
BUS
Bus voltage range (A, B, Y, Z)
(2)
– 10 to 15 VVoltage range at D, R, DE, RE
(2)
– 0.3 to V
CC
+ 0.5 VContinuous total power dissipation
(3)
Internally limitedTotal power dissipation See Dissipation Rating TableT
stg
Storage temperature range – 65 to 150 ° CI
O
Receiver output current range – 50 to 50 mAHBM (Human Body Model) EIA/JESD22-A114 ± 4 kVESD Electrostatic discharge MM (Machine Model) EIA/JESD22-A115 400 VCDM (Charge Device Model) EIA/JESD22-C101 1.5 kV
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) All voltage values are with respect to GND.(3) The maximum operating junction temperature is internally limited. Use the dissipation rating table to operate below this temperature.
T
A
≤25 ° C DERATING FACTOR T
A
= 70 ° C T
A
= 85 ° C T
A
= 125 ° CPACKAGE
(1)
POWER RATING ABOVE T
A
= 25 ° C POWER RATING POWER RATING POWER RATING
D 950 mW 7.6 mW/ ° C 608 mW 494 mW —N 1150 mW 9.2 mW/ ° C 736 mW 598 mW —RSA 3333 mW 26.67 mW/ ° C 2133 mW 1733 mW 400 mW
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TIWeb site at www.ti.com .
MIN NOM MAX UNIT
V
CC
Supply voltage 4.75 5 5.25 VV
IH
High-level input voltage D, DE, and RE 2 VV
IL
Low-level input voltage D, DE, and RE 0.8 VV
ID
Differential input voltage – 6
(1)
6 VV
O
, V
I
, or V
IC
Voltage at any bus terminal (separately or common mode) A, B, Y, or Z – 7
(1)
12 VY or Z – 60I
OH
High-level output current mAR – 8Y or Z 60I
OL
Low-level output current mAR 8SN55LBC180 – 55 125T
A
Operating free-air temperature SN65LBC180 – 40 85 ° CSN75LBC180 0 70
(1) The algebraic convention where the least positive (more negative) limit is designated minimum, is used in this data sheet for thedifferential input voltage, voltage at any bus terminal, operating temperature, input threshold voltage, and common-mode output voltage.
Copyright © 1994 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s): SN55LBC180 SN65LBC180 SN75LBC180
DRIVER SECTION
ELECTRICAL CHARACTERISTICS
SWITCHING CHARACTERISTICS
SWITCHING CHARACTERISTICS (SN55LBC180)
SN55LBC180
SN65LBC180
SN75LBC180
SLLS174G – FEBRUARY 1994 – REVISED APRIL 2009 ...................................................................................................................................................
www.ti.com
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
V
IK
Input clamp voltage I
I
= -18 mA – 1.5 VSN55LBC180 1 2.5 5R
L
= 54 Ω,
SN65LBC180 1.1 2.5 5See Figure 1
SN75LBC180 1.5 2.5 5| V
OD
| Differential output voltage magnitude
(2)
VSN55LBC180 1 2.5 5R
L
= 60 Ω,
SN65LBC180 1.1 2 5See Figure 2
SN75LBC180 1.5 2 5
Δ| V
OD
| Change in magnitude of differential output voltage
(3)
See Figure 1 and Figure 2 ± 0.2 VV
OC
Common-mode output voltage 1 2.5 3 VR
L
= 54 Ω, See Figure 1Change in magnitude of common-mode outputΔ| V
OC
| ± 0.2 Vvoltage
(3)
I
O
Output current with power off V
CC
= 0, V
O
= – 7 V to 12 V ± 100 µAI
OZ
High-impedance-state output current V
O
= – 7 V to 12 V ± 100 µAI
IH
High-level input current V
I
= 2.4 V 100 µAI
IL
Low-level input current V
I
= 0.4 V 100 µAI
OS
Short-circuit output current – 7 V ≤V
O
≤12 V ± 250 mAOutputs enabled 5I
CC
Supply current Receiver disabled mAOutputs disabled 3
(1) All typical values are at V
CC
= 5 V and T
A
= 25 ° C.(2) The minimum V
OD
specification may not fully comply with ANSI RS-485 at operating temperatures below 0 ° C. System designers shouldtake the possibly lower output signal into account in determining the maximum signal-transmission distance.(3) Δ|V
OD
| and Δ|V
OC
| are the changes in the steady-state magnitude of V
OD
and V
OC
, respectively, that occur when the input is changedfrom a high level to a low level.
V
CC
= 5 V, T
A
= 25 ° C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
d(OD)
Differential output delay time 7 12 18 nsR
L
= 54 Ω, See Figure 3t
t(OD)
Differential output transition time 5 10 20 nst
PZH
Output enable time to high level R
L
= 110 Ω, See Figure 4 35 nst
PZL
Output enable time to low level R
L
= 110 Ω, See Figure 5 35 nst
PHZ
Output disable time from high level R
L
= 110 Ω, See Figure 4 50 nst
PLZ
Output disable time from low level R
L
= 110 Ω, See Figure 5 35 ns
V
CC
= 5 V, T
A
= 25 ° C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
d(OD)
Differential output delay time 15 nsR
L
= 54 Ω, See Figure 3t
t(OD)
Differential output transition time 21 nst
PZH
Output enable time to high level 32R
L
= 110 Ω, See Figure 4 nst
PHZ
Output disable time from high level 55t
PZL
Output enable time to low level 32R
L
= 110 Ω, See Figure 5 nst
PLZ
Output disable time from low level 20
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Product Folder Link(s): SN55LBC180 SN65LBC180 SN75LBC180
RECEIVER SECTION
ELECTRICAL CHARACTERISTICS
SWITCHING CHARACTERISTICS
SWITCHING CHARACTERISTICS (SN55LBC180)
SN55LBC180
SN65LBC180
SN75LBC180
www.ti.com
................................................................................................................................................... SLLS174G – FEBRUARY 1994 – REVISED APRIL 2009
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
IT+
Positive-going input threshold voltage I
O
= – 8 mA 0.2 VV
IT –
Negative-going input threshold voltage I
O
= 8 mA – 0.2 VV
hys
Hysteresis voltage (V
IT+
– V
IT –
) 45 mVV
IK
Enable-input clamp voltage I
I
= – 18 mA -1.5 VV
OH
High-level output voltage V
ID
= 200 mV, I
OH
= – 8 mA 3.5 4.5 VV
OL
Low-level output voltage V
ID
= – 200 mV, I
OL
= 8 mA 0.3 0.5 VI
OZ
High-impedance-state output current V
O
= 0 V to V
CC
± 20 µAI
IH
High-level enable-input current V
IH
= 2.4 V – 50 AI
IL
Low-level enable-input current V
IL
= 0.4 V – 100 µAV
I
= 12 V, V
CC
= 5 V, Other input at 0 V 0.7 1V
I
= 12 V, V
CC
= 0 V, Other input at 0 V 0.8 1I
I
Bus input current mAV
I
= -7 V, V
CC
= 5 V, Other input at 0 V – 0.8 -0.5V
I
= -7 V, V
CC
= 0 V, Other input at 0 V – 0.8 – 0.5Outputs enabled 5I
CC
Supply current Driver disabled mAOutputs disabled 3
V
CC
= 5 V, T
A
= 25 ° C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
PHL
Propagation delay time, high- to low-level output 11 22 33 nst
PLH
Propagation delay time, low- to high-level output 11 22 33 nsV
ID
= – 1.5 V to 1.5 V, See Figure 6t
sk(p)
Pulse skew (| t
PHL
– t
PLH
|) 3 6 nst
t
Transition time 5 8 nst
PZH
Output enable time to high level 35 nst
PZL
Output enable time to low level 30 nsSee Figure 7t
PHZ
Output disable time from high level 35 nst
PLZ
Output disable time from low level 30 ns
V
CC
= 5 V, T
A
= 25 ° C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
PHL
Propagation delay time, high- to low-level output 26 nst
PLH
Propagation delay time, low- to high-level output 23 nsV
ID
= – 1.5 V to 1.5 V, See Figure 6t
sk(p)
Pulse skew (| t
PHL
– t
PLH
|) 3 nst
sk(p)t
Transition time 4 nst
PZH
Output enable time to high level 30 nst
PHZ
Output disable time from high level 26 nsSee Figure 4t
PZL
Output enable time to low level 30 nst
PLZ
Output disable time from low level 30 ns
Copyright © 1994 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): SN55LBC180 SN65LBC180 SN75LBC180
PARAMETER MEASUREMENT INFORMATION
VOD
VOC
RL
2
RL
2
0 V or 3 V
Z
D
DE at 3 V
Y
VOD
Vtest
R1
375 Ω
0 V or 3 V
Z
D
DE at 3 V R2
375 Ω
Vtest
Y
RL = 60 Ω
–7 V < Vtest < 12 V
0 V
3 V
tt(OD)
tt(OD)
1.5 V
td(OD)
50%
Output
Input
TEST CIRCUIT VOLTAGE WAVEFORMS
td(OD)
RL = 54 Ω
CL = 50 pF
(see Note B) Output
Generator
(see Note A) 50 Ω
1.5 V 1.5 V
50% ≈ 2.5 V
≈ – 2.5 V
Z
Y
DE at 3 V
90%
10%
10%
90%
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR > 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO= 50 Ω.
B. CL includes probe and jig capacitance.
SN55LBC180
SN65LBC180
SN75LBC180
SLLS174G – FEBRUARY 1994 – REVISED APRIL 2009 ...................................................................................................................................................
www.ti.com
Figure 1. Differential and Common-Mode Output Voltages
Figure 2. Driver V
OD
Test Circuit
Figure 3. Driver Test Circuit and Differential Output Delay and Transition Time Voltage Waveforms
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Product Folder Link(s): SN55LBC180 SN65LBC180 SN75LBC180
TEST CIRCUIT VOLTAGE WAVEFORMS
1.5 V
VOH
tPHZ
tPZH
0 V
3 V
1.5 V
2.3 V
Output
Input
Output
S1
0 V or 3 V
RL = 110 Ω
50 ΩVoff ≈ 0
0.5 V
DY
Z
DE
Input
Generator
(see Note A)
CL = 50 pF
(see Note B)
Output
TEST CIRCUIT VOLTAGE WAVEFORMS
VOL
tPLZ
tPZL
5 V
0.5 V
2.3 V
0 V
3 V
1.5 V1.5 V
5 V
Output
Input
S1
0 V or 3 V
50 Ω
RL = 110 Ω
DY
Z
DE
Input
Generator
(see Note A)
CL = 50 pF
(see Note B)
TEST CIRCUIT VOLTAGE WAVEFORMS
VOL
VOH
3 V
0 V
tPHL
tPLH
Output
Input 1.5 V
1.3 V
1.5 V
1.3 V
50 ΩOutput
0 V
1.5 V
Generator
(see Note A)
A
BRE
R
10%
90%90%
10%
tttt
Input
CL = 15 pF
(see Note B)
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO= 50 Ω.
B. CL includes probe and jig capacitance.
SN55LBC180
SN65LBC180
SN75LBC180
www.ti.com
................................................................................................................................................... SLLS174G – FEBRUARY 1994 – REVISED APRIL 2009
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 4. Driver Test Circuit and Enable and Disable Time Waveforms
Figure 5. Driver Test Circuit and Enable and Disable Time Voltage Waveforms
Figure 6. Receiver Test Circuit and Propagation Delay Time Voltage Waveforms
Copyright © 1994 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Link(s): SN55LBC180 SN65LBC180 SN75LBC180
SN55LBC180
SN65LBC180
SN75LBC180
SLLS174G – FEBRUARY 1994 – REVISED APRIL 2009 ...................................................................................................................................................
www.ti.com
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 7. Receiver Output Enable and Disable Times
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TYPICAL CHARACTERISTICS
SCHEMATICS OF INPUTS AND OUTPUTS
RECEIVERAINPUTEQUIVALENTOFD,DE,ANDRE INPUTS
RECEIVERBINPUT DRIVEROUTPUT TYPICALOFRECEIVEROUTPUT
Output
VCC
VCC
100kΩ
NOM
3kΩ
NOM
Input
18kΩ
NOM
1.1kΩ
NOM
1.1kΩ
NOM
3kΩ
NOM
18kΩ
NOM
100kΩ
NOM
Input
VCC
Input
VCC
22kΩ
VCC
ROutput
12kΩ
12kΩ
SN55LBC180
SN65LBC180
SN75LBC180
www.ti.com
................................................................................................................................................... SLLS174G – FEBRUARY 1994 – REVISED APRIL 2009
Copyright © 1994 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Link(s): SN55LBC180 SN65LBC180 SN75LBC180
2.5
1.5
1
00 10 20 30
− High-Level Output Voltage − V
3.5
4
5
40 50 60
VOH
IOH − High-Level Output Current − mA
4.5
3
2
0.5
VCC = 5 V
TA = 25°C
70 80 90 100
2.5
1.5
1
00 20 40 60
− Low-Level Output Voltage − V
3.5
4
5
80 100 120
VOL
IOL − Low-Level Output Current − mA
4.5
3
2
0.5
VCC = 5 V
TA = 25°C
-60 -40 -20 0 20 40 60 80 100 120
T - AmbientTemperature-°C
A
1.5
1.6
1.7
1.8
1.9
2
2.1
2.2
2.3
2.4
V -DriverOutputVoltage-V
OD
2
1.5
0.5
00 10 20 30 40 50 60
− Differential Output Voltage − V
2.5
3.5
4
70 80 90 100
1
3
VCC = 5 V
TA = 25°C
VOD
IO − Output Current − mA
SN55LBC180
SN65LBC180
SN75LBC180
SLLS174G – FEBRUARY 1994 – REVISED APRIL 2009 ...................................................................................................................................................
www.ti.com
DRIVER DRIVERHIGH-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT VOLTAGEvs vsHIGH-LEVEL OUTPUT CURRENT LOW-LEVEL OUTPUT CURRENT
Figure 8. Figure 9.
DRIVER DRIVERDIFFERENTIAL OUTPUT VOLTAGE DIFFERENTIAL OUTPUT VOLTAGEvs vsOUTPUT CURRENT FREE-AIR TEMPERATURE
Figure 10. Figure 11.
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Product Folder Link(s): SN55LBC180 SN65LBC180 SN75LBC180
6
8
10
12
14
16
18
20
-60 -40 -20 0 20 40 60 80 100 120
T - AmbientTemperature-°C
A
DriverOutputVoltage-ns
VCC − Supply V oltage − V
60
40
20
0
−20
−40
−60
654321
−80
80
0
RL = 54 Ω
− Output Current − mA
IO
IOL
IOH
0.3
0.2
0.1
00 5 10
− Low-Level Output Voltage − V
0.4
0.5
0.6
15 20 25 30
IOL − Low-Level Output Current − mA
VOL
VCC = 5 V
TA = 25°C
VID = − 200 mV
0.7
0.8
0.9
1
35 40
2
1
00 −10 − 20 − 30
− High-Level Output Voltage − V
3
4
5
− 40 − 50
IOH − High-Level Output Current − mA
VOH
6VID = 200 mV
SN55LBC180
SN65LBC180
SN75LBC180
www.ti.com
................................................................................................................................................... SLLS174G – FEBRUARY 1994 – REVISED APRIL 2009
DRIVER DRIVERDIFFERENTIAL DELAY TIMES OUTPUT CURRENTvs vsFREE-AIR TEMPERATURE SUPPLY VOLTAGE
Figure 12. Figure 13.
RECEIVER RECEIVERHIGH-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT VOLTAGEvs vsHIGH-LEVEL OUTPUT CURRENT LOW-LEVEL OUTPUT CURRENT
Figure 14. Figure 15.
Copyright © 1994 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Link(s): SN55LBC180 SN65LBC180 SN75LBC180
2
1
0
− Output Voltage − V
3
4
5
VID − Differential Input Voltage − mV
VO
− 80 − 60 − 40 − 20 0 20 40 60 80
6
VIC = 12 V
VIC = 0 V
VIC = −7 V
40
5
25
15
0
50
30
10 k 100 k 1 M 10 M 100 M
45
10
20
35
f − Frequency − Hz
− Average Supply Current − mAICC
60
55 TA = 25°C
VCC = 5 V
DRVR and RCVR Enabled
Driver Load = Receiver Inputs
Receiver Load = 50 pF
20
21
22
23
24
25
26
27
28
29
30
-60 -40 -20 0 20 40 60 80 100 120
T - AmbientTemperature-°C
A
ReceiverOutputDelay-ns
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
− 0.4
− 0.6
− 0.8
− 1
− 8 − 6 − 4 − 2 0 2
− Bus Input Current − mA
− 0.2
0
0.2
4 6 8 10 12
0.4
0.6
0.8
II
VI − Input Voltage − V
1TA = 25°C
VCC = 5 V
The shaded region of this graph represents
more than 1 unit load per RS-485.
SN55LBC180
SN65LBC180
SN75LBC180
SLLS174G – FEBRUARY 1994 – REVISED APRIL 2009 ...................................................................................................................................................
www.ti.com
RECEIVER
OUTPUT VOLTAGE AVERAGE SUPPLY CURRENTvs vsDIFFERENTIAL INPUT VOLTAGE FREQUENCY
Figure 16. Figure 17.
RECEIVER
BUS INPUT CURRENT RECEIVERvs PROPAGATION DELAY TIMEINPUT VOLTAGE vs(COMPLEMENTARY INPUT AT 0 V) FREE-AIR TEMPERATURE
Figure 18. Figure 19.
12 Submit Documentation Feedback Copyright © 1994 – 2009, Texas Instruments Incorporated
Product Folder Link(s): SN55LBC180 SN65LBC180 SN75LBC180
APPLICATION INFORMATION
Master Node
Slave Node Slave Node Slave Node
SN55LBC180
SN65LBC180
SN75LBC180
www.ti.com
................................................................................................................................................... SLLS174G – FEBRUARY 1994 – REVISED APRIL 2009
Figure 20. Full Duplex Application Circuit
Copyright © 1994 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Link(s): SN55LBC180 SN65LBC180 SN75LBC180
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
SN55LBC180RSAR ACTIVE QFN RSA 16 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
SN55LBC180RSAT ACTIVE QFN RSA 16 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
SN65LBC180D ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LBC180DG4 ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LBC180DR ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LBC180DRG4 ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LBC180N ACTIVE PDIP N 14 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
SN65LBC180NE4 ACTIVE PDIP N 14 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
SN65LBC180RSAR ACTIVE QFN RSA 16 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
SN65LBC180RSARG4 ACTIVE QFN RSA 16 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
SN65LBC180RSAT ACTIVE QFN RSA 16 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
SN65LBC180RSATG4 ACTIVE QFN RSA 16 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
SN75LBC180D ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75LBC180DG4 ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75LBC180DR ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75LBC180DRG4 ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75LBC180N ACTIVE PDIP N 14 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
SN75LBC180NE4 ACTIVE PDIP N 14 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
SN75LBC180RSAR ACTIVE QFN RSA 16 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
SN75LBC180RSARG4 ACTIVE QFN RSA 16 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
SN75LBC180RSAT ACTIVE QFN RSA 16 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
SN75LBC180RSATG4 ACTIVE QFN RSA 16 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
PACKAGE OPTION ADDENDUM
www.ti.com 17-Jul-2009
Addendum-Page 1
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN55LBC180, SN65LBC180, SN75LBC180 :
•Automotive: SN65LBC180-Q1
NOTE: Qualified Version Definitions:
•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
PACKAGE OPTION ADDENDUM
www.ti.com 17-Jul-2009
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN55LBC180RSAR QFN RSA 16 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
SN55LBC180RSAT QFN RSA 16 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
SN65LBC180DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN65LBC180RSAR QFN RSA 16 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
SN65LBC180RSAT QFN RSA 16 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
SN75LBC180DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN75LBC180RSAR QFN RSA 16 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
SN75LBC180RSAT QFN RSA 16 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN55LBC180RSAR QFN RSA 16 3000 367.0 367.0 35.0
SN55LBC180RSAT QFN RSA 16 250 210.0 185.0 35.0
SN65LBC180DR SOIC D 14 2500 333.2 345.9 28.6
SN65LBC180RSAR QFN RSA 16 3000 367.0 367.0 35.0
SN65LBC180RSAT QFN RSA 16 250 210.0 185.0 35.0
SN75LBC180DR SOIC D 14 2500 333.2 345.9 28.6
SN75LBC180RSAR QFN RSA 16 3000 367.0 367.0 35.0
SN75LBC180RSAT QFN RSA 16 250 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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