MC74HCT74AD - ON Semiconductor - Datasheet.Directory

October, 2006 − Rev. 10

1Publication Order Number:

MC74HCT74A/D

MC74HCT74A

Dual D Flip−Flop with Set

and Reset with LSTTL

Compatible Inputs

High−Performance Silicon−Gate CMOS

The MC74HCT74A is identical in pinout to the LS74. This device

may be used as a level converter for interfacing TTL or NMOS outputs

to High Speed CMOS inputs.

This device consists of two D flip−flops with individual Set, Reset,

and Clock inputs. Information at a D−input is transferred to the

corresponding Q output on the next positive going edge of the clock

input. Both Q and Q outputs are available from each flip−flop. The Set

and Reset inputs are asynchronous.

Features

•Output Drive Capability: 10 LSTTL Loads

•TTL NMOS Compatible Input Levels

•Outputs Directly Interface to CMOS, NMOS, and TTL

•Operating Voltage Range: 4.5 to 5.5 V

•Low Input Current: 1.0 mA

•In Compliance With the JEDEC Standard No. 7.0 A Requirements

•Chip Complexity: 136 FETs or 34 Equivalent Gates

•Pb−Free Packages are Available

LOGIC DIAGRAM

RESET 1

DATA 1

CLOCK 1

SET 1

RESET 2

DATA 2

CLOCK 2

SET 2

PIN 14 = VCC

PIN 7 = GND

ÎÎÎÎÎÎÎÎÎÎ

Design Criteria

ÎÎÎÎ

Value

ÎÎÎ

Units

ÎÎÎÎÎÎÎÎÎÎ

Internal Gate Count†

ÎÎÎÎ

ÎÎÎ

ea.

ÎÎÎÎÎÎÎÎÎÎ

Internal Gate Propagation Delay

ÎÎÎÎ

1.5

ÎÎÎ

ÎÎÎÎÎÎÎÎÎÎ

Internal Gate Power Dissipation

ÎÎÎÎ

5.0

ÎÎÎ

ÎÎÎÎÎÎÎÎÎÎ

Speed Power Product

ÎÎÎÎ

.0075

ÎÎÎ

†Equivalent to a two−input NAND gate.

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MARKING

DIAGRAMS

A = Assembly Location

L, WL = Wafer Lot

Y, YY = Year

W, WW = Work Week

G= Pb−Free Package

SOIC−14

D SUFFIX

CASE 751A

HCT74AG

AWLYWW

PDIP−14

N SUFFIX

CASE 646

MC74HCT74AN

AWLYYWWG

See detailed ordering and shipping information in the package

dimensions section on page 3 of this data sheet.

ORDERING INFORMATION

PIN ASSIGNMENT

SET 1

CLOCK 1

DATA 1

RESET 1

105

SET 2

CLOCK 2

DATA 2

RESET 2

VCC

GND

FUNCTION TABLE

Inputs Outputs

Set Reset Clock Data Q Q

LH XX HL

HL XX LH

L L X X H* H*

HH H HL

HH L LH

H H L X No Change

H H H X No Change

H H X No Change

*Both outputs will remain high as long as Set and

Reset are low, but the output states are unpredict-

able if Set and Reset go high simultaneously.

MC74HCT74A

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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

MAXIMUM RATINGS

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎ

Value

ÎÎÎ

Unit

ÎÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Voltage (Referenced to GND)

ÎÎÎÎÎ

– 0.5 to + 7.0

ÎÎÎ

ÎÎÎÎ

Vin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Voltage (Referenced to GND)

ÎÎÎÎÎ

– 0.5 to VCC + 0.5

ÎÎÎ

ÎÎÎÎ

Vout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Output Voltage (Referenced to GND)

ÎÎÎÎÎ

– 0.5 to VCC + 0.5

ÎÎÎ

ÎÎÎÎ

Iin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Current, per Pin

ÎÎÎÎÎ

±20

ÎÎÎ

ÎÎÎÎ

Iout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Output Current, per Pin

ÎÎÎÎÎ

±25

ÎÎÎ

ÎÎÎÎ

ICC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Current, VCC and GND Pins

ÎÎÎÎÎ

±50

ÎÎÎ

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Power Dissipation in Still Air Plastic DIP†

SOIC Package†

ÎÎÎÎÎ

ÎÎÎ

ÎÎÎÎÎ

750

500

ÎÎÎ

ÎÎÎÎ

Tstg

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Storage Temperature

ÎÎÎÎÎ

– 65 to + 150

ÎÎÎ

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Lead Temperature, 1 mm from Case for 10 Seconds

(Plastic DIP or SOIC Package)

ÎÎÎÎÎ

260

ÎÎÎ

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress

ratings only. Functional operation above the Recommended Operating Conditions is not implied.

Extended exposure to stresses above the Recommended Operating Conditions may affect device

reliability.

†Derating — Plastic DIP: –10mW/_C from 65_ to 125_C

SOIC Package: –7mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎ

Min

ÎÎÎ

Max

ÎÎÎ

Unit

ÎÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Voltage (Referenced to GND)

ÎÎÎ

4.5

ÎÎÎ

5.5

ÎÎÎ

ÎÎÎÎ

Vin, Vout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Voltage, Output Voltage (Referenced to GND)

ÎÎÎ

VCC

ÎÎÎ

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Operating Temperature, All Package Types

ÎÎÎ

– 55

ÎÎÎ

+ 125

ÎÎÎ

ÎÎÎÎ

tr, tf

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Input Rise and Fall Time (Figure 1)

ÎÎÎ

500

ÎÎÎ

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

Test Conditions

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎ

Guaranteed Limit

ÎÎÎ

Unit

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

– 55 to

25_C

ÎÎÎ

v 85_C

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

v 125_C

ÎÎÎÎ

VIH

ÎÎÎÎÎÎÎÎÎ

Minimum High−Level Input

Voltage

ÎÎÎÎÎÎÎÎÎ

Vout = 0.1 V or VCC – 0.1 V

|Iout| v 20 mA

ÎÎÎÎ

4.5

5.5

ÎÎÎÎ

2.0

ÎÎÎ

2.0

ÎÎÎÎ

2.0

ÎÎÎ

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

VIL

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

Maximum Low−Level Input

Voltage

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

Vout = 0.1 V or VCC – 0.1 V

|Iout| v 20 mA

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

4.5

5.5

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

0.8

ÎÎÎ

0.8

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

0.8

ÎÎÎ

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

VOH

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

Minimum High−Level Output

Voltage

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

Vin = VIH or VIL

|Iout| v 20 mA

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

4.5

5.5

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

4.4

5.4

ÎÎÎ

4.4

5.4

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

4.4

5.4

ÎÎÎ

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

Vin = VIH or VIL

|Iout| v 4.0 mA

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

4.5

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

3.98

ÎÎÎ

3.84

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

3.7

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

VOL

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

Maximum Low−Level Output

Voltage

ÎÎÎÎÎÎÎÎÎ

Vin = VIH or VIL

|Iout| v 20 mA

ÎÎÎÎ

4.5

5.5

ÎÎÎÎ

0.1

ÎÎÎ

0.1

ÎÎÎÎ

0.1

ÎÎÎ

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

Vin = VIH or VIL

|Iout| v 4.0 mA

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

4.5

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

0.26

ÎÎÎ

0.33

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

0.4

ÎÎÎÎ

Iin

ÎÎÎÎÎÎÎÎÎ

Maximum Input Leakage Current

ÎÎÎÎÎÎÎÎÎ

Vin = VCC or GND

ÎÎÎÎ

5.5

ÎÎÎÎ

±0.1

ÎÎÎ

±1.0

ÎÎÎÎ

±1.0

ÎÎÎ

ÎÎÎÎ

ICC

ÎÎÎÎÎÎÎÎÎ

Maximum Quiescent Supply

Current (per Package)

ÎÎÎÎÎÎÎÎÎ

Vin = VCC or GND

Iout = 0 mA

ÎÎÎÎ

5.5

ÎÎÎÎ

2.0

ÎÎÎ

ÎÎÎÎ

ÎÎÎ

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

DICC

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

Additional Quiescent Supply

Current

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

Vin = 2.4 V, Any One Input

Vin = VCC or GND, Other Inputs

lout = 0 mA

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

5.5

ÎÎÎÎ

≥−55_C

ÎÎÎÎÎÎ

25_C to 125_C

ÎÎÎ

ÎÎÎÎ

2.9

ÎÎÎÎÎÎ

2.4

1. Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).

This device contains protection

circuitry to guard against damage

due to high static voltages or electric

fields. However, precautions must

be taken to avoid applications of any

voltage higher than maximum rated

voltages to this high−impedance cir-

cuit. For proper operation, Vin and

Vout should be constrained to the

range GND v (Vin or Vout) v VCC.

Unused inputs must always be

tied to an appropriate logic voltage

level (e.g., either GND or VCC).

Unused outputs must be left open.

MC74HCT74A

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AC ELECTRICAL CHARACTERISTICS (VCC = 5.0 V ± 10%, CL = 50 pF, Input tr = tf = 6.0 ns)

Symbol Parameter

Guaranteed Limit

Unit

– 55 to

25_Cv 85_Cv 125_C

ÎÎÎÎ

fmax

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Clock Frequency (50% Duty Cycle)

(Figures 1 and 4)

ÎÎÎÎ

ÎÎÎ

MHz

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

tPLH,

tPHL

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Propagation Delay, Clock to Q or Q

(Figures 1 and 4)

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

ÎÎÎ

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

tPLH,

tPHL

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Propagation Delay, Set or Reset to Q or Q

(Figures 2 and 4)

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

ÎÎÎ

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

tTLH,

tTHL

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Output Transition Time, Any Output

(Figures 1 and 4)

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

ÎÎÎ

ÎÎÎÎ

Cin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Input Capacitance

ÎÎÎÎ

ÎÎÎ

2. For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON Semiconductor

High−Speed CMOS Data Book (DL129/D).

CPD Power Dissipation Capacitance (Per Enabled Output)*

Typical @ 25°C, VCC = 5.0 V

3. Used to determine the no−load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the

ON Semiconductor High−Speed CMOS Data Book (DL129/D).

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

TIMING REQUIREMENTS (VCC = 5.0 V ± 10%, CL = 50 pF, Input tr = tf = 6.0 ns)

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎ

Fig.

ÎÎÎÎÎÎÎÎÎÎÎÎ

Guaranteed Limit

ÎÎÎ

Units

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

– 55 to

25_C

ÎÎÎÎÎ

ÎÎÎ

ÎÎÎÎÎ

v 85_C

ÎÎÎÎÎ

ÎÎÎ

ÎÎÎÎÎ

v 125_C

ÎÎÎ

Min

ÎÎ

Max

ÎÎÎ

Min

ÎÎÎ

Max

ÎÎÎ

Min

ÎÎÎ

Max

ÎÎÎÎ

tsu

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Setup Time, Data to Clock

ÎÎÎ

ÎÎ

ÎÎÎ

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Hold Time, Clock to Data

ÎÎÎ

ÎÎ

ÎÎÎ

ÎÎÎÎ

trec

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Recovery Time, Set or Reset Inactive to Clock

ÎÎÎ

ÎÎ

ÎÎÎ

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Pulse Width, Clock

ÎÎÎ

ÎÎ

ÎÎÎ

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Pulse Width, Set or Reset

ÎÎÎ

ÎÎ

ÎÎÎ

ÎÎÎÎ

tr, tf

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Input Rise and Fall Times

ÎÎÎ

ÎÎ

500

ÎÎÎ

500

ÎÎÎ

500

ÎÎÎ

ORDERING INFORMATION

Device Package Shipping†

MC74HCT74AN PDIP−14

25 Units / Rail

MC74HCT74ANG PDIP−14

(Pb−Free)

MC74HCT74AD SOIC−14

55 Units / Rail

MC74HCT74ADG SOIC−14

(Pb−Free)

MC74HCT74ADR2 SOIC−14

2500 / Tape & Reel

MC74HCT74ADR2G SOIC−14

(Pb−Free)

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

MC74HCT74A

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SWITCHING WAVEFORMS

1/fmax

Figure 1.

CLOCK

Q OR Q

3 V

GND

2.7 V

1.3 V

0.3 V

90%

1.3 V

10%

tPLH tPHL

tTLH tTHL

Figure 2.

GND

SET OR

RESET

Q OR Q

CLOCK

tPLH

tPHL

DATA

CLOCK

Figure 3.

VALID

tsu th

trec

Figure 4. Expanded Logic Diagram

SET

DATA

RESET

4, 10

2, 12

1, 13

CLOCK

3, 11

5, 9

6, 8

*Includes all probe and jig capacitance

CL*

TEST POINT

DEVICE

UNDER

TEST

OUTPUT

Figure 5.

3 V

GND

3 V

1.3 V

GND

3 V

GND

3 V

1.3 V

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PACKAGE DIMENSIONS

PDIP−14

CASE 646−06

ISSUE P

14 8

ADIM MIN MAX MIN MAX

MILLIMETERSINCHES

A0.715 0.770 18.16 19.56

B0.240 0.260 6.10 6.60

C0.145 0.185 3.69 4.69

D0.015 0.021 0.38 0.53

F0.040 0.070 1.02 1.78

G0.100 BSC 2.54 BSC

H0.052 0.095 1.32 2.41

J0.008 0.015 0.20 0.38

K0.115 0.135 2.92 3.43

M−−− 10 −−− 10

N0.015 0.039 0.38 1.01

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN

FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

HG D

SEATING

PLANE

−T−

14 PL

0.13 (0.005)

J0.290 0.310 7.37 7.87

MC74HCT74A

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PACKAGE DIMENSIONS

SOIC−14

CASE 751A−03

ISSUE H

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE

DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.127

(0.005) TOTAL IN EXCESS OF THE D

DIMENSION AT MAXIMUM MATERIAL

CONDITION.

−A−

−B−

P7 PL

14 8

0.25 (0.010) B M

0.25 (0.010) A S

−T−

RX 45

SEATING

PLANE D14 PL K

_DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A8.55 8.75 0.337 0.344

B3.80 4.00 0.150 0.157

C1.35 1.75 0.054 0.068

D0.35 0.49 0.014 0.019

F0.40 1.25 0.016 0.049

G1.27 BSC 0.050 BSC

J0.19 0.25 0.008 0.009

K0.10 0.25 0.004 0.009

M0 7 0 7

P5.80 6.20 0.228 0.244

R0.25 0.50 0.010 0.019

__ __

7.04

14X

0.58

14X

1.52

1.27

DIMENSIONS: MILLIMETERS

PITCH

SOLDERING FOOTPRINT*

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should

Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,

and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal

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PUBLICATION ORDERING INFORMATION

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USA/Canada

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Phone: 421 33 790 2910

Japan Customer Focus Center

Phone: 81−3−5773−3850

MC74HCT74A/D

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