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04/21/04
IRF830AS/LPbF
SMPS MOSFET
HEXFET® Power MOSFET
lSwitch Mode Power Supply (SMPS)
lUninterruptable Power Supply
lHigh Speed Power Switching
lLead-Free
Benefits
Applications
lLow Gate Charge Qg Results in Simple
Drive Requirement
lImproved Gate, Avalanche and Dynamic
dv/dt Ruggedness
lFully Characterized Capacitance and
Avalanche Voltage and Current
lEffective Coss specified (See AN 1001)
VDSS RDS(on) max ID
500V 1.405.0A
Typical SMPS Topologies:
l Two Transistor Forward
l Half Bridge and Full Bridge
PD- 95139
Notes through are on page 10
Parameter Max. Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V5.0
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V3.2 A
IDM Pulsed Drain Current  20
PD @TA = 25°C Power Dissipation 3.1 W
PD @TC = 25°C Power Dissipation 74
Linear Derating Factor 0.59 W/°C
VGS Gate-to-Source Voltage ± 30 V
dv/dt Peak Diode Recovery dv/dt  5.3 V/ns
TJOperating Junction and -55 to + 150
TSTG Storage Temperature Range
Soldering Temperature, for 10 seconds 300 (1.6mm from case )
°C
Absolute Maximum Ratings
D2Pak TO-262
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Parameter Min. Typ. Max. Units Conditions
gfs Forward Transconductance 2.8 ––– ––– S VDS = 50V, ID = 3.0A
QgTotal Gate Charge –– ––– 24 ID = 5.0A
Qgs Gate-to-Source Charge ––– ––– 6.3 nC VDS = 400V
Qgd Gate-to-Drain ("Miller") Charge ––– ––– 11 VGS = 10V, See Fig. 6 and 13 
td(on) Turn-On Delay Time ––– 10 ––– VDD = 250V
trRise Time ––– 21 –– ID = 5.0A
td(off) Turn-Off Delay Time ––– 21 –– RG = 14
tfFall Time ––– 15 ––– RD = 49,See Fig. 10
Ciss Input Capacitance ––– 620 ––– VGS = 0V
Coss Output Capacitance ––– 93 ––– VDS = 25V
Crss Reverse Transfer Capacitance ––– 4.3 ––– pF ƒ = 1.0MHz, See Fig. 5
Coss Output Capacitance ––– 886 ––– VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
Coss Output Capacitance ––– 27 ––– VGS = 0V, VDS = 400V, ƒ = 1.0MHz
Coss eff. Effective Output Capacitance ––– 39 –– VGS = 0V, VDS = 0V to 400V 
Dynamic @ TJ = 25°C (unless otherwise specified)
ns
Parameter Typ. Max. Units
EAS Single Pulse Avalanche Energy ––– 230 mJ
IAR Avalanche Current ––– 5.0 A
EAR Repetitive Avalanche Energy––– 7.4 mJ
Avalanche Characteristics
S
D
G
Parameter Min. Typ. Max. Units Conditions
ISContinuous Source Current MOSFET symbol
(Body Diode) ––– ––– showing the
ISM Pulsed Source Current integral reverse
(Body Diode) ––– ––– p-n junction diode.
VSD Diode Forward Voltage ––– ––– 1.5 V TJ = 25°C, IS = 5.0A, VGS = 0V
trr Reverse Recovery Time ––– 430 650 ns TJ = 25°C, IF = 5.0A
Qrr Reverse RecoveryCharge ––– 2.0 3.0 µC di/dt = 100A/µs 
ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Diode Characteristics
5.0
20
A
Static @ TJ = 25°C (unless otherwise specified)
Parameter Min. Typ. Max. Units Conditions
V(BR)DSS Drain-to-Source Breakdown Voltage 500 –– –– V VGS = 0V, ID = 250µA
V(BR)DSS/TJ Breakdown Voltage Temp. Coefficient ––– 0.60 ––– V/°C Reference to 25°C, ID = 1mA
RDS(on) Static Drain-to-Source On-Resistance –– ––– 1.4 VGS = 10V, ID = 3.0A
VGS(th) Gate Threshold Voltage 2.0 ––– 4.5 V VDS = VGS, ID = 250µA
––– ––– 25 µA VDS = 500V, VGS = 0V
––– ––– 250 VDS = 400V, VGS = 0V, TJ = 125°C
Gate-to-Source Forward Leakage ––– ––– 100 VGS = 30V
Gate-to-Source Reverse Leakage ––– ––– -100 nA VGS = -30V
IGSS
IDSS Drain-to-Source Leakage Current
Parameter Typ. Max. Units
RθJC Junction-to-Case ––– 1.7 °C/W
RθJA Junction-to-Ambient ( PCB Mounted, steady-state)* –– 40
Thermal Resistance
IRF830AS/LPbF
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Fig 4. Normalized On-Resistance
Vs. Temperature
Fig 2. Typical Output CharacteristicsFig 1. Typical Output Characteristics
Fig 3. Typical Transfer Characteristics
0.01
0.1
1
10
100
0.1 1 10 100
20
µ
s PULSE WIDTH
T = 25 C
J°
TOP
BOTTOM
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
V , Drain-to-Source Voltage (V)
I , Drain-to-Source Current (A)
DS
D
4.5V
0.1
1
10
100
1 10 100
20
µ
s PULSE WIDTH
T = 150 C
J°
TOP
BOTTOM
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
V , Drain-to-Source Volta
g
e (V)
I , Drain-to-Source Current (A)
DS
D
4.5V
0.1
1
10
100
4.0 5.0 6.0 7.0 8.0
V = 50V
20
µ
s PULSE WIDTH
DS
V , Gate-to-Source Voltage (V)
I , Drain-to-Source Current (A)
GS
D
T = 25 C
J°
T = 150 C
J°
-60 -40 -20 020 40 60 80 100 120 140 160
0.0
0.5
1.0
1.5
2.0
2.5
T , Junction Temperature ( C)
R , Drain-to-Source On Resistance
(Normalized)
J
DS(on)
°
V =
I =
GS
D
10V
5.0A
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Fig 8. Maximum Safe Operating Area
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
Fig 7. Typical Source-Drain Diode
Forward Voltage
04812 16 20 24
0
4
8
12
16
20
Q , Total Gate Charge (nC)
V , Gate-to-Source Voltage (V)
G
GS
FOR TEST CIRCUIT
SEE FIGURE
I =
D
13
5.0A
V = 100V
DS
V = 250V
DS
V = 400V
DS
0.1
1
10
100
0.2 0.4 0.6 0.8 1.0 1.2
V ,Source-to-Drain Volta
g
e (V)
I , Reverse Drain Current (A)
SD
SD
V = 0 V
GS
T = 25 C
J°
T = 150 C
J°
0.1
1
10
100
10 100 1000 10000
OPERATION IN THIS AREA LIMITED
BY RDS(on)
Sin
g
le Pulse
T
T
= 150 C
= 25 C
°
°
J
C
V , Drain-to-Source Volta
g
e (V)
I , Drain Current (A)I , Drain Current (A)
DS
D
10us
100us
1ms
10ms
1
10
100
1000
10000
1 10 100 1000
C, Capacitance (pF)
DS
V , Drain-to-Source Volta
g
e
V
)
A
V = 0V
,
f = 1MHz
C = C + C
,
C SHO RTED
C = C
C = C + C
GS
iss
g
s
g
d ds
rs s
g
d
oss ds
g
d
C
iss
C
oss
C
rss
IRF830AS/LPbF
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Fig 10a. Switching Time Test Circuit
V
DS
90%
10%
V
GS
t
d(on)
t
r
t
d(off)
t
f
Fig 10b. Switching Time Waveforms
VDS
Pulse Width 1 µs
Duty Factor ≤ 0.1 %
RD
VGS
RG
D.U.T.
10V
+
-
VDD
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig 9. Maximum Drain Current Vs.
Case Temperature
0.01
0.1
1
10
0.00001 0.0001 0.001 0.01 0.1 1
Notes:
1. Duty factor D = t / t
2. Peak T = P x Z + T
1 2
JDM thJC C
P
t
t
DM
1
2
t , Rectangular Pulse Duration (sec)
Thermal Response (Z )
1
thJC
0.01
0.02
0.05
0.10
0.20
D = 0.50
SINGLE PULSE
(THERMAL RESPONSE)
25 50 75 100 125 150
0.0
1.0
2.0
3.0
4.0
5.0
T , Case Temperature ( C)
I , Drain Current (A)
°
C
D
IRF830AS/LPbF
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QG
QGS QGD
VG
Charge
D.U.T. V
DS
I
D
I
G
3mA
V
GS
.3µF
50K
.2µF
12V
Current Regulator
Same Type as D.U.T.
Current Sampling Resistors
+
-
10 V
Fig 13b. Gate Charge Test Circuit
Fig 13a. Basic Gate Charge Waveform
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
Fig 12b. Unclamped Inductive Waveforms
Fig 12a. Unclamped Inductive Test Circuit
tp
V
(BR)DSS
I
AS
R
G
I
AS
0.01
t
p
D.U.T
L
VDS
+
-V
DD
DRIVER
A
15V
20V
25 50 75 100 125 150
0
100
200
300
400
500
Starting T , Junction Temperature ( C)
E , Single Pulse Avalanche Energy (mJ)
J
AS
°
ID
TOP
BOTTOM
2.2A
3.2A
5.0A
Fig 12d. Typical Drain-to-Source Voltage
Vs. Avalanche Current
770
775
780
785
790
0.0 1.0 2.0 3.0 4.0 5.0
A
DSav
av
I , Avalanche Current (A)
V , Avalanche Voltage (V)
IRF830AS/LPbF
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P.W. Period
di/dt
Diode Recovery
dv/dt
Ripple 5%
Body Diode Forward Drop
Re-Applied
Voltage
Reverse
Recovery
Current
Body Diode Forward
Current
V
GS
=10V
V
DD
I
SD
Driver Gate Drive
D.U.T. I
SD
Waveform
D.U.T. V
DS
Waveform
Inductor Curent
D = P. W .
Period
+
-
+
+
+
-
-
-
Fig 14. For N-Channel HEXFET® Power MOSFET
* VGS = 5V for Logic Level Devices
Peak Diode Recovery dv/dt Test Circuit
RG
VDD
dv/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
D.U.T Circuit Layout Considerations
Low Stray Inductance
Ground Plane
Low Leakage Inductance
Current Transformer
*
IRF830AS/LPbF
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D2Pak Part Marking Information (Lead-Free)
D2Pak Package Outline
Dimensions are shown in millimeters (inches)
Note: "P " in as s embly line
pos ition indicates "L ead-F ree"
F530S
T HIS IS AN IR F 530S WIT H
LOT CODE 8024
ASS EMBLED ON WW 02, 2000
IN THE ASSEMBLY LINE "L"
AS S E MB L Y
LOT CODE
INT E R NAT ION AL
R E CT IF IE R
LOGO
PART NUMB ER
DAT E CODE
YE AR 0 = 2000
WEE K 02
LINE L
OR
F530S
A = ASSEMBLY SITE CODE
WEEK 02
P = DE S IGN AT E S L E AD -F R E E
PRODUCT (OPTIONAL)
RECTIFIER
INT E RNAT IONAL
LOGO
LOT CODE
ASSEMBLY
YE AR 0 = 2000
DATE CODE
PART NUMBER
IRF830AS/LPbF
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TO-262 Part Marking Information
TO-262 Package Outline
Dimensions are shown in millimeters (inches)
AS S E MB L Y
LOT CODE
R E CT IF IE R
INT E R NAT IONAL
AS S E MBL ED ON WW 19, 1997
Note: "P " in as s embly line
pos ition indi cates "L ead-F r ee"
IN THE ASSEMBLY LINE "C" LOGO
T H IS IS AN IR L 3103L
LOT CODE 1789
EXAMPLE:
LINE C
DATE CODE
WE EK 19
YE AR 7 = 1997
PART NUMBE R
PART NUMBE R
LOGO
LOT CODE
AS S E MB L Y
INT E R NAT IONAL
R E CT IF IE R
PRODUCT (OPTIONAL)
P = DE S IGNAT E S LE AD-F RE E
A = AS S E MB L Y S IT E CODE
WE EK 19
YE AR 7 = 1997
DATE CODE
OR
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Repetitive rating; pulse width limited by
max. junction temperature. ( See fig. 11 )
ISD 5.0A, di/dt 370A/µs, VDD V(BR)DSS,
TJ 150°C
Notes:
Starting TJ = 25°C, L = 18mH
RG = 25, IAS = 5.0A. (See Figure 12)
Pulse width 300µs; duty cycle 2%.
Coss eff. is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS
Uses IRF830A data and test conditions
* When mounted on 1" square PCB ( FR-4 or G-10 Material ).
For recommended footprint and soldering techniques refer to application note #AN-994.
D2Pak Tape & Reel Information
3
4
4
TRR
FEED DIRECTION
1.85
(
.0 7 3
)
1.65
(
.0 6 5
)
1.60
(
.063
)
1.50
(
.059
)
4.10
(
.161
)
3.90
(
.153
)
TRL
FEED DIRECTION
10.90
(
.429
)
10.70
(
.421
)
16.10
(
.634
)
15.90
(
.626
)
1.75
(
.069
)
1.25
(
.049
)
11.60
(
.457
)
11.40
(
.449
)
15.42
(
.609
)
15.22
(
.601
)
4.72
(
.1 36
)
4.52
(
.1 78
)
24.30
(
.957
)
23.90
(
.941
)
0.368
(
.0145
)
0.342
(
.0135
)
1.60
(
.06 3
)
1.50
(
.05 9
)
13.50
(
.532
)
12.80
(
.504
)
330.00
(
14.173
)
MAX.
27.40
(
1.079
)
23.90
(
.9 41
)
60.00
(
2.362
)
MIN.
30.40
(
1.197
)
MAX.
26.40
(
1.039
)
24.40
(
.961
)
NOTES :
1. CO MFOR M S TO EIA-418.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION MEASURED @ HUB.
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
Data and specifications subject to change without notice.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 04/04