19-4011; Rev 1; 12/96 General Description The MAX501/MAX502 are 12-bit, 4-quadrant, voltage- output, multiplying digital-to-analog converters (DACs) with an output amplifier. Thin-film resistors, laser trimmed at the wafer level, maintain accuracy over the full operating temperature range. The MAX501/MAX502 have buffered latches that are easily interfaced with microprocessors. Data is trans- ferred into the input register in either a right-justified 8+4-bit format (MAX501) or with a 12-bit-wide data path (MAX502). In the MAX501, an LDAC signal transfers data from the input register to the DAC register. In the MAX502, the input registers are controlled by standard CHIP SELECT (CS) and WRITE (WR) signals. For stand- alone operation, the CS and WR inputs are grounded, making all latches transparent. All logic inputs are level triggered and compatible with TTL and +5V CMOS logic levels. The internally compensated, low-input offset-voltage output amplifier provides an output voltage from +10V to -10V while sourcing and sinking up to 5mA. Applications Digital Attenuators Programmable-Gain Amplifiers Servo Controls Digital to 4mA-to-20mA Converters Automatic Test Equipment Programmable Power Supplies MAAIM Voltage-Output, 12-Bit Multiplying DACs je eoeooeoe 12-Bit Voltage Output DAC +10V and 5mA Output Drive Monotonic Over Temperature Four Range-Scaling Resistors 8+4 (MAX501) and 12-Bit (MAX502) Interface 24-Pin DIP and Wide SO Packages Features Ordering information PART TEMP. RANGE PIN- PACKAGE ERROR (LSBs) MAX501ACNG 0C to +70C 24 Narrow Plastic DIP 12 MAX501BCNG 0C to +70C 24 Narrow Plastic DIP +3/4 MAX501ACWG 0C to +70C 24 Wide SO 1/2 MAX501BCWG 0C to +70C 24 Wide SO 3/4 MAX501BC/D 0C to +70C Dice* +3/4 MAX501AENG -40C to +85C 24 Narrow Plastic DIP +1/2 MAX501BENG -40C to +85C 24 Narrow Plastic DIP +3/4 MAX501AEWG -40C to +85C 24 Wide SO +1/2 MAX501 BEWG -40C to +85C 24 Wide SO +3/4 MAXSO1AMRG -55C to +125C 24 Narrow CERDIP** 1/2 MAX501BMRG -55C to +125C 24 Narrow CERDIP** +3/4 Ordering Information continued on last page. * Contact factory for dice specifications. ** Contact factory for availability and processing to MIL-STD-883. Functional Diagram Pin Configurations TOP VIEW Voo RA RB RC RFB WW | 20 am [22 [23 | 24 Vour (3 [24] RFB 4 e 3 on [2] [23] RC SAR SARYARYR p10 3] [22] RB wT {4 p94] AAAxLM [2] RA VREFfy 12-BIT DAC Vy pss} MAX502 = [20] Voo MAKIM pour ov Ce [19] Vss MAX502 18 p CZ [1a] AGND aT AGND bs [8] [17] VREF 12-Bi 04 [a] [16] CS GONTROL LOGIC cs DATA LATCH 9 D3 fra] 115] WA 4 P Vss p2 Gi] [74] 00 DGND Liz 13] 01 wal =i[2 Te fie [15 DO...D11 DGND CS WR DIP/SO MAX501 on last page MAXISA Maxim Integrated Products 1 For free samples & the latest literature: http:/;www.maxim-ic.com, or phone 1-800-998-8800 ZOSXVW/LOSXVNMAX501/MAX502 Voltage-Output, 12-Bit Multiplying DACs ABSOLUTE MAXIMUM RATINGS Vop to DGND ........... ec cece cece eee -0.3V, +17V VgstoDGND ............0c cee eee woes +0.3V,-17V VREF toAGND ......... 0.0 e cc eee ee veeeeees OBV RFBtoAGND .............. eee c eee wee eens L25V RAtoAGND ................ bee e rece eens +25V RBtoAGND ............... tec eceee teeeee. 25V RCtOAGND ........ cece cece cece eeeee see 25V Vout to AGND (Note 1) ........... Vop +0.3V, Vsg -0.3V VDDtOAGND ........ cee cece cece enees -0.3V, +17V AGNDtoDGND .............00. tee eeeee -0.3V, Vop Digital Input Voltage to DGND ........... eee Continuous Power Dissipation (any package) to+75C ........ derate above +75C Operating Temperature Ranges: MAXS501_C__, MAX502_C__ ............ OCto+70C MAXS01_E__, MAX502_E_ ......... + ~40C to +85C MAXS01_M__, MAX502_M__ ......... -55C to +125C Storage Temperature Range ........... -65Cto +150C Lead Temperature (soldering, 10sec) ........ +e +300C Beebe mene rare esesees Note 1: Vout may be shorted to AGND, Vpp, or Vgs if the power dissipation of the package is not exceeded. Stresses beyond those under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the Specification is not impli absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS Dual Supply (Vpp = +11.4V to +15.75V, Vgg = -11.4V to -15.75V, VREF = +10V, A Ta = TMIN to Tmax, unless otherwise noted.) (Note 2) led. Exposure to GND = DGND = OV, Ri = 2kQ, Cr = 100pF, all grades, Ratio Matching PARAMETER | SYMBOL | CONDITIONS MIN TYP MAX | UNITS STATIC PERFORMANCE Resolution N 12 Bits MAX501/502A +1/2 Ta = +25C ; MAX501/502B 43/4 Relative Accuracy INL LSB Ta=T, toT a | MAX501/502A +3/4 = lo A MIN MAX MAX501/502B +1 Differential Nonlinearity DNL +1 LSB Ta = +25C +1 Zero-Code Offset Error Ta=T tot, MAX501/502_C/E +2 mv = 0 AS UMINTOUMAX THAX501/502_M +3 . AVos/ 0 Offset Temperature Coefficient ATemp +5 IVES RFB, Vout connected +3 Gain Error voce RB ponnected to Vour, +4% | LSB RA, Vout connected, VREF = 2.5V +6 . _ AGain/ 1o Gain Temperature Coefficient ATemp +1 ppm/C Reference Input Resistance RFB 8 12 16 kQ Application Resistor RA to RB to RC match 05 % MAAXLAAVoltage-Output, 12-Bit Multiplying DACs ELECTRICAL CHARACTERISTICS (continued) Dual Supply (Vpp = +11.4V to +15.75V, Vsg = -11.4V to -15.75V, VREF = +10V, AGND = DGND = OV, Ri = 2kQ, C_. = 100pF, all grades, Ta = TmIN to Tmax, unless otherwise noted.) (Note 2) PARAMETER SYMBOL | CONDITIONS MIN TYP MAX | UNITS DIGITAL INPUTS input Current Vin = OV and V Ta= *25C = A put Curren IN = OV and Vop P iN Ta = TMIN to TMAX +10 M Input Low Voltage VIL 0.8 Vv Input High Voltage Vin 2.4 Vv Input Capacitance CIN 7 pF POWER SUPPLIES Supply Voltage Vppb 11.40 15.75 V ul olta Pply 9 Vss -11.40 -15.75 I Vv unloaded 10 Supply Current DD OUT mA Iss Vout unloaded 4 VREF = -10V Vop = 15V + 5% AGain/AVpp +0.02 VREF = -8.9V oo Vop = 12V + 5% Power-Supply Rejection PSR %/% VREF = 10V . Vss = -15V + 5% AGain/AVss +0.02 VREF = 8.9V a Vss = -12V + 5% DYNAMIC PERFORMANCE (Note 3) Output-Voltage Settling Time ts To 0.01% of full scale 5 us Slew Rate SR 5 Wis DAC Glitch impulse Major carry transition 450 nv-s Multiplying Feedthrough Error VREF = +10V at 10kHz, DAC = all Os 5 mVp-_p oe Smail-Signal 3 MHz Full-Power Bandwidth 250 kHz Total Harmonic Distortion THD VREF = 6Vpws at 1kHz -90 dB OUTPUT CHARACTERISTICS Open-Loop Gain Avo RFB not connected, Vout = +10V, Rr = 2kQ 90 dB Output Resistance Ro 0.2 Q Short-Circuit Current Ta = +25C 20 mA Output Noise Voltage 0.1Hz to 10Hz, Ta = +25C 2 uVAMS f = 1kHz, Ta = +25C 25 nW//Hz MAXIM 3 cOSXVN/-LOSXVUNMAX501/MAX502 Voltage-Output, 12-Bit Multiplying DACs TIMING CHARACTERISTICS (See Figures 1a, 1b) Dual Supply (Vpp = +11.4V to +15.75V, Vss = -11.4V to -15.75V, VREF = +10V, AGND = DGND = OV, Ri = 2kQ, Cr = 100pF, all grades, Ta = TmIN to Tmax, unless otherwise noted.) (Note 2) PARAMETER | SYMBOL | CONDITIONS MIN TYP MAX | UNITS MAX501 Chip Select to Write-Setup Time tcs 0 ns Write Pulse Width twR Tas *25C $8 ns Ta = TMIN to Tmax 70 ; MAX501_C/E 50 Data-Setup Time tos ns MAX501_M 60 Data-Hold Time tbH 10 0 ns LDAC Pulse Width tLbac 70 ns CLR Pulse Width tcLR 70 ns SET Pulse Width tSET 200 ns MAX502 Chip Select to Write-Setup Time tcs 0 ns Ta = +26C 40 Write Pulse Width twR Ta = Tun to Tuax MAX502_C/E 50 ns MAX502_M 60 , MAX502_C/E 50 Data-Setup Time tos ns MAX502_M 60 Data-Hold Time tbH 10 0 ns Note 2: Vout must be less than Vpp - 2.5V and greater than Vsgg + 2.5V to ensure correct operation. Performance at supplies other than Vpp = +15V and Vsg = -15V is guaranteed by PSRR tests. Leave unused feedback resistors floating. Note 3: Dynamic Performance and Output Characteristics are included for design guidance and are not subject to test. MAXIMAVoltage-Output, 12-Bit Multiplying DACs FREQUENCY RESPONSE, GAIN =] +180 + So & PHASE (DEGREES) ok 8 GAIN (dB) Vop = +15V Vss = -15V VREF = 20Vp-p DAC CODE: 11... 111 100 = tk 10k 100k iM 10M FREQUENCY (Hz) NOISE SPECTRAL DENSITY Von = +15V Vsg = -15V Hz) = VREF = OV = DAC CODE: 11... 111 5 =-1 a a ) a E & a wn a o = 1 100 1k.~s10k_~100k FREQUENCY (Hz) MULTIPLYING FEEDTHROUGH ERROR VREF B 5V/DIV GND ; B Vour GND (FEEDTHROUGH) a 5mV/DIV 20us/DIV MAAXISMA Typical Operating Characteristics Vour (FEEDTHROUGH) (mVp.p) Vour (Vp-p) OUTPUT VOLJAGE SWING vs. RESISTIVE LOAD 28 Vpp = +15V 24 / Vos = -15V VREF = 30Vp_p @ 1kHz 16 12 8 4 1 10 100 tk 10k LOAD RESISTANCE (Q) THD vs. FREQUENCY T Vop = +15V Vsg = ~15V -25 |- VREF = 6Vpms DAC CODE: 11... 111 GAIN = -1 -50 -75 7 WA, a -100 100 1k 10k 100k FREQUENCY (Hz) MULTIPLYING FEEDTHROUGH ERROR vs. FREQUENCY 200 Vop = +15V Vgs = -15V | 160 |- VREF = 20Vp-p DAC CODE: 00... .000 | 420 GAIN =0 ] 80 40 0 100 tk 10k 100k 1M FREQUENCY (Hz) cOSXVN/LOSXVNMAX501/MAX502 Voltage-Output, 12-Bit Multiplying DACs tes CSLSB OR CSMSB WR \ ~< twa P} KN y DATA tos yt toy DATA VALID tLoac LDAC Figure ta. MAX501 Timing Diagram twa ] NY DATA tps >} ton ] DATA VALID Figure 1b. MAX502 Timing Diagram NOTES: 1. All input signal rise and fall times measured from 10% to 90% of +5V, ta = tp = 20ns. + 2. Timing measurement reference level is Von * Vin MAAXILMAVoltage-Output, 12-Bit Multiplying DACs Pin Descriptions MAX501 MAX502 PIN NAME FUNCTION PIN NAME FUNCTION 1 VouT Voltage Output 1 Vout Voltage Output 2 |LDAC Asynchronous Load DAC Input is 2-11 |D11-D2 _| Data Bits 2 to 11 (MSB) __ active low 12 |DGND _| Digital Ground 3 {SET Sets DAC register to all 1s 13,14 |D1,D0 __| Data Bits 0 to 1 (LSB) 4 CLR Sets DAC register to all Os 1s. |WR Write Input is active low 5-8 |D7-D4 Data Bits 7 to 4 16 6\cSs Chip-Select Input is active low 9 |03/D11__ | Data Bit 3 or 11 7 | VREF Reference Input to DAC 10 D2/D10 Data Bit 2 or 10 18 AGND Analog Ground n 1/9 Data Bit 1 or 9 19 |Vss -12V to -15V Supply Voltage Input 12 |DGND____| Digital Ground 20 |Vpp +12V to +15V Supply Voltage Input 13 |D0/D8_| Data Bit 0 or 8 (LSB) 21 [RA Scaling Resistor: RA = 4RFB 14 CSLSB LSB Chip-Select Input is active low 22 RB Scaling Resistor. RB = 2RFB 15 [WR Write Input is active low 23 [RC Scaling Resistor: RC = 2RFB 16 CSMSB MSB Chip-Select Input is active low 24 RFB Feedback Resistor 17 VREF Reference Input to DAC. 18 AGND Analog Ground 19 Vss -12V to -15V Supply Voltage Input 20 Vpp +12V to +15V Supply Voltage Input 21 RA Scaling Resistor: RA = 4RFB 22 RB Scaling Resistor: RB = 2RFB 23 RC Scaling Resistor: RC = 2RFB 24 RFB Feedback Resistor MAXKISA 7 ZOSXVW/LOSXVNMAX501/MAX502 Voltage-Output, 12-Bit Multiplying DACs Detailed Description Digital Circuit Figures 2a and 2b are simplified circuit diagrams of the MAX501 and MAX502_ input contro! logic. For the MAXS501, a low on CSLSB and WR with CSMSB high loads the least significant bit (LSB) byte into the input register. The LSB byte is then latched _into the input register on the rising edge of either a WR or a CSLSB. Similarly, a low on CSMSB and WR with CSLSB high Table 1. MAX501 Truth Table loads the most significant bit (MSB) nibble into the input register. The MSB nibble is then latched into the input register on the rising edge of either a WR or a CSMSB pulse. With all 12 bits loaded, a low on LDAC transfers the data to the DAC register. For the MAX502, a low on CS and WR transfers the data on the input registers to the DAC latch. Both parts digital inputs are TTL and CMOS compatible, providing easy microprocessor (uP) interfacing. Tables 1 and 2 are MAX501 and MAX502 truth tables. WR | CSMSB | CSLSB | LDAC CLR SET OPERATION x x x x xX 0 DAC Register overridden by 1s Input Register unaffected x x x xX 0 1 DAC Register overridden by 0's Input Register unaffected 0 0 1 1 1 1 Load MSB nibble into Input Register 0 1 0 1 1 1 Load LSB byte into Input Register x Xx xX 0 1 1 Transfer Input Register to DAC Register 1 x xX 1 1 1 No Operation 0 1 1 1 1 1 No Operation 0 R 1 1 1 1 Latching MSB nibble into Input Register R 0 1 1 1 1 _| Latching MSB nibble into Input Register 0 1 R 1 1 1 | Latching LSB byte into Input Register R 1 0 1 1 1 Latching LSB byte into input Register H = High State, L = Low State, R = Rising Edge, X = Don't Care Table 2. MAX502 Truth Table WR cs OPERATION H x No Operation x H No Operation L L Input Register is Transparent L R Input Register is Latched R L input Register is Latched H = High State, L = Low State, R = Rising Edge, X = Dont Care MAAXLAAVoltage-Output, 12-Bit Multiplying DACs CLR 4BIT | REGISTER 1287S > Lac 8-BIT REGISTER Figure 2a. MAX501 Input Control Logic . DAC at) ee pe Figure 2b. MAX502 Input Control Logic Digital-to-Analog Converter The MAX501/MAX502 have a 12-bit, binary-weighted, current-output DAC with standard R-2R ladder (Figure 3). Binarily weighted currents are switched between AGND and the inverting input of the internal output amplifier. The output amplifier, typically connected to the feedback resistor RFB, converts the output current to a voltage. With RFB connected to Vout, Vout = -D x VREF, where D is the fractional expression of the digital input code divided by full scale. D can vary from 0 to 4095/4096 in unipolar mode. VREF R R aR 2k aR { > 2k V2 Jan J2R JAR YR 4 RA RB RC RFB BETTY Dit (MSB) (LSB) +-__+__ - Vout + Figure 3. MAX501/MAX502 Simplified DAC and Amplifier Circuit MAAXIAA ZOSXVM/LOSXVWMAX501/MAX502 Voltage-Output, 12-Bit Multiplying DACs Output-Buffer Amplifier The output amplifier is an internally compensated, non- inverting, gain-scalable amplifier that can develop +10V across a 2kQ load. Maximum settling time is less than 5us (to within 0.01% FSR). Input offset voltage is laser trimmed at the wafer level. Slew rate is typically 7V/us. The gain-setting resistors (RA, RB, and RC) connect to the amplifier inverting terminal. Float unused gain-set- ting resistors. Unipolar Configuration Figure 4, a typical configuration for the MAX501/MAXS502, provides for unipolar-bipolar operation or two-quadrant multiplication when Vin is an AC signal. R1 adjusts gain and R3 adjusts zero offset. For fixed-reference applica- tions, trim the reference voltage and omit R1 and R2. if R1 and R2 are included, you must take into account their gain-temperature coefficient. The typical gain-tempera- Bipolar Operation Figure 5 shows a 4-quadrant, bipolar operation. Gain error may be adjusted by changing the R1 and R2 ratio. These resistors should be ratio-matched to 0.01% to stay within gain-error specifications and to eliminate trimming. The offset value is defined by matching the RB and RC internal resistors. Table 4 is the code table for bipolar-binary operation. Voo Vss 20} 19 ture coefficient of the MAX502 is 1ppm/C, which corres- VREF RB Vpp Vss ponds to a gain shift of 1/2LSB over a +100C temperature range. Table 3 is the code table for unipolar- MAXIM Von 1 Nour binary operation. MAX501 Vin = Voo_-R3_V ss DGND AGND PC 100k 9 wy ey 23| Ai S R4 en 20] 23 rs Figure 5. Bipolar Operation (4-Quadrant Multiplication) VREF = Voo FC Vss Table 4. MAX501/MAX502 Bipolar-Binary Code Table Vv MAXIM oO. DIGITAL INPUT ANALOG OUTPUT MAX501/MAX502 5047 R2 ae DGND AGND RFB 1000 1111 1111 1111 (+VIN) Soaa 1 = = 1000 0000 0001 (+ViN) 2048 Figure 4. Unipolar-Binary Operation 1000 0000 0000 ov (2-Quadrant Multiplication) 1 0111 1111 1111 (-VIN) S045 Table 3. MAX501/MAX502 Unipolar-Binary Code Table 2048 DIGITAL INPUT ANALOG OUTPUT 0000 0000 0000 (-VIN) 3048 = VIN- 4095 1111 1111 1111 (-VIN) 4096 2048. 1 1000 0000 0000 (-VIN) 3696 * "2 VIN 1 0000 =. 0000-~Ss(0001 (-VIN) 4006 0000 0000 0000 ov 10 MAMXIMAVoltage-Output, 12-Bit Multiplying DACs Applications information Noise AC or transient voltages between AGND and DGND can cause noise injection into the analog output. Tie the MAXS502 AGND to DGND to ensure both pins are at the same potential. If these ground pins connect to separate backplanes, use two back-to-back diodes to tie the pins together. Also, decouple Vpp and Vss to AGND, as MAX502 Microprocessor interfacing 16-Bit Microprocessor Systems Figures 7-9 show the MAX502 interfaced with the MC68000, the 8086, and the TMS32010. The MAX502 appears as a memory-mapped peripheral to the pro- cessors. In each case, a write instruction loads the MAX502 with the appropriate data. The particular instructions used are as follows: uP-based systems generally have noisy grounds that MC68000: MOVE couple into the power supplies. 8086: , MOV Digital Glitches TMS32010: OUT Any digital word written into the DAC causes a glitch impulse. This impulse couples across the stray capaci- tance of the DAC switches to the output bus. A glitch At-A23 impulse on this bus is converted to a voltage by RFB and ' the output amplifier. The output voltage glitch energy is MC6&8000 _the product of its duration and its average magnitude _ Abpress [16| (the net area under the curve), and is expressed in AS DECODE r cs (nV)(s). The energy is measured with VREF connected ___ MAXIM to analog ground and the DAC register alternately DIACK MAX502 loaded with ail Os and all 1s. RW 181A Digital Feedthrough Vos 14 00 D0~ -D11 Most of the MAX501/MAX502s digital inputs are directly O15 oY connected to the uP bus. These inputs are constantly changing, even when the DAC is not selected. High- frequency logic activity on the data bus can feed through the DAC package capacitance as noise on the DAC output. Figure 6 shows an interface that minimizes Figure 7. MAX502 to MC6800 Interface digital feedthrough. All data inputs are latched from the busy by CS. Alternatively, using peripheral interface devices reduces digital feedthrough. 5086 aug caren | | ADDRESS tl ts oxen | | DECODE ADDRESS MAXIM A0-A15 ADDRESS 4s - MAX502 MAXIM wR WR MAX502 14 HP a ADO-AD15 >} Do-p11 16 2 Wa nw LK 14 Figure 8. MAX502 to 8086 Interface Do-D15 16-BIT >, De-D11 LATCH 4 Figure 6. MAX502 Interface Circuit Latches Minimize Digital Feedthrough PMAAXKISAA 1 COSXVW/LOSXVNMAX501/MAX502 Voltage-Output, 12-Bit Multiplying DACs AO-AtI 1 i MAKIM TMS32010 ADDRESS |16| pecooe | jos MAXS02 wh St DO-D15 >| 00-011 2 Pin Configurations (continued) Figure 9. MAX502 to TMS32010 Interface MAX50O1 Microprocessor Interfacing 8-Bit Microprocessor Systems Figure 10 shows an interface circuit for the MAX501 to the 8085A 8-bit uP. The software routine to load data to the device is given in Table 3. Note that transferring 12 data bits requires two write operations. The first of these loads the 4 MSBs into the 7475 latch. The second write operation loads the 8 LSBs plus the 4 MSBs (which are held by the latch) into the DAC. TOP VIEW Vour [7] [24] RFB toac (24 [23] RC SET 3] 22} RB CREA] AAAXIM [2A] RA o7(s] 40 MAX501- [25] Von os [6] 119] Vss ps 7] [18} AGND 04 (ey 77] VREF p3/011 [9 | 16] CSMSB 02/010 Le] 15] WR pio Gr /44] CSLSB DGND 72] 43] DO/D8 DIP/SO ___ Ordering Information (continued) Figure 10. MAX501 to 8085A/8088 Interface PART TEMP. RANGE PACKAGE ts00) AB-A15 MAX502ACNG OCto+70C 24 Narrow Plastic DIP = 1/2 MAXS02BCNG 0C to +70C 24 Narrow Plastic DIP 3/4 1 ee MAXS02ACWG 0C to +70C 24 Wide SO v2 ALE aetd) ADDRESS 6 TSMSE MAX502BCWG 0C to+70C 24 Wide SO 3/4 8085A/8088 || LOAC MAX502BC/D 0C to +70C_ Dice* 3/4 ZN MAXIM MAXSO2AENG -40C to +85C 24 Narrow Plastic DIP 1/2 wR Pl wa MAX501 MAX502BENG 40C to +85C 24Narrow Plastic DIP 3/4 8 MAXSO2AEWG -40C to +85C 24 Wide SO 1/2 ADO-AD7 bo/D8-07 MAX502BEWG -40C to +85C 24 Wide SO 3/4 ; MAXSO2AMRG -55C to 125C 24NarrowCERDIP 1/2 MAXS02BMRG -55C to +125C 24.Narrow CERDIP* 3/4 * Contact factory for dice specifications. ** Contact factory for availability and processing to MIL-STD-883. Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 12 Maxim integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600 1996 Maxim Integrated Products Printed USA AMAAXUM is a registered trademark of Maxim Integrated Products.