MCP6022-I/STG - Microchip Technology

MCP6021/1R/2/3/4

Features

• Rail-to-Rail Input/Output

• Wide Bandwidth: 10 MHz (typ.)

• Low Noise: 8.7 nV/√Hz, at 10 kHz (typ.)

• Low Offset Voltage:

- Industrial Temperature: ±500 µV (max.)

- Extended Temperature: ±250 µV (max.)

• Mid-Supply VREF: MCP6021 and MCP6023

• Low Supply Current: 1 mA (typ.)

• Total Harmonic Distortion: 0.00053% (typ., G = 1)

• Unity Gain Stable

• Power Supply Range: 2.5V to 5.5V

• Temperature Range:

- Industrial: -40°C to +85°C

- Extended: -40°C to +125°C

Typical Applications

• Automotive

• Driving A/D Converters

• Multi-Pole Active Filters

• Barcode Scanners

• Audio Processing

• Communications

• DAC Buffer

• Test Equipment

• Medical Instrumentation

Available Tools

• SPICE Macro Model (at www.microchip.com)

•FilterLab

® software (at www.microchip.com)

Typical Application

Description

The MCP6 021, MCP60 21R, MCP6022, MC P6023 and

MCP6024 from Microchip Technology Inc. are rail-to-

rail input and output op amps with high performance.

Key specifications include: wide bandwidth (10 MHz),

low nois e (8.7 nV/√Hz), low input of fset volt age and low

distortion (0.00053% THD+N). The MCP6023 also

offers a C hi p Sel ect pi n ( CS ) tha t gi ve s powe r sa vi n gs

when the part is not in use.

The single MCP6021 and MCP6021R are available in

SOT-23-5. The sing le M CP602 1, si ngl e MC P6 023 and

dual MCP6022 are a vai la ble in 8-l ea d PDIP, SOIC and

TSSOP. The Extended Temperature single MCP6021

is available in 8-lead MSOP. The quad MCP6024 is

offered in 14-lead PDIP, SOIC and TSSOP packages.

The MCP6021/1R/2/3/4 family is available in Industrial

and Extended temperature ranges. It has a power

supply range of 2.5V to 5.5V.

Package Types

Photo

Detector

100 pF

5.6 pF

100 kΩ

VDD/2

MCP6021

Transimpedan ce Amplifier

MCP6021

SOT-23-5

VDD

VIN–

VOUT

VSS

VIN+

MCP6022

PDIP SOIC, TSSOP

VDD

VOUT

VREF

VIN–

VIN+

VSS

MCP6023

PDIP SOIC, TSSOP

VDD

VOUTB

VINB–

VINB+

VOUTA

VINA–

VINA+

VSS

MCP6024

PDIP SOIC, TSSOP

VOUTD

VIND–

VIND+

VSS

VOUTA

VINA–

VINA+

VDD VINC+

VINC–

VOUTC

VINB+

VINB–

VOUTB

MCP6021

PDIP SOIC,

MSOP, TSSOP

VDD

VOUT

VREF

VIN–

VIN+

VSS

MCP6021R

SOT-23-5

VSS

VIN–

VOUT

VDD

VIN+

Rail-to-Rail Input/Output, 10 MHz Op Amps

MCP6021/1R/2/3/4

1.0 ELECTRICAL

CHARACTERISTICS

Absolute Maximum Ratings †

VDD –V

SS ........................................................................7.0V

All Inputs and Outputs....................VSS – 0.3V to VDD +0.3V

Difference Input Voltage ...................................... |VDD –V

SS|

Output Short Circuit Current ................................ ..continuous

Current at Input Pins ..... .... ....... .... .. .... .. ......... .. .... .. .... ...±2 m A

Current at Output and Supply Pins ............................±30 mA

Storage Temperature..................... .... .. .. .. ......-65°C to +150°C

Junction Temperature...................... .. .... ......... .. .... .. .... .+150°C

ESD Protection on all pins (HBM; MM)................ ≥ 2 kV; 200V

† Notice: Stresses above those listed under “Absolute

Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of

the device at those or any other conditions above those

indicated in the operational listings of this specification is not

implied. Exposure to maximum rating conditions for extended

periods may affect device reliability.

DC ELECTRICAL CHARAC TERISTICS

Electrical Specifications: Unless otherwise indicated, T A = +25°C, VDD = +2. 5V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈VDD/2

and RL =10kΩ to VDD/2.

Parameters Sym Min Typ Max Units Conditions

Input Of fset

Input Offset Voltage:

Industrial Temperature Parts VOS -500 — +500 µV VCM = 0V

Extended Temperature Parts VOS -250 — +250 µV VCM = 0V, VDD = 5.0V

Extended Temperature Parts VOS -2.5 — +2.5 mV VCM = 0V, VDD = 5.0V

TA = -40°C to +125°C

Input Offset Voltage Temperature Drift ΔVOS/ΔTA—±3.5—µV/°CT

A = -40°C to +125°C

Power Supply Rejection Ratio PSRR 74 90 — dB VCM = 0V

Input Curr e nt and Impedan c e

Input Bias Current IB—1—pA

Industrial Temperature Parts IB— 30 150 pA TA = +85°C

Extended Temperature Parts IB— 640 5,000 pA TA = +125°C

Input Offset Current IOS —±1—pA

Common-Mode Input Impedance ZCM —10

13||6 — Ω||pF

Differential Input Impedance ZDIFF —10

13||3 — Ω||pF

Common-Mode

Common-Mode Input Range VCMR VSS-0.3 — VDD+0.3 V

Common-Mode Rejection Ratio CMRR 74 90 — dB VDD = 5V, VCM = -0.3V to 5.3V

CMRR 70 85 — dB VDD = 5V, VCM = 3.0V to 5.3V

CMRR 74 90 — dB VDD = 5V, VCM = -0.3V to 3.0V

Voltage Reference (MCP6021 and MCP6023 only)

VREF Accuracy (VREF –V

DD/2) VREF_ACC -50 — +50 mV

VREF Temperature Drift ΔVREF/ΔTA— ±100 — µV/°C TA = -40°C to +125°C

Open-Loop Gain

DC Open-Loop Gain (Large Signal) AOL 90 110 — dB VCM = 0V,

VOUT = VSS+0.3V to VDD-0.3V

Output

Maximum Output Voltage Swing VOL, VOH VSS+15 — VDD-20 mV 0.5V output overdrive

Output Short Circuit Current ISC —±30—mAV

DD = 2.5V

ISC —±22—mAV

DD = 5.5V

Power Supply

Supply Voltage VS2.5 — 5.5 V

Quiescent Current per Amplifier IQ0.5 1.0 1.35 mA IO = 0

MCP6021/1R/2/3/4

AC ELECTRICAL CHARAC TERISTICS

MCP6023 CHIP SELECT (CS) ELECTRICAL CHARACTERISTICS

Electrical Specifications: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/2,

VOUT ≈VDD/2, RL =10kΩ to VDD/2 and CL = 60 pF.

Parameters Sym Min Typ Max Units Conditions

AC Response

Gain Bandwidth Product GBWP — 10 — MHz

Phase Margin at Unity-Gain PM — 65 — ° G = +1

Settling Time, 0.2% tSETTLE — 250 — ns G = +1, VOUT = 100 mVp-p

Slew Rate SR — 7.0 — V/µs

Total Har m onic D ist o r t i on Plus N oise

f = 1 kHz, G = +1 V/V THD+N — 0.00053 — % VOUT = 0.25V to 3.25V (1.75V ± 1.50VPK),

VDD = 5.0V, BW = 22 kHz

f = 1 k H z, G = +1 V/V, RL = 600ΩTHD+N — 0.00064 — % VOUT = 0.25V to 3.25V (1.75V ± 1.50VPK),

VDD = 5.0V, BW = 22 kHz

f = 1 kHz, G = +1 V/V THD+N — 0.0014 — % VOUT = 4VP-P, VDD = 5.0V, BW = 22 kHz

f = 1 kHz, G = +10 V/V THD+N — 0.0009 — % VOUT = 4VP-P, VDD = 5.0V, BW = 22 kHz

f = 1 kHz, G = +100 V/V THD+N — 0.005 — % VOUT = 4VP-P, VDD = 5.0V, BW = 22 kHz

Noise

Input Noise Voltage Eni — 2.9 — µVp-p f = 0.1 Hz to 10 Hz

Input Noise Voltage Density eni —8.7—nV/√Hz f = 10 kHz

Input Noise Current Density ini —3—fA/√Hz f = 1 kHz

Electrical Specifications: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/2,

VOUT ≈VDD/2, RL =10kΩ to VDD/2 and CL = 60 pF.

Parameters Sym Min Typ Max Units Conditions

CS Low Specifications

CS Logic Threshold, Low VIL VSS —0.2V

DD V

CS Input Current, Low ICSL -1.0 0.01 — µA CS = VSS

CS High Specifications

CS Logic Threshold, High VIH 0.8 VDD —V

DD V

CS Input Current, High ICSH —0.012.0 µACS = VDD

GND Current ISS -2 -0.05 — µA CS = VDD

Amplifier Output Leakage IO(LEAK) —0.01— µACS = VDD

CS Dynamic Specifications

CS Low to Amplifier Output Turn-on Ti m e tON — 2 10 µs G = +1, VIN = VSS,

CS = 0.2VDD to VOUT = 0.45VDD time

CS High to Amplifier Output High-Z Time tOFF — 0.01 — µs G = +1, VIN = VSS,

CS = 0.8VDD to VOUT = 0.05VDD time

Hysteresis VHYST —0.6— VV

DD = 5.0V, Internal Switch

MCP6021/1R/2/3/4

TEMPERATURE CHARACTERISTICS

FIGURE 1-1: Timing diagram for the CS

pin on the MCP6023.

Electrical Specifications: Unless otherwise indicated, VDD = +2.5V to +5.5V and VSS = GND.

Parameters Sym Min Typ Max Units Conditions

Temperature Rang es

Industrial Temp erature Range TA-40 — +85 °C

Extended Temperature Range TA-40 — +125 °C

Operating Temperature Range TA-40 — +125 °C Note 1

Storage Temperature Range TA-65 — +150 °C

Thermal Package Resistances

Thermal Resistance, 5L-SOT-23 θJA — 256 — °C/W

Thermal Resistance, 8L-PDIP θJA —85—°C/W

Thermal Resistance, 8L-SOIC θJA — 163 — °C/W

Thermal Resistance, 8L-MSOP θJA — 206 — °C/W

Thermal Resistance, 8L-TSSOP θJA — 124 — °C/W

Thermal Resistance, 14L-PDIP θJA —70—°C/W

Thermal Resistance, 14L-SOIC θJA — 120 — °C/W

Thermal Resistance, 14L-TSSOP θJA — 100 — °C/W

Note 1: The industrial temperature devices operate over this extended temperature range, but with reduced performance. In any

case, the internal junction temperature (TJ) must not exceed the absolute maximum specification of 150°C.

High-Z

tON

tOFF

VOUT

-50 nA (typ.)

High-Z

ISS

ICS 10 nA (typ.) 1 0 nA (typ.) 10 nA (typ.)

-50 nA (typ.)

-1 mA (typ.)

Amplifier On

MCP6021/1R/2/3/4

2.0 TYPICAL PERFORMANCE CURVES

Note: Unless otherwise indicated, TA= +25°C, VDD =+2.5Vto+5.5V, V

SS = GND, VCM =V

DD/2, VOUT ≈VDD/2,

RL=10kΩto VDD/2 and C L=60 pF.

FIGURE 2-1: Input Offset Voltage,

(Industr i al Temperatu re Parts).

FIGURE 2-2: Input Offset Voltage,

(Extend ed Temperatu re Parts).

FIGURE 2-3: Input Offset Voltage vs.

Common Mode Input Voltage with VDD = 2.5V.

FIGURE 2-4: Input Offset Voltage Drift,

(Industrial Temperature Parts).

FIGURE 2-5: Input Offset Voltage Drift,

(Extended Temperature Parts).

FIGURE 2-6: Input Offset Voltage vs.

Common Mode Input Voltage with VDD = 5.5V.

Note: The g r ap hs and t ables prov id ed fol low i ng thi s n ote are a statis tic al s umm ar y based on a l im ite d n um ber of

samples and are provided for informational purposes only. The performance characteristics listed herein

are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified

operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

10%

12%

14%

16%

-500

-400

-300

-200

-100

100

200

300

400

500

Input Offset Voltage (µV)

Percentage of Occurances

1192 Samples

VCM = 0V

TA = +25°C

I-Temp

Parts

10%

12%

14%

16%

18%

20%

22%

24%

-240

-200

-160

-120

-80

-40

120

160

200

240

Input Offset Voltage (µV)

Percentage of Occurances

438 Samples

VDD = 5.0V

VCM = 0V

TA = +25°C

E-Temp

Parts

-500

-400

-300

-200

-100

100

200

300

400

500

-0.50.00.51.01.52.02.53.0

Common Mode Input Voltage (V)

Input Offset Voltage (µV)

VDD = 2.5V -40°C

+25°C

+85°C

+125°C

10%

12%

14%

16%

18%

20%

22%

24%

-20

-16

-12

-8

-4

Input Offset Voltage Drift (µV/°C)

Percentage of Occurances

1192 Samples

VCM = 0V

TA = -40°C to +85°C

I-Temp

Parts

10%

12%

14%

16%

18%

20%

22%

24%

-20

-16

-12

-8

-4

Input Offset Voltage Drift (µV/°C)

Percentage of Occurances

438 Samples

VCM = 0V

TA = -40°C t o + 1 2 5° C

E-Temp

Parts

-500

-400

-300

-200

-100

100

200

300

400

500

-0.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

Common Mode Input Voltage (V)

Input Offset Voltage (µV)

VDD = 5.5V -40°C

+25°C

+85°C

+125°C

MCP6021/1R/2/3/4

Note: Unless otherwise indicated, TA= +25°C, VDD =+2.5Vto+5.5V, V

SS = GND, VCM =V

DD/2, VOUT ≈VDD/2,

RL=10kΩto VDD/2 and C L=60 pF.

FIGURE 2-7: Input Offset Voltage vs.

Temperature.

FIGURE 2-8: Input Noise Voltage Density

vs. Frequency.

FIGURE 2-9: CMRR, PSRR vs.

Frequency.

FIGURE 2-10: Input Offset Vo ltage vs.

Output Voltage.

FIGURE 2-11: Input Noise Voltage Density

vs. Common Mode Input Voltage.

FIGURE 2-12: CMRR, PSRR vs.

Temperature.

-300

-250

-200

-150

-100

-50

100

-50 -25 0 25 50 75 100 125

Ambient Temperature (°C)

Input Offset Voltage (µV)

VDD = 5.0V

VCM = 0V

100

1,000

1.E-01 1.E+00 1.E+0 1 1.E+02 1. E+03 1.E +04 1.E+05 1 .E+06

Frequency (Hz)

Input Noise Vol tage Densi ty

(nV/√Hz)

0.1 1 10 100 1k 10k 1M100k

100

1.E+0 2 1.E+ 03 1.E+ 04 1.E +05 1.E +06

Frequency (Hz)

CMRR, PSRR (dB)

PSRR+

PSRR-

CMRR

100 1k 10k 100k 1M

-200

-150

-100

-50

100

150

200

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

Output Voltage (V)

Input Offset Voltage (µV)

VDD = 5.5V

VCM = VDD/2

VDD = 2.5V

-0.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

Common Mode Input Voltage (V)

Input Noise Vol tage Densi ty

(nV/√Hz)

VDD = 5.0V

f = 1 kHz

f = 10 kHz

100

105

110

-50 -25 0 25 50 75 100 125

Ambient Temper atu re (°C)

PSRR, CMRR (dB)

PSRR (VCM = 0V)

CMRR

MCP6021/1R/2/3/4

Note: Unless otherwise indicated, TA= +25°C, VDD =+2.5Vto+5.5V, V

SS = GND, VCM =V

DD/2, VOUT ≈VDD/2,

RL=10kΩto VDD/2 and C L=60 pF.

FIGURE 2-13: Input Bias, Offset Currents

vs. Common Mode Input Voltage.

FIGURE 2-14: Quiescent Current vs.

Supply Voltage.

FIGURE 2-15: Output Short-Circuit Current

vs. Supply Voltage.

FIGURE 2-16: Input Bias, Offset Currents

vs. Temperature.

FIGURE 2-17: Quiescent Current vs.

Temperature.

FIGURE 2-18: Open-Loop Gain, Phase vs.

Frequency.

100

1,000

10,000

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

Common Mode Input Voltage (V)

Input Bias, Offset Currents (pA)

IB, TA = +125°C

VDD = 5.5V

IOS, TA = +85°C

IOS, T A = +125°C

IB, TA = +85°C

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

1.1

1.2

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

Power Supply Voltage (V)

Quiescent Current

(mA/amplifier)

+125°C

+85°C

+25°C

-40°C

0.00.51.01.52.02.53.03.54.04.55.05.5

Supply Voltage (V)

Output Short Circuit Current

(mA)

+125°C

+85°C

+25°C

-40°C

100

1,000

10,000

25 35 45 55 65 75 85 95 105 115 125

Ambient Temperature (°C)

Input Bias, Offset Currents

(pA)

VCM = VDD

VDD = 5.5V

IOS

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

1.1

1.2

-50 -25 0 25 50 75 100 125

Ambient Temperature (°C)

Quiescent Current

(mA/amplifier)

VDD = 5.5V

VDD = 2.5V

VCM = VDD - 0.5V

-20

-10

100

110

120

1.E+00 1.E+01 1.E +02 1.E+03 1. E+04 1.E+0 5 1.E+06 1. E+07 1.E+08

Frequency (Hz)

Open-Loop Gain (dB)

-210

-195

-180

-165

-150

-135

-120

-105

-90

-75

-60

-45

-30

-15

Open-Loop Phase (°)

Gain

Phase

1 10010 1k 100k10k 1M 100M10M

MCP6021/1R/2/3/4

Note: Unless otherwise indicated, TA= +25°C, VDD =+2.5Vto+5.5V, V

SS = GND, VCM =V

DD/2, VOUT ≈VDD/2,

RL=10kΩto VDD/2 and C L=60 pF.

FIGURE 2-19: DC Open-Loop Gain vs.

Load Resistance.

FIGURE 2-20: Small Signal DC Open-Loop

Gain vs. Output Voltage Headroom.

FIGURE 2-21: Gain Bandwidth Product,

Phase Margin vs. Temperature.

FIGURE 2-22: DC Open-Loop Gain vs.

Temperature.

FIGURE 2-23: Gain Bandwidth Product,

Phase Margin vs. Common Mode Input Voltage.

FIGURE 2-24: Gain Bandwidth Product,

Phase Margin vs. Output Voltage.

100

110

120

130

1.E+02 1.E+03 1.E+ 04 1.E+0 5

Load Resist ance (Ω)

DC Open-Loop Gain (dB)

VDD = 5.5V

VDD = 2.5V

100 1k 10k 100k

100

110

120

0.00 0.05 0.10 0.15 0.20 0.25 0.30

Output Voltage Headroom (V);

VDD - VOH or VOL - VSS

DC Open-Loop Gain (dB)

VCM = VDD/2

VDD = 2.5V

VDD = 5.5V

-50 -25 0 25 50 75 100 125

Ambie nt Tem peratu re (°C)

Gain Bandwidth Product

(MHz)

100

Phase Margin, G = +1 (°)

GBWP, VDD = 5.5V

GBWP, VDD = 2.5V

PM, VDD = 2.5V

PM, VDD = 5.5V

100

105

110

115

120

-50 -25 0 25 50 75 100 125

Ambient Temperature (°C)

DC Open-Loop Gain (dB)

VDD = 5.5V

VDD = 2.5V

0.00.51.01.52.02.53.03.54.04.55.0

Common Mode Input Voltage (V)

Gain Bandwidth Product

(MHz)

105

Phase Margin, G = +1 (°)

Gain Bandwidth Product

Phase Margin, G = +1

VDD = 5.0V

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

Output Voltage (V)

Gain Bandwidth Product

(MHz)

105

Phase Margin, G = +1 (°)

Gain Bandwidth Product

Phase Margin, G = +1

VDD = 5.0V

VCM = VDD/2

MCP6021/1R/2/3/4

Note: Unless otherwise indicated, TA= +25°C, VDD =+2.5Vto+5.5V, V

SS = GND, VCM =V

DD/2, VOUT ≈VDD/2,

RL=10kΩto VDD/2 and C L=60 pF.

FIGURE 2-25: Slew Rate vs. Temperature.

FIGURE 2-26: Total Harmonic Distortion

plus Noise vs. Output V oltage with f = 1 kHz.

FIGURE 2-27: The MCP 6021 /1R/ 2/3/4

family shows no phase reversal under overdrive.

FIGURE 2-28: Maximum Output Voltage

Swing vs. Frequency.

FIGURE 2-29: Total Harmonic Distortion

plus Noise vs. Output Voltage with f = 20 kHz.

FIGURE 2-30: Channel-to-Channel

Separation vs. Frequency (MCP6022 and

MCP6024 only).

-50 -25 0 25 50 75 100 125

Ambie nt Tem pe rat ur e (°C)

Slew Rate (V/µs)

Falling, VDD = 2.5V

Rising, VDD = 2.5V

Falling, VDD = 5.5V

Rising, VDD = 5.5V

0.0001%

0.0010%

0.0100%

0.1000%

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

Output Voltage (VP-P)

THD+N (%)

f = 1 kHz

BWMeas = 22 kHz

VDD = 5.0V

G = +1 V/V

G = +10 V/V

G = +100 V/V

-1

0 102030405060708090100

Time (10 µs/div)

Input, Output Voltage (V)

VDD = 5.0V

G = +2 V/V

VIN

VOUT

0.1

1.E+04 1.E+0 5 1.E+06 1.E +07

Frequency (Hz)

Maximum Output Voltage

Swing (VP-P)

VDD = 5.5V

10k 100k 1M 10M

VDD = 2.5V

0.0001%

0.0010%

0.0100%

0.1000%

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

Output Voltage (VP-P)

THD+N (%)

G = +10 V/V

f = 20 kHz

BWMeas = 80 kHz

VDD = 5.0V

G = +1 V/V

G = +100 V/V

105

110

115

120

125

130

135

1.E+03 1.E+ 04 1.E+05 1.E +06

Frequency (Hz)

Channel to Channel Separation

(dB)

1k 1M100k10k

G = +1 V/V

MCP6021/1R/2/3/4

Note: Unless otherwise indicated, TA= +25°C, VDD =+2.5Vto+5.5V, V

SS = GND, VCM =V

DD/2, VOUT ≈VDD/2,

RL=10kΩto VDD/2 and C L=60 pF.

FIGURE 2-31: Output Voltage Headroom

vs. Output Current.

FIGURE 2-32: Small-Signal Non-inverting

Pulse Response.

FIGURE 2-33: Large-Signal Non-inverting

Pulse Response.

FIGURE 2-34: Output Voltage Headroom

vs. Temperature.

FIGURE 2-35: Small-Signal Inverting Pulse

Response.

FIGURE 2-36: Large-Signal Inverting Pulse

Response.

100

1,000

0.01 0.1 1 10

Output Current Magnitude (mA)

Output Voltage Headroom;

VDD-VOH or VOL-VSS (mV)

VDD - VOH

VOL - VSS

-6.E-02

-5.E-02

-4.E-02

-3.E-02

-2.E-02

-1.E-02

0.E+00

1.E-02

2.E-02

3.E-02

4.E-02

5.E-02

6.E-02

0.E+00 2.E-07 4.E-07 6. E-07 8.E-07 1. E-06 1.E- 06 1.E-06 2.E- 06 2.E-06 2.E-0 6

Time (200 ns/div)

Output Voltage (10 mV/div)

G = +1 V/V

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

0.E+00 5.E-07 1.E-0 6 2.E-06 2 .E-06 3.E- 06 3.E-06 4.E- 06 4.E-06 5.E -06 5.E-0 6

Time (500 ns/div)

Output Voltage (V)

G = +1 V/V

-50 -25 0 25 50 75 100 125

Ambient Tem perat ur e (°C)

Output Voltage Headroom

VDD-VOH or VOL-VSS (mV)

VDD - VOH

VOL - VSS

-6.E-02

-5.E-02

-4.E-02

-3.E-02

-2.E-02

-1.E-02

0.E+00

1.E-02

2.E-02

3.E-02

4.E-02

5.E-02

6.E-02

0.E+00 2.E-07 4.E-07 6.E-07 8.E-07 1.E-06 1.E-06 1.E-06 2.E-06 2.E-06 2.E-06

Time (200 ns/div)

Output Voltage (10 mV/div)

G = -1 V/V

RF = 1 kΩ

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

0.E+00 5.E-07 1.E-06 2. E-06 2.E-06 3. E-06 3.E- 06 4.E-06 4.E- 06 5.E-06 5.E-0 6

Time (500 ns/div)

Output Voltage (V)

G = -1 V/V

RF = 1 kΩ

MCP6021/1R/2/3/4

Note: Unless otherwise indicated, TA= +25°C, VDD =+2.5Vto+5.5V, V

SS = GND, VCM =V

DD/2, VOUT ≈VDD/2,

RL=10kΩto VDD/2 and C L=60 pF.

FIGURE 2-37: VREF Accuracy vs. Supply

Voltage (MCP6021 and MCP6023 only).

FIGURE 2-38: Chip Select (CS) Hysteresis

(MCP6023 only) with VDD = 2.5V.

FIGURE 2-39: Chip Select (CS) to

Amplifier Output Response Time (MCP602 3

only).

FIGURE 2-40: VREF Accuracy vs.

Temperature (MCP6021 and MCP6023 only).

FIGURE 2-41: Chip Select (CS) Hysteresis

(MCP6023 only) with VDD = 5.5V.

-50

-40

-30

-20

-10

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

Power Supply Voltage (V)

VREF Accuracy; VREF – VDD/2

(mV)

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

0.0 0.5 1.0 1.5 2.0 2.5

Chip Select Voltag e (V)

Quiescent Current

(mA/amplifier)

Op Amp

shuts off here

Op Amp

turns on he re

Hysteresis

VDD = 2.5V

G = +1 V/V

VIN = 1.25V

CS swept

low to high

CS swept

high to low

-0.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

0.0E+00 5.0E-06 1.0E -05 1.5E- 05 2.0E-05 2.5 E-05 3.0E-05 3. 5E-05

Time (5 µs/div)

Chip Select Voltage,

Output Voltage (V)

Output High-Z

VDD = 5.0V

G = +1 V/V

VIN = VSS

Output

VOUT

CS Voltage

-50

-40

-30

-20

-10

-50 -25 0 25 50 75 100 125

Ambient Temperature (°C)

VREF Accuracy; VREF – VDD/2

(mV)

VDD = 5.5V

VDD = 2.5V

Representative Part

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

0.00.51.01.52.02.53.03.54.04.55.05.5

Chip Select Voltage (V)

Quiescent Current

(mA/amplifier)

Op Amp

shuts off here

Op Amp

turns on here

Hysteresis

CS swept

high to low CS swept

low to high

VDD = 5.5V

G = +1 V/V

VIN = 2.75V

MCP6021/1R/2/3/4

3.0 PIN DESCRIPTIONS

Descriptions of the pins are listed in Table 3-1.

TABLE 3-1: PIN FUNCTION TABLE

3.1 Analog Outputs

The op amp output pins are low-impedance voltage

sources.

3.2 Analog Inputs

The op amp non-inverting and inverting inputs are high-

impedance CMOS inputs with low bias currents.

3.3 VREF Output (MCP6021 and

MCP6023)

Mid-su pply re fere nce voltage provi ded by the si ngle o p

amps (except in SOT-23-5 package). This is an

unbuffered, resistor voltage divider internal to the part.

3.4 CS Digital Input

This i s a CMOS , Schmitt-tri ggered i nput that places the

part into a low power mode of operation.

3.5 Power Supply (VSS and VDD)

The positive power supply pin (VDD) is 2.5V to 5.5V

higher than the negative power supply pin (VSS). For

normal operation, the other pins are at voltages

between VSS and VDD.

Typically, these parts are used in a single (positive)

supply configuration. In this case, VSS is connected to

ground and VDD is connected to the supply. VDD will

need a local bypass capacitor (typically 0.01 µF to

0.1 µF) within 2 mm of the VDD pin. These parts need

to us e a bu lk capac itor ( typic ally 1 µF or l arger) w ithin

100 mm of the VDD pin; it can be shared with nearby

analog parts.

MCP6021

(PDIP,

SOIC,

MSOP,

TSSOP)

(Note 1)

MCP6021

(SOT-23-5)

(Note 1)

MCP6021R

(SOT-23-5)

(Note 2) MCP6022 MCP6023 MCP6024 Symbol Description

61 1161V

OUT,V

OUTA Analog Output (op amp A)

24 4222V

IN–, VINA– Inverting Input (op amp A)

33 3333V

IN+, VINA+ Non-inverting Input (op amp A)

75 2874V

DD Positive Power Supp ly

—— — 5—5V

INB+ Non-inverting Input (op amp B)

—— — 6—6V

INB– Inverting Input (op amp B)

—— — 7—7V

OUTB Analog Output (op amp B)

—— ———8V

OUTC Analog Output (op amp C)

—— ———9V

INC– Inverting Input (op amp C)

—— ———10V

INC+ Non-inverting Input (op amp C)

42 54411V

SS Negative Power Supply

—— ———12V

IND+ Non-inverting Input (op amp D)

—— ———13V

IND– Inverting Input (op amp D)

—— ———14V

OUTD Analog Output (op amp D)

5— ——5—V

REF Reference Vo ltage

—— ——8—CS

Chip Select

1, 8 — — — 1 — NC No Internal Connection

Note 1: The MCP6021 in the 8-pin MSOP package is only available for E-temp (Ex tended Temperature) parts. The MCP6021

in the 8-pin TSSOP package is only available for I-temp (Industrial Temperature) parts.

2: The MCP6021R is only available in the 5-pin SOT - 23 package, and for E-temp (Extended Temperature) parts.

MCP6021/1R/2/3/4

4.0 APPLICATIONS INFORMATION

The MC P6021/1R/2/3/4 fa mily of opera tional amplifie rs

are fabricated on Microchip’s state-of-the-art CMOS

process. They are unity-gain stable and suitable for a

wide range of general-purpose applications.

4.1 Rail-to-Rail Input

The MCP6021/1R/2/3/4 amplifier family is designed to

not exhi bit pha se in ver sion wh en the i nput pi ns ex ceed

the supply voltages. Figure 2-27 shows an input volt-

age exceeding both supplies with no resulting phase

inversion.

The input stage of the MCP6021/1R/2/3/4 family of

devices uses two differential input stages in parallel;

one operates at low common-mode input voltage

(VCM), while the other operates at high VCM. With this

topolog y, the dev ice ope rates with VCM up to 0.3V past

eith er su ppl y r ai l (V SS – 0 .3V to VDD + 0.3V) at +25°C.

The amplifier input behaves linearly as long as VCM is

kept within the specified VCMR limits. The input offset

voltage is measured at both VCM =V

SS –0.3V and

VDD + 0.3V to ensure proper operation.

Input voltages that exceed the input voltage range

(VCMR) can cause excessive current to flow in or out of

the input pins. Current beyond ±2 mA introduces

possible reliability problems. Thus, applications that

exceed this ratin g must external ly limit the input current

with an input resistor (RIN), as shown in Figure 4-1.

FIGURE 4-1: RIN limits the current flow

into an input pin.

Total Harmonic Distortion Plus Noise (THD+N) can be

affected by the common mode input voltage (VCM). As

shown in Figure 2-3 and Figure 2-6, the input offset

voltage (VOS) is aff ected by the change from the NMOS

to the PMOS input d ifferential p airs. This chan ge in VOS

will increase the distortion if the input voltage includes

this transition region. This transition occurs between

VDD – 1.0V and VDD – 2.0V, depending on VDD and

temperature.

4.2 Rail-to-Rail Output

The Maximum Output Voltage Swing is the maximum

swing possible under a particular output load.

According to the specification table, the output can

reach within 20 mV of either supply rail when

RL=10kΩ. See Figure 2-31 and Figure 2-34 for more

information concerning typical performance.

4.3 Capacitive Loads

Driving large capacitive loads can cause stability

problems for voltage feedback op amps. As the load

capacitance increases, the feedback loop’s phase

margin decreases, and the closed loop bandwidth is

reduced. This produces gain-peaking in the frequency

response, with overshoot and ringing in the step

response.

When driving large capacitive loads with these op

amps (e.g., > 60 pF when G = +1), a small series

resistor at the output (RISO in Figure 4-2) improves the

feedback loop’s phase margin (stability) by making the

load res istiv e at hi gher fre quenci es. Th e band widt h wil l

be generally lower than the bandwidth with no

capacitive load.

FIGURE 4-2: Output resistor RISO

stabil izes large capacitive loads.

Figure 4-3 gives recommended RISO values for

different capacitive loads and gains. The x-axis is the

normalized load capacitance (CL/GN), where GN is the

circuit ’s noise g ain. For non-in verting gains , GN and the

Signal Gain are equal. For inverting gains, GN is

1+|Signal Gain| (e.g., -1 V/V gives GN = +2 V/V).

FIGURE 4-3: Recommended RISO values

for capacitive loads.

VIN

RIN VOUT

MCP602X

RIN

≥(Maximum expected

VIN

) -

VDD

2mA

RIN

≥

VSS

- (Minimum expected

VIN

)

2mA

VIN

MCP602X RISO VOUT

100

1,000

10 100 1,000 10,000

Normalized Ca pacitance; CL/GN (pF)

Recommended RISO (Ω)

GN ≥ +1

MCP6021/1R/2/3/4

After selecting RISO for your circuit, double-check the

resulting frequency response peaking and step

response overshoot. Modify RISO’s value until the

response is reasonable. Evaluation on the bench and

simulations with the MCP6021/1R/2/3/4 Spice macro

model are helpful.

4.4 Gain Peaking

Figure 2-35 and Figure 2-36 use RF=1kΩ to avoid

(frequency response) gain peaking and (step

respons e) overshoo t. The capac itance to ground at the

inverting input (CG) is the op amp’s common mode

input ca pac it ance p lus boa rd p arasiti c cap aci t ance. CG

is in para ll el with RG, which causes an increase in gain

at high fre quencies for non-inv erting gain s greater tha n

1 V/V (unity gain). CG also reduces the phase margin

of the feedback loop for both non-inverting and

inverting gains.

FIGURE 4-4: Non-inverti ng gain circuit

with parasitic capacitance.

The largest value of RF in Figure 4-4 that should be

used is a func tion of noi se gain (se e GN in Section 4.3

“Cap acitive Loads”) and CG. Figure 4-5 shows result s

for vari ous c on dit ion s. O the r c om pen sa tio n t echnique s

may be used, but they tend to be more complicated to

the design.

FIGURE 4-5: Non-inverti ng gain circuit

with parasitic capacitance.

4.5 MCP6023 Chip Select (CS)

The MCP6023 is a single amplifier with chip select

(CS). When CS is high, the supply current is less than

10 nA (typ) and travel s from the CS pin to VSS, with the

amplifier output being put into a high-impedance state.

When CS is low, the amplifier is enabled. If CS is left

floating, the amplifier may not operate properly.

Figure 1-1 and Figure 2-39 show the output voltage

and supply current response to a CS pulse.

4.6 MCP6021 and MCP6023 Reference

Voltage

The single op amps (MCP6021 and MCP6023), not in

the SOT-23-5 package, have an internal mid-supply

reference voltage connected to the VREF pin (see

Figure 4-6). The MCP6021 has CS internally tied to

VSS, which always keeps the op amp on and always

provides a mid-supply reference. With the MCP6023,

taking the CS pin high conserves power by shutting

down both the op amp and the VREF circuitry. Taking

the CS pin low turns on the op amp and VREF circuitry.

FIGURE 4-6: Simplified internal VREF

circuit (MCP6021 and MCP6023 only).

See Figure 4-7 for a non-in verting ga in circui t using th e

internal mid-supply reference. The DC-blocking

capacitor (CB) also reduces noise by coupling the op

amp input to the source.

FIGURE 4-7: Non-inverting gain circuit

using VREF (MCP6021 and MCP6023 only).

VIN

RGRF

VOUT

1.E+02

1.E+03

1.E+04

1.E+05

110

Noise Gain; GN (V/V)

Maximum RF (Ω)

GN > +1 V/V

100

10k

100k

CG = 7 pF

CG = 20 pF

CG = 50 pF

CG = 100 pF

VDD

VSS

VREF

50 kΩ

(CS tied internally to VSS for MCP6021)

VIN

RGRF

VOUT

CBVREF

MCP6021/1R/2/3/4

To use the internal mid-supply reference for an

inverting gain circuit, connect the VREF pin to the

non-inverting input, as shown in Figure 4-8. The

capacitor CB helps reduce power supply noise on the

output.

FIGURE 4-8: Inverting gain circuit using

VREF (MCP6021 and MCP6023 only).

If you don’t need the mid-supply reference, leave the

VREF pin open.

4.7 Supply Bypass

With this family of operational amplifiers, the power

supply pin (VDD for single supply) should have a local

bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm

for good, high-frequency performance. It also needs a

bulk capacitor (i.e., 1 µF or larger) within 100 mm to

provide large, slow curr ents. This bulk cap acitor ca n be

shared with nearby analog parts.

4.8 Unused Op Amps

An unused op amp in a quad package (MCP6024)

should be configured as shown in Figure 4-9. These

circuits prevent the output from toggling and causing

crosstalk. Circuit A can use any reference voltage

between the supplies, provides a buffered DC voltage,

and minimizes the supply current draw of the unused

op amp. C ircuit B uses the mini mum numb er of compo-

nent s an d opera tes as a comp arato r; it m ay draw more

current.

FIGURE 4-9: Unused Op Amps.

4.9 PCB Surface Leakage

In applications where low input bias current is critical,

PCB (printed circuit board) surface-leakage effects

need to be considered. Surface leakage is caused by

humidity, dust or other contamination on the board.

Under low humidity conditions, a typical resistance

betwee n nearby traces i s 1012Ω. A 5V dif ference would

cause 5 pA of current to flow, which is greater than the

MCP6021/1R/2/3/4 family’s bias current at +25°C

(1 pA, typ).

The easiest way to reduce surface leakage is to use a

guard ring around se nsi tiv e p ins (or t race s). The guard

ring is biased at the same voltage as the sensitive pin.

Figure 4-10 shows an example of this type of layout.

FIGURE 4-10: Example Guard Ring

Layout.

1. Non-inverting Gain and Unity-Gain Buffer.

a) Connect th e guard ring to the inverting input

pin (VIN–); this biases the guard ring to the

common mode input voltage.

b) Connect the non-inverting pin (VIN+) to the

input with a wire that does not touch the

PCB surface.

2. Inverting (Figure 4-10) and Transimpedance

Gain Amp lifiers (convert c urrent to volt age, such

as photo detectors).

a) Connect the guard ring to the non-inverting

input pin (VIN+). Thi s bi ases the gua rd ri ng

to the same reference voltage as the op

amp’s input (e.g., VDD/2 or ground).

b) Connect the inverting pi n (VIN–) to the input

with a wire that does not touch the PCB

surface.

4.10 High Speed PCB Layout

Due to their speed capabilities, a little extra care in the

PCB (Printed Circuit Board) layout can make a

significant difference in the performance of these op

amps. Good PC board layout techniques will help you

achieve the performance shown in Section 1.0 “Elec-

trical Characteristics” and Section 2.0 “T y pical Per-

formance Curves”, while also helping you minimize

EMC (Electro-Magnetic Compatibility) issues.

Use a so lid grou nd plan e and con nect the byp ass lo cal

capacitor(s) to this plane with minimal length traces.

This cuts down inductive and capacitive crosstalk.

VIN

RGRFVOUT

VREF

VDD

¼ MCP6 144 (A) ¼ MCP6144 (B)

VDD

Guard Ring VIN–V

IN+

MCP6021/1R/2/3/4

Separate digital from analog, low speed from high

speed a nd lo w po wer from high p ower. This will reduc e

interference.

Keep sensitive traces short and straight. Separating

them from interfering components and traces. This is

especially important for high-frequency (low rise-time)

signals.

Sometim es it hel p s to place gu ard trac es ne xt to vic tim

traces. They should be on both sides of the victim

trace, and as close as possible. Connect the guard

trace to ground plane at both ends, and in the middle

for long traces.

Use coax cables (or low inductance wiring) to route

signal and power to and from the PCB.

4.11 Typical Appl ications

4.11.1 A/D CONVERTER DRIVER AND

ANTI-ALIASING FILTER

Figure 4-11 shows a third-order Butterworth filter that

can be used as an A/D converter driver. It has a band-

wid th of 20 kHz and a reas on abl e s tep re sponse. I t wil l

work wel l for convers ion rates of 80 ksps and gre ater (it

has 29 dB attenuation at 60 kHz).

FIGURE 4-11: A/D converter driver and

anti-aliasing filter with a 20 kHz cutoff frequency.

This filt er c an ea sil y be ad jus ted to an othe r ba ndwi dth

by multiplying all capacitors by the same factor.

Altern ati vely, the res ist ors can all be s cal ed by another

common factor to adjust the bandwidth.

4.11.2 OPTICAL DETECTOR AMPLIFIER

Figure 4-12 shows the MCP6021 op amp used as a

transimpedance amplifier in a photo detector circuit.

The photo detector looks like a capacitive current

source, so th e 10 0 kΩ resis tor g ain s th e in put s ig nal to

a reasonable level. Th e 5.6 pF capacito r stabilizes this

circuit and produces a flat frequency response with a

bandwidth of 370 kHz.

FIGURE 4-12: Transimpedance Amplifier

for an Optical Detector .

14.7 kΩ33.2 kΩ

1.0 nF

100 pF

MCP602X

8.45 kΩ

1.2 nF

Photo

Detector

100 pF

5.6 pF

100 kΩ

VDD/2

MCP6021

MCP6021/1R/2/3/4

5.0 DESIGN TOOLS

Microchip provides the basic design tools needed for

the MCP6021/1R/2/3/4 family of op amps.

5.1 SPICE Macro Model

The latest SPICE macro model available for the

MCP60 21/1R/2/3 /4 op am ps is on Micr ochip’s w eb si te

at www.microchip.com. This model is intended as an

initial design tool that works well in the op amp’s linear

region of operation at room temperature. Within the

macro model file is information on its capabilities.

Bench testing is a ve ry important p art of any design and

cannot be replaced with simulations. Also, simulation

results usi ng th is ma cro m od el ne ed t o be validated b y

comparing them to the data sheet specifications and

characteristic curves.

5.2 FilterLab® Software

Microchip’s FilterLab® software is an innovative tool

that simplifies analog active filter (using op amps)

design. It is available free of charge from our web site

at www.microchip.com. The FilterLab software tool

provi des full schemati c diagrams of the filte r circuit with

component values. It also outputs the filter circuit in

SPICE format, which can be used with the macro

model to simulate actual filter performance.

MCP6021/1R/2/3/4

6.0 PACKAGING INFORMATION

6.1 Package Marking Information

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week ‘01’)

NNN Alphanumeric trac ea bil ity code

Pb-free JEDEC designator for Matte Tin (Sn)

*This package is Pb-free. The Pb-free JEDEC designator ( )

can be found on the outer packaging for this package.

Note: In the ev ent the fu ll Mic rochip part nu mber ca nnot be m arked o n one lin e, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

5-Lead SOT-23 (MCP6021/MCP6021R)Example: (E-temp)

XXNN EY25

Device E-Temp Code

MCP6021 EYNN

MCP6021R EZNN

Note: Applies to 5-Lead SOT-23

XXXXXXXX

XXXXXNNN

YYWW

8-Lead PDIP (300 mil) Example:

MCP6021

I/P256

0331

MCP6021

E/P^^256

0549

8-Lead SOIC (150 mil) Example:

XXXXXXXX

XXXXYYWW

NNN

MCP6021

I/SN0331

256

MCP6021E

SN^^0549

256

8-Lead MSOP Example:

XXXXXX

YWWNNN

6021E

549256

8-Lead TSSOP Example:

XXXX

YYWW

NNN

6021

E549

256

MCP6021/1R/2/3/4

Package Marking Information (Continued)

14-Lead PDIP (300 mil) (MCP6024) Example:

14-Lead TSSOP (MCP6024) Example:

14-Lead SOIC (150 mil) (MCP6024) Example:

XXXXXXXXXXXXXX

YYWWNNN

XXXXXXXXXX

YYWWNNN

XXXXXX

YYWW

NNN

MCP6024-I/P

XXXXXXXXXXXXXX

0331256

6024E

0331

256

XXXXXXXXXX

MCP6024ISL

0331256

XXXXXXXXXX

MCP6024

E/P^^

0549256

MCP6024

0549256

E/SL^^

MCP6021/1R/2/3/4

5-Lead Plastic Small Outline Transistor (OT) (SOT-23)

10501050

Mold Draft Angle Bottom 10501050

Mold Draft Angle Top 0.500.430.35.020.017.014BLead Width 0.200.150.09.008.006.004

Lead Thickness 10501050

Foot Angle 0.550.450.35.022.018.014LFoot Length 3.102.952.80.122.116.110DOverall Length 1.751.631.50.069.064.059E1Molded Package Width 3.002.802.60.118.110.102EOverall Width 0.150.080.00.006.003.000A1Standoff 1.301.100.90.051.043.035A2Molded Package Thickness 1.451.180.90.057.046.035AOv er all Height 1.90.075

Outside lead pitch (basic) 0.95.038

Pitch 55

Number of Pins MAXNOMMINMAXNOMMINDimension Limits MILLIMETERSINCHES

Units

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side.

Notes:

EIAJ Equivalent: SC-74A

Drawing No. C04-091

Contro lling Paramet er

Revised 09-12-05

MCP6021/1R/2/3/4

8-Lead Plastic Dual In-line (P) – 300 mil (PDIP)

Units INCHES* MILLIMETERS

Dime nsion Limits MIN NOM MAX MIN NOM M AX

Number of Pins n88

Pitch p.100 2.54

Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32

Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68

Base to Seating Plane A1 .015 0.38

Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.26

Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60

Overall Length D .360 .373 .385 9.14 9.46 9.78

Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43

Lead Thickness c.008 .012 .015 0.20 0.29 0.38

Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78

Lower Lead Width B .014 .018 .022 0.36 0.46 0.56

Overall Row Spacing § eB .310 .370 .430 7.87 9.40 10.92

Mold Draft Angle Top α51015 51015

Mold Draft Angle Bottom β51015 51015

* Controlling Parameter

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

JEDEC Equivalent: MS-001

Drawing No. C04-018

.010” (0.254mm) per side.

§ Significant Characteristic

MCP6021/1R/2/3/4

8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC)

Foot A ngle φ048048

1512015120

Mold Draft Angle Bottom 1512015120

Mold Draft Angle Top 0.510.420.33.020.017.013BLead Width 0.250.230.20.010.009.008

Lead Thickness

0.760.620.48.030.025.019LFoot Length 0.510.380.25.020.015.010hChamfer Distance 5.004.904.80.197.193.189DOverall Length 3.993.913.71.157.154.146E1Molded Pa ckag e Width 6.206.025.79.244.237.228EOverall Width 0.250.180.10.010.007.004A1Standoff § 1.551.421.32.061.056.052A2Molded Packag e Thickness 1.751.551.35.069.061.053AOverall Height 1.27.050

Pitch 88

Numb er of Pin s MAXNOMMINMAXNOMMINDimension Limits MILLIMETERSINCHES*Units

45°

* Controlling Parameter

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0.254mm) per side.

JEDEC Equiva lent : MS - 012

Drawing No. C04-057

§ Significant Characteristic

MCP6021/1R/2/3/4

8-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP)

βφ

10°5°0°10°5°0°

Mold Draft A n g le Bo tto m 10°5°0°10°5°0°

Mold Draft Angle Top 0.300.250.19.012.010.007BLead Width 0.200.150.09.008.006.004

Lead Thickness

0.700.600.50.028.024.020LFoot Length 3.103.002.90.122.118.114DMolded Package Length 4.504.404.30.177.173.169E1M olded Package Width 6.506.386.25.256.251.246EOverall Width 0.150.100.05.006.004.002A1Standoff 0.950.900.85.037.035.033A2Molded Package Thickness 1.101.051.00.043.041.039AOverall Height 0.65.026

Pitch 88

Number of Pins MAXNOMMINMAXNOMMINDimension Limits MILLIMETERS

INCHESUnits

Foot Angle

0° 4° 8° 0° 4° 8°

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side.

Notes:

JEDEC Equivalent: MO-153 Revised 07-21-05

Controlling Parameter

Drawing No. C04-086

MCP6021/1R/2/3/4

8-Lead Plastic Micro Small Outline Package (MS) (MSOP)

Bn1

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side.

.037 REFFFootprint (Reference)

Notes:

Revised 07-21-05

Controlling Parameter

Mold Draft Angle Top

Mold Draft Angle Bottom

Foot Angle

Lead Width

Lead Thickness

.003

.009 .006

.012

Dimension Limits

Overall Height

Molded Package Thickness

Molded Package Width

Overall Length

Foot Length

Standoff

Overall Width

Number of Pins

Pitch A

.016 .024

.118 BSC

.000

.030

.193 BSC

.033

MIN

Units

.026 BSC

NOM 8

INCHES

0.95 REF

.009

.016 0.08

0.22

0° 0.23

0.40

8°

MILLIMETERS

0.65 BSC

0.85

3.00 BSC

0.60

4.90 BSC

.043

.031

.037

.006

0.40

0.00

0.75

MIN

MAX NOM

1.10

0.80

0.15

0.95

MAX

15°5° - 15°5° -

JEDEC Equivalent: MO-187

0° - 8°

5°

5° -

-15°

15°

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

See ASME Y14.5M

Drawing No. C04-111

MCP6021/1R/2/3/4

14-Lead Plastic Dual In-line (P) – 300 mil (PDIP)

Units INCHES* MILLIMETERS

Dimen sion Li mits MIN NOM MAX MI N NOM MAX

Number of Pins n14 14

Pitch p.100 2.54

Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32

Molded Package Thickness A2 .11 5 .130 .145 2.92 3.30 3.68

Base to Seating Plane A1 .015 0.38

Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.26

Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60

Overal l Length D .740 .750 .7 60 1 8.8 0 19. 05 19.30

Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43

Lead Thickness c.008 .012 .015 0.20 0.29 0.38

Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78

Lower Lead Width B .014 .018 .022 0.36 0.46 0.56

Overall Row Spacin g § eB .3 10 .370 .430 7.87 9.40 10.92

Mold Draft Angle Top α5 10 15 5 10 15

β5 10 15 5 10 15Mold Draft Angle Bottom

* Controlling Parameter

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0.254mm) per side.

JEDEC Equivalent: MS-001

Drawing No. C04-005

§ Significant Characteristic

MCP6021/1R/2/3/4

14-Lead Plasti c Small Outline (SL) – Narrow, 150 mil (SOIC)

Foot A ngle φ048048

1512015120

Mold Draft Angle Bottom 1512015120

Mold Draft Angle Top 0.510.420.36.020.017.014BLead Width 0.250.230.20.010.009.008

Lead Thickness

1.270.840.41.050.033.016LFoot Length 0.510.380.25.020.015.010hChamfer Distance 8.818.698.56.347.342.337DOverall Length 3.993.903.81.157.154.150E1Molded Packag e Width 6.205.995.79.244.236.228EOverall Width 0.250.180.10.010.007.004A1Standoff § 1.551.421.32.061.056.052A2Mold ed Pa ckag e Thick ness 1.751.551.35.069.061.053AOverall Height 1.27.050

Pitch 1414

Number of Pins MAXNOMMINMAXNOMMINDimensi on Li mits MILLIMETERSINCHES*Units

45°

* Controlling Parameter

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0.254mm) per side.

JEDEC Equiva lent : MS- 012

Drawing No. C04-065

§ Significant Characteristic

MCP6021/1R/2/3/4

14-Lead Plasti c Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP)

A2A1

8°4°0°8°4°

0°

Foot Angle

Mold Draft Angle Bottom 12° REF

Mold Draft Angle Top 0.300.250.19.012.010.007BLead Width 0.200.150.09.008.006.004

Lead Thickness

0.700.600.50.028.024.020LFoot Length 5.105.004.90.201.197.193DMolded Package Length 4.504.404.30.177.173.169E1Molded Package Width 6.506.386.25.256.251.246EOver all Width 0.150.100.05.006.004.002A1Standoff 0.950.900.85.037.035.033A2Molded Package Thickness 1.101.051.00.043.041.039AOverall H eight 0.65 BSC.026 BSC

Pitch 1414

Number of Pins MAXNOMMINMAXNOMMINDimension Limits MILLIMETERS

INCHESUnits

Dimensions D and E1 do not include mold fla sh or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side.

Notes:

JEDEC Equivalent: MO-153 AB-1 Revised: 08-17-05

Controlling Parameter

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tole rance, for information purposes only.

See ASME Y14.5M

Drawing No. C04-087

12° REF 12° REF

12° REF

MCP6021/1R/2/3/4

NOTES:

MCP6021/1R/2/3/4

APPENDIX A: REVISION HISTORY

Revision C (March 2006)

The following is the list of modifications:

1. Added SOT-23-5 package option for single op

amp s MC P60 21 and M CP6021R (E-tem p o nly ).

2. Added MSOP-8 package option for E-temp

single op amp (MCP6021).

3. Corrected package drawing on front page for

dual op amp (MCP6022).

4. C larif ied spe c condi tions (I SC, PM and THD+N)

in Section 2.0 “Typical Performance

Curves”.

5. Added Sec tion 3.0 “Pin Descriptions”.

6. Updated Section 4.0 “Applications informa-

tion” for THD+N, unused op amps, and gain

peaking discussions.

7. Corrected and updated package marking infor-

mation in Section 6.0 “Packaging Informa-

tion”.

8. Added Appendix A: “REVISION HISTORY”.

Revision B (November 2003)

• Second Release o f thi s Docu ment

Revision A (November 2001)

• Original Release of this Document

MCP6021/1R/2/3/4

NOTES:

MCP6021/1R/2/3/4

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Device: MCP6021 Single Op Amp

MCP6021 T Single Op Amp

(Tape and Reel for SOT-23, SOIC, TSSOP,

MSOP)

MCP6021 R Sin gl e Op Amp

MCP6021RT Single Op Amp

(Tape and Reel for SOT-23)

MCP6022 Dual Op Amp

MCP6022T Dual Op Amp

(Tape and Reel for SOIC and TSSOP)

MCP6023 Single Op Amp w/ CS

MCP6023T Single Op Amp w/ CS

(Tape and Reel for SOIC and TSSOP)

MCP6024 Quad Op Amp

MCP6024T Quad Op Amp

(Tape and Reel for SOIC and TSSOP)

Temperature Range: I = -40°C to +85°C

E = -40°C to +125°C

Package: OT = Plastic Small Outline Transistor (SOT-23), 5-lead

(MCP6021, E-Temp; MCP6021R, E-Temp)

MS = Plastic MSOP, 8-lead

(MCP6021, E-Temp)

P = Plastic DIP (300 mil Body), 8-lead, 14-lead

SN = Plastic SOIC (150mil Body), 8-lead

SL = Plastic SOIC (150 mil Body), 14-lead

ST = Plastic TSSOP, 8-lead

(MCP6021,I-Temp; MCP6022, I-Temp, E-Temp;

MCP6023, I-Temp, E-Temp;)

ST = Plastic TSSOP, 14-lead

PART NO. X/XX

PackageTemperature

Range

Device

Examples:

a) MCP6021T-E/OT: Tape and Reel,

Extended temperature,

5LD SOT-23.

b) MCP6021-E/P: Extended temperature,

8LD PDIP.

c) MCP6021-E/SN: Extended temperature,

8LD SOIC.

a) MCP6021RT-E/OT:Tape and Reel,

Extended temperature,

5LD SOT-23.

a) MCP6022-I/P: Industrial temperature,

8LD PDIP.

b) MCP6022-E/P: Extended temperature,

8LD PDIP.

c) MCP6022T-E/ST: Tape and Reel,

Extended temperature,

8LD TSSOP.

a) MCP6023-I/P: Industrial temperature,

8LD PDIP.

b) MCP6023-E/P: Extended temperature,

8LD PDIP.

c) MCP6023-E/SN: Extended temperature,

8LD SOIC.

a) MCP6024-I/SL: Industrial temperature,

14LD SOIC.

b) MCP6024-E/SL: Extended temperature,

14LD SOIC.

c) MCP6024T-E/ST: Tape and Reel,

Extended temperature,

14LD TSSOP.

MCP6021/1R/2/3/4

NOTES:

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR WAR-

RANTIES OF ANY KIN D WHETHER EXPRESS OR IMPLIED ,

WRITTEN OR ORAL, STATUTORY OR OTHERWISE,

RELATED TO THE INFORMATION, INCLUDING BUT NOT

LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE,

MERCHANTABILITY OR FITNESS FOR PURPOSE.

Microchip disclaims all liability arising from this information and

its use. U se of Microchip de vices in life support and/or safety

applications is entirely at the buyer’s risk, and the buyer agrees

to de fend, in demnify an d hold har mless Micr ochip fro m any and

all damages, claims, suits, or expenses resulting from such

use. No licenses are conveyed, implicitly or otherwise, under

any Microchip intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,

dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICST ART ,

PRO MATE, PowerSmart, rfPIC, and SmartShunt are

registered trademarks of Microchip Technology Incorporated

in the U.S.A. and other countries.

AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB,

PICMASTER, SEEVAL, SmartSensor and The Embedded

Control Solutions Company are registered trademarks of

Microchip Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, dsPICDEM,

dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR,

FanSense, FlexROM, fuzzyLAB, In-Circuit Serial

Programming, ICSP, ICEPIC, Linear Active Thermistor,

MPASM, MPLIB, MPL I NK, MPSIM, PICk it, PI CDEM,

PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo,

PowerMate, Powe rTool, Real ICE, rfLAB, rfPICDEM, Select

Mode, Smart Serial, SmartTel, Total Endurance, UNI/O,

WiperLock and ZENA are trademarks of Microchip

Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that i t s family of products is one of the most secure families of it s kind on the market today, when used in t he

intended manner and under normal conditions.

• The re are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is c onstantly evolving. We a t Microchip are commit ted to continuously improving the code protect ion f eatures of our

products. Attempts to break Microchip’ s code protection f eature may be a violati on of t he Digit al Millennium Copyright Act. If such act s

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:2002 quality system certification for

its worldwide headquarters, design and wafer fabrication facilities in

Chandler and Tempe, Arizona and Mountain View, California in

October 2003. The Company’s quality system processes and

procedures are for its PICmicro

8-bit MC Us, KEELOQ

code hopping

devices, Serial EEPROMs, micro peripherals, nonvolat ile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

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02/16/06