ispLSI® 1016
In-System Programmable High Density PLD
1
USE ispLSI 1016EA FOR NEW
COMMERCIAL & INDUSTRIAL
DESIGNS
Functional Block Diagram
CLK
A0
A1
A2
A3
A4
A5
A6
A7
B
7
B
6
B
5
B
4
B
3
B
2
B
1
B
0
Output Routing Pool
Output Routing Pool
Global Routing Pool (GRP)
Logic
Array
DQ
DQ
DQ
DQ
GLB
Description
The ispLSI 1016 is a High-Density Programmable Logic
Device containing 96 Registers, 32 Universal I/O pins,
four Dedicated Input pins, three Dedicated Clock Input
pins and a Global Routing Pool (GRP). The GRP pro-
vides complete interconnectivity between all of these
elements. The ispLSI 1016 features 5-Volt in-system
programming and in-system diagnostic capabilities. It is
the first device which offers non-volatile reprogrammability
of the logic, as well as the interconnect to provide truly
reconfigurable systems.
The basic unit of logic on the ispLSI 1016 device is the
Generic Logic Block (GLB). The GLBs are labeled A0, A1
.. B7 (see figure 1). There are a total of 16 GLBs in the
ispLSI 1016 device. Each GLB has 18 inputs, a
programmable AND/OR/XOR array, and four outputs
which can be configured to be either combinatorial or
registered. Inputs to the GLB come from the GRP and
dedicated inputs. All of the GLB outputs are brought back
into the GRP so that they can be connected to the inputs
of any other GLB on the device.
1016_09
Features
• HIGH-DENSITY PROGRAMMABLE LOGIC
— High-Speed Global Interconnect
— 2000 PLD Gates
— 32 I/O Pins, Four Dedicated Inputs
— 96 Registers
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
— Security Cell Prevents Unauthorized Copying
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
— fmax = 110 MHz Maximum Operating Frequency
— fmax = 60 MHz for Industrial and Military/883 Devices
— tpd = 10 ns Propagation Delay
— TTL Compatible Inputs and Outputs
— Electrically Erasable and Reprogrammable
— Non-Volatile E2CMOS Technology
— 100% Tested
• IN-SYSTEM PROGRAMMABLE
— In-System Programmable™ (ISP™) 5-Volt Only
— Increased Manufacturing Yields, Reduced Time-to-
Market, and Improved Product Quality
— Reprogram Soldered Devices for Faster Debugging
• COMBINES EASE OF USE AND THE FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEX-
IBILITY OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue
Logic and Structured Designs
— Three Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
• ispDesignEXPERT™ – LOGIC COMPILER AND COM-
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER™
— PC and UNIX Platforms
Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. August 2000
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
Specifications ispLSI 1016
2
USE ispLSI 1016EA FOR NEW
COMMERCIAL & INDUSTRIAL
DESIGNS
Functional Block Diagram
Figure 1. ispLSI 1016 Functional Block Diagram
I/O 0
I/O 1
I/O 2
I/O 3
IN 3
MODE/IN 2
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 31
I/O 30
I/O 29
I/O 28
I/O 27
I/O 26
I/O 25
I/O 24
I/O 23
I/O 22
I/O 21
I/O 20
I/O 19
I/O 18
I/O 17
I/O 16
SDI/IN 0
SDO/IN 1
I/O 4
I/O 5
SCLK/Y2
ispEN
Global
Routing
Pool
(GRP)
CLK 0
CLK 1
CLK 2
IOCLK 0
IOCLK 1
Clock
Distribution
Network
A0
A1
A2
A3
A4
A5
A6
A7
B7
B6
B5
B4
B3
B2
B1
B 0
Output Routing Pool (ORP)
Generic
Logic Blocks
(GLBs)
Megablock
Output Routing Pool (ORP)
Input Bus
lnput Bus
*Note: Y1 and RESET
are multiplexed
on the same pin
Y0
Y1/RESET*
0139B(1a)-isp.eps
The device also has 32 I/O cells, each of which is directly
connected to an I/O pin. Each I/O cell can be individually
programmed to be a combinatorial input, registered in-
put, latched input, output or bi-directional I/O pin with
3-state control. Additionally, all outputs are polarity
selectable, active high or active low. The signal levels are
TTL compatible voltages and the output drivers can
source 4 mA or sink 8 mA.
Eight GLBs, 16 I/O cells, two dedicated inputs and one
ORP are connected together to make a Megablock (see
figure 1). The outputs of the eight GLBs are connected to
a set of 16 universal I/O cells by the ORP. The ispLSI
1016 device contains two of these Megablocks.
The GRP has as its inputs the outputs from all of the GLBs
and all of the inputs from the bi-directional I/O cells. All of
these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.
Clocks in the ispLSI 1016 device are selected using the
Clock Distribution Network. Three dedicated clock pins
(Y0, Y1 and Y2) are brought into the distribution network,
and five clock outputs (CLK 0, CLK 1, CLK 2, IOCLK 0
and IOCLK 1) are provided to route clocks to the GLBs
and I/O cells. The Clock Distribution Network can also be
driven from a special clock GLB (B0 on the ispLSI 1016
device). The logic of this GLB allows the user to create an
internal clock from a combination of internal signals
within the device.
Specifications ispLSI 1016
3
USE ispLSI 1016EA FOR NEW
COMMERCIAL & INDUSTRIAL
DESIGNS
Absolute Maximum Ratings 1
Supply Voltage Vcc .................................. -0.5 to +7.0V
Input Voltage Applied........................-2.5 to VCC +1.0V
Off-State Output Voltage Applied .....-2.5 to VCC +1.0V
Storage Temperature................................ -65 to 150°C
Case Temp. with Power Applied .............. -55 to 125°C
Max. Junction Temp. (TJ) with Power Applied ... 150°C
1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).
DC Recommended Operating Conditions
V
V
PARAMETERSYMBOL MIN. MAX. UNITS
5.25
5.5
5.5
0.8
Vcc + 1
Supply Voltage
VCC
VIL
VIH
Table 2- 0005Aisp w/mil.eps
4.75
4.5
4.5
0
2.0
Commercial T
A
=
0°C to +70°C
Industrial T
A
= -40°C to +85°C
Military/883 T
C
= -55°C to +125°C
Input Low Voltage
Input High Voltage
V
Capacitance (TA=25oC, f=1.0 MHz)
SYMBOL PARAMETER MAXIMUM1UNITS TEST CONDITIONS
C
1
Commercial/Industrial 8 pf V
CC
=5.0V, V
IN
=2.0V
Military 10 pf V
CC
=5.0V, V
IN
=2.0V
C
2
I/O and Clock Capacitance 10 pf V
CC
=5.0V, V
I/O
, V
Y
=2.0V
1. Guaranteed but not 100% tested. Table 2- 0006
Dedicated Input Capacitance
Data Retention Specifications
Table 2- 0008B
PARAMETER
Data Retention MINIMUM MAXIMUM UNITS
Erase/Reprogram Cycles 20
10000 —
—Years
Cycles
Specifications ispLSI 1016
4
USE ispLSI 1016EA FOR NEW
COMMERCIAL & INDUSTRIAL
DESIGNS
Switching Test Conditions
Input Pulse Levels GND to 3.0V
Input Rise and Fall Time ≤ 3ns 10% to 90%
Input Timing Reference Levels 1.5V
Output Timing Reference Levels 1.5V
Output Load See figure 2
3-state levels are measured 0.5V from steady-state
active level.
Table 2- 0003
Output Load Conditions (see figure 2)
T est Condition R1 R2 CL
A 470Ω390Ω35pF
B Active High 390Ω35pF
Active Low 470Ω390Ω35pF
Active High to Z 390Ω5pF
Cat VOH - 0.5V
Active Low to Z 470Ω390Ω5pF
at VOL + 0.5V
∞
∞
Table 2- 0004A
Figure 2. Test Load
+ 5V
R1
R2CL*
Device
Output Test
Point
*CL includes Test Fixture and Probe Capacitance.
DC Electrical Characteristics
Over Recommended Operating Conditions
0.4
–
-10
10
-150
-150
-200
150
170
VOL
VOH
IIL
IIH
IIL-isp
IIL-PU
IOS
1
I
CC
2,4
I
OL
=8 mA
I
OH
=-4 mA
0V ≤ V
IN
≤ V
IL
(MAX.)
3.5V ≤ V
IN
≤ V
CC
0V ≤ V
IN
≤ V
IL
(MAX.)
0V ≤ V
IN
≤ V
IL
V
CC
= 5V, V
OUT
= 0.5V
V
IL
= 0.5V, V
IH
= 3.0V Commercial
f
TOGGLE
= 1 MH z Industrial/Military
–
–
–
–
–
–
–
100
100
–
2.4
–
–
–
–
–
–
–
CONDITION
PARAMETER
SYMBOL MIN. MAX.
Output Low Voltage
Output High Voltage
Input or I/O Low Leakage Current
Input or I/O High Leakage Current
isp Input Low Leakage Current
I/O Active Pull-Up Current
Output Short Circuit Current
Operating Power Supply Current
UNITSTYP.
3
V
V
µA
µA
µA
µA
mA
mA
mA
1. One output at a time for a maximum duration of one second. V
out
= 0.5V was selected to avoid test problems by tester ground
degradation. Characterized but not 100% tested.
2. Measured using four 16-bit counters.
3. Typical values are at V
CC
= 5V and T
A
= 25oC.
4. Maximum I
CC
varies widely with specific device configuration and operating frequency. Refer to the Power Consumption sec-
tion of this datasheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate maximum
I
CC
.
Table 2-0007A-16 w/mil
Specifications ispLSI 1016
5
USE ispLSI 1016EA FOR NEW
COMMERCIAL & INDUSTRIAL
DESIGNS
External Timing Parameters
Over Recommended Operating Conditions
1. Unless noted otherwise, all parameters use a GRP load of 4 GLBs, 20 PTXOR path, ORP and Y0 clock.
2. Refer to Timing Model in this data sheet for further details.
3. Standard 16-Bit loadable counter using GRP feedback.
4. fmax (Toggle) may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%.
5. Reference Switching Test Conditions Section.
MIN. MAX.
Data Propagation Delay, 4PT bypass, ORP bypass
Data Propagation Delay, Worst Case Path
Clock Frequency with Internal Feedback
3
Clock Frequency with External Feedback
Clock Frequency, Max Toggle
4
GLB Reg. Setup Time before Clock, 4PT bypass
GLB Reg. Clock to Output Delay, ORP bypass
GLB Reg.
Hold Time after Clock, 4 PT bypass
GLB Reg. Setup Time before Clock
GLB Reg. Clock to Output Delay
GLB Reg. Hold Time after Clock
Ext. Reset Pin to Output Delay
Ext. Reset Pulse Duration
Input to Output Enable
Input to Output Disable
Ext. Sync. Clock Pulse Duration, High
Ext. Sync. Clock Pulse Duration, Low
I/O Reg. Setup Time before Ext. Sync. Clock (Y1, Y2)
I/O Reg. Hold Time after Ext. Sync. Clock (Y1, Y2)
ns
ns
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
pd1
t
pd2
f
max (Int.)
f
max (Ext.)
f
max (Tog.)
t
su1
t
co1
t
h1
t
su2
t
co2
t
h2
t
r1
t
rw1
t
en
t
dis
t
wh
t
wl
t
su5
t
h5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
A
A
A
–
–
–
A
–
–
–
–
A
–
B
C
–
–
–
–
DESCRIPTION
1
PARAMETER #
2
UNITS
TEST
5
COND.
1
tsu2 + tco1
( )
MIN. MAX.
–
–
111
70.1
125
4.5
–
0
7.5
–
0
–
10
–
–
4
4
2
5.5
10
14.5
–
–
–
–
7
–
–
8.5
–
14
–
15
15
–
–
–
–
-110 -90
–
–
90.9
58.8
125
6
–
0
9
–
0
–
10
–
–
4
4
2
6.5
12
17
–
–
–
–
8
–
–
10
–
15
–
15
15
–
–
–
–
Table 2-0030-16/110,90C
Specifications ispLSI 1016
6
USE ispLSI 1016EA FOR NEW
COMMERCIAL & INDUSTRIAL
DESIGNS
MIN. MAX.
Data Propagation Delay, 4PT bypass, ORP bypass
Data Propagation Delay, Worst Case Path
Clock Frequency with Internal Feedback
3
Clock Frequency with External Feedback
Clock Frequency, Max Toggle
4
GLB Reg. Setup Time before Clock, 4PT bypass
GLB Reg. Clock to Output Delay, ORP bypass
GLB Reg.
Hold Time after Clock, 4 PT bypass
GLB Reg. Setup Time before Clock
GLB Reg. Clock to Output Delay
GLB Reg. Hold Time after Clock
Ext. Reset Pin to Output Delay
Ext. Reset Pulse Duration
Input to Output Enable
Input to Output Disable
Ext. Sync. Clock Pulse Duration, High
Ext. Sync. Clock Pulse Duration, Low
I/O Reg. Setup Time before Ext. Sync. Clock (Y1, Y2)
I/O Reg. Hold Time after Ext. Sync. Clock (Y1, Y2)
ns
ns
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
pd1
t
pd2
f
max (Int.)
f
max (Ext.)
f
max (Tog.)
t
su1
t
co1
t
h1
t
su2
t
co2
t
h2
t
r1
t
rw1
t
en
t
dis
t
wh
t
wl
t
su5
t
h5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
A
A
A
–
–
–
A
–
–
–
–
A
–
B
C
–
–
–
–
DESCRIPTION
1
PARAMETER #
2
UNITS
TEST
5
COND.
1
tsu2 + tco1
( )
MIN. MAX.
–
–
80
50
100
7
–
0
10
–
0
–
10
–
–
5
5
2
6.5
15
20
–
–
–
–
10
–
–
12
–
17
–
18
18
–
–
–
–
–
–
60
38
83
9
–
0
13
–
0
–
13
–
–
6
6
2.5
8.5
20
25
–
–
–
–
13
–
–
16
–
22.5
–
24
24
–
–
–
–
-80 -60
Table 2-0030-16/80,60C
1. Unless noted otherwise, all parameters use a GRP load of 4 GLBs, 20 PTXOR path, ORP and Y0 clock.
2. Refer to Timing Model in this data sheet for further details.
3. Standard 16-Bit loadable counter using GRP feedback.
4. fmax (Toggle) may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%.
5. Reference Switching Test Conditions Section.
External Timing Parameters
Over Recommended Operating Conditions
Specifications ispLSI 1016
7
USE ispLSI 1016EA FOR NEW
COMMERCIAL & INDUSTRIAL
DESIGNS
Internal Timing Parameters1
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MIN. MAX.
DESCRIPTIONPARAMETER UNITS
-90
Inputs
tiobp
tiolat
tiosu
tioh
tioco
tior
tdin
GRP
tgrp1
tgrp4
tgrp8
tgrp12
tgrp16
GLB
t4ptbp
t1ptxor
t20ptxor
txoradj
tgbp
tgsu
tgh
tgco
tgr
tptre
tptoe
tptck
ORP
torp
torpbp
#2
20
21
22
23
24
25
26
27
28
29
30
31
33
34
35
36
37
38
39
40
41
42
43
44
45
46
I/O Register Bypass
I/O Latch Delay
I/O Register Setup Time before Clock
I/O Register Hold Time after Clock
I/O Register Clock to Out Delay
I/O Register Reset to Out Delay
Dedicated Input Delay
GRP Delay, 1 GLB Load
GRP Delay, 4 GLB Loads
GRP Delay, 8 GLB Loads
GRP Delay, 12 GLB Loads
GRP Delay, 16 GLB Loads
4 Product Term Bypass Path Delay
1 Product Term/XOR Path Delay
20 Product Term/XOR Path Delay
XOR Adjacent Path Delay3
GLB Register Bypass Delay
GLB Register Setup Time before Clock
GLB Register Hold Time after Clock
GLB Register Clock to Output Delay
GLB Register Reset to Output Delay
GLB Product Term Reset to Register Delay
GLB Product Term Output Enable to I/O Cell Delay
GLB Product Term Clock Delay
ORP Delay
ORP Bypass Delay
0.8
1.7
–
–
1.7
2.1
1.7
0.6
0.8
1.5
2.1
2.8
5.3
6.1
6.6
8.2
0.5
–
–
1.6
2.1
8.2
9.0
6.2
2.0
0.4
MIN. MAX.
-110
–
–
4.1
1.8
–
–
–
–
–
–
–
–
–
–
–
–
–
0.3
2.9
–
–
–
–
2.8
–
–
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR Adjacent path can only be used by Hard Macros.
–
–
4.5
2.0
–
–
–
–
–
–
–
–
–
–
–
–
–
1.0
3.5
–
–
–
–
3.5
–
–
1.0
2.0
–
–
2.0
2.5
2.0
0.7
1.0
1.8
2.6
3.4
6.5
7.0
8.0
9.5
0.5
–
–
1.5
2.5
10.0
9.0
7.5
2.5
0.5
Specifications ispLSI 1016
8
USE ispLSI 1016EA FOR NEW
COMMERCIAL & INDUSTRIAL
DESIGNS
Internal Timing Parameters1
ns
ns
ns
ns
ns
ns
ns
ns
ns
Outputs
tob
toen
todis
Clocks
tgy0
tgy1/2
tgcp
tioy1/2
tiocp
Global Reset
tgr
47
48
49
50
51
52
53
54
55
Output Buffer Delay
I/O Cell OE to Output Enabled
I/O Cell OE to Output Disabled
Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)
Clock Delay, Y1 or Y2 to Global GLB Clock Line
Clock Delay, Clock GLB to Global GLB Clock Line
Clock Delay, Y1 or Y2 to I/O Cell Global Clock Line
Clock Delay, Clock GLB to I/O Cell Global Clock Line
Global Reset to GLB and I/O Registers
MIN. MAX.
DESCRIPTIONPARAMETER UNITS
-90
#
2
–
–
–
2.9
2.1
0.8
2.1
0.8
–
MIN. MAX.
-110
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
2.1
3.3
3.3
2.9
3.8
4.2
3.8
4.2
7.9
–
–
–
3.5
2.5
1.0
2.5
1.0
–
2.5
4.0
4.0
3.5
4.5
5.0
4.5
5.0
7.5
Specifications ispLSI 1016
9
USE ispLSI 1016EA FOR NEW
COMMERCIAL & INDUSTRIAL
DESIGNS
Internal Timing Parameters1
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
–
–
7.3
1.3
–
–
–
–
–
–
–
–
–
–
–
–
–
1.3
6.0
–
–
–
–
4.6
–
–
2.7
4.0
–
–
4.0
3.3
5.3
2.0
2.7
4.0
5.0
6.0
8.6
9.3
10.6
12.7
1.3
–
–
2.7
3.3
13.3
12.0
9.9
3.3
0.7
MIN. MAX.
DESCRIPTIONPARAMETER UNITS
-60
Inputs
t
iobp
tiolat
tiosu
tioh
tioco
tior
tdin
GRP
tgrp1
tgrp4
tgrp8
tgrp12
tgrp16
GLB
t4ptbp
t1ptxor
t20ptxor
txoradj
tgbp
tgsu
tgh
tgco
tgr
tptre
tptoe
tptck
ORP
torp
torpbp
#
2
20
21
22
23
24
25
26
27
28
29
30
31
33
34
35
36
37
38
39
40
41
42
43
44
45
46
I/O Register Bypass
I/O Latch Delay
I/O Register Setup Time before Clock
I/O Register Hold Time after Clock
I/O Register Clock to Out Delay
I/O Register Reset to Out Delay
Dedicated Input Delay
GRP Delay, 1 GLB Load
GRP Delay, 4 GLB Loads
GRP Delay, 8 GLB Loads
GRP Delay, 12 GLB Loads
GRP Delay, 16 GLB Loads
4 Product Term Bypass Path Delay
1 Product Term/XOR Path Delay
20 Product Term/XOR Path Delay
XOR Adjacent Path Delay
3
GLB Register Bypass Delay
GLB Register Setup Time before Clock
GLB Register Hold Time after Clock
GLB Register Clock to Output Delay
GLB Register Reset to Output Delay
GLB Product Term Reset to Register Delay
GLB Product Term Output Enable to I/O Cell Delay
GLB Product Term Clock Delay
ORP Delay
ORP Bypass Delay
2.0
3.0
–
–
3.0
2.5
4.0
1.5
2.0
3.0
3.8
4.5
6.5
7.0
8.0
9.5
1.0
–
–
2.0
2.5
10.0
9.0
7.5
2.5
0.5
MIN. MAX.
-80
–
–
5.5
1.0
–
–
–
–
–
–
–
–
–
–
–
–
–
1.0
4.5
–
–
–
–
3.5
–
–
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR Adjacent path can only be used by Hard Macros.
Specifications ispLSI 1016
10
USE ispLSI 1016EA FOR NEW
COMMERCIAL & INDUSTRIAL
DESIGNS
Internal Timing Parameters1
ns
ns
ns
ns
ns
ns
ns
ns
ns
–
–
–
6.0
4.6
1.3
4.6
1.3
–
4.0
6.7
6.7
6.0
7.3
6.6
7.3
6.6
12.0
Outputs
tob
toen
todis
Clocks
tgy0
tgy1/2
tgcp
tioy1/2
tiocp
Global Reset
tgr
47
48
49
50
51
52
53
54
55
Output Buffer Delay
I/O Cell OE to Output Enabled
I/O Cell OE to Output Disabled
Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)
Clock Delay, Y1 or Y2 to Global GLB Clock Line
Clock Delay, Clock GLB to Global GLB Clock Line
Clock Delay, Y1 or Y2 to I/O Cell Global Clock Line
Clock Delay, Clock GLB to I/O Cell Global Clock Line
Global Reset to GLB and I/O Registers
MIN. MAX.
DESCRIPTIONPARAMETER UNITS
-60
#2
–
–
–
4.5
3.5
1.0
3.5
1.0
–
3.0
5.0
5.0
4.5
5.5
5.0
5.5
5.0
9.0
MIN. MAX.
-80
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
Specifications ispLSI 1016
11
USE ispLSI 1016EA FOR NEW
COMMERCIAL & INDUSTRIAL
DESIGNS
ispLSI 1016 Timing Model
GLB Reg
Delay
I/O Pin
(Output)
ORP
Delay
Feedback
4 PT Bypass
20 PT
XOR Delays
Control
PTs
GRP
Loading
Delay
Input
Register
Clock
Distribution
I/O Pin
(Input)
Y0
Y1,2
DQ
GRP 4 GLB Reg Bypass ORP Bypass
DQ
RST
RE
OE
CK
I/O Reg Bypass
I/O CellORPGLBGRPI/O Cell
#21 - 25 #27, 29,
30, 31, 32
#28 #33
#34, 35, 36
#51, 52,
53, 54 #42, 43,
44
#50
#45
#46
Reset
Ded. In #26
#20
RST
#55
#55
#37
#38, 39,
40, 41
#48, 49
#47
Derivations of tsu, th and tco from the Product Term Clock
1
t
su = Logic + Reg su - Clock (min)
= (tiobp + tgrp4 + t20ptxor) + (tgsu) - ( tiobp + tgrp4 + tptck(min))
= (#20 + #28 + #35) + (#38) - (#20 + #28 + #44)
5.5 ns = (1.0 + 1.0 + 8.0) + (1.0) - (1.0 + 1.0 + 3.5)
th = Clock (max) + Reg h - Logic
= (tiobp + tgrp4 + tptck(max)) + (tgh) - (tiobp + tgrp4 + t20ptxor)
= (#20 + #28 + #44) + (#39) - (#20 + #28 + #35)
3.0 ns = (1.0 + 1.0 + 7.5) + (3.5) - (1.0 + 1.0 + 8.0)
tco = Clock (max) + Reg co + Output
= (tiobp + tgrp4 + tptck(max)) + (tgco) + (torp + tob)
= (#20 + #28 + #44 ) + (#40) + (#45 + #47)
16.0 ns = (1.0+ 1.0 +7.5) + (1.5) + (2.5 + 2.5)
Derivations of tsu, th and tco from the Clock GLB
1
t
su = Logic + Reg su - Clock (min)
= (tiobp + tgrp4 + t20ptxor) + (tgsu) - ( tgy0(min) + tgco + tgcp(min))
= (#20 + #28 + #35) + (#38) - (#50 + #40 + #52)
5.0 ns = (1.0 + 1.0 + 8.0) + (1.0) - (3.5 + 1.5 + 1.0)
th = Clock (max) + Reg h - Logic
= (tgy0(max) + tgco + tgcp(max)) + (tgh) - (tiobp + tgrp4 + t20ptxor)
= (#50 + #40 + #52) + (#39) - (#20 + #28 + #35)
3.5 ns = (3.5 + 1.5 + 5.0) + (3.5) - (1.0 + 1.0 + 8.0)
tco = Clock (max) + Reg co + Output
= (tgy0(max) + tgco + tgcp(max)) + (tgco) + (torp + tob)
= (#50 + #40 + #52 ) + (#40) + (#45 + #47)
16.5 ns = (3.5 + 1.5 + 5.0) + (1.5) + (2.5 + 2.5)
1. Calculations are based upon timing specifications for the ispLSI 1016-90.
Specifications ispLSI 1016
12
USE ispLSI 1016EA FOR NEW
COMMERCIAL & INDUSTRIAL
DESIGNS
Maximum GRP Delay vs GLB Loads
ispLSI 1016-60
ispLSI 1016-80
ispLSI 1016-90/-110
0126A-80-16-isp.eps
1
2
3
4 8 12 16
GLB Loads
GRP Delay (ns)
4
5
6
0
Power Consumption
Power consumption in the ispLSI 1016 device depends
on two primary factors: the speed at which the device is
operating, and the number of Product Terms used. Fig-
ure 3 shows the relationship between power and operat-
ing speed.
Figure 3. Typical Device Power Consumption vs fmax
50
100
150
0 10203040506070
fmax (MHz)
ICC (mA)
80
Notes: Configuration of Four 16-bit Counters
Typical Current at 5V, 25ßC
ispLSI 1016
90 100 110
ICC can be estimated for the ispLSI 1016 using the following equation:
ICC = 31 + (# of PTs * 0.45) + (# of nets * Max. freq * 0.009) where:
# of PTs = Number of Product Terms used in design
# of nets = Number of Signals used in device
Max. freq = Highest Clock Frequency to the device
The ICC estimate is based on typical conditions (VCC = 5.0V, room temperature) and an assumption of 2 GLB loads on
average exists. These values are for estimates only. Since the value of ICC is sensitive to operating conditions and the
program in the device, the actual ICC should be verified.
Specifications ispLSI 1016
13
USE ispLSI 1016EA FOR NEW
COMMERCIAL & INDUSTRIAL
DESIGNS
Input – Dedicated in-system programming enable
input pin. This pin is brought low to enable the
programming mode. The MODE, SDI, SDO and
SCLK options become active.
Input – This pin performs two functions. It is a
dedicated input pin when ispEN is logic high. When
ispEN is logic low, it functions as an input pin to load
programming data into the device. SDI/IN 0 also is
used as one of the two control pins for the isp state
machine.
Input – This pin performs two functions. It is a
dedicated input pin when ispEN is logic high. When
ispEN is logic low, it functions as a pin to control the
operation of the isp state machine.
Input/Output – This pin performs two functions. It is a
dedicated input pin when ispEN is logic high. When
ispEN is logic low, it functions as an output pin to read
serial shift register data.
Input – This pin performs two functions. It is a
dedicated clock input when ispEN is logic high. This
clock input is brought into the Clock Distribution
Network, and can optionally be routed to any GLB
and/or I/O cell on the device. When ispEN is logic low,
it functions as a clock pin for the Serial Shift Register.
Dedicated Clock input. This clock input is connected
to one of the clock inputs of all of the GLBs on the
device.
This pin performs two functions:
–Dedicated clock input. This clock input is brought
into the Clock Distribution Network, and can
optionally be routed to any GLB and/or I/O
cell on the device.
–Active Low (0) Reset pin which resets all of the
GLB and I/O registers in the device.
1. Pins have dual function capability.
GND 1, 23 17, 39 1, 23
V
CC 12, 34 6, 28 12, 34
Input/Output Pins - These are the general purpose I/O
pins used by the logic array.
Dedicated input pins to the device.
IN 3 2 40 2
I/O 0 - I/O 3 15, 16, 17, 18, 9, 10, 11, 12, 15, 16, 17, 18,
I/O 4 - I/O 7 19, 20, 21, 22, 13, 14, 15, 16, 19, 20, 21, 22,
I/O 8 - I/O 11 25, 26, 27, 28, 19, 20, 21, 22, 25, 26, 27, 28,
I/O 12 - I/O 15 29, 30, 31, 32, 23, 24, 25, 26, 29, 30, 31, 32,
I/O 16 - I/O 19 37, 38, 39, 40, 31, 32, 33, 34, 37, 38, 39, 40,
I/O 20 - I/O 23 41, 42, 43, 44, 35, 36, 37, 38, 41, 42, 43, 44,
I/O 24 - I/O 27 3, 4, 5, 6, 41, 42, 43, 44, 3, 4, 5, 6,
I/O 28 - I/O 31 7, 8, 9, 10 1, 2, 3, 4 7, 8, 9, 10
Table 2 - 0002C-16-isp
Ground (GND)
V
CC
ispEN 13 7 13
SDI/IN 0
1
14 8 14
MODE/IN 2
1
36 30 36
SDO/IN 1
1
24 18 24
SCLK/Y2
1
33 27 33
Y0 11 5 11
Y1/RESET 35 29 35
PLCC
PIN NUMBERS TQFP
PIN NUMBERS JLCC
PIN NUMBERS DESCRIPTIONNAME
Pin Description
Specifications ispLSI 1016
14
USE ispLSI 1016EA FOR NEW
COMMERCIAL & INDUSTRIAL
DESIGNS
Pin Configuration
ispLSI 1016 44-Pin PLCC Pinout Diagram
ispLSI 1016 44-Pin TQFP Pinout Diagram
I/O 18
I/O 17
I/O 16
IN 2/MODE1
Y1/RESET
VCC
Y2/SCLK1
I/O 15
I/O 14
I/O 13
I/O 12
I/O 28
I/O 29
I/O 30
I/O 31
Y0
VCC
ispEN
1SDI/IN 0
I/O 0
I/O 1
I/O 2
I/O 27
I/O 26
I/O 25
I/O 24
IN 3
GND
I/O 23
I/O 22
I/O 21
I/O 20
I/O 19
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
GND
1 SDO/IN 1
I/O 8
I/O 9
I/O 10
I/O 11
ispLSI 1016
Top View
7
8
9
10
12
11
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
6
18
5
19
4
20
3
21
2
22
1
23
44
24
43
25
42
26
41
27
40
28
0123A-isp1016
1. Pins have dual function capability.
I/O 18
I/O 17
I/O 16
IN2/MODE1
Y1/RESET
VCC
Y2/SCLK1
I/O 15
I/O 14
I/O 13
I/O 12
I/O 28
I/O 29
I/O 30
I/O 31
Y0
VCC
ispEN
1 SDI/IN 0
I/O 0
I/O 1
I/O 2
I/O 27
I/O 26
I/O 25
I/O 24
IN 3
GND
I/O 23
I/O 22
I/O 21
I/O 20
I/O 19
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
GND
1 SDO/IN 1
I/O 8
I/O 9
I/O 10
I/O 11
ispLSI 1016
Top View
1
2
3
4
6
5
7
8
9
10
11
33
32
31
30
29
28
27
26
25
24
23
44
12
43
13
42
14
41
15
40
16
39
17
38
18
37
19
36
20
35
21
34
22
0851-16/TQFP
1. Pins have dual function capability.
Specifications ispLSI 1016
15
USE ispLSI 1016EA FOR NEW
COMMERCIAL & INDUSTRIAL
DESIGNS
Pin Configuration
ispLSI 1016 44-Pin JLCC Pinout Diagram
I/O 27
I/O 26
I/O 25
I/O 24
IN 3
GND
I/O 23
I/O 22
I/O 21
I/O 20
I/O 19
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
GND
1 SDO/IN 1
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
Y2/SCLK1
VCC
Y1/RESET
IN 2/MODE1
I/O 16
I/O 17
I/O 18
18 19 20 21 2322 24 25 26 27 28
654321
44 43 42 41 40
17 29
16 30
15 31
14 32
13 33
12 34
11 35
10 36
937
838
739
I/O 2
I/O 1
I/O 0
1 SDI/IN 0
ispEN
VCC
Y0
I/O 31
I/O 30
I/O 29
I/O 28
ispLSI 1016/883
Top View
1. Pins have dual function capability.
0123-16-isp/JLCC
Specifications ispLSI 1016
16
USE ispLSI 1016EA FOR NEW
COMMERCIAL & INDUSTRIAL
DESIGNS
Part Number Description
Device Number
Grade
Blank = Commercial
I = Industrial
/883 = 883 Military Process
ispLSI
1016 XXX X XXX X
Speed
110 = 110 MHz fmax
90 = 90 MHz fmax
80 = 80 MHz fmax
60 = 60 MHz fmax Power
L = Low
Package
J = PLCC
T44 = TQFP
H = JLCC
—
Device Family
0212-80B-isp1016
ispLSI
Ordering Information
t
pd (ns)
f
max (MHz)
Ordering Number Package
90 12
90 12
ispLSI 1016-90LJ
ispLSI 1016-90LT44
44-Pin PLCC
44-Pin TQFP
COMMERCIAL
110 10 ispLSI 1016-110LJ 44-Pin PLCC
t
pd (ns)
f
max (MHz)
Ordering Number Package
60 20 ispLSI 1016-60LJI 44-Pin PLCC
INDUSTRIAL
Family
ispLSI
ispLSI
Family
Note: Lattice Semiconductor recognizes the trend in military device procurement towards
using SMD compliant devices, as such, ordering by this number is recommended.
80 15 ispLSI 1016-80LT44 44-Pin TQFP
60 20
60 20
ispLSI 1016-60LJ
ispLSI 1016-60LT44
44-Pin PLCC
44-Pin TQFP
80 15 ispLSI 1016-80LJ 44-Pin PLCC
MILITARY/883
Table 2-0041-16-isp1016
t
pd (ns)
f
max (MHz)
Ordering Number Package
60 20 ispLSI 1016-60LH/883 44-Pin JLCC
ispLSI
Family SMD #
5962-9476201MXC
60 20 ispLSI 1016-60LT44I 44-Pin TQFP
