PIC18F1220/1320 Data Sheet 18/20/28-Pin High Performance, Enhanced FLASH Microcontrollers with 10-bit A/D and nanoWatt Technology 2002 Microchip Technology Inc. Preliminary DS39605B Note the following details of the code protection feature on PICmicro(R) MCUs. * * * * * * The PICmicro family meets the specifications contained in the Microchip Data Sheet. Microchip believes that its family of PICmicro microcontrollers is one of the most secure products of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the PICmicro microcontroller in a manner outside the operating specifications contained in the data sheet. The person doing so may be engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable". Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our product. If you have any further questions about this matter, please contact the local sales office nearest to you. Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, KEELOQ, MPLAB, PIC, PICmicro, PICSTART and PRO MATE are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, microID, MXDEV, MXLAB, PICMASTER, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. dsPIC, dsPICDEM.net, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, microPort, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2002, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999 and Mountain View, California in March 2002. The Company's quality system processes and procedures are QS-9000 compliant for its PICmicro(R) 8-bit MCUs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, non-volatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001 certified. DS39605B - page ii Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 18/20/28-Pin High Performance, Enhanced FLASH MCUs with 10-bit A/D and nanoWatt Technology Low Power Features: Peripheral Highlights: * Power Managed modes: - RUN CPU on, peripherals on - IDLE CPU off, peripherals on - SLEEP CPU off, peripherals off * Power Consumption modes: - PRI_RUN 150 A, 1 MHz, 2V - PRI_IDLE 37 A, 1 MHz, 2V - SEC_RUN 14 A, 32 kHz, 2V - SEC_IDLE 5.8 A, 32 kHz, 2V - RC_RUN 110 A, 1 MHz, 2V - RC_IDLE 52 A, 1 MHz, 2V - SLEEP 0.1 A, 1 MHz, 2V * Timer1 oscillator 1.1 A, 32 kHz, 2V * Watchdog Timer 2.1 A * Two-speed Oscillator Start-up * High current sink/source 25 mA/25 mA * Three external interrupts * Enhanced Capture/Compare/PWM (ECCP) module: - One, two, or four PWM outputs - Selectable polarity - Programmable dead-time - Auto shutdown and auto restart - Capture is 16-bit, max resolution 6.25 ns (TCY/16) - Compare is 16-bit, max resolution 100 ns (TCY) * Compatible 10-bit, up to 13-channel Analog-toDigital Converter module (A/D) with programmable acquisition time * Dual analog comparators * Enhanced USART module: - Supports RS-485, RS-232, and LIN 1.2 - Auto wake-up on START bit - Auto baud detect Oscillators: * Four Crystal modes: - LP, XT, HS up to 25 MHz - HSPLL 4 - 10 MHz (16 - 40 MHz internal) * Two External RC modes, up to 4 MHz * Two External Clock modes, up to 40 MHz * Internal oscillator block: - 8 user selectable frequencies: 31 kHz, 125 kHz, 250 kHz, 500 kHz, 1 MHz, 2 MHz, 4 MHz, 8 MHz - 125 kHz - 8 MHz calibrated to 1% - Two modes select one or two I/O pins - OSCTUNE - Allows user to shift frequency * Secondary oscillator using Timer1 @ 32 kHz * Fail-Safe Clock Monitor - Allows for safe shutdown if peripheral clock stops Program Memory Device Special Microcontroller Features: * 100,000 erase/write cycle Enhanced FLASH program memory typical * 1,000,000 erase/write cycle Data EEPROM memory typical * FLASH/Data EEPROM Retention: > 40 years * Self-programmable under software control * Priority levels for interrupts * 8 X 8 Single Cycle Hardware Multiplier * Extended Watchdog Timer (WDT): - Programmable period from 41 ms to 131s - 2% stability over VDD and Temperature * Single supply 5V In-Circuit Serial ProgrammingTM (ICSPTM) via two pins * In-Circuit Debug (ICD) via two pins * Wide operating voltage range: 2.0V to 5.5V Data Memory FLASH # Single Word SRAM EEPROM (bytes) Instructions (bytes) (bytes) I/O 10-bit A/D (ch) ECCP (PWM) EUSART Comparators Timers 8/16-bit PIC18F1220 4K 2048 256 256 16 7 1 Y 2 1/3 PIC18F1320 8K 4096 256 256 16 7 1 Y 2 1/3 2002 Microchip Technology Inc. Preliminary DS39605B-page 1 PIC18F1220/1320 Pin Diagrams 20-Pin SSOP 18-Pin PDIP, SOIC 18 RB3/CCP1/P1A RA1/AN1/LVDIN 2 17 RB2/P1B/INT2 15 OSC2/CLKO/RA6 14 VDD/AVDD RB7/PGD/T1OSI/ P1D/KBI3 RB6/PGC/T1OSO/ T1CKI/P1C/KBI2 RA2/AN2/VREF- 6 RA3/AN3/VREF+ 7 12 RB0/AN4/INT0 8 11 RB5/PGM/KBI1 RB1/AN5/TX/ CK/INT1 9 10 RB4/AN6/RX/ DT/KBI0 DS39605B-page 2 19 RB2/P1B/INT2 3 18 OSC1/CLKI/RA7 MCLR/VPP/RA5 4 17 OSC2/CLKO/RA6 16 VDD 15 AVDD VSS 5 AVSS 6 RA2/AN2/VREF- 7 RA3/AN3/VREF+ 8 13 RB0/AN4/INT0 9 12 RB5/PGM/KBI1 10 11 RB4/AN6/RX/ DT/KBI0 RA0/AN0 NC 26 25 NC RA4/T0CKI RA1/AN1/LVDIN 27 RB1/AN5/TX/ CK/INT1 28 28-Pin QFN 2 RA4/T0CKI 22 13 RA1/AN1/LVDIN RB3/CCP1/P1A 5 OSC1/CLKI/RA7 RB3/CCP1/P1A RB2/P1B/INT2 VSS/AVSS 4 16 20 23 MCLR/VPP/RA5 3 1 24 RA4/T0CKI RA0/AN0 PIC18F1X20 1 PIC18F1X20 RA0/AN0 14 RB7/PGD/T1OSI/ P1D/KBI3 RB6/PGC/T1OSO/ T1CKI/P1C/KBI2 MCLR/VPP/RA5 1 21 OSC1/CLKI/RA7 NC VSS 2 20 OSC2/CLKO/RA6 3 19 VDD NC 4 18 NC AVSS 5 17 AVDD NC 6 16 RB7/PGD/T1OSI/P1D/KBI3 RA2/AN2/VREF- 7 15 RB6/PGC/T1OSO/T1CKI/P1C/KBI2 10 11 12 13 14 NC RB4/AN6/RX/DT/KBI0 RB5/PGM/KBI1 NC 9 RB0/AN4/INT0 RB1/AN5/TX/CK/INT1 8 RA3/AN3/VREF+ PIC18F1X20 Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 5 2.0 Oscillator Configurations ............................................................................................................................................................ 11 3.0 Power Managed Modes ............................................................................................................................................................. 19 4.0 Reset .......................................................................................................................................................................................... 33 5.0 Memory Organization ................................................................................................................................................................. 43 6.0 FLASH Program Memory ........................................................................................................................................................... 59 7.0 Data EEPROM Memory ............................................................................................................................................................. 69 8.0 8 X 8 Hardware Multiplier ........................................................................................................................................................... 73 9.0 Interrupts .................................................................................................................................................................................... 75 10.0 I/O Ports ..................................................................................................................................................................................... 89 11.0 Timer0 Module ......................................................................................................................................................................... 101 12.0 Timer1 Module ......................................................................................................................................................................... 105 13.0 Timer2 Module ......................................................................................................................................................................... 111 14.0 Timer3 Module ......................................................................................................................................................................... 113 15.0 Enhanced Capture/Compare/PWM (ECCP) Module................................................................................................................ 117 16.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (USART) ................................................................. 133 17.0 10-bit Analog-to-Digital Converter (A/D) Module...................................................................................................................... 155 18.0 Low Voltage Detect .................................................................................................................................................................. 165 19.0 Special Features of the CPU.................................................................................................................................................... 171 20.0 Instruction Set Summary .......................................................................................................................................................... 189 21.0 Development Support............................................................................................................................................................... 231 22.0 Electrical Characteristics .......................................................................................................................................................... 237 23.0 Preliminary DC and AC Characteristics Graphs and Tables.................................................................................................... 263 24.0 Packaging Information.............................................................................................................................................................. 267 Appendix A: Revision History............................................................................................................................................................. 273 Appendix B: Device Differences ........................................................................................................................................................ 273 Appendix C: Conversion Considerations ........................................................................................................................................... 274 Appendix D: Migration from Baseline to Enhanced Devices.............................................................................................................. 274 Appendix E: Migration from Mid-range to Enhanced Devices ........................................................................................................... 275 Appendix F: Migration from High-end to Enhanced Devices ............................................................................................................. 275 Index .................................................................................................................................................................................................. 277 On-Line Support................................................................................................................................................................................. 285 Systems Information and Upgrade Hot Line ...................................................................................................................................... 285 Reader Response .............................................................................................................................................................................. 286 PIC18F1220/1320 Product Identification System .............................................................................................................................. 287 2002 Microchip Technology Inc. Preliminary DS39605B-page 3 PIC18F1220/1320 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@mail.microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: * Microchip's Worldwide Web site; http://www.microchip.com * Your local Microchip sales office (see last page) * The Microchip Corporate Literature Center; U.S. FAX: (480) 792-7277 When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com/cn to receive the most current information on all of our products. DS39605B-page 4 Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 1.0 DEVICE OVERVIEW This document contains device specific information for the following devices: * PIC18F1220 * PIC18F1320 This family offers the advantages of all PIC18 microcontrollers - namely, high computational performance at an economical price - with the addition of high endurance Enhanced FLASH program memory. On top of these features, the PIC18F1220/1320 family introduces design enhancements that make these microcontrollers a logical choice for many high performance, power sensitive applications. 1.1 1.1.1 New Core Features NANOWATT TECHNOLOGY All of the devices in the PIC18F1220/1320 family incorporate a range of features that can significantly reduce power consumption during operation. Key items include: * Alternate RUN Modes: By clocking the controller from the Timer1 source or the Internal Oscillator block, power consumption during code execution can be reduced by as much as 90%. * Multiple IDLE Modes: The controller can also run with its CPU core disabled, but the peripherals still active. In these states, power consumption can be reduced even further, to as little as 4% of normal operation requirements. * On-the-fly Mode Switching: The Power Managed modes are invoked by user code during operation, allowing the user to incorporate power saving ideas into their application's software design. * Lower Consumption in Key Modules: The power requirements for both Timer1 and the Watchdog Timer have been reduced by up to 80%, with typical values of 1.1 and 2.1 A, respectively. 1.1.2 MULTIPLE OSCILLATOR OPTIONS AND FEATURES All of the devices in the PIC18F1220/1320 family offer nine different oscillator options, allowing the users a wide range of choices in developing application hardware. These include: * Four Crystal modes, using crystals or ceramic resonators. * Two External Clock modes, offering the option of using two pins (oscillator input and a divide-by-4 clock output), or one pin (oscillator input, with the second pin re-assigned as general I/O). * Two external RC Oscillator modes, with the same pin options as the External Clock modes. * An internal oscillator block which provides an 8 MHz clock (2% accuracy) and an INTRC source (approximately 31 kHz, stable over temperature and VDD), as well as a range of 6 user selectable clock frequencies (from 125 kHz to 4 MHz) for a total of 8 clock frequencies. 2002 Microchip Technology Inc. Besides its availability as a clock source, the internal oscillator block provides a stable reference source that gives the family additional features for robust operation: * Fail-Safe Clock Monitor: This option constantly monitors the main clock source against a reference signal provided by the internal oscillator. If a clock failure occurs, the controller is switched to the internal oscillator block, allowing for continued low speed operation, or a safe application shutdown. * Two-Speed Start-up: This option allows the internal oscillator to serve as the clock source from Power-on Reset, or wake-up from SLEEP mode, until the primary clock source is available. This allows for code execution during what would otherwise be the clock start-up interval, and can even allow an application to perform routine background activities and return to SLEEP without returning to full power operation. 1.2 Other Special Features * Memory Endurance: The Enhanced FLASH cells for both program memory and data EEPROM are rated to last for many thousands of erase/write cycles - up to 100,000 for program memory and 1,000,000 for EEPROM. Data retention without refresh is conservatively estimated to be greater than 40 years. * Self-programmability: These devices can write to their own program memory spaces under internal software control. By using a bootloader routine located in the protected Boot Block at the top of program memory, it becomes possible to create an application that can update itself in the field. * Enhanced CCP module: In PWM mode, this module provides 1, 2 or 4 modulated outputs for controlling half-bridge and full-bridge drivers. Other features include Auto Shutdown, for disabling PWM outputs on interrupt or other select conditions, and Auto Restart, to re-activate outputs once the condition has cleared. * Enhanced USART: This serial communication module features automatic wake-up on START bit and automatic baud rate detection, and supports RS-232, RS-485, and LIN 1.2 protocols, making it ideally suited for use in Local Interconnect Network (LIN) bus applications. * 10-bit A/D Converter: This module incorporates Programmable Acquisition Time, allowing for a channel to be selected and a conversion to be initiated without waiting for a sampling period and thus, reduce code overhead. * Extended Watchdog Timer (WDT): This enhanced version incorporates a 16-bit prescaler, allowing a time-out range from 4 ms to over 2 minutes, that is stable across operating voltage and temperature. Preliminary DS39605B-page 5 PIC18F1220/1320 1.3 Details on Individual Family Members Devices in the PIC18F1220/1320 family are available in 18-pin, 20-pin, and 28-pin packages. A block diagram for this device family is shown in Figure 1-1. The devices are differentiated from each other only in the amount of on-chip FLASH program memory (4 Kbytes for the PIC18F1220 device, 8 Kbytes for PIC18F1320). These and other features are summarized in Table 1-1. A block diagram of the PIC18F1220/1320 device architecture is provided in Figure 1-1. The pinouts for this device family are listed in Table 1-2. TABLE 1-1: DEVICE FEATURES Features Operating Frequency PIC18F1220 PIC18F1320 DC - 40 MHz DC - 40 MHz Program Memory (Bytes) 4096 8192 Program Memory (Instructions) 2048 4096 Data Memory (Bytes) 256 256 Data EEPROM Memory (Bytes) 256 256 Interrupt Sources 15 15 Ports A, B Ports A, B Timers 4 4 Enhanced Capture/Compare/PWM Modules 1 1 Enhanced USART Enhanced USART 7 input channels 7 input channels I/O Ports Serial Communications 10-bit Analog-to-Digital Module RESETS (and Delays) Programmable Low Voltage Detect Programmable Brown-out Reset Instruction Set Packages DS39605B-page 6 POR, BOR, POR, BOR, RESET Instruction, Stack Full, RESET Instruction, Stack Full, Stack Underflow (PWRT, OST), Stack Underflow (PWRT, OST), MCLR (optional), WDT MCLR (optional), WDT Yes Yes Yes Yes 75 Instructions 75 Instructions 18-pin SDIP 18-pin SOIC 20-pin SSOP 28-pin QFN 18-pin SDIP 18-pin SOIC 20-pin SSOP 28-pin QFN Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 FIGURE 1-1: PIC18F1220/1320 BLOCK DIAGRAM Data Bus<8> 21 Table Pointer <2> 21 8 8 8 PORTA Data Latch 8 RA0/AN0 Data RAM inc/dec logic RA1/AN1/LVDIN 21 Address Latch 20 Address Latch Program Memory (4 Kbytes) PIC18F1220 (8 Kbytes) PIC18F1320 PCLATU PCLATH PCU PCH PCL Program Counter 4 BSR 31 Level Stack Data Latch 16 Decode Table Latch 8 RA2/AN2/VREF- 12(2) Address<12> RA3/AN3/VREF+ 12 4 FSR0 Bank0, F FSR1 FSR2 12 RA4/T0CKI MCLR/VPP/RA5(1) OSC2/CLKO/RA6(2) inc/dec logic OSC2/CLKI/RA7(2) ROM Latch PORTB RB0/AN4/INT0 Instruction Register RB1/AN5/TX/CK/INT1 8 Instruction Decode & Control RB2/P1B/INT2 PRODH PRODL 3 RB3/CCP1/P1A 8 x 8 Multiply RB4/AN6/RX/DT/KBI0 8 OSC1(2) OSC2(2) T1OSI Timing Generation INT RC Oscillator T1OSO BIT OP 8 Power-up Timer Oscillator Start-up Timer WREG 8 RB6/PGC/T1OSO/ T1CKI/P1C/KBI2 8 MCLR VDD, VSS Timer0 Low Voltage Programming Brown-out Reset In-Circuit Debugger Fail-Safe Clock Monitor Timer1 8 Precision Voltage Reference Timer2 Timer3 Enhanced USART Enhanced CCP Note RB7/PGD/T1OSI/ P1D/KBI3 ALU<8> Power-on Reset Watchdog Timer (1) RB5/PGM/KBI1 8 A/D Converter Data EEPROM 1: RA5 is available only when the MCLR Resets are disabled. 2: OSC1, OSC2, CLKI and CLKO are only available in select Oscillator modes and when these pins are not being used as digital I/O. Refer to Section 2.0 for additional information. 2002 Microchip Technology Inc. Preliminary DS39605B-page 7 PIC18F1220/1320 TABLE 1-2: PIC18F1220/1320 PINOUT I/O DESCRIPTIONS Pin Number Pin Buffer PDIP/ SSOP QFN Type Type SOIC Pin Name MCLR/VPP/RA5 MCLR 4 4 1 VPP RA5 OSC1/CLKI/RA7 OSC1 16 18 I ST P I -- ST 21 I CLKI I RA7 I/O OSC2/CLKO/RA6 OSC2 15 17 Description Master Clear (input) or programming voltage (input). Master Clear (Reset) input. This pin is an active low RESET to the device. Programming voltage input. Digital input. Oscillator crystal or external clock input. Oscillator crystal input or external clock source input. ST buffer when configured in RC mode, CMOS otherwise. CMOS External clock source input. Always associated with pin function OSC1. (See related OSC1/CLKI, OSC2/CLKO pins.) ST General purpose I/O pin. ST 20 O -- CLKO O -- RA6 I/O ST Oscillator crystal or clock output. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. In RC, EC and INTRC modes, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1 and denotes instruction cycle rate. General purpose I/O pin. PORTA is a bi-directional I/O port. RA0/AN0 RA0 AN0 1 RA1/AN1/LVDIN RA1 AN1 LVDIN 2 RA2/AN2/VREFRA2 AN2 VREF- 6 RA3/AN3/VREF+ RA3 AN3 VREF+ 7 RA4/T0CKI RA4 T0CKI 3 1 2 7 8 3 26 I/O I ST Analog Digital I/O. Analog input 0. I/O I I ST Analog Analog Digital I/O. Analog input 1. Low Voltage Detect input. I/O I I ST Analog Analog Digital I/O. Analog input 2. A/D Reference Voltage (Low) input. I/O I I ST Analog Analog Digital I/O. Analog input 3. A/D Reference Voltage (High) input. I/O I ST/OD ST Digital I/O. Open drain when configured as output. Timer0 external clock input. 27 7 8 28 RA5 See the MCLR/VPP/RA5 pin. RA6 See the OSC2/CLKO/RA6 pin. RA7 See the OSC1/CLKI/RA7 pin. Legend: TTL ST O OD = = = = DS39605B-page 8 TTL compatible input Schmitt Trigger input with CMOS levels Output Open Drain (no P diode to VDD) CMOS = CMOS compatible input or output I = Input P = Power Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 TABLE 1-2: PIC18F1220/1320 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer PDIP/ SSOP QFN Type Type SOIC Pin Name Description PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. RB0/AN4/INT0 RB0 AN4 INT0 8 RB1/AN5/TX/CK/INT1 RB1 AN5 TX CK INT1 9 RB2/P1B/INT2 RB2 P1B INT2 17 RB3/CCP1/P1A RB3 CCP1 P1A 18 RB4/AN6/RX/DT/KBI0 RB4 AN6 RX DT KBI0 10 RB5/PGM/KBI1 RB5 PGM KBI1 11 RB6/PGC/T1OSO/ T1CKI/P1C/KBI2 RB6 PGC T1OSO T1CKI P1C KBI2 12 RB7/PGD/T1OSI/ P1D/KBI3 RB7 PGD T1OSI P1D KBI3 13 VSS 5 VDD Legend: TTL ST O OD 14 = = = = 9 10 19 20 11 12 13 14 5, 6 9 I/O I I TTL Analog ST Digital I/O. Analog input 4. External interrupt 0. I/O I O I/O I TTL Analog -- ST ST Digital I/O. Analog input 5. USART Asynchronous Transmit USART Synchronous Clock (see related RX/DT). External interrupt 1. I/O O I TTL -- ST Digital I/O. Enhanced CCP1 output. External interrupt 2. I/O I/O O TTL ST -- Digital I/O. Capture1 input, Compare1 output, PWM1 output. Enhanced CCP1 output. I/O I I I/O I TTL Analog ST ST TTL Digital I/O. Analog input 6. USART Asynchronous Receive. USART Synchronous Data (see related TX/CK). Interrupt-on-change pin. I/O I/O I TTL ST TTL Digital I/O. Low Voltage ICSP programming enable pin. Interrupt-on-change pin. I/O I/O O I O I TTL ST -- ST -- TTL Digital I/O. In-Circuit Debugger and ICSP programming clock pin. Timer1 oscillator output. Timer1 external clock output. Enhanced CCP1 output. Interrupt-on-change pin. I/O I/O I O I TTL ST CMOS -- TTL Digital I/O. In-Circuit Debugger and ICSP programming data pin. Timer1 oscillator input. Enhanced CCP1 output. Interrupt-on-change pin. P -- P -- 10 23 24 12 13 15 16 3, 5 15, 16 17, 19 TTL compatible input Schmitt Trigger input with CMOS levels Output Open Drain (no P diode to VDD) 2002 Microchip Technology Inc. Ground reference for logic and I/O pins. Positive supply for logic and I/O pins. CMOS = CMOS compatible input or output I = Input P = Power Preliminary DS39605B-page 9 PIC18F1220/1320 NOTES: DS39605B-page 10 Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 2.0 OSCILLATOR CONFIGURATIONS 2.1 Oscillator Types FIGURE 2-1: C1(1) The PIC18F1220 and PIC18F1320 devices can be operated in ten different Oscillator modes. The user can program the configuration bits FOSC3:FOSC0 in Configuration Register 1H to select one of these ten modes: 1. 2. 3. 4. LP XT HS HSPLL 5. RC 6. RCIO 7. INTIO1 8. INTIO2 9. EC 10. ECIO 2.2 Low Power Crystal Crystal/Resonator High Speed Crystal/Resonator High Speed Crystal/Resonator with PLL enabled External Resistor/Capacitor with FOSC/4 output on RA6 External Resistor/Capacitor with I/O on RA6 Internal Oscillator with FOSC/4 output on RA6 and I/O on RA7 Internal Oscillator with I/O on RA6 and RA7 External Clock with FOSC/4 output External Clock with I/O on RA6 The oscillator design requires the use of a parallel cut crystal. Note: Use of a series cut crystal may give a frequency out of the crystal manufacturers specifications. OSC1 XTAL To Internal Logic RF(3) SLEEP RS(2) C2(1) PIC18FXXXX OSC2 Note 1: See Table 2-1 and Table 2-2 for initial values of C1 and C2. 2: A series resistor (RS) may be required for AT strip cut crystals. 3: RF varies with the Oscillator mode chosen. TABLE 2-1: CAPACITOR SELECTION FOR CERAMIC RESONATORS Typical Capacitor Values Used: Mode Freq OSC1 OSC2 XT 455 kHz 2.0 MHz 4.0 MHz 56 pF 47 pF 33 pF 56 pF 47 pF 33 pF HS 8.0 MHz 16.0 MHz 27 pF 22 pF 27 pF 22 pF Crystal Oscillator/Ceramic Resonators In XT, LP, HS or HSPLL Oscillator modes, a crystal or ceramic resonator is connected to the OSC1 and OSC2 pins to establish oscillation. Figure 2-1 shows the pin connections. CRYSTAL/CERAMIC RESONATOR OPERATION (XT, LP, HS OR HSPLL CONFIGURATION) Capacitor values are for design guidance only. These capacitors were tested with the resonators listed below for basic start-up and operation. These values are not optimized. Different capacitor values may be required to produce acceptable oscillator operation. The user should test the performance of the oscillator over the expected VDD and temperature range for the application. See the notes on page 12 for additional information. Resonators Used: 455 kHz 4.0 MHz 2.0 MHz 8.0 MHz 16.0 MHz 2002 Microchip Technology Inc. Preliminary DS39605B-page 11 PIC18F1220/1320 Osc Type LP XT HS CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR Crystal Freq Typical Capacitor Values Tested: C1 C2 32 kHz 33 pF 33 pF 200 kHz 15 pF 15 pF 1 MHz 33 pF 33 pF 4 MHz 27 pF 27 pF 4 MHz 27 pF 27 pF 8 MHz 22 pF 22 pF 20 MHz 15 pF 15 pF 2.3 Different capacitor values may be required to produce acceptable oscillator operation. The user should test the performance of the oscillator over the expected VDD and temperature range for the application. See the notes following this table for additional information. 8 MHz 1 MHz 20 MHz OSC1 PIC18FXXXX OSC2 HSPLL A Phase Locked Loop (PLL) circuit is provided as an option for users who wish to use a lower frequency crystal oscillator circuit, or to clock the device up to its highest rated frequency from a crystal oscillator. This may be useful for customers who are concerned with EMI due to high frequency crystals. The HSPLL mode makes use of the HS mode oscillator for frequencies up to 10 MHz. A PLL then multiplies the oscillator output frequency by 4 to produce an internal clock frequency up to 40 MHz. FIGURE 2-3: Note 1: Higher capacitance increases the stability of oscillator, but also increases the start-up time. 2: When operating below 3V VDD, or when using certain ceramic resonators at any voltage, it may be necessary to use the HS mode or switch to a crystal oscillator. PLL BLOCK DIAGRAM HS Osc Enable PLL Enable (from Configuration Register 1H) OSC2 OSC1 Crystal FIN Osc FOUT 3: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components. 4: Rs may be required to avoid overdriving crystals with low drive level specification. 5: Always verify oscillator performance over the VDD and temperature range that is expected for the application. DS39605B-page 12 (HS Mode) The PLL is enabled only when the oscillator configuration bits are programmed for HSPLL mode. If programmed for any other mode, the PLL is not enabled. Crystals Used: 4 MHz EXTERNAL CLOCK INPUT OPERATION (HS OSC CONFIGURATION) Open These capacitors were tested with the crystals listed below for basic start-up and operation. These values are not optimized. 32 kHz FIGURE 2-2: Clock from Ext. System Capacitor values are for design guidance only. 200 kHz An external clock source may also be connected to the OSC1 pin in the HS mode, as shown in Figure 2-2. Preliminary Phase Comparator Loop Filter /4 VCO MUX TABLE 2-2: SYSCLK 2002 Microchip Technology Inc. PIC18F1220/1320 2.4 External Clock Input 2.5 The EC and ECIO Oscillator modes require an external clock source to be connected to the OSC1 pin. There is no oscillator start-up time required after a Power-on Reset, or after an exit from SLEEP mode. In the EC Oscillator mode, the oscillator frequency divided by 4 is available on the OSC2 pin. This signal may be used for test purposes, or to synchronize other logic. Figure 2-4 shows the pin connections for the EC Oscillator mode. FIGURE 2-4: EXTERNAL CLOCK INPUT OPERATION (EC CONFIGURATION) OSC1/CLKI Clock from Ext. System PIC18FXXXX FOSC/4 OSC2/CLKO RC Oscillator For timing insensitive applications, the "RC" and "RCIO" device options offer additional cost savings. The RC oscillator frequency is a function of the supply voltage, the resistor (REXT) and capacitor (CEXT) values and the operating temperature. In addition to this, the oscillator frequency will vary from unit to unit due to normal manufacturing variation. Furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low CEXT values. The user also needs to take into account variation, due to tolerance of external R and C components used. Figure 2-6 shows how the R/C combination is connected. In the RC Oscillator mode, the oscillator frequency divided by 4 is available on the OSC2 pin. This signal may be used for test purposes, or to synchronize other logic. FIGURE 2-6: The ECIO Oscillator mode functions like the EC mode, except that the OSC2 pin becomes an additional general purpose I/O pin. The I/O pin becomes bit 6 of PORTA (RA6). Figure 2-5 shows the pin connections for the ECIO Oscillator mode. RC OSCILLATOR MODE VDD REXT OSC1 Internal Clock CEXT FIGURE 2-5: EXTERNAL CLOCK INPUT OPERATION (ECIO CONFIGURATION) PIC18FXXXX VSS FOSC/4 OSC2/CLKO Recommended values: 3 k REXT 100 k CEXT > 20 pF OSC1/CLKI Clock from Ext. System PIC18FXXXX RA6 I/O (OSC2) The RCIO Oscillator mode (Figure 2-7) functions like the RC mode, except that the OSC2 pin becomes an additional general purpose I/O pin. The I/O pin becomes bit 6 of PORTA (RA6). FIGURE 2-7: RCIO OSCILLATOR MODE VDD REXT OSC1 Internal Clock CEXT PIC18FXXXX VSS RA6 I/O (OSC2) Recommended values: 3 k REXT 100 k CEXT > 20 pF 2002 Microchip Technology Inc. Preliminary DS39605B-page 13 PIC18F1220/1320 2.6 Internal Oscillator Block 2.6.2 The PIC18F1220/1320 devices include an internal oscillator block, which generates two different clock signals; either can be used as the system's clock source. This can eliminate the need for external oscillator circuits on the OSC1 and/or OSC2 pins. The main output (INTOSC) is an 8 MHz clock source, which can be used to directly drive the system clock. It also drives a postscaler, which can provide a range of clock frequencies from 125 kHz to 4 MHz. The INTOSC output is enabled when a system clock frequency from 125 kHz to 8 MHz is selected. INTRC OUTPUT FREQUENCY The internal oscillator block is calibrated at the factory to produce an INTOSC output frequency of 8.0 MHz (see Table 22.5). This changes the frequency of the INTRC source from its nominal 31.25 kHz. Peripherals and features that depend on the INTRC source will be affected by this shift in frequency. Once set during factory calibration, the INTRC frequency will remain within 2% as temperature and VDD change across their full specified operating ranges. 2.6.3 OSCTUNE REGISTER The other clock source is the internal RC oscillator (INTRC), which provides a 31 kHz output. The INTRC oscillator is enabled by selecting the internal oscillator block as the system clock source, or when any of the following are enabled: The internal oscillator's output has been calibrated at the factory, but can be adjusted in the user's application. This is done by writing to the OSCTUNE register (Register 2-1). The tuning sensitivity is constant throughout the tuning range. * * * * When the OSCTUNE register is modified, the INTOSC and INTRC frequencies will begin shifting to the new frequency. The INTRC clock will reach the new frequency within 8 clock cycles (approximately 8 * 32 s = 256 s). The INTOSC clock will stabilize within 1 ms. Code execution continues during this shift. There is no indication that the shift has occurred. Operation of features that depend on the INTRC clock source frequency, such as the WDT, Fail-Safe Clock Monitor and peripherals, will also be affected by the change in frequency. Power-up Timer Fail-Safe Clock Monitor Watchdog Timer Two-Speed Start-up These features are discussed in greater detail in Section 19.0 ("Special Features of the CPU"). The clock source frequency (INTOSC direct, INTRC direct or INTOSC postscaler) is selected by configuring the IRCF bits of the OSCCON register (Register 2-2). 2.6.1 INTIO MODES Using the internal oscillator as the clock source can eliminate the need for up to two external oscillator pins, which can then be used for digital I/O. Two distinct configurations are available: * In INTIO1 mode, the OSC2 pin outputs FOSC/4, while OSC1 functions as RA7 for digital input and output. * In INTIO2 mode, OSC1 functions as RA7 and OSC2 functions as RA6, both for digital input and output. DS39605B-page 14 Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 REGISTER 2-1: OSCTUNE: OSCILLATOR TUNING REGISTER U-0 -- bit 7 bit 7-6 bit 5-0 U-0 -- R/W-0 TUN4 R/W-0 TUN3 R/W-0 TUN2 R/W-0 TUN1 R/W-0 TUN0 bit 0 Unimplemented: Read as `0' TUN<5:0>: Frequency Tuning bits 011111 = Maximum frequency * * * * 000001 000000 = Center frequency. Oscillator module is running at the calibrated frequency. 111111 * * * * 100000 = Minimum frequency Legend: R = Readable bit -n = Value at POR 2.7 R/W-0 TUN5 W = Writable bit `1' = Bit is set Clock Sources and Oscillator Switching Like previous PIC18 devices, the PIC18F1220/1320 devices include a feature that allows the system clock source to be switched from the main oscillator to an alternate low frequency clock source. PIC18F1220/1320 devices offer two alternate clock sources. When enabled, these give additional options for switching to the various Power Managed Operating modes. Essentially, there are three clock sources for these devices: * Primary oscillators * Secondary oscillators * Internal oscillator block The primary oscillators include the external Crystal and Resonator modes, the external RC modes, the external Clock modes and the internal oscillator block. The particular mode is defined on POR by the contents of Configuration Register 1H. The details of these modes are covered earlier in this chapter. U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown PIC18F1220/1320 devices offer only the Timer1 oscillator as a secondary oscillator. This oscillator, in all Power Managed modes, is often the time-base for functions such as a real-time clock. Most often, a 32.768 kHz watch crystal is connected between the RC0/T1OSO and RC1/T1OSI pins. Like the LP mode oscillator circuit, loading capacitors are also connected from each pin to ground. The Timer1 oscillator is discussed in greater detail in Section 12.2. In addition to being a primary clock source, the internal oscillator block is available as a Power Managed mode clock source. The INTRC source is also used as the clock source for several special features, such as the WDT and Fail-Safe Clock Monitor. The clock sources for the PIC18F1220/1320 devices are shown in Figure 2-8. See Section 12.0 for further details of the Timer1 oscillator. See Section 19.1 for Configuration Register details. The secondary oscillators are those external sources not connected to the OSC1 or OSC2 pins. These sources may continue to operate even after the controller is placed in a Power Managed mode. 2002 Microchip Technology Inc. Preliminary DS39605B-page 15 PIC18F1220/1320 2.7.1 OSCILLATOR CONTROL REGISTER when the internal oscillator block has stabilized, and is providing the system clock in RC clock modes. The T1RUN bit (T1CON<6>) indicates when the Timer1 oscillator is providing the system clock in Secondary Clock modes. In Power Managed modes, only one of these three bits will be set at any time. If none of these bits are set, the INTRC is providing the system clock, or the internal oscillator block has just started and is not yet stable. The OSCCON register (Register 2-2) controls several aspects of the system clock's operation, both in full power operation and in Power Managed modes. The System Clock Select bits, SCS1:SCS0, select the clock source that is used when the device is operating in Power Managed modes. The available clock sources are the primary clock (defined in Configuration Register 1H), the secondary clock (Timer1 oscillator), and the internal oscillator block. The clock selection has no effect until a SLEEP instruction is executed and the device enters a Power Managed mode of operation. The SCS bits are cleared on all forms of RESET. The IDLEN bit controls the selective shutdown of the controller's CPU in Power Managed modes. The uses of these bits are discussed in more detail in Section 3.0 ("Power Managed Modes"). The Internal Oscillator Select bits, IRCF2:IRCF0, select the frequency output of the internal oscillator block that is used to drive the system clock. The choices are the INTRC source, the INTOSC source (8 MHz), or one of the six frequencies derived from the INTOSC postscaler (125 kHz to 4 MHz). If the internal oscillator block is supplying the system clock, changing the states of these bits will have an immediate change on the internal oscillator's output. Note 1: The Timer1 oscillator must be enabled to select the secondary clock source. The Timer1 oscillator is enabled by setting the T1OSCEN bit in the Timer1 Control register (T1CON<3>). If the Timer1 oscillator is not enabled, then any attempt to select a secondary clock source when executing a SLEEP instruction will be ignored. The OSTS, IOFS and T1RUN bits indicate which clock source is currently providing the system clock. The OSTS indicates that the Oscillator Start-up Timer has timed out, and the primary clock is providing the system clock in Primary Clock modes. The IOFS bit indicates 2: It is recommended that the Timer1 oscillator be operating and stable before executing the SLEEP instruction, or a very long delay may occur while the Timer1 oscillator starts. FIGURE 2-8: PIC18F1220/1320 CLOCK DIAGRAM PIC18F1220/1320 Primary Oscillator OSCCON<1:0> HSPLL 4 x PLL SLEEP Clock Control CONFIG1H <3:0> OSC2 Secondary Oscillator T1OSC T1OSO OSCCON<6:4> 8 MHz OSCCON<6:4> 4 MHz Internal Oscillator Block 8 MHz (INTOSC) Postscaler INTRC Source 2 MHz 1 MHz 500 kHz 250 kHz 125 kHz 31 kHz DS39605B-page 16 Peripherals Internal Oscillator CPU 111 110 IDLEN 101 100 011 MUX T1OSI Clock Source Option for Other Modules T1OSCEN Enable Oscillator MUX LP, XT, HS, RC, EC OSC1 010 001 000 Preliminary WDT, FSCM 2002 Microchip Technology Inc. PIC18F1220/1320 REGISTER 2-2: OSCCON REGISTER R/W-0 IDLEN bit 7 bit 7 bit 6-4 bit 3 bit 2 bit 1-0 R/W-0 IRCF2 R/W-0 IRCF1 R/W-0 IRCF0 R(1) OSTS R-0 IOFS R/W-0 SCS1 R/W-0 SCS0 bit 0 IDLEN: IDLE Enable bits 1 = IDLE mode enabled; CPU core is not clocked in Power Managed modes 0 = RUN mode enabled; CPU core is clocked in Power Managed modes IRCF2:IRCF0: Internal Oscillator Frequency Select bits 111 = 8 MHz (8 MHz source drives clock directly) 110 = 4 MHz 101 = 2 MHz 100 = 1 MHz 011 = 500 kHz 010 = 250 kHz 001 = 125 kHz 000 = 31 kHz (INTRC source drives clock directly) OSTS: Oscillator Start-up Time-out Status bit 1 = Oscillator start-up time-out timer has expired; primary oscillator is running 0 = Oscillator start-up time-out timer is running; primary oscillator is not ready IOFS: INTOSC Frequency Stable bit 1 = INTOSC frequency is stable 0 = INTOSC frequency is not stable SCS1:SCS0: System Clock Select bits 1x = Internal oscillator block (RC modes) 01 = Timer1 oscillator (Secondary modes) 00 = Primary oscillator (SLEEP and PRI_IDLE modes) Note 1: Depends on state of the IESO bit in Configuration Register 1H. Legend: R = Readable bit - n = Value at POR 2002 Microchip Technology Inc. W = Writable bit `1' = Bit is set Preliminary U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown DS39605B-page 17 PIC18F1220/1320 2.7.2 OSCILLATOR TRANSITIONS The PIC18F1220/1320 devices contain circuitry to prevent clocking "glitches" when switching between clock sources. A short pause in the system clock occurs during the clock switch. The length of this pause is between 8 and 9 clock periods of the new clock source. This ensures that the new clock source is stable and that its pulse width will not be less than the shortest pulse width of the two clock sources. If the SLEEP mode is selected, all clock sources are stopped. Since all the transistor switching currents have been stopped, SLEEP mode achieves the lowest current consumption of the device (only leakage currents). Clock transitions are discussed in greater detail in Section 3.1.2, "Entering Power Managed Modes". Enabling any on-chip feature that will operate during SLEEP will increase the current consumed during SLEEP. The INTRC is required to support WDT operation. The Timer1 oscillator may be operating to support a real-time clock. Other features may be operating that do not require a system clock source (i.e., SSP slave, PSP, INTn pins, A/D conversions, and others). 2.8 2.9 Effects of Power Managed Modes on the Various Clock Sources When the device executes a SLEEP instruction, the system is switched to one of the Power Managed modes, depending on the state of the IDLEN and SCS1:SCS0 bits of the OSCCON register. See Section 3.0 ("Power Managed Modes") for details. When PRI_IDLE mode is selected, the designated primary oscillator continues to run without interruption. For all other Power Managed modes, the oscillator using the OSC1 pin is disabled. The OSC1 pin (and OSC2 pin, if used by the oscillator) will stop oscillating. In Secondary Clock modes (SEC_RUN and SEC_IDLE), the Timer1 oscillator is operating and providing the system clock. The Timer1 oscillator may also run in all Power Managed modes if required to clock Timer1 or Timer3. In Internal Oscillator modes (RC_RUN and RC_IDLE), the internal oscillator block provides the system clock source. The INTRC output can be used directly to provide the system clock and may be enabled to support various special features, regardless of the Power Managed mode (see Sections 19.2 through 19.4). The INTOSC output at 8 MHz may be used directly to clock the system, or may be divided down first. The INTOSC output is disabled if the system clock is provided directly from the INTRC output. TABLE 2-3: Power-up Delays Power-up delays are controlled by two timers, so that no external RESET circuitry is required for most applications. The delays ensure that the device is kept in RESET until the device power supply is stable under normal circumstances, and the primary clock is operating and stable. For additional information on power-up delays, see Sections 4.1 through 4.5. The first timer is the Power-up Timer (PWRT), which provides a fixed delay on power-up (parameter 33, Table 22-7), if enabled in Configuration Register 2L. The second timer is the Oscillator Start-up Timer (OST), intended to keep the chip in RESET until the crystal oscillator is stable (LP, XT and HS modes). The OST does this by counting 1024 oscillator cycles before allowing the oscillator to clock the device. When the HSPLL Oscillator mode is selected, the device is kept in RESET for an additional 2 ms following the HS mode OST delay, so the PLL can lock to the incoming clock frequency. There is a delay of 5 to 10 s following POR while the controller becomes ready to execute instructions. This delay runs concurrently with any other delays. This may be the only delay that occurs when any of the EC, RC, or INTIO modes are used as the primary clock source. OSC1 AND OSC2 PIN STATES IN SLEEP MODE OSC Mode OSC1 Pin OSC2 Pin RC, INTIO1 Floating, external resistor should pull high At logic low (clock/4 output) RCIO, INTIO2 Floating, external resistor should pull high Configured as PORTA, bit 6 ECIO Floating, pulled by external clock Configured as PORTA, bit 6 EC Floating, pulled by external clock At logic low (clock/4 output) LP, XT, and HS Feedback inverter disabled at quiescent voltage level Feedback inverter disabled at quiescent voltage level Note: See Table 4-1 in Section 4.0, for time-outs due to SLEEP and MCLR Reset. DS39605B-page 18 Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 3.0 POWER MANAGED MODES 3.1 Selecting Power Managed Modes Selecting a Power Managed mode requires deciding if the CPU is to be clocked or not, and selecting a clock source. The IDLEN bit controls CPU clocking, while the SC1:SCS0 bits select a clock source. The individual modes, bit settings, clock sources, and affected modules are summarized in Table 3-1. The PIC18F1220/1320 devices offer a total of six Operating modes for more efficient power management. These provide a variety of options for selective power conservation in applications where resources may be limited (i.e., battery powered devices). There are three categories of Power Managed modes: 3.1.1 * SLEEP mode * IDLE modes * RUN modes CLOCK SOURCES The clock source is selected by setting the SCS bits of the OSCCON register (Register 2-2). Three clock sources are available for use in Power Managed IDLE modes: the primary clock (as configured in Configuration Register 1H), the secondary clock (Timer1 oscillator), and the internal oscillator block. The secondary and internal oscillator block sources are available for the Power Managed modes (PRI_RUN mode is the normal Full Power Execution mode; the CPU and peripherals are clocked by the primary oscillator source). These categories define which portions of the device are clocked and sometimes, what speed. The RUN and IDLE modes may use any of the three available clock sources (Primary, Secondary or INTOSC multiplexer); the SLEEP mode does not use a clock source. The clock switching feature offered in other PIC18 devices (i.e., using the Timer1 oscillator in place of the primary oscillator), and the SLEEP mode offered by all PICmicro(R) devices (where all system clocks are stopped) are both offered in the PIC18F1220/1320 devices (SEC_RUN and SLEEP modes, respectively). However, additional Power Managed modes are available that allow the user greater flexibility in determining what portions of the device are operating. The Power Managed modes are event driven; that is, some specific event must occur for the device to enter or (more particularly) exit these Operating modes. For PIC18F1220/1320 devices, the Power Managed modes are invoked by using the existing SLEEP instruction. All modes exit to PRI_RUN mode when triggered by an interrupt, a RESET, or a WDT time-out (PRI_RUN mode is the normal Full Power Execution mode; the CPU and peripherals are clocked by the primary oscillator source). In addition, Power Managed RUN modes may also exit to SLEEP mode, or their corresponding IDLE mode. TABLE 3-1: POWER MANAGED MODES OSCCON Bits Mode Module Clocking Available Clock and Oscillator Source IDLEN <7> SCS1:SCS0 <1:0> CPU Peripherals SLEEP 0 00 Off Off PRI_RUN 0 00 Clocked Clocked Primary - LP, XT, HS, HSPLL, RC, EC, INTRC(1) This is the normal Full Power Execution mode. SEC_RUN 0 01 Clocked Clocked Secondary - Timer1 Oscillator RC_RUN 0 1X Clocked Clocked Internal Oscillator Block(1) PRI_IDLE 1 00 Off Clocked Primary - LP, XT, HS, HSPLL, RC, EC SEC_IDLE 1 01 Off Clocked Secondary - Timer1 Oscillator RC_IDLE 1 1X Off Clocked Internal Oscillator Block(1) None - All clocks are disabled Note 1: Includes INTOSC and INTOSC postscaler, as well as the INTRC source. 2002 Microchip Technology Inc. Preliminary DS39605B-page 19 PIC18F1220/1320 3.1.2 ENTERING POWER MANAGED MODES In general, entry, exit, and switching between Power Managed clock sources requires clock source switching. In each case, the sequence of events is the same. Any change in the Power Managed mode begins with loading the OSCCON register and executing a SLEEP instruction. The SCS1:SCS0 bits select one of three power managed clock sources; the primary clock (as defined in Configuration Register 1H), the secondary clock (the Timer1 oscillator), and the internal oscillator block (used in RC modes). Modifying the SCS bits will have no effect until a SLEEP instruction is executed. Entry to the Power Managed mode is triggered by the execution of a SLEEP instruction. Figure 3-5 shows how the system is clocked while switching from the primary clock to the Timer1 oscillator. When the SLEEP instruction is executed, clocks to the device are stopped at the beginning of the next instruction cycle. Eight clock cycles from the new clock source are counted to synchronize with the new clock source. After 8 clock pulses from the new clock source are counted, clocks from the new clock source resume clocking the system. The actual length of the pause is between 8 and 9 clock periods from the new clock source. This ensures that the new clock source is stable and that its pulse width will not be less than the shortest pulse width of the two clock sources. Three bits indicate the current clock source: OSTS and IOFS in the OSCCON register, and T1RUN in the T1CON register. Only one of these bits will be set while in a Power Managed mode. When the OSTS bit is set, the primary clock is providing the system clock. When the IOFS bit is set, the INTOSC output is providing a stable 8 MHz clock source and is providing the system clock. When the T1RUN bit is set, the Timer1 oscillator is providing the system clock. If none of these bits are set, then either the INTRC clock source is clocking the system, or the INTOSC source is not yet stable. If the internal oscillator block is configured as the primary clock source in Configuration Register 1H, then both the OSTS and IOFS bits may be set when in PRI_RUN or PRI_IDLE modes. This indicates that the primary clock (INTOSC output) is generating a stable 8 MHz output. Entering an RC Power Managed mode (same frequency) would clear the OSTS bit. Note 1: Caution should be used when modifying a single IRCF bit. If VDD is less than 3V, it is possible to select a higher clock speed than is supported by the low VDD. Improper device operation may result if the VDD/FOSC specifications are violated. 2: Executing a SLEEP instruction does not necessarily place the device into SLEEP mode; executing a SLEEP instruction is simply a trigger to place the controller into a Power Managed mode selected by the OSCCON register, one of which is SLEEP mode. 3.1.3 MULTIPLE SLEEP COMMANDS The Power Managed mode that is invoked with the SLEEP instruction is determined by the settings of the IDLEN and SCS bits at the time the instruction is executed. If another SLEEP instruction is executed, the device will enter the Power Managed mode specified by these same bits at that time. If the bits have changed, the device will enter the new Power Managed mode specified by the new bit settings. 3.1.4 COMPARISONS BETWEEN RUN AND IDLE MODES Clock source selection for the RUN modes is identical to the corresponding IDLE modes. When a SLEEP instruction is executed, the SCS bits in the OSCCON register are used to switch to a different clock source. As a result, if there is a change of clock source at the time a SLEEP instruction is executed, a clock switch will occur. In IDLE modes, the CPU is not clocked and is not running. In RUN modes, the CPU is clocked and executing code. This difference modifies the operation of the WDT when it times out. In IDLE modes, a WDT timeout results in a wake from Power Managed modes. In RUN modes, a WDT time-out results in a WDT Reset (see Table 3-2). During a wake-up from an IDLE mode, the CPU starts executing code by entering the corresponding RUN mode, until the primary clock becomes ready. When the primary clock becomes ready, the clock source is automatically switched to the primary clock. The IDLEN and SCS bits are unchanged during and after the wake-up. Figure 3-2 shows how the system is clocked during the clock source switch. The example assumes the device was in SEC_IDLE or SEC_RUN mode when a wake is triggered (the primary clock was configured in HSPLL mode). DS39605B-page 20 Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 TABLE 3-2: Power Managed Mode SLEEP COMPARISON BETWEEN POWER MANAGED MODES CPU is clocked by ... WDT time-out causes a ... Not clocked None, or INTOSC multiplexer if Two-Speed Start-up or Fail-Safe Clock Monitor are enabled Any IDLE mode Not clocked (not running) Wake-up Primary, Secondary, or INTOSC multiplexer Unchanged from IDLE mode (CPU operates as in corresponding RUN mode) Any RUN mode Secondary, or INTOSC multiplexer Secondary, or INTOSC Unchanged from RUN mode multiplexer 3.2 Not clocked (not running) Wake-up Clock during Wake-up (while primary becomes ready) Peripherals are clocked by ... RESET SLEEP Mode 3.3 IDLE Modes The Power Managed SLEEP mode in the PIC18F1220/ 1320 devices is identical to that offered in all other PICmicro microcontrollers. It is entered by clearing the IDLEN and SCS1:SCS0 bits (this is the RESET state), and executing the SLEEP instruction. This shuts down the primary oscillator, and the OSTS bit is cleared (see Figure 3-1). The IDLEN bit allows the microcontroller's CPU to be selectively shutdown while the peripherals continue to operate. Clearing IDLEN allows the CPU to be clocked. Setting IDLEN disables clocks to the CPU, effectively stopping program execution (see Register 2-2). The peripherals continue to be clocked regardless of the setting of the IDLEN bit. When a wake event occurs in SLEEP mode (by interrupt, RESET, or WDT time-out), the system will not be clocked until the primary clock source becomes ready (see Figure 3-2), or it will be clocked from the internal oscillator block if either the Two-Speed Start-up or the Fail-Safe Clock Monitor are enabled (see Section 19.0, "Special Features of the CPU"). In either case, the OSTS bit is set when the primary clock is providing the system clocks. The IDLEN and SCS bits are not affected by the wake-up. There is one exception to how the IDLEN bit functions. When all the low power OSCCON bits are cleared (IDLEN:SCS1:SCS0 = 000), the device enters SLEEP mode upon the execution of the SLEEP instruction. This is both the RESET state of the OSCCON register, and the setting that selects SLEEP mode. This maintains compatibility with other PICmicro devices that do not offer Power Managed modes. If the IDLE Enable bit, IDLEN (OSCCON<7>), is set to a `1' when a SLEEP instruction is executed, the peripherals will be clocked from the clock source selected using the SCS1:SCS0 bits; however, the CPU will not be clocked. Since the CPU is not executing instructions, the only exits from any of the IDLE modes are by interrupt, WDT time-out or a RESET. When a wake event occurs, CPU execution is delayed approximately 10 s while it becomes ready to execute code. When the CPU begins executing code, it is clocked by the same clock source as was selected in the Power Managed mode (i.e., when waking from RC_IDLE mode, the internal oscillator block will clock the CPU and peripherals until the primary clock source becomes ready - this is essentially RC_RUN mode). This continues until the primary clock source becomes ready. When the primary clock becomes ready, the OSTS bit is set, and the system clock source is switched to the primary clock (see Figure 3-4). The IDLEN and SCS bits are not affected by the wake-up. While in any IDLE mode or the SLEEP mode, a WDT time-out will result in a WDT wake-up to full power operation. 2002 Microchip Technology Inc. Preliminary DS39605B-page 21 PIC18F1220/1320 FIGURE 3-1: TIMING TRANSITION FOR ENTRY TO SLEEP MODE Q1 Q2 Q3 Q4 Q1 OSC1 CPU Clock Peripheral Clock SLEEP Program Counter PC FIGURE 3-2: PC + 2 TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 TOST(1) PLL Clock Output TPLL(1) CPU Clock Peripheral Clock Program Counter PC Wake Event Note PC + 2 PC + 4 PC + 6 PC + 8 OSTS bit Set 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale. DS39605B-page 22 Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 3.3.1 PRI_IDLE MODE This mode is unique among the three Low Power IDLE modes, in that it does not disable the primary system clock. For timing sensitive applications, this allows for the fastest resumption of device operation with its more accurate primary clock source, since the clock source does not have to "warm up" or transition from another oscillator. When a wake event occurs, the CPU is clocked from the primary clock source. A delay of approximately 10 s is required between the wake event and code execution starts. This is required to allow the CPU to become ready to execute instructions. After the wakeup, the OSTS bit remains set. The IDLEN and SCS bits are not affected by the wake-up (see Figure 3-4). PRI_IDLE mode is entered by setting the IDLEN bit, clearing the SCS bits, and executing a SLEEP instruction. Although the CPU is disabled, the peripherals continue to be clocked from the primary clock source specified in Configuration Register 1H. The OSTS bit remains set in PRI_IDLE mode (see Figure 3-3). FIGURE 3-3: TRANSITION TIMING TO PRI_IDLE MODE Q1 Q3 Q2 Q4 Q1 OSC1 CPU Clock Peripheral Clock Program Counter FIGURE 3-4: PC PC + 2 TRANSITION TIMING FOR WAKE FROM PRI_IDLE MODE Q1 Q3 Q2 Q4 OSC1 CPU Start-up Delay CPU Clock Peripheral Clock Program Counter PC + 2 PC Wake Event 2002 Microchip Technology Inc. Preliminary DS39605B-page 23 PIC18F1220/1320 3.3.2 SEC_IDLE MODE When a wake event occurs, the peripherals continue to be clocked from the Timer1 oscillator. After a 10 s delay following the wake event, the CPU begins executing code, being clocked by the Timer1 oscillator. The microcontroller operates in SEC_RUN mode until the primary clock becomes ready. When the primary clock becomes ready, a clock switchback to the primary clock occurs (see Figure 3-6). When the clock switch is complete, the T1RUN bit is cleared, the OSTS bit is set, and the primary clock is providing the system clock. The IDLEN and SCS bits are not affected by the wake-up. The Timer1 oscillator continues to run. In SEC_IDLE mode, the CPU is disabled, but the peripherals continue to be clocked from the Timer1 oscillator. This mode is entered by setting the IDLE bit, modifying to SCS1:SCS0 = 01, and executing a SLEEP instruction. When the clock source is switched (see Figure 3-5) to the Timer1 oscillator, the primary oscillator is shutdown, the OSTS bit is cleared, and the T1RUN bit is set. Note: The Timer1 oscillator should already be running prior to entering SEC_IDLE mode. If the T1OSCEN bit is not set when the SLEEP instruction is executed, the SLEEP instruction will be ignored and entry to SEC_IDLE mode will not occur. If the Timer1 oscillator is enabled, but not yet running, peripheral clocks will be delayed until the oscillator has started; in such situations, initial oscillator operation is far from stable and unpredictable operation may result. FIGURE 3-5: TIMING TRANSITION FOR ENTRY TO SEC_IDLE MODE Q1 Q2 Q3 Q4 Q1 1 T1OSI 2 3 OSC1 4 5 6 Clock Transition 7 8 CPU Clock Peripheral Clock Program Counter PC FIGURE 3-6: PC + 2 TIMING TRANSITION FOR WAKE FROM SEC_RUN MODE (HSPLL) Q1 Q2 Q3 Q4 Q2 Q3 Q4 Q1 Q2 Q3 Q1 T1OSI OSC1 TOST(1) TPLL(1) PLL Clock Output 1 2 3 4 5 6 Clock Transition 7 8 CPU Clock Peripheral Clock Program Counter PC Wake from Interrupt Event Note PC + 4 PC + 2 PC + 6 OSTS bit Set 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale. DS39605B-page 24 Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 3.3.3 RC_IDLE MODE ously at a non-zero value before the SLEEP instruction was executed, and the INTOSC source was already stable, the IOFS bit will remain set. If the IRCF bits are all clear, the INTOSC output is not enabled, and the IOFS bit will remain clear; there will be no indication of the current clock source. In RC_IDLE mode, the CPU is disabled, but the peripherals continue to be clocked from the internal oscillator block using the INTOSC multiplexer. This mode allows for controllable power conservation during IDLE periods. When a wake event occurs, the peripherals continue to be clocked from the INTOSC multiplexer. After a 10 s delay following the wake event, the CPU begins executing code, being clocked by the INTOSC multiplexer. The microcontroller operates in RC_RUN mode until the primary clock becomes ready. When the primary clock becomes ready, a clock switchback to the primary clock occurs (see Figure 3-8). When the clock switch is complete, the IOFS bit is cleared, the OSTS bit is set, and the primary clock is providing the system clock. The IDLEN and SCS bits are not affected by the wakeup. The INTRC source will continue to run if either the WDT or the Fail-Safe Clock Monitor is enabled. This mode is entered by setting the IDLEN bit, setting SCS1 (SCS0 is ignored), and executing a SLEEP instruction. The INTOSC multiplexer may be used to select a higher clock frequency by modifying the IRCF bits before executing the SLEEP instruction. When the clock source is switched to the INTOSC multiplexer (see Figure 3-7), the primary oscillator is shutdown, and the OSTS bit is cleared. If the IRCF bits are set to a non-zero value (thus, enabling the INTOSC output), the IOFS bit becomes set after the INTOSC output becomes stable, in about 1 ms. Clocks to the peripherals continue while the INTOSC source stabilizes. If the IRCF bits were previ- FIGURE 3-7: TIMING TRANSITION TO RC_IDLE MODE Q1 Q2 Q3 Q4 Q1 1 INTRC 2 3 4 5 6 7 8 Clock Transition OSC1 CPU Clock Peripheral Clock Program Counter PC FIGURE 3-8: PC + 2 TIMING TRANSITION FOR WAKE FROM RC_RUN MODE (RC_RUN TO PRI_RUN) Q4 Q1 Q2 Q3 Q4 Q2 Q3 Q4 Q1 Q2 Q3 Q1 INTOSC Multiplexer OSC1 TOST(1) TPLL(1) PLL Clock Output 1 2 3 4 5 6 Clock Transition 7 8 CPU Clock Peripheral Clock Program Counter PC Wake from Interrupt Event Note PC + 4 PC + 2 PC + 6 OSTS bit Set 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale. 2002 Microchip Technology Inc. Preliminary DS39605B-page 25 PIC18F1220/1320 3.4 RUN Modes SEC_RUN mode is entered by clearing the IDLEN bit, setting SCS1:SCS0 = 01, and executing a SLEEP instruction. The system clock source is switched to the Timer1 oscillator (see Figure 3-9), the primary oscillator is shutdown, the T1RUN bit (T1CON<6>) is set, and the OSTS bit is cleared. If the IDLEN bit is clear when a SLEEP instruction is executed, the CPU and peripherals are both clocked from the source selected using the SCS1:SCS0 bits. While these operating modes may not afford the power conservation of IDLE or SLEEP modes, they do allow the device to continue executing instructions by using a lower frequency clock source. RC_RUN mode also offers the possibility of executing code at a frequency greater than the primary clock. Note: Wake-up from a Power Managed RUN mode can be triggered by an interrupt, or any RESET, to return to full power operation. As the CPU is executing code in RUN modes, several additional exits from RUN modes are possible. They include exit to SLEEP mode, exit to a corresponding IDLE mode, and exit by executing a RESET instruction. While the device is in any of the Power Managed RUN modes, a WDT time-out will result in a WDT Reset. 3.4.1 When a wake event occurs, the peripherals and CPU continue to be clocked from the Timer1 oscillator while the primary clock is started. When the primary clock becomes ready, a clock switchback to the primary clock occurs (see Figure 3-6). When the clock switch is complete, the T1RUN bit is cleared, the OSTS bit is set, and the primary clock is providing the system clock. The IDLEN and SCS bits are not affected by the wake-up. The Timer1 oscillator continues to run. PRI_RUN MODE The PRI_RUN mode is the normal Full Power Execution mode. If the SLEEP instruction is never executed, the microcontroller operates in this mode (a SLEEP instruction is executed to enter all other Power Managed modes). All other Power Managed modes exit to PRI_RUN mode when an interrupt or WDT time-out occur. Firmware can force an exit from SEC_RUN mode. By clearing the T1OSCEN bit (T1CON<3>), an exit from SEC_RUN back to normal full power operation is triggered. The Timer1 oscillator will continue to run and provide the system clock, even though the T1OSCEN bit is cleared. The primary clock is started. When the primary clock becomes ready, a clock switchback to the primary clock occurs (see Figure 3-6). When the clock switch is complete, the Timer1 oscillator is disabled, the T1RUN bit is cleared, the OSTS bit is set, and the primary clock is providing the system clock. The IDLEN and SCS bits are not affected by the wake-up. There is no entry to PRI_RUN mode. The OSTS bit is set. The IOFS bit may be set if the internal oscillator block is the primary clock source (see Section 2.7.1, "Oscillator Control Register"). 3.4.2 SEC_RUN MODE The SEC_RUN mode is the compatible mode to the "clock switching" feature offered in other PIC18 devices. In this mode, the CPU and peripherals are clocked from the Timer1 oscillator. This gives users the option of lower power consumption while still using a high accuracy clock source. FIGURE 3-9: The Timer1 oscillator should already be running prior to entering SEC_RUN mode. If the T1OSCEN bit is not set when the SLEEP instruction is executed, the SLEEP instruction will be ignored and entry to SEC_RUN mode will not occur. If the Timer1 oscillator is enabled, but not yet running, system clocks will be delayed until the oscillator has started; in such situations, initial oscillator operation is far from stable and unpredictable operation may result. TIMING TRANSITION FOR ENTRY TO SEC_RUN MODE Q1 Q2 Q3 Q4 Q1 Q2 1 T1OSI OSC1 2 3 4 5 6 Clock Transition 7 Q3 Q4 Q1 Q2 Q3 8 CPU Clock Peripheral Clock Program Counter PC DS39605B-page 26 PC + 2 Preliminary PC + 2 2002 Microchip Technology Inc. PIC18F1220/1320 3.4.3 RC_RUN MODE Note: In RC_RUN mode, the CPU and peripherals are clocked from the internal oscillator block using the INTOSC multiplexer, and the primary clock is shutdown. When using the INTRC source, this mode provides the best power conservation of all the RUN modes, while still executing code. It works well for user applications which are not highly timing sensitive, or do not require high speed clocks at all times. Caution should be used when modifying a single IRCF bit. If VDD is less than 3V, it is possible to select a higher clock speed than is supported by the low VDD. Improper device operation may result if the VDD/ FOSC specifications are violated. If the IRCF bits are all clear, the INTOSC output is not enabled and the IOFS bit will remain clear; there will be no indication of the current clock source. The INTRC source is providing the system clocks. If the primary clock source is the internal oscillator block (either of the INTIO1 or INTIO2 oscillators), there are no distinguishable differences between PRI_RUN and RC_RUN modes during execution. However, a clock switch delay will occur during entry to, and exit from RC_RUN mode. Therefore, if the primary clock source is the internal oscillator block, the use of RC_RUN mode is not recommended. If the IRCF bits are changed from all clear (thus, enabling the INTOSC output), the IOFS bit becomes set after the INTOSC output becomes stable. Clocks to the system continue while the INTOSC source stabilizes, in approximately 1 ms. If the IRCF bits were previously at a non-zero value before the SLEEP instruction was executed, and the INTOSC source was already stable, the IOFS bit will remain set. This mode is entered by clearing the IDLEN bit, setting SCS1 (SCS0 is ignored), and executing a SLEEP instruction. The IRCF bits may select the clock frequency before the SLEEP instruction is executed. When the clock source is switched to the INTOSC multiplexer (see Figure 3-10), the primary oscillator is shutdown, and the OSTS bit is cleared. When a wake event occurs, the system continues to be clocked from the INTOSC multiplexer while the primary clock is started. When the primary clock becomes ready, a clock switch to the primary clock occurs (see Figure 3-8). When the clock switch is complete, the IOFS bit is cleared, the OSTS bit is set, and the primary clock is providing the system clock. The IDLEN and SCS bits are not affected by the wake-up. The INTRC source will continue to run if either the WDT or the Fail-Safe Clock Monitor is enabled. The IRCF bits may be modified at any time to immediately change the system clock speed. Executing a SLEEP instruction is not required to select a new clock frequency from the INTOSC multiplexer. FIGURE 3-10: TIMING TRANSITION TO RC_RUN MODE Q4 Q1 Q2 Q3 Q4 Q1 1 INTRC Q2 2 3 4 5 6 7 Q3 Q4 Q1 Q2 Q3 8 Clock Transition OSC1 CPU Clock Peripheral Clock Program Counter PC 2002 Microchip Technology Inc. PC + 2 Preliminary PC + 4 DS39605B-page 27 PIC18F1220/1320 3.4.4 3.5 EXIT TO IDLE MODE An exit from a Power Managed RUN mode to its corresponding IDLE mode is executed by setting the IDLEN bit and executing a SLEEP instruction. The CPU is halted at the beginning of the instruction following the SLEEP instruction. There are no changes to any of the clock source status bits (OSTS, IOFS, or T1RUN). While the CPU is halted, the peripherals continue to be clocked from the previously selected clock source. 3.4.5 An exit from any of the Power Managed modes is triggered by an interrupt, a RESET, or a WDT time-out. This section discusses the triggers that cause exits from Power Managed modes. The clocking subsystem actions are discussed in each of the Power Managed modes (see Sections 3.2 through 3.4). Note: EXIT TO SLEEP MODE An exit from a Power Managed RUN mode to SLEEP mode is executed by clearing the IDLEN and SCS1:SCS0 bits and executing a SLEEP instruction. The code is no different than the method used to invoke SLEEP mode from the normal Operating (Full Power) mode. The primary clock and internal oscillator block are disabled. The INTRC will continue to operate if the WDT is enabled. The Timer1 oscillator will continue to run, if enabled in the T1CON register (Register 12-1). All clock source status bits are cleared (OSTS, IOFS, and T1RUN). DS39605B-page 28 Wake from Power Managed Modes If application code is timing sensitive, it should wait for the OSTS bit to become set before continuing. Use the interval during the low power exit sequence (before OSTS is set) to perform timing insensitive "housekeeping" tasks. Device behavior during Low Power mode exits is summarized in Table 3-3. 3.5.1 EXIT BY INTERRUPT Any of the available interrupt sources can cause the device to exit a Power Managed mode and resume full power operation. To enable this functionality, an interrupt source must be enabled by setting its enable bit in one of the INTCON or PIE registers. The exit sequence is initiated when the corresponding interrupt flag bit is set. On all exits from Lower Power mode by interrupt, code execution branches to the interrupt vector if the GIE/GIEH bit (INTCON<7>) is set. Otherwise, code execution continues or resumes without branching (see Section 9.0, "Interrupts"). Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 TABLE 3-3: Clock in Power Managed Mode ACTIVITY AND EXIT DELAY ON WAKE FROM SLEEP MODE OR ANY IDLE MODE (BY CLOCK SOURCES) Primary System Clock LP, XT, HS Primary System HSPLL Clock (1) (PRI_IDLE mode) EC, RC, INTRC INTOSC(2) LP, XT, HS T1OSC or INTRC(1) HSPLL (2) LP, XT, HS INTOSC(2) SLEEP mode HSPLL -- IOFS OST 5-10 s(5) 1 ms (4) OSTS -- IOFS OST OSTS 5-10 s(5) -- INTOSC(2) None IOFS LP, XT, HS OST HSPLL OST + 2 ms EC, RC, INTRC(1) INTOSC Note 1: 2: 3: 4: 5: 5-10 s(5) OST + 2 ms EC, RC, INTRC(1) Clock Ready Status Bit (OSCCON) OSTS OST + 2 ms EC, RC, INTRC(1) INTOSC Power Managed Mode Exit Delay (2) 5-10 s(5) 1 ms(4) OSTS -- IOFS Activity during Wake from Power Managed Mode Exit by Interrupt CPU and peripherals clocked by primary clock and executing instructions. Exit by RESET Not clocked, or Two-Speed Start-up (if enabled)(3). CPU and peripherals clocked by selected Power Managed mode clock, and executing instructions until primary clock source becomes ready. Not clocked, or Two-Speed Start-up (if enabled) until primary clock source becomes ready(3). In this instance, refers specifically to the INTRC clock source. Includes both the INTOSC 8 MHz source and postscaler derived frequencies. Two-Speed Start-up is covered in greater detail in Section 19.3. Execution continues during the INTOSC stabilization period. Required delay when waking from SLEEP and all IDLE modes. This delay runs concurrently with any other required delays (see Section 3.3). 2002 Microchip Technology Inc. Preliminary DS39605B-page 29 PIC18F1220/1320 3.5.2 EXIT BY RESET 3.5.4 Normally, the device is held in RESET by the Oscillator Start-up Timer (OST) until the primary clock (defined in Configuration Register 1H) becomes ready. At that time, the OSTS bit is set, and the device begins executing code. Code execution can begin before the primary clock becomes ready. If either the Two-Speed Start-up (see Section 19.3), or Fail-Safe Clock Monitor (see Section 19.4) are enabled in Configuration Register 1H, the device may begin execution as soon as the RESET source has cleared. Execution is clocked by the INTOSC multiplexer driven by the internal oscillator block. Since the OSCCON register is cleared following all RESETS, the INTRC clock source is selected. A higher speed clock may be selected by modifying the IRCF bits in the OSCCON register. Execution is clocked by the internal oscillator block until either the primary clock becomes ready, or a Power Managed mode is entered before the primary clock becomes ready; the primary clock is then shutdown. 3.5.3 EXIT BY WDT TIME-OUT A WDT time-out will cause different actions, depending on which Power Managed mode the device is in when the time-out occurs. If the device is not executing code (all IDLE modes and SLEEP mode), the time-out will result in a wake from the Power Managed mode (see Sections 3.2 through 3.4). If the device is executing code (all RUN modes), the time-out will result in a WDT Reset (see Section 19.2, "Watchdog Timer (WDT)"). The WDT timer and postscaler are cleared by executing a SLEEP or CLRWDT instruction, the loss of a currently selected clock source (if the Fail-Safe Clock Monitor is enabled), and modifying the IRCF bits in the OSCCON register if the internal oscillator block is the system clock source. DS39605B-page 30 EXIT WITHOUT AN OSCILLATOR START-UP DELAY Certain exits from Power Managed modes do not invoke the OST at all. These are: * PRI_IDLE mode, where the primary clock source is not stopped; and * the primary clock source is not any of LP, XT, HS or HSPLL modes. In these cases, the primary clock source either does not require an oscillator start-up delay, since it is already running (PRI_IDLE), or normally does not require an oscillator start-up delay (RC, EC, and INTIO Oscillator modes). However, a fixed delay (approximately 10 s) following the wake event is required when leaving SLEEP and IDLE modes. This delay is required for the CPU to prepare for execution. Instruction execution resumes on the first clock cycle following this delay. 3.6 INTOSC Frequency Drift The factory calibrates the internal oscillator block output (INTOSC) for 8 MHz (see Table 22.5). However, this frequency may drift as VDD or temperature changes, which can affect the controller operation in a variety of ways. It is possible to adjust the INTOSC frequency by modifying the value in the OSCTUNE register (Register 2-1). This has the side effect that the INTRC clock source frequency is also affected. However, the features that use the INTRC source often do not require an exact frequency. These features include the Fail-Safe Clock Monitor, the Watchdog Timer, and the RC_RUN/ RC_IDLE modes when the INTRC clock source is selected. Being able to adjust the INTOSC requires knowing when an adjustment is required, in which direction it should be made, and in some cases, how large a change is needed. Three examples are shown below, but other techniques may be used. Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 3.6.1 EXAMPLE - USART 3.6.3 An adjustment may be indicated when the USART begins to generate framing errors, or receives data with errors while in Asynchronous mode. Framing errors indicate that the system clock frequency is too high - try decrementing the value in the OSCTUNE register to reduce the system clock frequency. Errors in data may suggest that the system clock speed is too low - increment OSCTUNE. 3.6.2 EXAMPLE - TIMERS This technique compares system clock speed to some reference clock. Two timers may be used; one timer is clocked by the peripheral clock, while the other is clocked by a fixed reference source, such as the Timer1 oscillator. Both timers are cleared, but the timer clocked by the reference generates interrupts. When an interrupt occurs, the internally clocked timer is read and both timers are cleared. If the internally clocked timer value is greater than expected, then the internal oscillator block is running too fast - decrement OSCTUNE. 2002 Microchip Technology Inc. EXAMPLE - CCP IN CAPTURE MODE A CCP module can use free running Timer1 (or Timer3), clocked by the internal oscillator block and an external event with a known period (i.e., AC power frequency). The time of the first event is captured in the CCPRxH:CCPRxL registers, and is recorded for use later. When the second event causes a capture, the time of the first event is subtracted from the time of the second event. Since the period of the external event is known, the time difference between events can be calculated. If the measured time is much greater than the calculated time, the internal oscillator block is running too fast - decrement OSCTUNE. If the measured time is much less than the calculated time, the internal oscillator block is running too slow - increment OSCTUNE. Preliminary DS39605B-page 31 PIC18F1220/1320 NOTES: DS39605B-page 32 Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 4.0 RESET The PIC18F1220/1320 devices differentiate between various kinds of RESET: a) b) c) d) e) f) g) h) Power-on Reset (POR) MCLR Reset during normal operation MCLR Reset during SLEEP Watchdog Timer (WDT) Reset (during execution) Programmable Brown-out Reset (BOR) RESET Instruction Stack Full Reset Stack Underflow Reset A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 4-1. The Enhanced MCU devices have a MCLR noise filter in the MCLR Reset path. The filter will detect and ignore small pulses. Most registers are unaffected by a RESET. Their status is unknown on POR and unchanged by all other RESETS. The other registers are forced to a "RESET state", depending on the type of RESET that occurred. FIGURE 4-1: Most registers are not affected by a WDT wake-up, since this is viewed as the resumption of normal operation. Status bits from the RCON register (Register 4-1), RI, TO, PD, POR and BOR, are set or cleared differently in different RESET situations, as indicated in Table 4-2. These bits are used in software to determine the nature of the RESET. See Table 4-3 for a full description of the RESET states of all registers. The MCLR pin is not driven low by any internal RESETS, including the WDT. The MCLR input provided by the MCLR pin can be disabled with the MCLRE bit in Configuration Register 3H (CONFIG3H<7>). SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT RESET Instruction Stack Pointer Stack Full/Underflow Reset External Reset MCLR MCLRE ( )_IDLE SLEEP WDT Time-out VDD Rise Detect VDD POR Pulse Brown-out Reset S BOREN OST/PWRT OST 1024 Cycles Chip_Reset 10-bit Ripple Counter R Q OSC1 32 s INTRC(1) PWRT 65.5 ms 11-bit Ripple Counter Enable PWRT Enable OST(2) Note 1: This is a separate oscillator from the RC oscillator of the CLKI pin. 2: See Table 4-1 for time-out situations. 2002 Microchip Technology Inc. Preliminary DS39605B-page 33 PIC18F1220/1320 4.1 Power-on Reset (POR) 4.3 A Power-on Reset pulse is generated on-chip when VDD rise is detected. To take advantage of the POR circuitry, just tie the MCLR pin through a resistor (1k to 10 k) to VDD. This will eliminate external RC components usually needed to create a Power-on Reset delay. A minimum rise rate for VDD is specified (parameter D004). For a slow rise time, see Figure 4-2. When the device starts normal operation (i.e., exits the RESET condition), device operating parameters (voltage, frequency, temperature, etc.) must be met to ensure operation. If these conditions are not met, the device must be held in RESET until the operating conditions are met. FIGURE 4-2: EXTERNAL POWER-ON RESET CIRCUIT (FOR SLOW VDD POWER-UP) D R R1 C MCLR PIC18FXXXX Note 1: External Power-on Reset circuit is required only if the VDD power-up slope is too slow. The diode D helps discharge the capacitor quickly when VDD powers down. 2: R < 40 k is recommended to make sure that the voltage drop across R does not violate the device's electrical specification. 3: R1 1 k will limit any current flowing into MCLR from external capacitor C, in the event of MCLR/VPP pin breakdown due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). 4.2 Power-up Timer (PWRT) The Power-up Timer (PWRT) of the PIC18F1220/1320 is an 11-bit counter, which uses the INTRC source as the clock input. This yields a count of 2048 x 32 s = 65.6 ms. While the PWRT is counting, the device is held in RESET. The power-up time delay will vary from chip-to-chip due to VDD, temperature and process variation. See DC parameter #33 for details. The PWRT is enabled by clearing configuration bit PWRTEN. DS39605B-page 34 The Oscillator Start-up Timer (OST) provides a 1024 oscillator cycle (from OSC1 input) delay after the PWRT delay is over (parameter #33). This ensures that the crystal oscillator or resonator has started and stabilized. The OST time-out is invoked only for XT, LP, HS and HSPLL modes, and only on Power-on Reset, or on exit from most Low Power modes. 4.4 PLL Lock Time-out With the PLL enabled in its PLL mode, the time-out sequence following a Power-on Reset is slightly different from other Oscillator modes. A portion of the Power-up Timer is used to provide a fixed time-out that is sufficient for the PLL to lock to the main oscillator frequency. This PLL lock time-out (TPLL) is typically 2 ms and follows the Oscillator Start-up Time-out (OST). 4.5 VDD VDD Oscillator Start-up Timer (OST) Brown-out Reset (BOR) A configuration bit, BOREN, can disable (if clear/programmed), or enable (if set) the Brown-out Reset circuitry. If VDD falls below VBOR (parameter D005) for greater than TBOR (parameter #35), the brown-out situation will reset the chip. A RESET may not occur if VDD falls below VBOR for less than TBOR. The chip will remain in Brown-out Reset until VDD rises above VBOR. If the Power-up Timer is enabled, it will be invoked after VDD rises above VBOR; it then will keep the chip in RESET for an additional time delay TPWRT (parameter #33). If VDD drops below VBOR while the Power-up Timer is running, the chip will go back into a Brown-out Reset and the Power-up Timer will be initialized. Once VDD rises above VBOR, the Power-up Timer will execute the additional time delay. Enabling BOR Reset does not automatically enable the PWRT. 4.6 Time-out Sequence On power-up, the time-out sequence is as follows: First, after the POR pulse has cleared, PWRT time-out is invoked (if enabled). Then, the OST is activated. The total time-out will vary based on oscillator configuration and the status of the PWRT. For example, in RC mode with the PWRT disabled, there will be no time-out at all. Figure 4-3, Figure 4-4, Figure 4-5, Figure 4-6 and Figure 4-7 depict time-out sequences on power-up. Since the time-outs occur from the POR pulse, if MCLR is kept low long enough, all time-outs will expire. Bringing MCLR high will begin execution immediately (Figure 4-5). This is useful for testing purposes or to synchronize more than one PIC18FXXXX device operating in parallel. Table 4-2 shows the RESET conditions for some Special Function Registers, while Table 4-3 shows the RESET conditions for all the registers. Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 TABLE 4-1: TIME-OUT IN VARIOUS SITUATIONS Power-up(2) and Brown-out Oscillator Configuration PWRTEN = 1 Exit from Low Power Mode 1024 TOSC + 2 ms(2) 1024 TOSC + 2 ms(2) PWRTEN = 0 HSPLL 66 ms (1) + 1024 TOSC + 2 ms (2) HS, XT, LP 66 ms(1) + 1024 TOSC 1024 TOSC 1024 TOSC EC, ECIO 66 ms(1) 5-10 s(3) 5-10 s(3) RC, RCIO 66 ms(1) (3) 5-10 s 5-10 s(3) INTIO1, INTIO2 66 ms(1) 5-10 s(3) 5-10 s(3) Note 1: 66 ms (65.5 ms) is the nominal Power-up Timer (PWRT) delay. 2: 2 ms is the nominal time required for the 4x PLL to lock. 3: The program memory bias start-up time is always invoked on POR, wake-up from SLEEP, or on any exit from Power Managed mode that disables the CPU and instruction execution. REGISTER 4-1: RCON REGISTER BITS AND POSITIONS R/W-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 IPEN -- -- RI TO PD POR BOR bit 7 Note: TABLE 4-2: bit 0 Refer to Section 5.14 (page 58) for bit definitions. STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR RCON REGISTER Program Counter RCON Register RI TO PD POR BOR STKFUL STKUNF Power-on Reset 0000h 0--1 1100 1 1 1 0 0 0 0 RESET Instruction 0000h 0--0 uuuu 0 u u u u u u Brown-out 0000h 0--1 11u- 1 1 1 u 0 u u MCLR during Power Managed RUN modes 0000h 0--u 1uuu u 1 u u u u u MCLR during Power Managed IDLE modes and SLEEP 0000h 0--u 10uu u 1 0 u u u u WDT Time-out during Full Power or Power Managed RUN 0000h 0--u 0uuu u 0 u u u u u u u 1 u u 1 Condition MCLR during Full Power Execution Stack Full Reset (STVREN = 1) 0000h 0--u uuuu u u u u u Stack Underflow RESET (STVREN = 1) Stack Underflow Error (not an actual RESET, STVREN = 0) 0000h u--u uuuu u u u u u u 1 WDT Time-out during Power Managed IDLE or SLEEP PC + 2 u--u 00uu u 0 0 u u u u Interrupt Exit from Power Managed modes PC + 2 u--u u0uu u u 0 u u u u Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0' Note: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the interrupt vector (0x000008h or 0x000018h). 2002 Microchip Technology Inc. Preliminary DS39605B-page 35 PIC18F1220/1320 TABLE 4-3: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets WDT Reset RESET Instruction Stack Resets Wake-up via WDT or Interrupt TOSU 1220 1320 ---0 0000 ---0 0000 ---0 uuuu(3) TOSH 1220 1320 0000 0000 0000 0000 uuuu uuuu(3) TOSL 1220 1320 0000 0000 0000 0000 uuuu uuuu(3) STKPTR 1220 1320 00-0 0000 00-0 0000 uu-u uuuu(3) PCLATU 1220 1320 ---0 0000 ---0 0000 ---u uuuu PCLATH 1220 1320 0000 0000 0000 0000 uuuu uuuu PCL 1220 1320 0000 0000 0000 0000 PC + 2(2) TBLPTRU 1220 1320 --00 0000 --00 0000 --uu uuuu TBLPTRH 1220 1320 0000 0000 0000 0000 uuuu uuuu TBLPTRL 1220 1320 0000 0000 0000 0000 uuuu uuuu TABLAT 1220 1320 0000 0000 0000 0000 uuuu uuuu PRODH 1220 1320 xxxx xxxx uuuu uuuu uuuu uuuu PRODL 1220 1320 xxxx xxxx uuuu uuuu uuuu uuuu INTCON 1220 1320 0000 000x 0000 000u uuuu uuuu(1) INTCON2 1220 1320 1111 -1-1 1111 -1-1 uuuu -u-u(1) INTCON3 1220 1320 11-0 0-00 11-0 0-00 uu-u u-uu(1) INDF0 1220 1320 N/A N/A N/A POSTINC0 1220 1320 N/A N/A N/A POSTDEC0 1220 1320 N/A N/A N/A PREINC0 1220 1320 N/A N/A N/A PLUSW0 1220 1320 N/A N/A N/A FSR0H 1220 1320 ---- 0000 ---- 0000 ---- uuuu FSR0L 1220 1320 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu WREG 1220 1320 xxxx xxxx uuuu uuuu INDF1 1220 1320 N/A N/A N/A POSTINC1 1220 1320 N/A N/A N/A POSTDEC1 1220 1320 N/A N/A N/A PREINC1 1220 1320 N/A N/A N/A PLUSW1 1220 1320 N/A N/A N/A Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table 4-2 for RESET value for specific condition. 5: Bits 6 and 7 of PORTA, LATA, and TRISA are enabled, depending on the Oscillator mode selected. When not enabled as PORTA pins, they are disabled and read `0'. 6: Bit 5 of PORTA is enabled if MCLR is disabled. DS39605B-page 36 Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 TABLE 4-3: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets WDT Reset RESET Instruction Stack Resets Wake-up via WDT or Interrupt FSR1H 1220 1320 ---- 0000 ---- 0000 ---- uuuu FSR1L 1220 1320 xxxx xxxx uuuu uuuu uuuu uuuu BSR 1220 1320 ---- 0000 ---- 0000 ---- uuuu INDF2 1220 1320 N/A N/A N/A POSTINC2 1220 1320 N/A N/A N/A POSTDEC2 1220 1320 N/A N/A N/A PREINC2 1220 1320 N/A N/A N/A PLUSW2 1220 1320 N/A N/A N/A FSR2H 1220 1320 ---- 0000 ---- 0000 ---- uuuu FSR2L 1220 1320 xxxx xxxx uuuu uuuu uuuu uuuu STATUS 1220 1320 ---x xxxx ---u uuuu ---u uuuu TMR0H 1220 1320 0000 0000 0000 0000 uuuu uuuu TMR0L 1220 1320 xxxx xxxx uuuu uuuu uuuu uuuu T0CON 1220 1320 1111 1111 1111 1111 uuuu uuuu OSCCON 1220 1320 0000 q000 0000 00q0 uuuu uuqu LVDCON 1220 1320 --00 0101 --00 0101 --uu uuuu WDTCON 1220 1320 ---- ---0 ---- ---0 ---- ---u RCON(4) 1220 1320 0--1 11q0 0--q qquu u--u qquu TMR1H 1220 1320 xxxx xxxx uuuu uuuu uuuu uuuu TMR1L 1220 1320 xxxx xxxx uuuu uuuu uuuu uuuu T1CON 1220 1320 0000 0000 u0uu uuuu uuuu uuuu TMR2 1220 1320 0000 0000 0000 0000 uuuu uuuu PR2 1220 1320 1111 1111 1111 1111 1111 1111 T2CON 1220 1320 -000 0000 -000 0000 -uuu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table 4-2 for RESET value for specific condition. 5: Bits 6 and 7 of PORTA, LATA, and TRISA are enabled, depending on the Oscillator mode selected. When not enabled as PORTA pins, they are disabled and read `0'. 6: Bit 5 of PORTA is enabled if MCLR is disabled. 2002 Microchip Technology Inc. Preliminary DS39605B-page 37 PIC18F1220/1320 TABLE 4-3: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets WDT Reset RESET Instruction Stack Resets Wake-up via WDT or Interrupt ADRESH 1220 1320 xxxx xxxx uuuu uuuu uuuu uuuu ADRESL 1220 1320 xxxx xxxx uuuu uuuu uuuu uuuu ADCON0 1220 1320 00-0 0000 00-0 0000 uu-u uuuu ADCON1 1220 1320 -000 0000 -000 0000 -uuu uuuu ADCON2 1220 1320 0-00 0000 0-00 0000 u-uu uuuu CCPR1H 1220 1320 xxxx xxxx uuuu uuuu uuuu uuuu CCPR1L 1220 1320 xxxx xxxx uuuu uuuu uuuu uuuu CCP1CON 1220 1320 0000 0000 0000 0000 uuuu uuuu PWM1CON 1220 1320 0000 0000 0000 0000 uuuu uuuu ECCPAS 1220 1320 0000 0000 0000 0000 uuuu uuuu TMR3H 1220 1320 xxxx xxxx uuuu uuuu uuuu uuuu TMR3L 1220 1320 xxxx xxxx uuuu uuuu uuuu uuuu T3CON 1220 1320 0000 0000 uuuu uuuu uuuu uuuu SPBRGH 1220 1320 0000 0000 0000 0000 uuuu uuuu SPBRG 1220 1320 0000 0000 0000 0000 uuuu uuuu RCREG 1220 1320 0000 0000 0000 0000 uuuu uuuu TXREG 1220 1320 0000 0000 0000 0000 uuuu uuuu TXSTA 1220 1320 0000 0010 0000 0010 uuuu uuuu RCSTA 1220 1320 0000 000x 0000 000x uuuu uuuu BAUDCTL 1220 1320 -1-1 0-00 -1-1 0-00 -u-u u-uu EEADR 1220 1320 0000 0000 0000 0000 uuuu uuuu EEDATA 1220 1320 0000 0000 0000 0000 uuuu uuuu EECON1 1220 1320 xx-0 x000 uu-0 u000 uu-0 u000 EECON2 1220 1320 0000 0000 0000 0000 0000 0000 Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table 4-2 for RESET value for specific condition. 5: Bits 6 and 7 of PORTA, LATA, and TRISA are enabled, depending on the Oscillator mode selected. When not enabled as PORTA pins, they are disabled and read `0'. 6: Bit 5 of PORTA is enabled if MCLR is disabled. DS39605B-page 38 Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 TABLE 4-3: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets WDT Reset RESET Instruction Stack Resets Wake-up via WDT or Interrupt IPR2 1220 1320 1--1 -11- 1--1 -11- u--u -uu- PIR2 1220 1320 0--0 -00- 0--0 -00- u--u -uu-(1) PIE2 1220 1320 0--0 -00- 0--0 -00- u--u -uu- IPR1 1220 1320 -111 -111 -111 -111 -uuu -uuu PIR1 1220 1320 -000 -000 -000 -000 -uuu -uuu(1) PIE1 1220 1320 -000 -000 -000 -000 -uuu -uuu OSCTUNE 1220 1320 --00 0000 --00 0000 --uu uuuu TRISB 1220 1320 1111 1111 1111 1111 uuuu uuuu (5) 1111(5) TRISA 1220 1320 11-1 LATB 1220 1320 xxxx xxxx LATA(5) PORTB (5,6) PORTA xxxx(5) 1220 1320 xx-x 1220 1320 xxxx xxxx 1220 1320 xx0x 0000(5,6) 11-1 1111(5) uuuu uuuu uu-u uuuu(5) uuuu uuuu uu0u 0000(5,6) uu-u uuuu(5) uuuu uuuu uu-u uuuu(5) uuuu uuuu uuuu uuuu(5,6) Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table 4-2 for RESET value for specific condition. 5: Bits 6 and 7 of PORTA, LATA, and TRISA are enabled, depending on the Oscillator mode selected. When not enabled as PORTA pins, they are disabled and read `0'. 6: Bit 5 of PORTA is enabled if MCLR is disabled. 2002 Microchip Technology Inc. Preliminary DS39605B-page 39 PIC18F1220/1320 FIGURE 4-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 FIGURE 4-4: VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 FIGURE 4-5: VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET DS39605B-page 40 Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 FIGURE 4-6: SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT) 5V VDD 1V 0V MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET TIME-OUT SEQUENCE ON POR W/ PLL ENABLED (MCLR TIED TO VDD) FIGURE 4-7: VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST TPLL OST TIME-OUT PLL TIME-OUT INTERNAL RESET Note: TOST = 1024 clock cycles. TPLL 2 ms max. First three stages of the PWRT timer. 2002 Microchip Technology Inc. Preliminary DS39605B-page 41 PIC18F1220/1320 NOTES: DS39605B-page 42 Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 5.0 MEMORY ORGANIZATION 5.1 There are three memory types in Enhanced MCU devices. These memory types are: * Program Memory * Data RAM * Data EEPROM Data and program memory use separate busses, which allows for concurrent access of these types. Additional detailed information for FLASH program memory and Data EEPROM is provided in Section 6.0 and Section 7.0, respectively. Program Memory Organization A 21-bit program counter is capable of addressing the 2-Mbyte program memory space. Accessing a location between the physically implemented memory and the 2-Mbyte address will cause a read of all `0's (a NOP instruction). The PIC18F1220 has 4 Kbytes of FLASH memory and can store up to 2,048 single word instructions. The PIC18F1320 has 8 Kbytes of FLASH memory and can store up to 4,096 single word instructions. The RESET vector address is at 0000h and the interrupt vector addresses are at 0008h and 0018h. The Program Memory Maps for the PIC18F1220 and PIC18F1320 devices are shown in Figure 5-1 and Figure 5-2, respectively. PROGRAM MEMORY MAP AND STACK FOR PIC18F1220 FIGURE 5-2: PROGRAM MEMORY MAP AND STACK FOR PIC18F1320 PC<20:0> 21 CALL,RCALL,RETURN RETFIE,RETLW Stack Level 1 PC<20:0> 21 CALL,RCALL,RETURN RETFIE,RETLW Stack Level 1 * * * * * * Stack Level 31 Stack Level 31 RESET Vector RESET Vector 0000h 0000h High Priority Interrupt Vector 0008h High Priority Interrupt Vector 0008h Low Priority Interrupt Vector 0018h Low Priority Interrupt Vector 0018h On-Chip Program Memory On-Chip Program Memory 0FFFh 1000h User Memory Space 1FFFh Read `0' 2000h Read `0' 1FFFFFh 200000h 1FFFFFh 200000h 2002 Microchip Technology Inc. User Memory Space FIGURE 5-1: Preliminary DS39605B-page 43 PIC18F1220/1320 5.2 Return Address Stack 5.2.2 The return address stack allows any combination of up to 31 program calls and interrupts to occur. The PC (Program Counter) is pushed onto the stack when a CALL or RCALL instruction is executed, or an interrupt is Acknowledged. The PC value is pulled off the stack on a RETURN, RETLW or a RETFIE instruction. PCLATU and PCLATH are not affected by any of the RETURN or CALL instructions. The STKPTR register (Register 5-1) contains the stack pointer value, the STKFUL (stack full) status bit, and the STKUNF (stack underflow) status bits. The value of the stack pointer can be 0 through 31. The stack pointer increments before values are pushed onto the stack and decrements after values are popped off the stack. At RESET, the stack pointer value will be zero. The user may read and write the stack pointer value. This feature can be used by a Real-Time Operating System for return stack maintenance. The stack operates as a 31-word by 21-bit RAM and a 5-bit stack pointer, with the stack pointer initialized to 00000B after all RESETS. There is no RAM associated with stack pointer 00000B. This is only a RESET value. During a CALL type instruction, causing a push onto the stack, the stack pointer is first incremented and the RAM location pointed to by the stack pointer is written with the contents of the PC (already pointing to the instruction following the call). During a RETURN type instruction, causing a pop from the stack, the contents of the RAM location pointed to by the STKPTR are transferred to the PC and then the stack pointer is decremented. After the PC is pushed onto the stack 31 times (without popping any values off the stack), the STKFUL bit is set. The STKFUL bit is cleared by software or by a POR. The action that takes place when the stack becomes full depends on the state of the STVREN (Stack Overflow Reset Enable) configuration bit. (Refer to Section 19.1 for a description of the device configuration bits.) If STVREN is set (default), the 31st push will push the (PC + 2) value onto the stack, set the STKFUL bit, and reset the device. The STKFUL bit will remain set and the stack pointer will be set to zero. The stack space is not part of either program or data space. The stack pointer is readable and writable, and the address on the top of the stack is readable and writable through the top-of-stack special file registers. Data can also be pushed to, or popped from, the stack using the top-of-stack SFRs. Status bits indicate if the stack is full, has overflowed or underflowed. 5.2.1 RETURN STACK POINTER (STKPTR) If STVREN is cleared, the STKFUL bit will be set on the 31st push and the stack pointer will increment to 31. Any additional pushes will not overwrite the 31st push, and STKPTR will remain at 31. When the stack has been popped enough times to unload the stack, the next pop will return a value of zero to the PC and sets the STKUNF bit, while the stack pointer remains at zero. The STKUNF bit will remain set until cleared by software or a POR occurs. TOP-OF-STACK ACCESS The top of the stack is readable and writable. Three register locations, TOSU, TOSH and TOSL hold the contents of the stack location pointed to by the STKPTR register (Figure 5-3). This allows users to implement a software stack if necessary. After a CALL, RCALL or interrupt, the software can read the pushed value by reading the TOSU, TOSH and TOSL registers. These values can be placed on a user defined software stack. At return time, the software can replace the TOSU, TOSH and TOSL and do a return. Note: Returning a value of zero to the PC on an underflow has the effect of vectoring the program to the RESET vector, where the stack conditions can be verified and appropriate actions can be taken. This is not the same as a RESET, as the contents of the SFRs are not affected. The user must disable the global interrupt enable bits while accessing the stack to prevent inadvertent stack corruption. FIGURE 5-3: RETURN ADDRESS STACK AND ASSOCIATED REGISTERS Return Address Stack 11111 11110 11101 TOSU 00h TOSH 1Ah TOSL 34h Top-of-Stack DS39605B-page 44 STKPTR<4:0> 00010 00011 001A34h 00010 000D58h 00001 00000 Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 REGISTER 5-1: STKPTR REGISTER R/C-0 R/C-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STKFUL STKUNF -- SP4 SP3 SP2 SP1 SP0 bit 7 bit 0 bit 7(1) STKFUL: Stack Full Flag bit 1 = Stack became full or overflowed 0 = Stack has not become full or overflowed bit 6(1) STKUNF: Stack Underflow Flag bit 1 = Stack underflow occurred 0 = Stack underflow did not occur bit 5 Unimplemented: Read as '0' bit 4-0 SP4:SP0: Stack Pointer Location bits Note 1: Bit 7 and bit 6 are cleared by user software or by a POR. Legend: 5.2.3 R = Readable bit W = Writable bit U = Unimplemented C = Clearable only bit - n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown PUSH AND POP INSTRUCTIONS 5.2.4 Since the Top-of-Stack (TOS) is readable and writable, the ability to push values onto the stack and pull values off the stack, without disturbing normal program execution, is a desirable option. To push the current PC value onto the stack, a PUSH instruction can be executed. This will increment the stack pointer and load the current PC value onto the stack. TOSU, TOSH and TOSL can then be modified to place data or a return address on the stack. STACK FULL/UNDERFLOW RESETS These RESETS are enabled by programming the STVREN bit in Configuration Register 4L. When the STVREN bit is cleared, a full or underflow condition will set the appropriate STKFUL or STKUNF bit, but not cause a device RESET. When the STVREN bit is set, a full or underflow condition will set the appropriate STKFUL or STKUNF bit and then cause a device RESET. The STKFUL or STKUNF bits are cleared by the user software or a POR Reset. The ability to pull the TOS value off of the stack and replace it with the value that was previously pushed onto the stack, without disturbing normal execution, is achieved by using the POP instruction. The POP instruction discards the current TOS by decrementing the stack pointer. The previous value pushed onto the stack then becomes the TOS value. 2002 Microchip Technology Inc. Preliminary DS39605B-page 45 PIC18F1220/1320 5.3 Fast Register Stack 5.4 A "fast return" option is available for interrupts. A Fast Register Stack is provided for the STATUS, WREG and BSR registers and is only one in depth. The stack is not readable or writable and is loaded with the current value of the corresponding register when the processor vectors for an interrupt. The values in the registers are then loaded back into the working registers, if the RETFIE, FAST instruction is used to return from the interrupt. All interrupt sources will push values into the stack registers. If both low and high priority interrupts are enabled, the stack registers cannot be used reliably to return from low priority interrupts. If a high priority interrupt occurs while servicing a low priority interrupt, the stack register values stored by the low priority interrupt will be overwritten. Users must save the key registers in software during a low priority interrupt. If interrupt priority is not used, all interrupts may use the Fast Register Stack for returns from interrupt. If no interrupts are used, the Fast Register Stack can be used to restore the STATUS, WREG and BSR registers at the end of a subroutine call. To use the Fast Register Stack for a subroutine call, a CALL LABEL, FAST instruction must be executed to save the STATUS, WREG, and BSR registers to the Fast Register Stack. A RETURN, FAST instruction is then executed to restore these registers from the Fast Register Stack. PCL, PCLATH and PCLATU The program counter (PC) specifies the address of the instruction to fetch for execution. The PC is 21-bits wide. The low byte, known as the PCL register, is both readable and writable. The high byte, or PCH register, contains the PC<15:8> bits and is not directly readable or writable. Updates to the PCH register may be performed through the PCLATH register. The upper byte is called PCU. This register contains the PC<20:16> bits and is not directly readable or writable. Updates to the PCU register may be performed through the PCLATU register. The contents of PCLATH and PCLATU will be transferred to the program counter by any operation that writes PCL. Similarly, the upper two bytes of the program counter will be transferred to PCLATH and PCLATU by an operation that reads PCL. This is useful for computed offsets to the PC (see Section 5.8.1). The PC addresses bytes in the program memory. To prevent the PC from becoming misaligned with word instructions, the LSB of PCL is fixed to a value of `0'. The PC increments by 2 to address sequential instructions in the program memory. The CALL, RCALL, GOTO and program branch instructions write to the program counter directly. For these instructions, the contents of PCLATH and PCLATU are not transferred to the program counter. Example 5-1 shows a source code example that uses the Fast Register Stack during a subroutine call and return. EXAMPLE 5-1: CALL SUB1, FAST * * * * RETURN FAST FAST REGISTER STACK CODE EXAMPLE ;STATUS, WREG, BSR ;SAVED IN FAST REGISTER ;STACK SUB1 DS39605B-page 46 ;RESTORE VALUES SAVED ;IN FAST REGISTER STACK Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 5.5 Clocking Scheme/Instruction Cycle 5.6 Instruction Flow/Pipelining An "Instruction Cycle" consists of four Q cycles (Q1, Q2, Q3 and Q4). The instruction fetch and execute are pipelined such that fetch takes one instruction cycle, while decode and execute takes another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g., GOTO), then two cycles are required to complete the instruction (Example 5-2). The clock input (from OSC1) is internally divided by four to generate four non-overlapping quadrature clocks, namely Q1, Q2, Q3 and Q4. Internally, the program counter (PC) is incremented every Q1, the instruction is fetched from the program memory and latched into the instruction register in Q4. The instruction is decoded and executed during the following Q1 through Q4. The clocks and instruction execution flow are shown in Figure 5-4. A fetch cycle begins with the program counter (PC) incrementing in Q1. In the execution cycle, the fetched instruction is latched into the "Instruction Register" (IR) in cycle Q1. This instruction is then decoded and executed during the Q2, Q3, and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write). FIGURE 5-4: CLOCK/INSTRUCTION CYCLE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Q1 Q2 Internal Phase Clock Q3 Q4 PC OSC2/CLKO (RC Mode) EXAMPLE 5-2: PC Execute INST (PC-2) Fetch INST (PC) Execute INST (PC) Fetch INST (PC+2) TCY0 TCY1 Fetch 1 Execute 1 2. MOVWF PORTB 4. BSF PC+4 Execute INST (PC+2) Fetch INST (PC+4) INSTRUCTION PIPELINE FLOW 1. MOVLW 55h 3. BRA PC+2 SUB_1 Fetch 2 TCY2 TCY3 TCY4 TCY5 Execute 2 Fetch 3 Execute 3 Fetch 4 PORTA, BIT3 (Forced NOP) Flush (NOP) Fetch SUB_1 Execute SUB_1 5. Instruction @ address SUB_1 All instructions are single cycle, except for any program branches. These take two cycles, since the fetch instruction is "flushed" from the pipeline, while the new instruction is being fetched and then executed. 2002 Microchip Technology Inc. Preliminary DS39605B-page 47 PIC18F1220/1320 5.7 Instructions in Program Memory The program memory is addressed in bytes. Instructions are stored as two bytes or four bytes in program memory. The Least Significant Byte of an instruction word is always stored in a program memory location with an even address (LSB = 0). Figure 5-5 shows an example of how instruction words are stored in the program memory. To maintain alignment with instruction boundaries, the PC increments in steps of 2 and the LSB will always read '0' (see Section 5.4). FIGURE 5-5: INSTRUCTIONS IN PROGRAM MEMORY Program Memory Byte Locations 5.7.1 The CALL and GOTO instructions have the absolute program memory address embedded into the instruction. Since instructions are always stored on word boundaries, the data contained in the instruction is a word address. The word address is written to PC<20:1>, which accesses the desired byte address in program memory. Instruction #2 in Figure 5-5 shows how the instruction "GOTO 000006h' is encoded in the program memory. Program branch instructions, which encode a relative address offset, operate in the same manner. The offset value stored in a branch instruction represents the number of single word instructions that the PC will be offset by. Section 20.0 provides further details of the instruction set. Instruction 1: Instruction 2: MOVLW GOTO 055h 000006h Instruction 3: MOVFF 123h, 456h TWO-WORD INSTRUCTIONS PIC18F1220/1320 devices have four two-word instructions: MOVFF, CALL, GOTO and LFSR. The second word of these instructions has the 4 MSBs set to `1's and is decoded as a NOP instruction. The lower 12 bits of the second word contain data to be used by the instruction. If the first word of the instruction is executed, the data in the second word is accessed. If the EXAMPLE 5-3: LSB = 1 LSB = 0 0Fh EFh F0h C1h F4h 55h 03h 00h 23h 56h Word Address 000000h 000002h 000004h 000006h 000008h 00000Ah 00000Ch 00000Eh 000010h 000012h 000014h second word of the instruction is executed by itself (first word was skipped), it will execute as a NOP. This action is necessary when the two-word instruction is preceded by a conditional instruction that results in a skip operation. A program example that demonstrates this concept is shown in Example 5-3. Refer to Section 20.0 for further details of the instruction set. TWO-WORD INSTRUCTIONS CASE 1: Object Code Source Code 0110 0110 0000 0000 TSTFSZ REG1 1100 0001 0010 0011 MOVFF REG1, REG2 ; No, skip this word ADDWF REG3 1111 0100 0101 0110 0010 0100 0000 0000 ; is RAM location 0? ; Execute this word as a NOP ; continue code CASE 2: Object Code Source Code 0110 0110 0000 0000 TSTFSZ REG1 1100 0001 0010 0011 MOVFF REG1, REG2 ; Yes, execute this word 1111 0100 0101 0110 0010 0100 0000 0000 DS39605B-page 48 ; is RAM location 0? ; 2nd word of instruction ADDWF REG3 ; continue code Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 5.8 Lookup Tables 5.9 Lookup tables are implemented two ways: The data memory is implemented as static RAM. Each register in the data memory has a 12-bit address, allowing up to 4096 bytes of data memory. Figure 5-6 shows the data memory organization for the PIC18F1220/1320 devices. * Computed GOTO * Table Reads 5.8.1 COMPUTED GOTO A computed GOTO is accomplished by adding an offset to the program counter. An example is shown in Example 5-4. A lookup table can be formed with an ADDWF PCL instruction and a group of RETLW 0xnn instructions. WREG is loaded with an offset into the table before executing a call to that table. The first instruction of the called routine is the ADDWF PCL instruction. The next instruction executed will be one of the RETLW 0xnn instructions, that returns the value 0xnn to the calling function. The offset value (in WREG) specifies the number of bytes that the program counter should advance, and should be multiples of 2 (LSB = 0). In this method, only one data byte may be stored in each instruction location and room on the return address stack is required. EXAMPLE 5-4: ORG TABLE 5.8.2 MOVFW CALL 0xnn00 ADDWF RETLW RETLW RETLW . . . COMPUTED GOTO USING AN OFFSET VALUE OFFSET TABLE The data memory map is divided into as many as 16 banks that contain 256 bytes each. The lower 4 bits of the Bank Select Register (BSR<3:0>) select which bank will be accessed. The upper 4 bits for the BSR are not implemented. The data memory contains Special Function Registers (SFR) and General Purpose Registers (GPR). The SFRs are used for control and status of the controller and peripheral functions, while GPRs are used for data storage and scratch pad operations in the user's application. The SFRs start at the last location of Bank 15 (FFFh) and extend towards F80h. Any remaining space beyond the SFRs in the Bank may be implemented as GPRs. GPRs start at the first location of Bank 0 and grow upwards. Any read of an unimplemented location will read as `0's. The entire data memory may be accessed directly or indirectly. Direct addressing may require the use of the BSR register. Indirect addressing requires the use of a File Select Register (FSRn) and a corresponding Indirect File Operand (INDFn). Each FSR holds a 12-bit address value that can be used to access any location in the Data Memory map without banking. See Example 5.12 for indirect addressing details. The instruction set and architecture allow operations across all banks. This may be accomplished by indirect addressing or by the use of the MOVFF instruction. The MOVFF instruction is a two-word/two-cycle instruction that moves a value from one register to another. PCL 0xnn 0xnn 0xnn TABLE READS/TABLE WRITES A better method of storing data in program memory allows two bytes of data to be stored in each instruction location. Lookup table data may be stored two bytes per program word by using table reads and writes. The table pointer (TBLPTR) specifies the byte address and the table latch (TABLAT) contains the data that is read from, or written to program memory. Data is transferred to/from program memory, one byte at a time. The Table Read/Table Write operation is discussed further in Section 6.1. 2002 Microchip Technology Inc. Data Memory Organization To ensure that commonly used registers (SFRs and select GPRs) can be accessed in a single cycle, regardless of the current BSR values, an Access Bank is implemented. A segment of Bank 0 and a segment of Bank 15 comprise the Access RAM. Section 5.10 provides a detailed description of the Access RAM. 5.9.1 GENERAL PURPOSE REGISTER FILE Enhanced MCU devices may have banked memory in the GPR area. GPRs are not initialized by a Power-on Reset and are unchanged on all other RESETS. Data RAM is available for use as GPR registers by all instructions. The second half of Bank 15 (F80h to FFFh) contains SFRs. All other banks of data memory contain GPRs, starting with Bank 0. Preliminary DS39605B-page 49 PIC18F1220/1320 FIGURE 5-6: DATA MEMORY MAP FOR PIC18F1220/1320 DEVICES BSR<3:0> = 0000 Data Memory Map 00h Access RAM FFh GPR Bank 0 000h 07Fh 080h 0FFh Access Bank Access RAM low = 0001 = 1110 Bank 1 to Bank 14 00h 7Fh Access RAM high 80h (SFRs) FFh Unused Read '00h' When a = 0, The BSR is ignored and the Access Bank is used. = 1111 00h Unused FFh SFR Bank 15 EFFh F00h F7Fh F80h FFFh The first 128 bytes are General Purpose RAM (from Bank 0). The second 128 bytes are Special Function Registers (from Bank 15). When a = 1, The BSR specifies the Bank used by the instruction. DS39605B-page 50 Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 5.9.2 SPECIAL FUNCTION REGISTERS The Special Function Registers (SFRs) are registers used by the CPU and Peripheral Modules for controlling the desired operation of the device. These registers are implemented as static RAM. A list of these registers is given in Table 5-1 and Table 5-2. The SFRs can be classified into two sets: those associated with the "core" function and those related to the peripheral functions. Those registers related to the "core" are described in this section, while those related to the operation of the peripheral features are described in the section of that peripheral feature. The SFRs are typically distributed among the peripherals whose functions they control. The unused SFR locations will be unimplemented and read as `0's. TABLE 5-1: Address SPECIAL FUNCTION REGISTER MAP FOR PIC18F1220/1320 DEVICES Name Address Name FFFh TOSU FDFh INDF2(2) FFEh TOSH FDEh POSTINC2(2) FFDh TOSL FDDh POSTDEC2(2) FFCh STKPTR Address Name Address Name FBFh CCPR1H F9Fh IPR1 FBEh CCPR1L F9Eh PIR1 FBDh CCP1CON F9Dh PIE1 FDCh PREINC2(2) FBCh -- F9Ch -- FFBh PCLATU FDBh PLUSW2(2) FBBh -- F9Bh OSCTUNE FFAh PCLATH FDAh FSR2H FBAh -- F9Ah -- FF9h PCL FD9h FSR2L FB9h -- F99h -- FF8h TBLPTRU FD8h STATUS FB8h -- F98h -- FF7h TBLPTRH FD7h TMR0H FB7h PWM1CON F97h -- FF6h TBLPTRL FD6h TMR0L FB6h ECCPAS F96h -- FF5h TABLAT FD5h T0CON FB5h -- F95h -- FF4h PRODH FD4h -- FB4h -- F94h -- FF3h PRODL FD3h OSCCON FB3h TMR3H F93h TRISB FF2h INTCON FD2h LVDCON FB2h TMR3L F92h TRISA FF1h INTCON2 FD1h WDTCON FB1h T3CON F91h -- FF0h INTCON3 FD0h RCON FB0h SPBRGH F90h -- FEFh FEEh INDF0 (2) POSTINC0(2) FEDh POSTDEC0(2) FCFh TMR1H FAFh SPBRG F8Fh -- FCEh TMR1L FAEh RCREG F8Eh -- FCDh T1CON FADh TXREG F8Dh -- FCCh TMR2 FACh TXSTA F8Ch -- FECh PREINC0(2) FEBh PLUSW0(2) FCBh PR2 FABh RCSTA F8Bh -- FEAh FSR0H FCAh T2CON FAAh BAUDCTL F8Ah LATB FE9h FSR0L FC9h -- FA9h EEADR F89h LATA FE8h WREG FC8h -- FA8h EEDATA F88h -- FC7h -- FA7h EECON2 F87h -- FC6h -- FA6h EECON1 F86h -- FC5h -- FA5h -- F85h -- FC4h ADRESH FA4h -- F84h -- FE7h FE6h INDF1 (2) POSTINC1(2) (2) FE5h POSTDEC1 FE4h PREINC1(2) FE3h PLUSW1(2) FC3h ADRESL FA3h -- F83h -- FE2h FSR1H FC2h ADCON0 FA2h IPR2 F82h -- FE1h FSR1L FC1h ADCON1 FA1h PIR2 F81h PORTB FE0h BSR FC0h ADCON2 FA0h PIE2 F80h PORTA Note 1: Unimplemented registers are read as `0'. 2: This is not a physical register. 2002 Microchip Technology Inc. Preliminary DS39605B-page 51 PIC18F1220/1320 TABLE 5-2: File Name REGISTER FILE SUMMARY (PIC18F1220/1320) Bit 7 Bit 6 Bit 5 -- -- -- Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Details on page: ---0 0000 36, 44 TOSH Top-of-Stack High Byte (TOS<15:8>) 0000 0000 36, 44 TOSL Top-of-Stack Low Byte (TOS<7:0>) 0000 0000 36, 44 Return Stack Pointer 00-0 0000 36, 45 Holding Register for PC<20:16> TOSU STKPTR STKFUL STKUNF -- PCLATU -- -- bit21(3) Top-of-Stack Upper Byte (TOS<20:16>) Value on POR, BOR ---0 0000 36, 46 PCLATH Holding Register for PC<15:8> 0000 0000 36, 46 PCL PC Low Byte (PC<7:0>) 0000 0000 36, 46 --00 0000 36, 62 TBLPTRU -- -- bit21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 0000 0000 36, 62 TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 0000 0000 36, 62 TABLAT Program Memory Table Latch 0000 0000 36, 62 PRODH Product Register High Byte xxxx xxxx 36, 73 PRODL Product Register Low Byte xxxx xxxx 36, 73 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0E RBIE TMR0IF INT0F RBIF 0000 000x 36, 77 INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 -- TMR0IP -- RBIP 1111 -1-1 36, 78 INT2P INT1P -- INT2E INT1E -- INT2F INT1F INTCON3 11-0 0-00 36, 79 INDF0 Uses contents of FSR0 to address data memory - value of FSR0 not changed (not a physical register) n/a 36, 55 POSTINC0 Uses contents of FSR0 to address data memory - value of FSR0 post-incremented (not a physical register) n/a 36, 55 POSTDEC0 Uses contents of FSR0 to address data memory - value of FSR0 post-decremented (not a physical register) n/a 36, 55 PREINC0 Uses contents of FSR0 to address data memory - value of FSR0 pre-incremented (not a physical register) n/a 36, 55 PLUSW0 Uses contents of FSR0 to address data memory - value of FSR0 offset by W (not a physical register) n/a 36, 55 ---- 0000 36, 55 36, 55 FSR0H -- -- -- -- Indirect Data Memory Address Pointer 0 High FSR0L Indirect Data Memory Address Pointer 0 Low Byte xxxx xxxx WREG Working Register xxxx xxxx 36 INDF1 Uses contents of FSR1 to address data memory - value of FSR1 not changed (not a physical register) n/a 36, 55 POSTINC1 Uses contents of FSR1 to address data memory - value of FSR1 post-incremented (not a physical register) n/a 36, 55 POSTDEC1 Uses contents of FSR1 to address data memory - value of FSR1 post-decremented (not a physical register) n/a 36, 55 PREINC1 Uses contents of FSR1 to address data memory - value of FSR1 pre-incremented (not a physical register) n/a 36, 55 PLUSW1 Uses contents of FSR1 to address data memory - value of FSR1 offset by W (not a physical register) n/a 36, 55 Indirect Data Memory Address Pointer 1 High ---- 0000 37, 55 xxxx xxxx 37, 55 Bank Select Register ---- 0000 37, 54 FSR1H -- FSR1L -- -- -- Indirect Data Memory Address Pointer 1 Low Byte BSR -- -- -- -- INDF2 Uses contents of FSR2 to address data memory - value of FSR2 not changed (not a physical register) n/a 37, 55 POSTINC2 Uses contents of FSR2 to address data memory - value of FSR2 post-incremented (not a physical register) n/a 37, 55 POSTDEC2 Uses contents of FSR2 to address data memory - value of FSR2 post-decremented (not a physical register) n/a 37, 55 PREINC2 Uses contents of FSR2 to address data memory - value of FSR2 pre-incremented (not a physical register) n/a 37, 55 PLUSW2 Uses contents of FSR2 to address data memory - value of FSR2 offset by W (not a physical register) n/a 37, 55 ---- 0000 37, 55 FSR2H FSR2L STATUS -- -- -- -- Indirect Data Memory Address Pointer 2 High Indirect Data Memory Address Pointer 2 Low Byte -- -- -- N OV Z DC C xxxx xxxx 37, 55 ---x xxxx 37, 57 TMR0H Timer0 Register High Byte 0000 0000 37, 103 TMR0L Timer0 Register Low Byte xxxx xxxx 37, 103 37, 101 TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111 OSCCON T0CON IDLEN IRCF2 IRCF1 IRCF0 OSTS FLTS SCS1 SCS0 0000 q000 37, 17 LVDCON -- -- IVRST LVDEN LVDL3 LVDL2 LVDL1 LVDL0 --00 0101 37, 167 -- -- -- -- -- -- -- SWDTEN --- ---0 37, 180 IPEN -- -- RI TO PD POR BOR 0--1 11q0 35, 58, 86 WDTCON RCON Legend: Note 1: 2: 3: 4: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition RA6 and associated bits are configured as port pins in RCIO, ECIO, and INTIO2 (with port function on RA6) Oscillator mode only, and read `0' in all other Oscillator modes. RA7 and associated bits are configured as port pins in INTIO2 Oscillator mode only, and read `0' in all other modes. Bit 21 of the PC is only available in Test mode and Serial Programming modes. The RA5 port bit is only available when MCLRE fuse (CONFIG3H<7>) is programmed to `0'. Otherwise, RA5 reads `0'. This bit is read only. DS39605B-page 52 Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 TABLE 5-2: File Name REGISTER FILE SUMMARY (PIC18F1220/1320) (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Details on page: 37, 109 TMR1H Timer1 Register High Byte xxxx xxxx TMR1L Timer1 Register Low Byte xxxx xxxx 37, 109 0000 0000 37, 105 37, 111 T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON TMR2 Timer2 Register 0000 0000 PR2 Timer2 Period Register 1111 1111 37, 111 -000 0000 37, 111 38, 164 T2CON -- TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 ADRESH A/D Result Register High Byte xxxx xxxx ADRESL A/D Result Register Low Byte xxxx xxxx 38, 164 00-0 0000 38, 155 ADCON0 VCFG1 VCFG0 -- CHS2 CHS1 CHS0 GO/DONE ADON ADCON1 -- PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 --00 0000 38, 156 ADCON2 ADFM -- ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 0-00 0000 38, 157 CCPR1H Capture/Compare/PWM Register1 High Byte xxxx xxxx 38. 118 CCPR1L Capture/Compare/PWM Register1 Low Byte xxxx xxxx 38, 118 CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 38, 117 PWM1CON PRSEN PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 0000 0000 38, 128 ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 ECCPAS 0000 0000 38, 129 TMR3H Timer3 Register High Byte xxxx xxxx 38, 116 TMR3L Timer3 Register Low Byte xxxx xxxx 38, 116 0000 0000 38, 113 T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON SPBRGH USART Baud Rate Generator High Byte 0000 0000 38 SPBRG USART Baud Rate Generator Low Byte 0000 0000 38, 137 RCREG USART Receive Register 0000 0000 38, 145, 144 TXREG USART Transmit Register 0000 0000 38, 142, 144 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 38, 134 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 38, 135 -- RCIDL -- SCKP BRG16 -- W4E ABDEN -1-1 0-00 38 EEPROM Address Register 0000 0000 38, 69 EEDATA EEPROM Data Register 0000 0000 38, 72 EECON2 EEPROM Control Register2 (not a physical register) 0000 0000 38, 60, 69 BAUDCTL EEADR EECON1 EEPGD CFGS -- FREE WRERR WREN WR RD xx-0 x000 38, 61, 70 IPR2 OSCFIP -- -- EEIP -- LVDIP TMR3IP -- 1--1 -11- 39, 85 PIR2 OSCFIF -- -- EEIF -- LVDIF TMR3IF -- 0--0 -00- 39, 81 PIE2 OSCFIE -- -- EEIE -- LVDIE TMR3IE -- 0--0 -00- 39, 83 IPR1 -- ADIP RCIP TXIP -- CCP1IP TMR2IP TMR1IP -111 -111 39, 84 PIR1 -- ADIF RCIF TXIF -- CCP1IF TMR2IF TMR1IF -000 -000 39, 80 PIE1 -- ADIE RCIE TXIE -- CCP1IE TMR2IE TMR1IE -000 -000 39, 82 OSCTUNE -- -- TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 --00 0000 39, 15 1111 1111 39, 100 TRISB Data Direction Control Register for PORTB TRISA7(2) TRISA LATB TRISA6(1) -- Data Direction Control Register for PORTA Read/Write PORTB Data Latch LATA LATA<7>(2) LATA<6>(1) PORTB Read PORTB pins, Write PORTB Data Latch PORTA Legend: Note 1: 2: 3: 4: RA7(2) RA6(1) -- RA5(4) Read/Write PORTA Data Latch Read PORTA pins, Write PORTA Data Latch 11-1 1111 39, 91 xxxx xxxx 39, 100 xx-x xxxx 39, 91 xxxx xxxx 39, 100 xx0x 0000 39, 91 x = unknown, u = unchanged, - = unimplemented, q = value depends on condition RA6 and associated bits are configured as port pins in RCIO, ECIO, and INTIO2 (with port function on RA6) Oscillator mode only, and read `0' in all other Oscillator modes. RA7 and associated bits are configured as port pins in INTIO2 Oscillator mode only, and read `0' in all other modes. Bit 21 of the PC is only available in Test mode and Serial Programming modes. The RA5 port bit is only available when MCLRE fuse (CONFIG3H<7>) is programmed to `0'. Otherwise, RA5 reads `0'. This bit is read only. 2002 Microchip Technology Inc. Preliminary DS39605B-page 53 PIC18F1220/1320 5.10 Access Bank 5.11 The Access Bank is an architectural enhancement which is very useful for C compiler code optimization. The techniques used by the C compiler may also be useful for programs written in assembly. The need for a large general purpose memory space dictates a RAM banking scheme. The data memory is partitioned into as many as sixteen banks. When using direct addressing, the BSR should be configured for the desired bank. This data memory region can be used for: * * * * * BSR<3:0> holds the upper 4 bits of the 12-bit RAM address. The BSR<7:4> bits will always read `0's, and writes will have no effect (see Figure 5-7). Intermediate computational values Local variables of subroutines Faster context saving/switching of variables Common variables Faster evaluation/control of SFRs (no banking) A MOVLB instruction has been provided in the instruction set to assist in selecting banks. If the currently selected bank is not implemented, any read will return all '0's and all writes are ignored. The STATUS register bits will be set/cleared as appropriate for the instruction performed. The Access Bank is comprised of the last 128 bytes in Bank 15 (SFRs) and the first 128 bytes in Bank 0. These two sections will be referred to as Access RAM High and Access RAM Low, respectively. Figure 5-6 indicates the Access RAM areas. Each Bank extends up to FFh (256 bytes). All data memory is implemented as static RAM. A bit in the instruction word specifies if the operation is to occur in the bank specified by the BSR register or in the Access Bank. This bit is denoted as the `a' bit (for access bit). A MOVFF instruction ignores the BSR, since the 12-bit addresses are embedded into the instruction word. Section 5.12 provides a description of indirect addressing, which allows linear addressing of the entire RAM space. When forced in the Access Bank (a = 0), the last address in Access RAM Low is followed by the first address in Access RAM High. Access RAM High maps the Special Function registers, so these registers can be accessed without any software overhead. This is useful for testing status flags and modifying control bits. FIGURE 5-7: Bank Select Register (BSR) DIRECT ADDRESSING Direct Addressing BSR<7:4> 0 0 0 BSR<3:0> 7 From Opcode(3) 0 0 Bank Select(2) Location Select(3) 00h 01h 0Eh 0Fh 000h 100h E00h F00h 0FFh 1FFh EFFh FFFh Bank 14 Bank 15 Data Memory(1) Bank 0 Bank 1 Note 1: For register file map detail, see Table 5-1. 2: The access bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the registers of the Access Bank. 3: The MOVFF instruction embeds the entire 12-bit address in the instruction. DS39605B-page 54 Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 5.12 Indirect Addressing, INDF and FSR Registers Indirect addressing is a mode of addressing data memory, where the data memory address in the instruction is not fixed. An FSR register is used as a pointer to the data memory location that is to be read or written. Since this pointer is in RAM, the contents can be modified by the program. This can be useful for data tables in the data memory and for software stacks. Figure 5-8 shows how the fetched instruction is modified prior to being executed. Indirect addressing is possible by using one of the INDF registers. Any instruction, using the INDF register, actually accesses the register pointed to by the File Select Register, FSR. Reading the INDF register itself, indirectly (FSR = 0), will read 00h. Writing to the INDF register indirectly, results in a no operation. The FSR register contains a 12-bit address, which is shown in Figure 5-9. The INDFn register is not a physical register. Addressing INDFn actually addresses the register whose address is contained in the FSRn register (FSRn is a pointer). This is indirect addressing. Example 5-5 shows a simple use of indirect addressing to clear the RAM in Bank1 (locations 100h-1FFh) in a minimum number of instructions. EXAMPLE 5-5: HOW TO CLEAR RAM (BANK1) USING INDIRECT ADDRESSING FSR0 ,0x100 ; POSTINC0 ; Clear INDF ; register then ; inc pointer BTFSS FSR0H, 1 ; All done with ; Bank1? GOTO NEXT ; NO, clear next CONTINUE ; YES, continue NEXT LFSR CLRF There are three indirect addressing registers. To address the entire data memory space (4096 bytes), these registers are 12-bit wide. To store the 12 bits of addressing information, two 8-bit registers are required: 1. 2. 3. FSR0: composed of FSR0H:FSR0L FSR1: composed of FSR1H:FSR1L FSR2: composed of FSR2H:FSR2L In addition, there are registers INDF0, INDF1 and INDF2, which are not physically implemented. Reading or writing to these registers activates indirect addressing, with the value in the corresponding FSR register being the address of the data. If an instruction writes a value to INDF0, the value will be written to the address pointed to by FSR0H:FSR0L. A read from INDF1 reads the data from the address pointed to by FSR1H:FSR1L. INDFn can be used in code anywhere an operand can be used. 2002 Microchip Technology Inc. If INDF0, INDF1 or INDF2 are read indirectly via an FSR, all `0's are read (zero bit is set). Similarly, if INDF0, INDF1 or INDF2 are written to indirectly, the operation will be equivalent to a NOP instruction and the STATUS bits are not affected. 5.12.1 INDIRECT ADDRESSING OPERATION Each FSR register has an INDF register associated with it, plus four additional register addresses. Performing an operation using one of these five registers determines how the FSR will be modified during indirect addressing. When data access is performed using one of the five INDFn locations, the address selected will configure the FSRn register to: * Do nothing to FSRn after an indirect access (no change) - INDFn * Auto-decrement FSRn after an indirect access (post-decrement) - POSTDECn * Auto-increment FSRn after an indirect access (post-increment) - POSTINCn * Auto-increment FSRn before an indirect access (pre-increment) - PREINCn * Use the value in the WREG register as an offset to FSRn. Do not modify the value of the WREG or the FSRn register after an indirect access (no change) - PLUSWn When using the auto-increment or auto-decrement features, the effect on the FSR is not reflected in the STATUS register. For example, if the indirect address causes the FSR to equal `0', the Z bit will not be set. Auto-incrementing or auto-decrementing an FSR affects all 12 bits. That is, when FSRnL overflows from an increment, FSRnH will be incremented automatically. Adding these features allows the FSRn to be used as a stack pointer, in addition to its uses for table operations in data memory. Each FSR has an address associated with it that performs an indexed indirect access. When a data access to this INDFn location (PLUSWn) occurs, the FSRn is configured to add the signed value in the WREG register and the value in FSR to form the address before an indirect access. The FSR value is not changed. The WREG offset range is -128 to +127. If an FSR register contains a value that points to one of the INDFn, an indirect read will read 00h (zero bit is set), while an indirect write will be equivalent to a NOP (STATUS bits are not affected). If an indirect addressing write is performed when the target address is an FSRnH or FSRnL register, the data is written to the FSR register, but no pre- or post-increment/decrement is performed. Preliminary DS39605B-page 55 PIC18F1220/1320 FIGURE 5-8: INDIRECT ADDRESSING OPERATION RAM 0h Instruction Executed Opcode Address FFFh 12 File Address = Access of an Indirect Addressing Register BSR<3:0> Instruction Fetched 4 Opcode FIGURE 5-9: 12 12 8 File FSR INDIRECT ADDRESSING Indirect Addressing FSRnH:FSRnL 3 0 7 0 11 0 Location Select 0000h Data Memory(1) 0FFFh Note 1: For register file map detail, see Table 5-1. DS39605B-page 56 Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 5.13 STATUS Register The STATUS register, shown in Register 5-2, contains the arithmetic status of the ALU. The STATUS register can be the operand for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC, C, OV, or N bits, then the write to these five bits is disabled. These bits are set or cleared according to the device logic. Therefore, the result of an instruction with the STATUS register as destination may be different than intended. REGISTER 5-2: For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged). It is recommended, therefore, that only BCF, BSF, SWAPF, MOVFF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect the Z, C, DC, OV, or N bits in the STATUS register. For other instructions not affecting any status bits, see Table 20-2. Note: The C and DC bits operate as a borrow and digit borrow bit respectively, in subtraction. STATUS REGISTER U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x -- -- -- N OV Z DC C bit 7 bit 0 bit 7-5 Unimplemented: Read as '0' bit 4 N: Negative bit This bit is used for signed arithmetic (2's complement). It indicates whether the result was negative (ALU MSB = 1). 1 = Result was negative 0 = Result was positive bit 3 OV: Overflow bit This bit is used for signed arithmetic (2's complement). It indicates an overflow of the 7-bit magnitude, which causes the sign bit (bit 7) to change state. 1 = Overflow occurred for signed arithmetic (in this arithmetic operation) 0 = No overflow occurred bit 2 Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1 DC: Digit carry/borrow bit For ADDWF, ADDLW, SUBLW, and SUBWF instructions 1 = A carry-out from the 4th low order bit of the result occurred 0 = No carry-out from the 4th low order bit of the result Note: bit 0 For borrow, the polarity is reversed. A subtraction is executed by adding the two's complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the bit 4 or bit 3 of the source register. C: Carry/borrow bit For ADDWF, ADDLW, SUBLW, AND SUBWF instructions 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note: For borrow, the polarity is reversed. A subtraction is executed by adding the two's complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the source register. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR `1' = Bit is set `0' = Bit is cleared 2002 Microchip Technology Inc. Preliminary x = Bit is unknown DS39605B-page 57 PIC18F1220/1320 5.14 RCON Register Note 1: If the BOREN configuration bit is set (Brown-out Reset enabled), the BOR bit is `1' on a Power-on Reset. After a Brown-out Reset has occurred, the BOR bit will be cleared, and must be set by firmware to indicate the occurrence of the next Brown-out Reset. The Reset Control (RCON) register contains flag bits that allow differentiation between the sources of a device RESET. These flags include the TO, PD, POR, BOR and RI bits. This register is readable and writable. 2: It is recommended that the POR bit be set after a Power-on Reset has been detected, so that subsequent Power-on Resets may be detected. REGISTER 5-3: RCON REGISTER R/W-0 U-0 U-0 R/W-1 R-1 R-1 R/W-0 R/W-0 IPEN -- -- RI TO PD POR BOR bit 7 bit 0 bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) bit 6-5 Unimplemented: Read as '0' bit 4 RI: RESET Instruction Flag bit 1 = The RESET instruction was not executed (set by firmware only) 0 = The RESET instruction was executed causing a device RESET (must be set in software after a Brown-out Reset occurs) bit 3 TO: Watchdog Time-out Flag bit 1 = Set by power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred bit 2 PD: Power-down Detection Flag bit 1 = Set by power-up or by the CLRWDT instruction 0 = Cleared by execution of the SLEEP instruction bit 1 POR: Power-on Reset Status bit 1 = A Power-on Reset has not occurred (set by firmware only) 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit 1 = A Brown-out Reset has not occurred (set by firmware only) 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) Legend: DS39605B-page 58 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR `1' = Bit is set `0' = Bit is cleared Preliminary x = Bit is unknown 2002 Microchip Technology Inc. PIC18F1220/1320 6.0 FLASH PROGRAM MEMORY The program memory space is 16-bits wide, while the data RAM space is 8-bits wide. Table Reads and Table Writes move data between these two memory spaces through an 8-bit register (TABLAT). The FLASH Program Memory is readable, writable, and erasable during normal operation over the entire VDD range. Table Read operations retrieve data from program memory and place it into TABLAT in the data RAM space. Figure 6-1 shows the operation of a Table Read with program memory and data RAM. A read from program memory is executed on one byte at a time. A write to program memory is executed on blocks of 8 bytes at a time. Program memory is erased in blocks of 64 bytes at a time. A bulk erase operation may not be issued from user code. Table Write operations store data from TABLAT in the data memory space into holding registers in program memory. The procedure to write the contents of the holding registers into program memory is detailed in Section 6.5, "Writing to FLASH Program Memory". Figure 6-2 shows the operation of a Table Write with program memory and data RAM. While writing or erasing program memory, instruction fetches cease until the operation is complete. The program memory cannot be accessed during the write or erase, therefore, code cannot execute. An internal programming timer terminates program memory writes and erases. Table operations work with byte entities. A table block containing data, rather than program instructions, is not required to be word aligned. Therefore, a table block can start and end at any byte address. If a Table Write is being used to write executable code into program memory, program instructions will need to be word aligned (TBLPTRL<0> = 0). A value written to program memory does not need to be a valid instruction. Executing a program memory location that forms an invalid instruction results in a NOP. 6.1 Table Reads and Table Writes In order to read and write program memory, there are two operations that allow the processor to move bytes between the program memory space and the data RAM: The EEPROM on-chip timer controls the write and erase times. The write and erase voltages are generated by an on-chip charge pump rated to operate over the voltage range of the device for byte or word operations. * Table Read (TBLRD) * Table Write (TBLWT) FIGURE 6-1: TABLE READ OPERATION Instruction: TBLRD* Program Memory Table Pointer(1) TBLPTRU TBLPTRH Table Latch (8-bit) TBLPTRL TABLAT Program Memory (TBLPTR) Note 1: Table Pointer points to a byte in program memory. 2002 Microchip Technology Inc. Preliminary DS39605B-page 59 PIC18F1220/1320 FIGURE 6-2: TABLE WRITE OPERATION Instruction: TBLWT* Program Memory Holding Registers Table Pointer(1) TBLPTRU TBLPTRH Table Latch (8-bit) TBLPTRL TABLAT Program Memory (TBLPTR) Note 1: Table Pointer actually points to one of eight holding registers, the address of which is determined by TBLPTRL<2:0>. The process for physically writing data to the Program Memory Array is discussed in Section 6.5. 6.2 Control Registers Several control registers are used in conjunction with the TBLRD and TBLWT instructions. These include the: * * * * EECON1 register EECON2 register TABLAT register TBLPTR registers 6.2.1 EECON1 AND EECON2 REGISTERS EECON1 is the control register for memory accesses. EECON2 is not a physical register. Reading EECON2 will read all `0's. The EECON2 register is used exclusively in the memory write and erase sequences. Control bit EEPGD determines if the access will be to program or data EEPROM memory. When clear, operations will access the data EEPROM memory. When set, program memory is accessed. Control bit CFGS determines if the access will be to the configuration registers, or to program memory/data EEPROM memory. When set, subsequent operations access configuration registers. When CFGS is clear, the EEPGD bit selects either program FLASH or Data EEPROM memory. The FREE bit controls program memory erase operations. When the FREE bit is set, the erase operation is initiated on the next WR command. When FREE is clear, only writes are enabled. DS39605B-page 60 The WREN bit enables and disables erase and write operations. When set, erase and write operations are allowed. When clear, erase and write operations are disabled - the WR bit cannot be set while the WREN bit is clear. This process helps to prevent accidental writes to memory due to errant (unexpected) code execution. Firmware should keep the WREN bit clear at all times, except when starting erase or write operations. Once firmware has set the WR bit, the WREN bit may be cleared. Clearing the WREN bit will not affect the operation in progress. The WRERR bit is set when a write operation is interrupted by a RESET. In these situations, the user can check the WRERR bit and rewrite the location. It will be necessary to reload the data and address registers (EEDATA and EEADR) as these registers have cleared as a result of the RESET. Control bits RD and WR start read and erase/write operations, respectively. These bits are set by firmware, and cleared by hardware at the completion of the operation. The RD bit cannot be set when accessing program memory (EEPGD = 1). Program memory is read using Table Read instructions. See Section 6.3 regarding Table Reads. Note: Preliminary Interrupt flag bit EEIF, in the PIR2 register, is set when the write is complete. It must be cleared in software. 2002 Microchip Technology Inc. PIC18F1220/1320 REGISTER 6-1: EECON1 REGISTER R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0 EEPGD CFGS -- FREE WRERR WREN WR RD bit 7 bit 0 bit 7 EEPGD: FLASH Program or Data EEPROM Memory Select bit 1 = Access program FLASH memory 0 = Access data EEPROM memory bit 6 CFGS: FLASH Program/Data EE or Configuration Select bit 1 = Access configuration registers 0 = Access program FLASH or data EEPROM memory bit 5 Unimplemented: Read as '0' bit 4 FREE: FLASH Row Erase Enable bit 1 = Erase the program memory row addressed by TBLPTR on the next WR command (cleared by completion of erase operation -- TBLPTR<5:0> are ignored) 0 = Perform write only bit 3 WRERR: EEPROM Error Flag bit 1 = A write operation was prematurely terminated (any RESET during self-timed programming) 0 = The write operation completed normally Note: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error condition. bit 2 WREN: Write Enable bit 1 = Allows erase or write cycles 0 = Inhibits erase or write cycles bit 1 WR: Write Control bit 1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle. (The operation is self-timed and the bit is cleared by hardware once write is complete. The WR bit can only be set (not cleared) in software.) 0 = Write cycle completed bit 0 RD: Read Control bit 1 = Initiates a memory read (Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared) in software. RD bit cannot be set when EEPGD = 1.) 0 = Read completed Legend: R = Readable bit S = Settable only U = Unimplemented bit, read as `0' W = Writable bit - n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown 2002 Microchip Technology Inc. Preliminary DS39605B-page 61 PIC18F1220/1320 6.2.2 TABLAT - TABLE LATCH REGISTER 6.2.4 The Table Latch (TABLAT) is an 8-bit register mapped into the SFR space. The Table Latch is used to hold 8-bit data during data transfers between program memory and data RAM. 6.2.3 TBLPTR is used in reads, writes, and erases of the FLASH program memory. When a TBLRD is executed, all 22 bits of the Table Pointer determine which byte is read from program or configuration memory into TABLAT. TBLPTR - TABLE POINTER REGISTER When a TBLWT is executed, the three LSbs of the Table Pointer (TBLPTR<2:0>) determine which of the eight program memory holding registers is written to. When the timed write to program memory (long write) begins, the 19 MSbs of the Table Pointer, TBLPTR (TBLPTR<21:3>), will determine which program memory block of 8 bytes is written to (TBLPTR<2:0> are ignored). For more detail, see Section 6.5 ("Writing to FLASH Program Memory"). The Table Pointer (TBLPTR) addresses a byte within the program memory. The TBLPTR is comprised of three SFR registers: Table Pointer Upper Byte, Table Pointer High Byte and Table Pointer Low Byte (TBLPTRU:TBLPTRH:TBLPTRL). These three registers join to form a 22-bit wide pointer. The low order 21 bits allow the device to address up to 2 Mbytes of program memory space. Setting the 22nd bit allows access to the Device ID, the User ID and the Configuration bits. When an erase of program memory is executed, the 16 MSbs of the Table Pointer (TBLPTR<21:6>) point to the 64-byte block that will be erased. The Least Significant bits (TBLPTR<5:0>) are ignored. The Table Pointer, TBLPTR, is used by the TBLRD and TBLWT instructions. These instructions can update the TBLPTR in one of four ways, based on the table operation. These operations are shown in Table 6-1. These operations on the TBLPTR only affect the low order 21 bits. TABLE 6-1: TABLE POINTER BOUNDARIES Figure 6-3 describes the relevant boundaries of TBLPTR based on FLASH program memory operations. TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS Example Operation on Table Pointer TBLRD* TBLWT* TBLRD*+ TBLWT*+ TBLRD*TBLWT*TBLRD+* TBLWT+* TBLPTR is not modified FIGURE 6-3: 21 TBLPTR is incremented after the read/write TBLPTR is decremented after the read/write TBLPTR is incremented before the read/write TABLE POINTER BOUNDARIES BASED ON OPERATION TBLPTRU 16 15 TBLPTRH 8 7 TBLPTRL 0 ERASE - TBLPTR<21:6> LONG WRITE - TBLPTR<21:3> READ or WRITE - TBLPTR<21:0> DS39605B-page 62 Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 6.3 Reading the FLASH Program Memory The TBLRD instruction is used to retrieve data from program memory and place into data RAM. Table Reads from program memory are performed one byte at a time. The internal program memory is typically organized by words. The Least Significant bit of the address selects between the high and low bytes of the word. Figure 6-4 shows the interface between the internal program memory and the TABLAT. TBLPTR points to a byte address in program space. Executing a TBLRD instruction places the byte pointed to into TABLAT. In addition, TBLPTR can be modified automatically for the next Table Read operation. FIGURE 6-4: READS FROM FLASH PROGRAM MEMORY Program Memory Odd (High) Byte Even (Low) Byte TBLPTR LSB = 0 TBLPTR LSB = 1 Instruction Register (IR) EXAMPLE 6-1: TABLAT Read Register READING A FLASH PROGRAM MEMORY WORD MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL ; Load TBLPTR with the base ; address of the word READ_WORD TBLRD*+ MOVFW MOVWF TBLRD*+ MOVFW MOVWF TABLAT WORD_EVEN TABLAT WORD_ODD 2002 Microchip Technology Inc. ; read into TABLAT and increment TBLPTR ; get data ; read into TABLAT and increment TBLPTR ; get data Preliminary DS39605B-page 63 PIC18F1220/1320 6.4 Erasing FLASH Program Memory 6.4.1 The minimum erase block size is 32 words or 64 bytes under firmware control. Only through the use of an external programmer, or through ICSP control, can larger blocks of program memory be bulk erased. Word erase in FLASH memory is not supported. FLASH PROGRAM MEMORY ERASE SEQUENCE The sequence of events for erasing a block of internal program memory location is: 1. When initiating an erase sequence from the microcontroller itself, a block of 64 bytes of program memory is erased. The Most Significant 16 bits of the TBLPTR<21:6> point to the block being erased. TBLPTR<5:0> are ignored. 2. The EECON1 register commands the erase operation. The EEPGD bit must be set to point to the FLASH program memory. The CFGS bit must be clear to access program FLASH and data EEPROM memory. The WREN bit must be set to enable write operations. The FREE bit is set to select an erase operation. The WR bit is set as part of the required instruction sequence (as shown in Example 6-2), and starts the actual erase operation. It is not necessary to load the TABLAT register with any data as it is ignored. 3. 4. 5. 6. 7. 8. 9. For protection, the write initiate sequence using EECON2 must be used. Load table pointer with address of row being erased. Set the EECON1 register for the erase operation: * set EEPGD bit to point to program memory; * clear the CFGS bit to access program memory; * set WREN bit to enable writes; * set FREE bit to enable the erase. Disable interrupts. Write 55h to EECON2. Write AAh to EECON2. Set the WR bit. This will begin the row erase cycle. The CPU will stall for duration of the erase (about 2 ms using internal timer). Execute a NOP. Re-enable interrupts. A long write is necessary for erasing the internal FLASH. Instruction execution is halted while in a long write cycle. The long write will be terminated by the internal programming timer. EXAMPLE 6-2: ERASING A FLASH PROGRAM MEMORY ROW MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL ; load TBLPTR with the base ; address of the memory block BSF BSF BSF BCF MOVLW MOVWF MOVLW MOVWF BSF NOP BSF EECON1,EEPGD EECON1,WREN EECON1,FREE INTCON,GIE 55h EECON2 AAh EECON2 EECON1,WR ; ; ; ; INTCON,GIE ; re-enable interrupts ERASE_ROW Required Sequence DS39605B-page 64 point to FLASH program memory enable write to memory enable Row Erase operation disable interrupts ; write 55H ; write AAH ; start erase (CPU stall) Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 6.5 Writing to FLASH Program Memory The programming block size is 4 words or 8 bytes. Word or byte programming is not supported. Table Writes are used internally to load the holding registers needed to program the FLASH memory. There are 8 holding registers used by the Table Writes for programming. FIGURE 6-5: Since the Table Latch (TABLAT) is only a single byte, the TBLWT instruction has to be executed 8 times for each programming operation. All of the Table Write operations will essentially be short writes, because only the holding registers are written. At the end of updating 8 registers, the EECON1 register must be written to, to start the programming operation with a long write. The long write is necessary for programming the internal FLASH. Instruction execution is halted while in a long write cycle. The long write will be terminated by the internal programming timer. TABLE WRITES TO FLASH PROGRAM MEMORY TABLAT Write Register 8 8 TBLPTR = xxxxx0 8 TBLPTR = xxxxx2 TBLPTR = xxxxx1 Holding Register Holding Register Holding Register 8 TBLPTR = xxxxx7 Holding Register Program Memory 6.5.1 FLASH PROGRAM MEMORY WRITE SEQUENCE The sequence of events for programming an internal program memory location should be: 1. 2. 3. 4. 5. 6. 7. Read 64 bytes into RAM. Update data values in RAM as necessary. Load Table Pointer with address being erased. Do the row erase procedure (see Section 6.4.1). Load Table Pointer with address of first byte being written. Write the first 8 bytes into the holding registers with auto-increment. Set the EECON1 register for the write operation: * set EEPGD bit to point to program memory; * clear the CFGS bit to access program memory; * set WREN bit to enable byte writes. 2002 Microchip Technology Inc. 8. 9. 10. 11. 12. 13. 14. 15. 16. Disable interrupts. Write 55h to EECON2. Write AAh to EECON2. Set the WR bit. This will begin the write cycle. The CPU will stall for duration of the write (about 2 ms using internal timer). Execute a NOP. Re-enable interrupts. Repeat steps 6-14 seven times, to write 64 bytes. Verify the memory (Table Read). This procedure will require about 18 ms to update one row of 64 bytes of memory. An example of the required code is given in Example 6-3. Preliminary DS39605B-page 65 PIC18F1220/1320 EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF D'64 COUNTER BUFFER_ADDR_HIGH FSR0H BUFFER_ADDR_LOW FSR0L CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL TBLRD*+ MOVF MOVWF DECFSZ GOTO TABLAT, W POSTINC0 COUNTER READ_BLOCK MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF DATA_ADDR_HIGH FSR0H DATA_ADDR_LOW FSR0L NEW_DATA_LOW POSTINC0 NEW_DATA_HIGH INDF0 ; number of bytes in erase block ; point to buffer ; Load TBLPTR with the base ; address of the memory block ; 6 LSB = 0 READ_BLOCK ; ; ; ; ; read into TABLAT, and inc get data store data and increment FSR0 done? repeat MODIFY_WORD ; point to buffer ; update buffer word and increment FSR0 ; update buffer word ERASE_BLOCK MOVLW CODE_ADDR_UPPER MOVWF TBLPTRU MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL BCF EECON1,CFGS BSF EECON1,EEPGD BSF EECON1,WREN BSF EECON1,FREE BCF INTCON,GIE MOVLW 55h MOVWF EECON2 MOVLW AAh MOVWF EECON2 BSF EECON1,WR NOP BSF INTCON,GIE WRITE_BUFFER_BACK MOVLW 8 MOVWF COUNTER_HI MOVLW BUFFER_ADDR_HIGH MOVWF FSR0H MOVLW BUFFER_ADDR_LOW MOVWF FSR0L PROGRAM_LOOP MOVLW 8 MOVWF COUNTER WRITE_WORD_TO_HREGS MOVF POSTINC0, W MOVWF TABLAT TBLWT+* DECFSZ COUNTER GOTO WRITE_WORD_TO_HREGS DS39605B-page 66 ; load TBLPTR with the base ; address of the memory block ; 6 LSB = 0 ; ; ; ; ; ; ; point to PROG/EEPROM memory point to FLASH program memory enable write to memory enable Row Erase operation disable interrupts Required sequence write 55H ; write AAH ; start erase (CPU stall) ; re-enable interrupts ; number of write buffer groups of 8 bytes ; point to buffer ; number of bytes in holding register ; ; ; ; get low byte of buffer data and increment FSR0 present data to table latch short write to internal TBLWT holding register, increment TBLPTR ; loop until buffers are full Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY (CONTINUED) PROGRAM_MEMORY BCF INTCON,GIE MOVLW 55h MOVWF EECON2 MOVLW AAh MOVWF EECON2 BSF EECON1,WR NOP BSF INTCON,GIE DECFSZ COUNTER_HI GOTO PROGRAM_LOOP BCF EECON1,WREN 6.5.2 ; disable interrupts ; required sequence ; write 55H ; write AAH ; start program (CPU stall) ; re-enable interrupts ; loop until done ; disable write to memory 6.6 WRITE VERIFY Depending on the application, good programming practice may dictate that the value written to the memory should be verified against the original value. This should be used in applications where excessive writes can stress bits near the specification limit. 6.5.3 FLASH Program Operation During Code Protection See "Special Features of the CPU" (Section 19.0) for details on code protection of FLASH program memory. UNEXPECTED TERMINATION OF WRITE OPERATION If a write is terminated by an unplanned event, such as loss of power or an unexpected RESET, the memory location just programmed should be verified and reprogrammed if needed.The WRERR bit is set when a write operation is interrupted by a MCLR Reset, or a WDT Time-out Reset during normal operation. In these situations, users can check the WRERR bit and rewrite the location. TABLE 6-2: Name TBLPTRU REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY Bit 7 Bit 6 Bit 5 -- -- bit21 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) Value on: POR, BOR Value on all other RESETS --00 0000 --00 0000 TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 0000 0000 0000 0000 TBLPTRL Program Memory Table Pointer High Byte (TBLPTR<7:0>) 0000 0000 0000 0000 TABLAT Program Memory Table Latch INTCON GIE/GIEH PEIE/GIEL TMR0IE EECON2 EEPROM Control Register2 (not a physical register) 0000 0000 0000 0000 INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u -- -- EECON1 EEPGD CFGS -- FREE WRERR WREN WR RD xx-0 x000 uu-0 u000 IPR2 OSCFIP -- -- EEIP -- LVDIP TMR3IP -- 1--1 1111 1--1 1111 PIR2 OSCFIF -- -- EEIF -- LVDIF TMR3IF -- 0--0 0000 0--0 0000 PIE2 OSCFIE -- -- EEIE -- LVDIE TMR3IE -- 0--0 0000 0--0 0000 Legend: x = unknown, u = unchanged, r = reserved, - = unimplemented, read as '0'. Shaded cells are not used during FLASH/EEPROM access. 2002 Microchip Technology Inc. Preliminary DS39605B-page 67 PIC18F1220/1320 NOTES: DS39605B-page 68 Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 7.0 DATA EEPROM MEMORY The Data EEPROM is readable and writable during normal operation over the entire VDD range. The data memory is not directly mapped in the register file space. Instead, it is indirectly addressed through the Special Function Registers (SFR). There are four SFRs used to read and write the program and data EEPROM memory. These registers are: * * * * EECON1 EECON2 EEDATA EEADR The EEPROM data memory allows byte read and write. When interfacing to the data memory block, EEDATA holds the 8-bit data for read/write and EEADR holds the address of the EEPROM location being accessed. These devices have 256 bytes of data EEPROM with an address range from 00h to FFh. The EEPROM data memory is rated for high erase/write cycle endurance. A byte write automatically erases the location and writes the new data (erase-before-write). The write time is controlled by an on-chip timer. The write time will vary with voltage and temperature, as well as from chip to chip. Please refer to parameter D122 (Table 22-1 in the "Electrical Characteristics" section) for exact limits. 7.1 EEADR The address register can address 256 bytes of data EEPROM. 7.2 EECON1 and EECON2 Registers Control bit CFGS determines if the access will be to the configuration registers or to program memory/data EEPROM memory. When set, subsequent operations access configuration registers. When CFGS is clear, the EEPGD bit selects either program FLASH, or Data EEPROM memory. The WREN bit enables and disables erase and write operations. When set, erase and write operations are allowed. When clear, erase and write operations are disabled - the WR bit cannot be set while the WREN bit is clear. This mechanism helps to prevent accidental writes to memory due to errant (unexpected) code execution. Firmware should keep the WREN bit clear at all times, except when starting erase or write operations. Once firmware has set the WR bit, the WREN bit may be cleared. Clearing the WREN bit will not affect the operation in progress. The WRERR bit is set when a write operation is interrupted by a RESET. In these situations, the user can check the WRERR bit and rewrite the location. It is necessary to reload the data and address registers (EEDATA and EEADR), as these registers have cleared as a result of the RESET. Control bits, RD and WR, start read and erase/write operations, respectively. These bits are set by firmware, and cleared by hardware at the completion of the operation. The RD bit cannot be set when accessing program memory (EEPGD = 1). Program memory is read using Table Read instructions. See Section 6.1 regarding Table Reads. Note: EECON1 is the control register for memory accesses. EECON2 is not a physical register. Reading EECON2 will read all `0's. The EECON2 register is used exclusively in the memory write and erase sequences. Interrupt flag bit, EEIF in the PIR2 register, is set when write is complete. It must be cleared in software. Control bit EEPGD determines if the access will be to program or data EEPROM memory. When clear, operations will access the data EEPROM memory. When set, program memory is accessed. 2002 Microchip Technology Inc. Preliminary DS39605B-page 69 PIC18F1220/1320 REGISTER 7-1: EECON1 REGISTER R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0 EEPGD CFGS -- FREE WRERR WREN WR RD bit 7 bit 0 bit 7 EEPGD: FLASH Program or Data EEPROM Memory Select bit 1 = Access program FLASH memory 0 = Access data EEPROM memory bit 6 CFGS: FLASH Program/Data EE or Configuration Select bit 1 = Access configuration or calibration registers 0 = Access program FLASH or data EEPROM memory bit 5 Unimplemented: Read as `0' bit 4 FREE: FLASH Row Erase Enable bit 1 = Erase the program memory row addressed by TBLPTR on the next WR command (cleared by completion of erase operation) 0 = Perform write only bit 3 WRERR: EEPROM Error Flag bit 1 = A write operation was prematurely terminated (MCLR or WDT Reset during self-timed erase or program operation) 0 = The write operation completed normally Note: When a WRERR occurs, the EEPGD or FREE bits are not cleared. This allows tracing of the error condition. bit 2 WREN: Erase/Write Enable bit 1 = Allows erase/write cycles 0 = Inhibits erase/write cycles bit 1 WR: Write Control bit 1 = Initiates a data EEPROM erase/write cycle, or a program memory erase cycle, or write cycle. (The operation is self-timed and the bit is cleared by hardware once write is complete. The WR bit can only be set (not cleared) in software.) 0 = Write cycle is completed bit 0 RD: Read Control bit 1 = Initiates a memory read (Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared) in software. RD bit cannot be set when EEPGD = 1.) 0 = Read completed Legend: R = Readable bit S = Settable only U = Unimplemented bit, read as `0' W = Writable bit - n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown DS39605B-page 70 Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 7.3 Reading the Data EEPROM Memory To read a data memory location, the user must write the address to the EEADR register, clear the EEPGD control bit (EECON1<7>) and then set control bit RD (EECON1<0>). The data is available for the very next instruction cycle; therefore, the EEDATA register can be read by the next instruction. EEDATA will hold this value until another read operation, or until it is written to by the user (during a write operation). 7.4 To write an EEPROM data location, the address must first be written to the EEADR register and the data written to the EEDATA register. The sequence in Example 7-2 must be followed to initiate the write cycle. The write will not begin if this sequence is not exactly followed (write 55h to EECON2, write AAh to EECON2, then set WR bit) for each byte. It is strongly recommended that interrupts be disabled during this code segment. Additionally, the WREN bit in EECON1 must be set to enable writes. This mechanism prevents accidental writes to data EEPROM due to unexpected code execution (i.e., runaway programs). The WREN bit should be kept clear at all times, except when updating the EEPROM. The WREN bit is not cleared by hardware. MOVLW MOVWF BCF BSF MOVF Write Verify Depending on the application, good programming practice may dictate that the value written to the memory should be verified against the original value. This should be used in applications where excessive writes can stress bits near the specification limit. 7.6 Protection Against Spurious Write There are conditions when the device may not want to write to the data EEPROM memory. To protect against spurious EEPROM writes, various mechanisms have been built-in. On power-up, the WREN bit is cleared. Also, the Power-up Timer (72 ms duration) prevents EEPROM write. The write initiate sequence and the WREN bit together help prevent an accidental write during brown-out, power glitch, or software malfunction. DATA EEPROM READ DATA_EE_ADDR EEADR EECON1, EEPGD EECON1, RD EEDATA, W EXAMPLE 7-2: Required Sequence At the completion of the write cycle, the WR bit is cleared in hardware and the EEPROM Interrupt Flag bit (EEIF) is set. The user may either enable this interrupt, or poll this bit. EEIF must be cleared by software. 7.5 Writing to the Data EEPROM Memory EXAMPLE 7-1: After a write sequence has been initiated, EECON1, EEADR and EEDATA cannot be modified. The WR bit will be inhibited from being set unless the WREN bit is set. The WREN bit must be set on a previous instruction. Both WR and WREN cannot be set with the same instruction. ; ; ; ; ; Data Memory Address to read Point to DATA memory EEPROM Read W = EEDATA DATA EEPROM WRITE MOVLW MOVWF MOVLW MOVWF BCF BSF BCF MOVLW MOVWF MOVLW MOVWF BSF BSF DATA_EE_ADDR EEADR DATA_EE_DATA EEDATA EECON1, EEPGD EECON1, WREN INTCON, GIE 55h EECON2 AAh EECON2 EECON1, WR INTCON, GIE ; ; ; ; ; ; ; ; ; ; ; ; ; SLEEP BCF EECON1, WREN ; Wait for interrupt to signal write complete ; Disable writes 2002 Microchip Technology Inc. Data Memory Address to write Data Memory Value to write Point to DATA memory Enable writes Disable Interrupts Write 55h Write AAh Set WR bit to begin write Enable Interrupts Preliminary DS39605B-page 71 PIC18F1220/1320 7.7 Operation During Code Protect 7.8 Data EEPROM memory has its own code protect bits in configuration words. External Read and Write operations are disabled if either of these mechanisms are enabled. Using the Data EEPROM The Data EEPROM is a high endurance, byte addressable array that has been optimized for the storage of frequently changing information (e.g., program variables or other data that are updated often). Frequently changing values will typically be updated more often than specification D124 or D124A. If this is not the case, an array refresh must be performed. For this reason, variables that change infrequently (such as constants, IDs, calibration, etc.) should be stored in FLASH program memory. The microcontroller itself can both read and write to the internal Data EEPROM, regardless of the state of the code protect configuration bit. Refer to "Special Features of the CPU" (Section 19.0) for additional information. A simple data EEPROM refresh routine is shown in Example 7-3. Note: EXAMPLE 7-3: DATA EEPROM REFRESH ROUTINE clrf bcf bcf bcf bsf EEADR EECON1,CFGS EECON1,EEPGD INTCON,GIE EECON1,WREN bsf movlw movwf movlw movwf bsf btfsc bra incfsz bra EECON1,RD 55h EECON2 AAh EECON2 EECON1,WR EECON1,WR $-2 EEADR,F Loop bcf bsf EECON1,WREN INTCON,GIE ; ; ; ; ; ; ; ; ; ; ; ; ; Loop TABLE 7-1: Name INTCON If data EEPROM is only used to store constants and/or data that changes rarely, an array refresh is likely not required. See specification D124 or D124A. Start at address 0 Set for memory Set for Data EEPROM Disable interrupts Enable writes Loop to refresh array Read current address Write 55h Write AAh Set WR bit to begin write Wait for write to complete ; Increment address ; Not zero, do it again ; Disable writes ; Enable interrupts REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY Value on all other RESETS Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR GIE/GIEH PEIE/GIEL TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u EEADR EEPROM Address Register 0000 0000 0000 0000 EEDATA EEPROM Data Register 0000 0000 0000 0000 EECON2 EEPROM Control Register2 (not a physical register) -- -- EECON1 EEPGD CFGS -- FREE WRERR WREN WR RD xx-0 x000 uu-0 u000 1--1 1111 1--1 1111 IPR2 OSCFIP -- -- EEIP BCLIP LVDIP TMR3IP CCP2IP PIR2 OSCFIF -- -- EEIF BCLIF LVDIF TMR3IF CCP2IF 0--0 0000 0--0 0000 PIE2 OSCFIE -- -- EEIE BCLIE LVDIE TMR3IE CCP2IE 0--0 0000 0--0 0000 Legend: x = unknown, u = unchanged, r = reserved, - = unimplemented, read as '0'. Shaded cells are not used during FLASH/EEPROM access. DS39605B-page 72 Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 8.0 8 X 8 HARDWARE MULTIPLIER Making the 8 x 8 multiplier execute in a single cycle gives the following advantages: 8.1 Introduction * Higher computational throughput * Reduces code size requirements for multiply algorithms An 8 x 8 hardware multiplier is included in the ALU of the PIC18F1220/1320 devices. By making the multiply a hardware operation, it completes in a single instruction cycle. This is an unsigned multiply that gives a 16-bit result. The result is stored into the 16-bit product register pair (PRODH:PRODL). The multiplier does not affect any flags in the STATUS register. TABLE 8-1: Table 8-1 shows a performance comparison between enhanced devices using the single cycle hardware multiply, and performing the same function without the hardware multiply. PERFORMANCE COMPARISON Routine 8 x 8 unsigned 8 x 8 signed 16 x 16 unsigned 16 x 16 signed 8.2 The performance increase allows the device to be used in applications previously reserved for Digital Signal Processors. Multiply Method Program Memory (Words) Cycles (Max) @ 40 MHz @ 10 MHz @ 4 MHz Without hardware multiply 13 69 6.9 s 27.6 s 69 s Time Hardware multiply 1 1 100 ns 400 ns 1 s Without hardware multiply 33 91 9.1 s 36.4 s 91 s Hardware multiply 6 6 600 ns 2.4 s 6 s Without hardware multiply 21 242 24.2 s 96.8 s 242 s Hardware multiply 24 24 2.4 s 9.6 s 24 s Without hardware multiply 52 254 25.4 s 102.6 s 254 s Hardware multiply 36 36 3.6 s 14.4 s 36 s Operation EXAMPLE 8-1: Example 8-1 shows the sequence to do an 8 x 8 unsigned multiply. Only one instruction is required when one argument of the multiply is already loaded in the WREG register. Example 8-2 shows the sequence to do an 8 x 8 signed multiply. To account for the sign bits of the arguments, each argument's Most Significant bit (MSb) is tested and the appropriate subtractions are done. 2002 Microchip Technology Inc. MOVF MULWF ARG1, W ARG2 EXAMPLE 8-2: MOVF MULWF ARG1, W ARG2 BTFSC SUBWF ARG2, SB PRODH, F MOVF BTFSC SUBWF ARG2, W ARG1, SB PRODH, F Preliminary 8 x 8 UNSIGNED MULTIPLY ROUTINE ; ; ARG1 * ARG2 -> ; PRODH:PRODL 8 x 8 SIGNED MULTIPLY ROUTINE ; ; ; ; ; ARG1 * ARG2 -> PRODH:PRODL Test Sign Bit PRODH = PRODH - ARG1 ; Test Sign Bit ; PRODH = PRODH ; - ARG2 DS39605B-page 73 PIC18F1220/1320 Example 8-3 shows the sequence to do a 16 x 16 unsigned multiply. Equation 8-1 shows the algorithm that is used. The 32-bit result is stored in four registers, RES3:RES0. EQUATION 8-1: 16 x 16 UNSIGNED MULTIPLICATION ALGORITHM RES3:RES0 = ARG1H:ARG1L * ARG2H:ARG2L = (ARG1H * ARG2H * 216)+ (ARG1H * ARG2L * 28) + (ARG1L * ARG2H * 28) + (ARG1L * ARG2L) EXAMPLE 8-3: MOVF MULWF EQUATION 8-2: RES3:RES0 = ARG1H:ARG1L * ARG2H:ARG2L = (ARG1H * ARG2H * 216) + (ARG1H * ARG2L * 28) + (ARG1L * ARG2H * 28) + (ARG1L * ARG2L) + (-1 * ARG2H<7> * ARG1H:ARG1L * 216) + (-1 * ARG1H<7> * ARG2H:ARG2L * 216) EXAMPLE 8-4: 16 x 16 UNSIGNED MULTIPLY ROUTINE ARG1L, W ARG2L MOVFF MOVFF ; ARG1L * ARG2L -> ; PRODH:PRODL PRODH, RES1 ; PRODL, RES0 ; MOVF MULWF ARG1H, W ARG2H MOVFF MOVFF MOVF MULWF ARG1L, W ARG2H MOVF ADDWF MOVF ADDWFC CLRF ADDWFC PRODL, RES1, PRODH, RES2, WREG RES3, MOVF MULWF ARG1H, W ARG2L MOVF ADDWF MOVF ADDWFC CLRF ADDWFC PRODL, RES1, PRODH, RES2, WREG RES3, W F W F F ARG1L * ARG2H -> PRODH:PRODL Add cross products W F W F F ARG1H * ARG2L -> PRODH:PRODL Add cross products MOVFF MOVFF PRODH, RES1 PRODL, RES0 MOVF MULWF ARG1H, W ARG2H MOVFF MOVFF PRODH, RES3 PRODL, RES2 MOVF MULWF ARG1L, W ARG2H MOVF ADDWF MOVF ADDWFC CLRF ADDWFC PRODL, RES1, PRODH, RES2, WREG RES3, MOVF MULWF ARG1H, W ARG2L MOVF ADDWF MOVF ADDWFC CLRF ADDWFC PRODL, RES1, PRODH, RES2, WREG RES3, BTFSS BRA MOVF SUBWF MOVF SUBWFB ARG2H, 7 SIGN_ARG1 ARG1L, W RES2 ARG1H, W RES3 ; ARG2H:ARG2L neg? ; no, check ARG1 ; ; ; ARG1H, 7 CONT_CODE ARG2L, W RES2 ARG2H, W RES3 ; ARG1H:ARG1L neg? ; no, done ; ; ; ; ARG1L * ARG2L -> ; PRODH:PRODL ; ; ; ARG1H * ARG2H -> ; PRODH:PRODL ; ; W F W F F ; ; ; ; ; ; ; ; ARG1L * ARG2H -> PRODH:PRODL Add cross products W F W F F ; ; ; ; ; ; ; ; ; ARG1H * ARG2L -> PRODH:PRODL Add cross products ; Example 8-4 shows the sequence to do a 16 x 16 signed multiply. Equation 8-2 shows the algorithm used. The 32-bit result is stored in four registers, RES3:RES0. To account for the sign bits of the arguments, each argument pairs' Most Significant bit (MSb) is tested and the appropriate subtractions are done. DS39605B-page 74 ARG1L, W ARG2L ; ; ; ; ; ; ; ; ; ; ; MOVF MULWF ; ; ; ; ; ; ; ; ; ; 16 x 16 SIGNED MULTIPLY ROUTINE ; ; ; ARG1H * ARG2H -> ; PRODH:PRODL PRODH, RES3 ; PRODL, RES2 ; 16 x 16 SIGNED MULTIPLICATION ALGORITHM ; SIGN_ARG1 BTFSS BRA MOVF SUBWF MOVF SUBWFB ; CONT_CODE : Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 9.0 INTERRUPTS The PIC18F1220/1320 devices have multiple interrupt sources and an interrupt priority feature that allows each interrupt source to be assigned a high priority level or a low priority level. The high priority interrupt vector is at 000008h and the low priority interrupt vector is at 000018h. High priority interrupt events will interrupt any low priority interrupts that may be in progress. There are ten registers which are used to control interrupt operation. These registers are: * * * * * * * RCON INTCON INTCON2 INTCON3 PIR1, PIR2 PIE1, PIE2 IPR1, IPR2 It is recommended that the Microchip header files supplied with MPLAB(R) IDE be used for the symbolic bit names in these registers. This allows the assembler/ compiler to automatically take care of the placement of these bits within the specified register. Each interrupt source has three bits to control its operation. The functions of these bits are: When an interrupt is responded to, the Global Interrupt Enable bit is cleared to disable further interrupts. If the IPEN bit is cleared, this is the GIE bit. If interrupt priority levels are used, this will be either the GIEH or GIEL bit. High priority interrupt sources can interrupt a low priority interrupt. Low priority interrupts are not processed while high priority interrupts are in progress. The return address is pushed onto the stack and the PC is loaded with the interrupt vector address (000008h or 000018h). Once in the Interrupt Service Routine, the source(s) of the interrupt can be determined by polling the interrupt flag bits. The interrupt flag bits must be cleared in software before re-enabling interrupts to avoid recursive interrupts. The "return from interrupt" instruction, RETFIE, exits the interrupt routine and sets the GIE bit (GIEH or GIEL, if priority levels are used), which re-enables interrupts. For external interrupt events, such as the INT pins or the PORTB input change interrupt, the interrupt latency will be three to four instruction cycles. The exact latency is the same for one or two-cycle instructions. Individual interrupt flag bits are set, regardless of the status of their corresponding enable bit, or the GIE bit. * Flag bit to indicate that an interrupt event occurred * Enable bit that allows program execution to branch to the interrupt vector address when the flag bit is set * Priority bit to select high priority or low priority The interrupt priority feature is enabled by setting the IPEN bit (RCON<7>). When interrupt priority is enabled, there are two bits which enable interrupts globally. Setting the GIEH bit (INTCON<7>) enables all interrupts that have the priority bit set (high priority). Setting the GIEL bit (INTCON<6>) enables all interrupts that have the priority bit cleared (low priority). When the interrupt flag, enable bit and appropriate global interrupt enable bit are set, the interrupt will vector immediately to address 000008h or 000018h, depending on the priority bit setting. Individual interrupts can be disabled through their corresponding enable bits. 2002 Microchip Technology Inc. When the IPEN bit is cleared (default state), the interrupt priority feature is disabled and interrupts are compatible with PICmicro(R) mid-range devices. In Compatibility mode, the interrupt priority bits for each source have no effect. INTCON<6> is the PEIE bit, which enables/disables all peripheral interrupt sources. INTCON<7> is the GIE bit, which enables/disables all interrupt sources. All interrupts branch to address 000008h in Compatibility mode. Note: Preliminary Do not use the MOVFF instruction to modify any of the interrupt control registers while any interrupt is enabled. Doing so may cause erratic microcontroller behavior. DS39605B-page 75 PIC18F1220/1320 FIGURE 9-1: INTERRUPT LOGIC TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP INT0IF INT0IE Wake-up if in Low Power Mode Interrupt to CPU Vector to Location 0008h INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP INT0IF INT0IE INT0IP GIEH/GIE ADIF ADIE ADIP IPE IPEN RCIF RCIE RCIP GIEL/PEIE IPEN Additional Peripheral Interrupts High Priority Interrupt Generation Low Priority Interrupt Generation INT0IF INT0IE INT0IP ADIF ADIE ADIP RBIF RBIE RBIP RCIF RCIE RCIP INT0IF INT0IE Additional Peripheral Interrupts DS39605B-page 76 Interrupt to CPU Vector to Location 0018h TMR0IF TMR0IE TMR0IP GIEL\PEIE GIE\GIEH INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 9.1 INTCON Registers Note: The INTCON Registers are readable and writable registers, which contain various enable, priority and flag bits. REGISTER 9-1: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. INTCON REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF bit 7 bit 0 bit 7 GIE/GIEH: Global Interrupt Enable bit When IPEN = 0: 1 = Enables all unmasked interrupts 0 = Disables all interrupts When IPEN = 1: 1 = Enables all high priority interrupts 0 = Disables all interrupts bit 6 PEIE/GIEL: Peripheral Interrupt Enable bit When IPEN = 0: 1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts When IPEN = 1: 1 = Enables all low priority peripheral interrupts 0 = Disables all low priority peripheral interrupts bit 5 TMR0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 overflow interrupt 0 = Disables the TMR0 overflow interrupt bit 4 INT0IE: INT0 External Interrupt Enable bit 1 = Enables the INT0 external interrupt 0 = Disables the INT0 external interrupt bit 3 RBIE: RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt bit 2 TMR0IF: TMR0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow bit 1 INT0IF: INT0 External Interrupt Flag bit 1 = The INT0 external interrupt occurred (must be cleared in software) 0 = The INT0 external interrupt did not occur bit 0 RBIF: RB Port Change Interrupt Flag bit 1 = At least one of the RB7:RB4 pins changed state (must be cleared in software) 0 = None of the RB7:RB4 pins have changed state Note: A mismatch condition will continue to set this bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR `1' = Bit is set `0' = Bit is cleared 2002 Microchip Technology Inc. Preliminary x = Bit is unknown DS39605B-page 77 PIC18F1220/1320 REGISTER 9-2: INTCON2 REGISTER R/W-1 R/W-1 R/W-1 R/W-1 U-0 R/W-1 U-0 R/W-1 RBPU INTEDG0 INTEDG1 INTEDG2 -- TMR0IP -- RBIP bit 7 bit 0 bit 7 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values bit 6 INTEDG0: External Interrupt0 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 5 INTEDG1: External Interrupt1 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 4 INTEDG2: External Interrupt2 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 3 Unimplemented: Read as '0' bit 2 TMR0IP: TMR0 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 Unimplemented: Read as '0' bit 0 RBIP: RB Port Change Interrupt Priority bit 1 = High priority 0 = Low priority Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR `1' = Bit is set `0' = Bit is cleared Note: DS39605B-page 78 x = Bit is unknown Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 REGISTER 9-3: INTCON3 REGISTER R/W-1 R/W-1 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 INT2IP INT1IP -- INT2IE INT1IE -- INT2IF INT1IF bit 7 bit 0 bit 7 INT2IP: INT2 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 INT1IP: INT1 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 Unimplemented: Read as '0' bit 4 INT2IE: INT2 External Interrupt Enable bit 1 = Enables the INT2 external interrupt 0 = Disables the INT2 external interrupt bit 3 INT1IE: INT1 External Interrupt Enable bit 1 = Enables the INT1 external interrupt 0 = Disables the INT1 external interrupt bit 2 Unimplemented: Read as '0' bit 1 INT2IF: INT2 External Interrupt Flag bit 1 = The INT2 external interrupt occurred (must be cleared in software) 0 = The INT2 external interrupt did not occur bit 0 INT1IF: INT1 External Interrupt Flag bit 1 = The INT1 external interrupt occurred (must be cleared in software) 0 = The INT1 external interrupt did not occur Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR `1' = Bit is set `0' = Bit is cleared Note: 2002 Microchip Technology Inc. x = Bit is unknown Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. Preliminary DS39605B-page 79 PIC18F1220/1320 9.2 PIR Registers Note 1: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). The PIR registers contain the individual flag bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are two Peripheral Interrupt Flag Registers (PIR1, PIR2). REGISTER 9-4: 2: User software should ensure the appropriate interrupt flag bits are cleared prior to enabling an interrupt, and after servicing that interrupt. PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1 U-0 R/W-0 R-0 R-0 U-0 R/W-0 R/W-0 R/W-0 -- ADIF RCIF TXIF -- CCP1IF TMR2IF TMR1IF bit 7 bit 0 bit 7 Unimplemented: Read as `0' bit 6 ADIF: A/D Converter Interrupt Flag bit 1 = An A/D conversion completed (must be cleared in software) 0 = The A/D conversion is not complete bit 5 RCIF: USART Receive Interrupt Flag bit 1 = The USART receive buffer, RCREG, is full (cleared when RCREG is read) 0 = The USART receive buffer is empty bit 4 TXIF: USART Transmit Interrupt Flag bit 1 = The USART transmit buffer, TXREG, is empty (cleared when TXREG is written) 0 = The USART transmit buffer is full bit 3 Unimplemented: Read as `0' bit 2 CCP1IF: CCP1 Interrupt Flag bit Capture mode: 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare mode: 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM mode: Unused in this mode bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit 1 = TMR2 to PR2 match occurred (must be cleared in software) 0 = No TMR2 to PR2 match occurred bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared in software) 0 = TMR1 register did not overflow Legend: DS39605B-page 80 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR `1' = Bit is set `0' = Bit is cleared Preliminary x = Bit is unknown 2002 Microchip Technology Inc. PIC18F1220/1320 REGISTER 9-5: PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2 R/W-0 U-0 U-0 R/W-0 U-0 R/W-0 R/W-0 U-0 OSCFIF -- -- EEIF -- LVDIF TMR3IF -- bit 7 bit 0 bit 7 OSCFIF: Oscillator Fail Interrupt Flag bit 1 = System oscillator failed, clock input has changed to INTOSC (must be cleared in software) 0 = System clock operating bit 6-5 Unimplemented: Read as '0' bit 4 EEIF: Data EEPROM/FLASH Write Operation Interrupt Flag bit 1 = The write operation is complete (must be cleared in software) 0 = The write operation is not complete, or has not been started bit 3 Unimplemented: Read as '0' bit 2 LVDIF: Low Voltage Detect Interrupt Flag bit 1 = A low voltage condition occurred (must be cleared in software) 0 = The device voltage is above the Low Voltage Detect trip point bit 1 TMR3IF: TMR3 Overflow Interrupt Flag bit 1 = TMR3 register overflowed (must be cleared in software) 0 = TMR3 register did not overflow bit 0 Unimplemented: Read as '0' Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR `1' = Bit is set `0' = Bit is cleared 2002 Microchip Technology Inc. Preliminary x = Bit is unknown DS39605B-page 81 PIC18F1220/1320 9.3 PIE Registers The PIE registers contain the individual enable bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are two Peripheral Interrupt Enable Registers (PIE1, PIE2). When IPEN = 0, the PEIE bit must be set to enable any of these peripheral interrupts. REGISTER 9-6: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 -- ADIE RCIE TXIE -- CCP1IE TMR2IE TMR1IE bit 7 bit 0 bit 7 Unimplemented: Read as `0' bit 6 ADIE: A/D Converter Interrupt Enable bit 1 = Enables the A/D interrupt 0 = Disables the A/D interrupt bit 5 RCIE: USART Receive Interrupt Enable bit 1 = Enables the USART receive interrupt 0 = Disables the USART receive interrupt bit 4 TXIE: USART Transmit Interrupt Enable bit 1 = Enables the USART transmit interrupt 0 = Disables the USART transmit interrupt bit 3 Unimplemented: Read as '0' bit 2 CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt Legend: DS39605B-page 82 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR `1' = Bit is set `0' = Bit is cleared Preliminary x = Bit is unknown 2002 Microchip Technology Inc. PIC18F1220/1320 REGISTER 9-7: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 R/W-0 U-0 U-0 R/W-0 U-0 R/W-0 R/W-0 U-0 OSCFIE -- -- EEIE -- LVDIE TMR3IE -- bit 7 bit 7 bit 0 OSCFIE: Oscillator Fail Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6-5 Unimplemented: Read as `0' bit 4 EEIE: Data EEPROM/FLASH Write Operation Interrupt Enable bit 1 = Enabled 0 = Disabled bit 3 Unimplemented: Read as `0' bit 2 LVDIE: Low Voltage Detect Interrupt Enable bit 1 = Enabled 0 = Disabled bit 1 TMR3IE: TMR3 Overflow Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 Unimplemented: Read as '0' Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR `1' = Bit is set `0' = Bit is cleared 2002 Microchip Technology Inc. Preliminary x = Bit is unknown DS39605B-page 83 PIC18F1220/1320 9.4 IPR Registers The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are two peripheral Interrupt Priority Registers (IPR1, IPR2). Using the priority bits requires that the Interrupt Priority Enable (IPEN) bit be set. REGISTER 9-8: IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1 U-0 R/W-1 R/W-1 R/W-1 U-0 R/W-1 R/W-1 R/W-1 -- ADIP RCIP TXIP -- CCP1IP TMR2IP TMR1IP bit 7 bit 0 bit 7 Unimplemented: Read as `0' bit 6 ADIP: A/D Converter Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 RCIP: USART Receive Interrupt Priority bit 1 = High priority 0 = Low priority bit 4 TXIP: USART Transmit Interrupt Priority bit 1 = High priority 0 = Low priority bit 3 Unimplemented: Read as '0' bit 2 CCP1IP: CCP1 Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 TMR2IP: TMR2 to PR2 Match Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 TMR1IP: TMR1 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority Legend: DS39605B-page 84 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR `1' = Bit is set `0' = Bit is cleared Preliminary x = Bit is unknown 2002 Microchip Technology Inc. PIC18F1220/1320 REGISTER 9-9: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2 R/W-1 U-0 U-0 R/W-1 U-0 R/W-1 R/W-1 U-0 OSCFIP -- -- EEIP -- LVDIP TMR3IP -- bit 7 bit 0 bit 7 OSCFIP: Oscillator Fail Interrupt Priority bit 1 = High priority 0 = Low priority bit 6-5 Unimplemented: Read as '0' bit 4 EEIP: Data EEPROM/FLASH Write Operation Interrupt Priority bit 1 = High priority 0 = Low priority bit 3 Unimplemented: Read as '0' bit 2 LVDIP: Low Voltage Detect Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 TMR3IP: TMR3 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 Unimplemented: Read as '0' Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR `1' = Bit is set `0' = Bit is cleared 2002 Microchip Technology Inc. Preliminary x = Bit is unknown DS39605B-page 85 PIC18F1220/1320 9.5 RCON Register The RCON register contains bits used to determine the cause of the last RESET or wake-up from Low Power mode. RCON also contains the bit that enables interrupt priorities (IPEN). REGISTER 9-10: RCON REGISTER R/W-0 U-0 U-0 R/W-1 R-1 R-1 R/W-0 R/W-0 IPEN -- -- RI TO PD POR BOR bit 7 bit 0 bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) bit 6-5 Unimplemented: Read as '0' bit 4 RI: RESET Instruction Flag bit For details of bit operation, see Register 5-3 bit 3 TO: Watchdog Time-out Flag bit For details of bit operation, see Register 5-3 bit 2 PD: Power-down Detection Flag bit For details of bit operation, see Register 5-3 bit 1 POR: Power-on Reset Status bit For details of bit operation, see Register 5-3 bit 0 BOR: Brown-out Reset Status bit For details of bit operation, see Register 5-3 Legend: DS39605B-page 86 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR `1' = Bit is set `0' = Bit is cleared Preliminary x = Bit is unknown 2002 Microchip Technology Inc. PIC18F1220/1320 9.6 INTn Pin Interrupts 9.7 External interrupts on the RB0/INT0, RB1/INT1 and RB2/INT2 pins are edge triggered: either rising, if the corresponding INTEDGx bit is set in the INTCON2 register, or falling, if the INTEDGx bit is clear. When a valid edge appears on the RBx/INTx pin, the corresponding flag bit INTxF is set. This interrupt can be disabled by clearing the corresponding enable bit INTxE. Flag bit INTxF must be cleared in software in the Interrupt Service Routine before re-enabling the interrupt. All external interrupts (INT0, INT1 and INT2) can wake-up the processor from Low Power modes, if bit INTxE was set prior to going into Low Power modes. If the global interrupt enable bit GIE is set, the processor will branch to the interrupt vector following wake-up. Interrupt priority for INT1 and INT2 is determined by the value contained in the interrupt priority bits, INT1IP (INTCON3<6>) and INT2IP (INTCON3<7>). There is no priority bit associated with INT0. It is always a high priority interrupt source. TMR0 Interrupt In 8-bit mode (which is the default), an overflow (FFh 00h) in the TMR0 register will set flag bit TMR0IF. In 16-bit mode, an overflow (FFFFh 0000h) in the TMR0H:TMR0L registers will set flag bit TMR0IF. The interrupt can be enabled/disabled by setting/clearing enable bit TMR0IE (INTCON<5>). Interrupt priority for Timer0 is determined by the value contained in the interrupt priority bit TMR0IP (INTCON2<2>). See Section 11.0 for further details on the Timer0 module. 9.8 PORTB Interrupt-on-Change An input change on PORTB<7:4> sets flag bit RBIF (INTCON<0>). The interrupt can be enabled/disabled by setting/clearing enable bit, RBIE (INTCON<3>). Interrupt priority for PORTB interrupt-on-change is determined by the value contained in the interrupt priority bit, RBIP (INTCON2<0>). 9.9 Context Saving During Interrupts During interrupts, the return PC address is saved on the stack. Additionally, the WREG, STATUS and BSR registers are saved on the fast return stack. If a fast return from interrupt is not used (see Section 5.3), the user may need to save the WREG, STATUS and BSR registers on entry to the Interrupt Service Routine. Depending on the user's application, other registers may also need to be saved. Example 9-1 saves and restores the WREG, STATUS and BSR registers during an Interrupt Service Routine. EXAMPLE 9-1: MOVWF MOVFF MOVFF ; ; USER ; MOVFF MOVF MOVFF SAVING STATUS, WREG AND BSR REGISTERS IN RAM W_TEMP STATUS, STATUS_TEMP BSR, BSR_TEMP ; W_TEMP is in virtual bank ; STATUS_TEMP located anywhere ; BSR_TMEP located anywhere ISR CODE BSR_TEMP, BSR W_TEMP, W STATUS_TEMP,STATUS 2002 Microchip Technology Inc. ; Restore BSR ; Restore WREG ; Restore STATUS Preliminary DS39605B-page 87 PIC18F1220/1320 NOTES: DS39605B-page 88 Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 10.0 I/O PORTS Depending on the device selected and features enabled, there are up to five ports available. Some pins of the I/O ports are multiplexed with an alternate function from the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. Each port has three registers for its operation. These registers are: * TRIS register (data direction register) * PORT register (reads the levels on the pins of the device) * LAT register (output latch) The data latch (LAT register) is useful for read-modify-write operations on the value that the I/O pins are driving. A simplified model of a generic I/O port without the interfaces to other peripherals is shown in Figure 10-1. FIGURE 10-1: D WR LAT or Port Q I/O pin(1) CK Data Latch D WR TRIS Q The fourth pin of PORTA (RA5/MCLR/VPP) is an input only pin. Its operation is controlled by the MCLRE configuration bit in Configuration Register 3H (CONFIG3H<7>). When selected as a port pin (MCLRE = 0), it functions as a digital input only pin; as such, it does not have TRIS or LAT bits associated with its operation. Otherwise, it functions as the device's Master Clear input. In either configuration, RA5 also functions as the programming voltage input during programming. Note: CK Input Buffer On a Power-on Reset, RA3:RA0 are configured as analog inputs and read as `0'. RA4 is configured as a digital input. The RA4/T0CKI/C1OUT pin is a Schmitt Trigger input and an open drain output. All other PORTA pins have TTL input levels and full CMOS output drivers. RD TRIS Q On a Power-on Reset, RA5 is enabled as a digital input only if Master Clear functionality is disabled. The other PORTA pins are multiplexed with analog inputs, the analog VREF+ and VREF- inputs and the LVD input. The operation of pins RA3:RA0 as A/D converter inputs is selected by clearing/setting the control bits in the ADCON1 register (A/D Control Register1). Note: TRIS Latch D The TRISA register controls the direction of the RA pins, even when they are being used as analog inputs. The user must ensure the bits in the TRISA register are maintained set when using them as analog inputs. ENEN RD Port Note 1: The RA4 pin is multiplexed with the Timer0 module clock input and one of the comparator outputs to become the RA4/T0CKI/C1OUT pin. Pins RA6 and RA7 are multiplexed with the main oscillator pins; they are enabled as oscillator or I/O pins by the selection of the main oscillator in Configuration Register 1H (see Section 19.1 for details). When they are not used as port pins, RA6 and RA7 and their associated TRIS and LAT bits are read as `0'. GENERIC I/O PORT OPERATION RD LAT Data Bus The Data Latch register (LATA) is also memory mapped. Read-modify-write operations on the LATA register reads and writes the latched output value for PORTA. I/O pins have diode protection to VDD and VSS. EXAMPLE 10-1: CLRF PORTA 10.1 PORTA, TRISA and LATA Registers CLRF LATA PORTA is a 8-bit wide, bi-directional port. The corresponding Data Direction register is TRISA. Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., put the contents of the output latch on the selected pin). MOVLW 0x7F MOVWF ADCON1 MOVLW 0XD0 MOVWF Reading the PORTA register reads the status of the pins, whereas writing to it will write to the port latch. 2002 Microchip Technology Inc. Preliminary TRISA INITIALIZING PORTA ; ; ; ; ; ; ; ; ; ; ; ; ; Initialize PORTA by clearing output data latches Alternate method to clear output data latches Configure A/D for digital inputs Value used to initialize data direction Set RA<3:0> as outputs RA<7:4> as inputs DS39605B-page 89 PIC18F1220/1320 FIGURE 10-2: BLOCK DIAGRAM OF RA3:RA0 PINS FIGURE 10-4: BLOCK DIAGRAM OF RA4/T0CKI PIN RD LATA RD LATA Data Bus WR LATA or PORTA D Data Bus WR LATA or PORTA Q VDD CK Q P Data Latch WR TRISA Analog Input Mode D Q CK Q D Q CK Q I/O pin(1) N Data Latch N (1) I/O pin WR TRISA VSS D Q CK Q VSS Schmitt Trigger Input Buffer TRIS Latch TRIS Latch RD TRISA RD TRISA Q Schmitt Trigger Input Buffer D EN Q D ENEN RD PORTA RD PORTA TMR0 Clock Input To A/D Converter and LVD Modules Note 1: Note 1: I/O pins have protection diodes to VDD and VSS. FIGURE 10-3: I/O pins have protection diodes to VDD and VSS. FIGURE 10-5: BLOCK DIAGRAM OF OSC2/CLKO/RA6 PIN RA6 Enable Data Bus RA7 Enable RD LATA RD LATA WR LATA or PORTA D Q CK Q WR LATA or PORTA VDD P D Q CK Q D Q CK Q VDD P Data Latch N I/O pin(1) WR TRISA VSS TRIS Latch Schmitt Trigger Input Buffer RD TRISA ECIO or RCIO Enable D Q CK Q N VSS RD TRISA Schmitt Trigger Input Buffer Q D I/O pins have protection diodes to VDD and VSS. DS39605B-page 90 D EN EN RD PORTA I/O pin(1) TRIS Latch RA7 Enable Q Note 1: To Oscillator Data Bus Data Latch WR TRISA BLOCK DIAGRAM OF OSC1/CLKI/RA7 PIN RD PORTA Note 1: Preliminary I/O pins have protection diodes to VDD and VSS. 2002 Microchip Technology Inc. PIC18F1220/1320 FIGURE 10-6: MCLR/RA5 PIN BLOCK DIAGRAM MCLRE Data Bus MCLR/RA5 RD TRISA Schmitt Trigger RD LATA Latch Q D EN RD PORTA High Voltage Detect HV Internal MCLR Filter Low Level MCLR Detect TABLE 10-1: PORTA FUNCTIONS Name RA0/AN0 Bit# Buffer bit0 ST Function Input/output or analog input. RA1/AN1/LVDIN bit1 ST Input/output or analog input. RA2/AN2/VREF- bit2 ST Input/output, analog input or VREF-. RA3/AN3/VREF+ bit3 ST Input/output, analog input or VREF+. RA4/T0CKI bit4 ST Input/output, external clock input for Timer0. Output is open drain type. MCLR/VPP/RA5 bit5 ST Master Clear input or programming voltage input (if MCLR is enabled); input only port pin or programming voltage input (if MCLR is disabled). OSC2/CLKO/RA6 bit6 ST OSC2, clock output or I/O pin. OSC1/CLKI/RA7 bit7 ST OSC1, clock input or I/O pin. Legend: TTL = TTL input, ST = Schmitt Trigger input TABLE 10-2: Name PORTA LATA TRISA ADCON1 SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other RESETS RA4 RA3 RA2 RA1 RA0 xx0x 0000 uu0u 0000 xx-x xxxx uu-u uuuu 11-1 1111 11-1 1111 -000 0000 -000 0000 Bit 7 Bit 6 Bit 5 RA7(1) RA6(1) RA5(2) LATA7(1) LATA6(1) -- LATA Data Output Register -- PORTA Data Direction Register TRISA7 -- (1) (1) TRISA6 PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by PORTA. Note 1: RA7:RA6 and their associated latch and data direction bits are enabled as I/O pins based on oscillator configuration; otherwise, they are read as `0'. 2: RA5 is an input only if MCLR is enabled or disabled. 2002 Microchip Technology Inc. Preliminary DS39605B-page 91 PIC18F1220/1320 10.2 PORTB, TRISB and LATB Registers This interrupt can wake the device from SLEEP. The user, in the Interrupt Service Routine, can clear the interrupt in the following manner: PORTB is an 8-bit wide, bi-directional port. The corresponding Data Direction register is TRISB. Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i.e., put the contents of the output latch on the selected pin). The Data Latch register (LATB) is also memory mapped. Read-modify-write operations on the LATB register reads and writes the latched output value for PORTB. EXAMPLE 10-2: CLRF CLRF MOVLW MOVWF MOVLW MOVWF PORTB INITIALIZING PORTB ; Initialize PORTB by ; ; LATB ; ; ; 0x70 ; ADCON1 ; ; 0xCF ; ; TRISB ; ; ; a) Any read or write of PORTB (except with the MOVFF instruction). This will end the mismatch condition. Clear flag bit RBIF. b) A mismatch condition will continue to set flag bit RBIF. Reading PORTB will end the mismatch condition and allow flag bit RBIF to be cleared. The interrupt-on-change feature is recommended for wake-up on key depression operation and operations where PORTB is only used for the interrupt-on-change feature. Polling of PORTB is not recommended while using the interrupt-on-change feature. FIGURE 10-7: clearing output data latches Alternate method to clear output data latches Set RB0, RB1, RB4 as digital I/O pins Value used to initialize data direction Set RB<3:0> as inputs RB<5:4> as outputs RB<7:6> as inputs VDD RBPU(2) Analog Input Mode Data Bus D WR LATB or PORTB Q I/O pin(1) CK D Pins RB0 - RB2 are multiplexed with INT0 - INT2; pins RB0, RB1, and RB4 are multiplexed with A/D inputs; pins RB1 and RB4 are multiplexed with USART; and pins RB2, RB3, RB6, and RB7 are multiplexed with ECCP. Each of the PORTB pins has a weak internal pull-up. A single control bit can turn on all the pull-ups. This is performed by clearing bit RBPU (INTCON2<7>). The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on a Power-on Reset. On a Power-on Reset, RB4:RB0 are configured as analog inputs by default, and read as `0'; RB7:RB5 are configured as digital inputs. Q CK TTL Input Buffer TRIS Latch RD TRISB RD LATB Q D ENEN RD PORTB Schmitt Trigger Buffer INTx To A/D Converter Note 1: Four of the PORTB pins (RB7:RB4) have an interrupt-on-change feature. Only pins configured as inputs can cause this interrupt to occur (i.e., any RB7:RB4 pin configured as an output is excluded from the interrupt-on-change comparison). The input pins (of RB7:RB4) are compared with the old value latched on the last read of PORTB. The "mismatch" outputs of RB7:RB4 are ORed together to generate the RB Port Change Interrupt with flag bit, RBIF (INTCON<0>). DS39605B-page 92 Weak P Pull-up Data Latch WR TRISB Note: BLOCK DIAGRAM OF RB0/AN4/INT0 PIN Preliminary 2: I/O pins have diode protection to VDD and VSS. To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>). 2002 Microchip Technology Inc. PIC18F1220/1320 FIGURE 10-8: BLOCK DIAGRAM OF RB1/AN5/TX/CK/INT1 PIN USART Enable 1 TX/CK Data 0 TX/CK TRIS VDD RBPU(2) Analog Input Mode Data Bus WR LATB or PORTB WR TRISB Weak P Pull-up Data Latch D Q RB1 pin(1) CK TRIS Latch D Q CK TTL Input Buffer RD TRISB RD LATB Q RD PORTB D EN RD PORTB Schmitt Trigger Input Buffer INT1/CK Input Analog Input Mode To A/D Converter Note 1: 2: I/O pins have diode protection to VDD and VSS. To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>). 2002 Microchip Technology Inc. Preliminary DS39605B-page 93 PIC18F1220/1320 FIGURE 10-9: BLOCK DIAGRAM OF RB2/P1B/INT2 PIN VDD RBPU(2) P Weak Pull-up P1B Enable P1B Data 1 P1B/D Tri-state Auto Shutdown 0 Data Bus WR LATB or PORTB WR TRISB Data Latch D Q RB2 pin(1) CK TRIS Latch D Q TTL Input Buffer CK RD TRISB RD LATB Q RD PORTB EN Schmitt Trigger INT2 Input Note 1: 2: DS39605B-page 94 D RD PORTB I/O pins have diode protection to VDD and VSS. To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>). Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 FIGURE 10-10: BLOCK DIAGRAM OF RB3/CCP1/P1A PIN ECCP1(3) pin Output Enable ECCP1(4) pin Input Enable VDD RBPU(2) Weak P Pull-up P1A/C Tri-state Auto Shutdown ECCP1/P1A Data Out VDD 1 P RD LATB Data Bus WR LATB or PORTB D CK 0 Q RB3 pin Q Data Latch D N Q VSS WR TRISB CK Q TTL Input Buffer TRIS Latch RD TRISB Q D EN RD PORTB ECCP1 Input Schmitt Trigger Note 1: I/O pins have diode protection to VDD and VSS. 2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>). 3: ECCP1 pin Output Enable active for any PWM mode and Compare mode, where CCP1M<3:0> = 1000 or 1001. 4: ECCP1 pin Input Enable active for Capture mode only. 2002 Microchip Technology Inc. Preliminary DS39605B-page 95 PIC18F1220/1320 FIGURE 10-11: BLOCK DIAGRAM OF RB4/AN6/RX/DT/KBI0 PIN USART Enabled RBPU(2) Analog Input Mode P Weak Pull-up DT TRIS DT Data 1 0 RD LATB Data Bus WR LATB or PORTB D CK Q RB4 pin Q Data Latch D WR TRISB CK Q Q TRIS Latch TTL Input Buffer RD TRISB Q Set RBIF EN RD PORTB From other RB7:RB4 pins D Q D RD PORTB EN Note 1: 2: DS39605B-page 96 Q3 Schmitt Trigger RX/DT Input To A/D Converter Q1 Analog Input Mode I/O pins have diode protection to VDD and VSS. To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>). Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 FIGURE 10-12: BLOCK DIAGRAM OF RB5/PGM/KBI1 PIN VDD RBPU(2) Weak P Pull-up Data Latch Data Bus WR LATB or PORTB D Q I/O pin(1) CK TRIS Latch D Q WR TRISB TTL Input Buffer CK ST Buffer RD TRISB RD LATB Latch Q D RD PORTB EN Set RBIF Q From Other RB7:RB5 and RB4 pins D EN Q1 RD PORTB Q3 RB7:RB5 in Serial Programming Mode Note 1: 2: I/O pins have diode protection to VDD and VSS. To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>). 2002 Microchip Technology Inc. Preliminary DS39605B-page 97 PIC18F1220/1320 FIGURE 10-13: BLOCK DIAGRAM OF RB6/PGC/T1OSO/T1CKI/P1C/KBI2 PIN ECCP1 P1C/D Enable RBPU(2) P Weak Pull-up P1B/D Tri-state Auto Shutdown P1C Data 1 0 RD LATB Data Bus WR LATB or PORTB D CK RB6 pin Q Data Latch D WR TRISB Q CK Q Q Timer1 Oscillator TRIS Latch T1OSCEN ST Input Buffer RD TRISB Q Set RBIF From Other RB7:RB4 pins Q D EN From RB7 pin D EN RD PORTB Schmitt Trigger Q1 RD PORTB Q3 PGC T1CKI Note 1: 2: I/O pins have diode protection to VDD and VSS. To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>). DS39605B-page 98 Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 FIGURE 10-14: BLOCK DIAGRAM OF RB7/PGD/T1OSI/P1D/KBI3 PIN ECCP1 P1C/D Enable RBPU(2) P Weak Pull-up P1B/D Tri-state Auto Shutdown P1D Data To RB6 pin 1 0 RD LATB Data Bus WR LATB or PORTB D CK RB7 pin Q Data Latch D WR TRISB Q CK Q Q TRIS Latch T1OSCEN TTL Input Buffer RD TRISB Q Set RBIF From Other RB7:RB4 pins D EN RD PORTB Q D EN Schmitt Trigger Q1 RD PORTB Q3 PGD Note 1: 2: I/O pins have diode protection to VDD and VSS. To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>). 2002 Microchip Technology Inc. Preliminary DS39605B-page 99 PIC18F1220/1320 TABLE 10-3: PORTB FUNCTIONS Name Bit# Buffer RB0/AN4/INT0 bit0 TTL(1)/ST(2) Input/output port pin or Timer1 oscillator output/Timer1 clock input. RB1/AN5/TX/CK/INT1 bit1 TTL(1)/ST(2) Input/output port pin, Enhanced USART Asynchronous Transmit, or Addressable USART Synchronous Clock. RB2/P1B/INT2 bit2 TTL(1)/ST(2) Input/output pin, external interrupt input2 or analog input. Internal software programmable weak pull-up. RB3/CCP1/P1A bit3 TTL(1)/ST(3) Input/output pin or analog input. Capture1 input/Compare1 output/PWM output. Internal software programmable weak pull-up. RB4/AN6/RX/DT bit4 TTL/ST(4) Input/output port pin, Enhanced USART Asynchronous Receive, or Addressable USART Synchronous Data. RB5/PGM bit5 TTL/ST(5) Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. Low voltage ICSP enable pin. RB6/PGC/T1OSO/T1CKI/P1C bit6 TTL/ST(5) Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. Serial programming clock. RB7/PGD/T1OSI/P1D bit7 TTL/ST(5) Input/output pin (with interrupt-on-change) Timer1 oscillator input. Internal software programmable weak pull-up. Serial programming data. Legend: Note 1: 2: 3: 4: 5: TTL = TTL input, ST = Schmitt Trigger input This buffer is a TTL input when configured as an analog input. This buffer is a Schmitt Trigger input when configured as the external interrupt. This buffer is a Schmitt Trigger input when configured as the CCP2 input. This buffer is a Schmitt Trigger input when used as USART receive input. This buffer is a Schmitt Trigger input when used in Serial Programming mode. TABLE 10-4: Name PORTB Function SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other RESETS RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxq qqqq uuuu uuuu uuuu uuuu LATB LATB Data Output Register xxxx xxxx TRISB PORTB Data Direction Register 1111 1111 1111 1111 INTCON GIE/GIEH PEIE/GIEL TMR0IE RBIF 0000 000x 0000 000u 1111 -1-1 INT0IE INTEDG0 INTEDG1 INTEDG2 RBIE TMR0IF INT0IF INTCON2 RBPU -- TMR0IP -- RBIP 1111 -1-1 INTCON3 INT2IP INT1IP -- INT2IE INT1IE -- INT2IF INT1IF 11-0 0-00 11-0 0-00 ADCON1 -- PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 -000 0000 -000 0000 Legend: x = unknown, u = unchanged, q = value depends on condition. Shaded cells are not used by PORTB. DS39605B-page 100 Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 11.0 TIMER0 MODULE The Timer0 module has the following features: * Software selectable as an 8-bit or 16-bit timer/ counter * Readable and writable * Dedicated 8-bit software programmable prescaler * Clock source selectable to be external or internal * Interrupt-on-overflow from FFh to 00h in 8-bit mode and FFFFh to 0000h in 16-bit mode * Edge select for external clock REGISTER 11-1: Figure 11-1 shows a simplified block diagram of the Timer0 module in 8-bit mode and Figure 11-2 shows a simplified block diagram of the Timer0 module in 16-bit mode. The T0CON register (Register 11-1) is a readable and writable register that controls all the aspects of Timer0, including the prescale selection. T0CON: TIMER0 CONTROL REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 bit 7 bit 0 bit 7 TMR0ON: Timer0 On/Off Control bit 1 = Enables Timer0 0 = Stops Timer0 bit 6 T08BIT: Timer0 8-bit/16-bit Control bit 1 = Timer0 is configured as an 8-bit timer/counter 0 = Timer0 is configured as a 16-bit timer/counter bit 5 T0CS: Timer0 Clock Source Select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (CLKO) bit 4 T0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin bit 3 PSA: Timer0 Prescaler Assignment bit 1 = TImer0 prescaler is NOT assigned. Timer0 clock input bypasses prescaler. 0 = Timer0 prescaler is assigned. Timer0 clock input comes from prescaler output. bit 2-0 T0PS2:T0PS0: Timer0 Prescaler Select bits 111 =1:256 prescale value 110 =1:128 prescale value 101 =1:64 prescale value 100 =1:32 prescale value 011 =1:16 prescale value 010 =1:8 prescale value 001 =1:4 prescale value 000 =1:2 prescale value Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR `1' = Bit is set `0' = Bit is cleared 2002 Microchip Technology Inc. Preliminary x = Bit is unknown DS39605B-page 101 PIC18F1220/1320 FIGURE 11-1: TIMER0 BLOCK DIAGRAM IN 8-BIT MODE Data Bus RA4/T0CKI/C1OUT pin FOSC/4 0 0 1 Programmable Prescaler 1 3 PSA 8 Sync with Internal Clocks TMR0 (2 TCY Delay) T0SE Set Interrupt Flag bit TMR0IF on Overflow T0PS2, T0PS1, T0PS0 T0CS Note: Upon RESET, Timer0 is enabled in 8-bit mode with clock input from T0CKI maximum prescale. FIGURE 11-2: RA4/T0CKI/ C1OUT pin TIMER0 BLOCK DIAGRAM IN 16-BIT MODE FOSC/4 0 0 Sync with Internal Clocks 1 T0SE Programmable Prescaler 1 TMR0L TMR0 High Byte 8 (2 TCY Delay) 3 Set Interrupt Flag bit TMR0IF on Overflow Read TMR0L T0PS2, T0PS1, T0PS0 T0CS PSA Write TMR0L 8 8 TMR0H 8 Data Bus<7:0> Note: Upon RESET, Timer0 is enabled in 8-bit mode with clock input from T0CKI maximum prescale. DS39605B-page 102 Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 11.1 Timer0 Operation 11.2.1 SWITCHING PRESCALER ASSIGNMENT Timer0 can operate as a timer or as a counter. The prescaler assignment is fully under software control (i.e., it can be changed "on-the-fly" during program execution). Timer mode is selected by clearing the T0CS bit. In Timer mode, the Timer0 module will increment every instruction cycle (without prescaler). If the TMR0 register is written, the increment is inhibited for the following two instruction cycles. The user can work around this by writing an adjusted value to the TMR0 register. 11.3 The TMR0 interrupt is generated when the TMR0 register overflows from FFh to 00h in 8-bit mode, or FFFFh to 0000h in 16-bit mode. This overflow sets the TMR0IF bit. The interrupt can be masked by clearing the TMR0IE bit. The TMR0IE bit must be cleared in software by the Timer0 module Interrupt Service Routine before re-enabling this interrupt. The TMR0 interrupt cannot awaken the processor from Low Power SLEEP mode, since the timer requires clock cycles, even when T0CS is set. Counter mode is selected by setting the T0CS bit. In Counter mode, Timer0 will increment, either on every rising or falling edge of pin RA4/T0CKI. The incrementing edge is determined by the Timer0 Source Edge Select bit (T0SE). Clearing the T0SE bit selects the rising edge. When an external clock input is used for Timer0, it must meet certain requirements. The requirements ensure the external clock can be synchronized with the internal phase clock (TOSC). Also, there is a delay in the actual incrementing of Timer0 after synchronization. 11.2 11.4 Prescaler The PSA and T0PS2:T0PS0 bits determine the prescaler assignment and prescale ratio. Clearing bit PSA will assign the prescaler to the Timer0 module. When the prescaler is assigned to the Timer0 module, prescale values of 1:2, 1:4,..., 1:256 are selectable. A write to the high byte of Timer0 must also take place through the TMR0H buffer register. Timer0 high byte is updated with the contents of TMR0H when a write occurs to TMR0L. This allows all 16-bits of Timer0 to be updated at once. When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g., CLRF TMR0, MOVWF TMR0, BSF TMR0, X....etc.) will clear the prescaler count. Writing to TMR0 when the prescaler is assigned to Timer0 will clear the prescaler count, but will not change the prescaler assignment. TABLE 11-1: Name 16-Bit Mode Timer Reads and Writes TMR0H is not the high byte of the timer/counter in 16-bit mode, but is actually a buffered version of the high byte of Timer0 (refer to Figure 11-2). The high byte of the Timer0 counter/timer is not directly readable nor writable. TMR0H is updated with the contents of the high byte of Timer0 during a read of TMR0L. This provides the ability to read all 16-bits of Timer0, without having to verify that the read of the high and low byte were valid due to a rollover between successive reads of the high and low byte. An 8-bit counter is available as a prescaler for the Timer0 module. The prescaler is not readable or writable. Note: Timer0 Interrupt REGISTERS ASSOCIATED WITH TIMER0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other RESETS TMR0L Timer0 Module Low Byte Register xxxx xxxx uuuu uuuu TMR0H Timer0 Module High Byte Register 0000 0000 0000 0000 0000 000u INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111 1111 1111 TRISA RA7(1) RA6(1) -- 11-1 1111 11-1 1111 PORTA Data Direction Register Legend: x = unknown, u = unchanged, - = unimplemented locations read as `0'. Shaded cells are not used by Timer0. Note 1: RA6 and RA7 are enabled as I/O pins, depending on the Oscillator mode selected in Configuration Word 1H. 2002 Microchip Technology Inc. Preliminary DS39605B-page 103 PIC18F1220/1320 NOTES: DS39605B-page 104 Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 12.0 TIMER1 MODULE The Timer1 module timer/counter has the following features: * 16-bit timer/counter (two 8-bit registers: TMR1H and TMR1L) * Readable and writable (both registers) * Internal or external clock select * Interrupt-on-overflow from FFFFh to 0000h * RESET from CCP module special event trigger * Status of system clock operation Figure 12-1 is a simplified block diagram of the Timer1 module. REGISTER 12-1: Register 12-1 details the Timer1 control register. This register controls the Operating mode of the Timer1 module, and contains the Timer1 oscillator enable bit (T1OSCEN). Timer1 can be enabled or disabled by setting or clearing control bit TMR1ON (T1CON<0>). The Timer1 oscillator can be used as a secondary clock source in Power Managed modes. When the T1RUN bit is set, the Timer1 oscillator is providing the system clock. If the Fail-Safe Clock Monitor is enabled and the Timer1 oscillator fails while providing the system clock, polling the T1RUN bit will indicate whether the clock is being provided by the Timer1 oscillator or another source. Timer1 can also be used to provide Real-Time Clock (RTC) functionality to applications, with only a minimal addition of external components and code overhead. T1CON: TIMER1 CONTROL REGISTER R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON bit 7 bit 0 bit 7 RD16: 16-bit Read/Write Mode Enable bit 1 = Enables register read/write of TImer1 in one 16-bit operation 0 = Enables register read/write of Timer1 in two 8-bit operations bit 6 T1RUN: Timer1 System Clock Status bit 1 = System clock is derived from Timer1 oscillator 0 = System clock is derived from another source bit 5-4 T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value bit 3 T1OSCEN: Timer1 Oscillator Enable bit 1 = Timer1 oscillator is enabled 0 = Timer1 oscillator is shut-off The oscillator inverter and feedback resistor are turned off to eliminate power drain. bit 2 T1SYNC: Timer1 External Clock Input Synchronization Select bit When TMR1CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input When TMR1CS = 0: This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0. bit 1 TMR1CS: Timer1 Clock Source Select bit 1 = External clock from pin RC0/T1OSO/T13CKI (on the rising edge) 0 = Internal clock (FOSC/4) bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR `1' = Bit is set `0' = Bit is cleared 2002 Microchip Technology Inc. Preliminary x = Bit is unknown DS39605B-page 105 PIC18F1220/1320 12.1 Timer1 Operation When TMR1CS = 0, Timer1 increments every instruction cycle. When TMR1CS = 1, Timer1 increments on every rising edge of the external clock input or the Timer1 oscillator, if enabled. Timer1 can operate in one of these modes: * As a timer * As a synchronous counter * As an asynchronous counter When the Timer1 oscillator is enabled (T1OSCEN is set), the RC1/T1OSI/CCP2 and RC0/T1OSO/T1CKI pins become inputs. That is, the TRISC1:TRISC0 value is ignored, and the pins are read as `0'. The Operating mode is determined by the clock select bit, TMR1CS (T1CON<1>). FIGURE 12-1: Timer1 also has an internal "RESET input". This RESET can be generated by the CCP module (see Section 15.4.4,"Special Event Trigger"). TIMER1 BLOCK DIAGRAM CCP Special Event Trigger TMR1IF Overflow Interrupt Flag Bit TMR1 TMR1H 1 TMR1ON On/Off T1OSC T1CKI/T1OSO T1OSCEN Enable Oscillator(1) T1OSI Synchronized Clock Input 0 CLR TMR1L T1SYNC 1 Synchronize Prescaler 1, 2, 4, 8 FOSC/4 Internal Clock det 0 2 T1CKPS1:T1CKPS0 Peripheral Clocks TMR1CS Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain. FIGURE 12-2: TIMER1 BLOCK DIAGRAM: 16-BIT READ/WRITE MODE Data Bus<7:0> 8 TMR1H 8 8 Write TMR1L CCP Special Event Trigger Read TMR1L TMR1IF Overflow Interrupt Flag bit TMR1 8 Timer 1 High Byte CLR TMR1L 1 TMR1ON on/off T1OSC T13CKI/T1OSO T1OSI Synchronized Clock Input 0 T1SYNC 1 T1OSCEN Enable Oscillator(1) Synchronize Prescaler 1, 2, 4, 8 FOSC/4 Internal Clock det 0 2 Peripheral Clocks TMR1CS T1CKPS1:T1CKPS0 Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain. DS39605B-page 106 Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 12.2 Timer1 Oscillator 12.3 A crystal oscillator circuit is built-in between pins T1OSI (input) and T1OSO (amplifier output). It is enabled by setting control bit T1OSCEN (T1CON<3>). The oscillator is a low power oscillator rated for 32 kHz crystals. It will continue to run during all Power Managed modes. The circuit for a typical LP oscillator is shown in Figure 12-3. Table 12-1 shows the capacitor selection for the Timer1 oscillator. The user must provide a software time delay to ensure proper start-up of the Timer1 oscillator. FIGURE 12-3: EXTERNAL COMPONENTS FOR THE TIMER1 LP OSCILLATOR C1 33 pF PIC18FXXXX Timer1 Oscillator Layout Considerations The Timer1 oscillator circuit draws very little power during operation. Due to the low power nature of the oscillator, it may also be sensitive to rapidly changing signals in close proximity. The oscillator circuit shown in Figure 12-3 should be located as close as possible to the microcontroller. There should be no circuits passing within the oscillator circuit boundaries other than VSS or VDD. If a high speed circuit must be located near the oscillator (such as the CCP1 pin in output compare or PWM mode, or the primary oscillator using the OSC2 pin), a grounded guard ring around the oscillator circuit, as shown in Figure 12-4, may be helpful when used on a single sided PCB, or in addition to a ground plane. FIGURE 12-4: T1OSI XTAL 32.768 kHz OSCILLATOR CIRCUIT WITH GROUNDED GUARD RING VDD T1OSO VSS C2 33 pF Note: TABLE 12-1: Osc Type LP OSC1 See the Notes with Table 12-1 for additional information about capacitor selection. OSC2 CAPACITOR SELECTION FOR THE TIMER OSCILLATOR RC0 Freq RC1 32 kHz C1 27 pF C2 (1) 27 pF(1) Note 1: Microchip suggests this value as a starting point in validating the oscillator circuit. 2: Higher capacitance increases the stability of the oscillator, but also increases the start-up time. 3: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components. 4: Capacitor values are for design guidance only. 2002 Microchip Technology Inc. RC2 Note: Not drawn to scale. 12.4 Timer1 Interrupt The TMR1 register pair (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h. The Timer1 interrupt, if enabled, is generated on overflow, which is latched in interrupt flag bit, TMR1IF (PIR1<0>). This interrupt can be enabled/disabled by setting/clearing Timer1 interrupt enable bit, TMR1IE (PIE1<0>). Preliminary DS39605B-page 107 PIC18F1220/1320 12.5 Resetting Timer1 Using a CCP Trigger Output 12.7 If the CCP module is configured in Compare mode to generate a "special event trigger" (CCP1M3:CCP1M0 = 1011), this signal will reset Timer1 and start an A/D conversion, if the A/D module is enabled (see Section 15.4.4 for more information.). Note: The special event triggers from the CCP1 module will not set interrupt flag bit, TMR1IF (PIR1<0>). Timer1 must be configured for either Timer or Synchronized Counter mode to take advantage of this feature. If Timer1 is running in Asynchronous Counter mode, this RESET operation may not work. In the event that a write to Timer1 coincides with a special event trigger from CCP1, the write will take precedence. In this mode of operation, the CCPR1H:CCPR1L registers pair effectively becomes the period register for Timer1. 12.6 Timer1 16-Bit Read/Write Mode Timer1 can be configured for 16-bit reads and writes (see Figure 12-2). When the RD16 control bit (T1CON<7>) is set, the address for TMR1H is mapped to a buffer register for the high byte of Timer1. A read from TMR1L will load the contents of the high byte of Timer1 into the Timer1 high byte buffer. This provides the user with the ability to accurately read all 16 bits of Timer1 without having to determine whether a read of the high byte, followed by a read of the low byte, is valid, due to a rollover between reads. Using Timer1 as a Real-Time Clock Adding an external LP oscillator to Timer1 (such as the one described in Section 12.2, above), gives users the option to include RTC functionality to their applications. This is accomplished with an inexpensive watch crystal to provide an accurate time-base, and several lines of application code to calculate the time. When operating in SLEEP mode and using a battery or super capacitor as a power source, it can completely eliminate the need for a separate RTC device and battery backup. The application code routine, RTCisr, shown in Example 12-1, demonstrates a simple method to increment a counter at one-second intervals using an Interrupt Service Routine. Incrementing the TMR1 register pair to overflow triggers the interrupt and calls the routine, which increments the seconds counter by one; additional counters for minutes and hours are incremented as the previous counter overflow. Since the register pair is 16-bits wide, counting up to overflow the register directly from a 32.768 kHz clock would take 2 seconds. To force the overflow at the required one-second intervals, it is necessary to preload it; the simplest method is to set the MSbit of TMR1H with a BSF instruction. Note that the TMR1L register is never preloaded or altered; doing so may introduce cumulative error over many cycles. For this method to be accurate, Timer1 must operate in Asynchronous mode, and the Timer1 Overflow Interrupt must be enabled (PIE1<0> = 1), as shown in the routine RTCinit. The Timer1 oscillator must also be enabled and running at all times. A write to the high byte of Timer1 must also take place through the TMR1H buffer register. Timer1 high byte is updated with the contents of TMR1H when a write occurs to TMR1L. This allows a user to write all 16 bits to both the high and low bytes of Timer1 at once. The high byte of Timer1 is not directly readable or writable in this mode. All reads and writes must take place through the Timer1 high byte buffer register. Writes to TMR1H do not clear the Timer1 prescaler. The prescaler is only cleared on writes to TMR1L. DS39605B-page 108 Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 EXAMPLE 12-1: IMPLEMENTING A REAL-TIME CLOCK USING A TIMER1 INTERRUPT SERVICE RTCinit MOVLW MOVWF CLRF MOVLW MOVWF CLRF CLRF MOVLW MOVWF BSF RETURN 0x80 TMR1H TMR1L b'00001111' T1OSC secs mins .12 hours PIE1, TMR1IE BSF BCF INCF MOVLW CPFSGT RETURN CLRF INCF MOVLW CPFSGT RETURN CLRF INCF MOVLW CPFSGT RETURN MOVLW MOVWF RETURN TMR1H,7 PIR1,TMR1IF secs,F .59 secs ; Preload TMR1 register pair ; for 1 second overflow ; Configure for external clock, ; Asynchronous operation, external oscillator ; Initialize timekeeping registers ; ; Enable Timer1 interrupt RTCisr TABLE 12-2: Name secs mins,F .59 mins mins hours,F .23 hours ; ; ; ; Preload for 1 sec overflow Clear interrupt flag Increment seconds 60 seconds elapsed? ; ; ; ; No, done Clear seconds Increment minutes 60 minutes elapsed? ; ; ; ; No, done clear minutes Increment hours 24 hours elapsed? ; No, done ; Reset hours to 1 .01 hours ; Done REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other RESETS INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000 TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 u0uu uuuu Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Timer1 module. Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F1220/1320 devices; always maintain these bits clear. 2002 Microchip Technology Inc. Preliminary DS39605B-page 109 PIC18F1220/1320 NOTES: DS39605B-page 110 Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 13.0 TIMER2 MODULE 13.1 The Timer2 module timer has the following features: * * * * * * 8-bit timer (TMR2 register) 8-bit period register (PR2) Readable and writable (both registers) Software programmable prescaler (1:1, 1:4, 1:16) Software programmable postscaler (1:1 to 1:16) Interrupt on TMR2 match with PR2 Timer2 has a control register shown in Register 13-1. TMR2 can be shut-off by clearing control bit TMR2ON (T2CON<2>) to minimize power consumption. Figure 13-1 is a simplified block diagram of the Timer2 module. Register 13-1 shows the Timer2 control register. The prescaler and postscaler selection of Timer2 are controlled by this register. Timer2 Operation Timer2 can be used as the PWM time-base for the PWM mode of the CCP module. The TMR2 register is readable and writable, and is cleared on any device RESET. The input clock (FOSC/4) has a prescale option of 1:1, 1:4 or 1:16, selected by control bits T2CKPS1:T2CKPS0 (T2CON<1:0>). The match output of TMR2 goes through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling inclusive) to generate a TMR2 interrupt (latched in flag bit TMR2IF, (PIR1<1>)). The prescaler and postscaler counters are cleared when any of the following occurs: * A write to the TMR2 register * A write to the T2CON register * Any device RESET (Power-on Reset, MCLR Reset, Watchdog Timer Reset, or Brown-out Reset) TMR2 is not cleared when T2CON is written. REGISTER 13-1: T2CON: TIMER2 CONTROL REGISTER U-0 R/W-0 R/W-0 R/W-0 R/W-0 -- TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 R/W-0 R/W-0 TMR2ON T2CKPS1 R/W-0 T2CKPS0 bit 7 bit 0 bit 7 Unimplemented: Read as '0' bit 6-3 TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits 0000 = 1:1 postscale 0001 = 1:2 postscale * * * 1111 = 1:16 postscale bit 2 TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off bit 1-0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1X = Prescaler is 16 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR `1' = Bit is set `0' = Bit is cleared 2002 Microchip Technology Inc. Preliminary x = Bit is unknown DS39605B-page 111 PIC18F1220/1320 13.2 Timer2 Interrupt 13.3 The Timer2 module has an 8-bit period register, PR2. Timer2 increments from 00h until it matches PR2 and then resets to 00h on the next increment cycle. PR2 is a readable and writable register. The PR2 register is initialized to FFh upon RESET. FIGURE 13-1: Output of TMR2 The output of TMR2 (before the postscaler) is fed to the Synchronous Serial Port module, which optionally uses it to generate the shift clock. TIMER2 BLOCK DIAGRAM Sets Flag bit TMR2IF TMR2 Output(1) Prescaler 1:1, 1:4, 1:16 FOSC/4 TMR2 2 Comparator RESET EQ Postscaler 1:1 to 1:16 T2CKPS1:T2CKPS0 4 PR2 TOUTPS3:TOUTPS0 TABLE 13-1: Name REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Value on all other RESETS Bit 0 Value on POR, BOR 0000 000x 0000 000u TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF PIR1 -- ADIF RCIF TXIF -- CCP1IF TMR2IF TMR1IF -000 -000 0000 0000 PIE1 -- ADIE RCIE TXIE -- CCP1IE TMR2IE TMR1IE -000 -000 0000 0000 IPR1 -- ADIP RCIP TXIP -- CCP1IP TMR2IP TMR1IP -000 -000 0000 0000 INTCON GIE/GIEH PEIE/GIEL TMR2 T2CON PR2 Timer2 Module Register -- 0000 0000 0000 0000 TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 Timer2 Period Register 1111 1111 1111 1111 Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Timer2 module. DS39605B-page 112 Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 14.0 TIMER3 MODULE The Timer3 module timer/counter has the following features: * 16-bit timer/counter (two 8-bit registers; TMR3H and TMR3L) * Readable and writable (both registers) * Internal or external clock select * Interrupt-on-overflow from FFFFh to 0000h * RESET from CCP module trigger REGISTER 14-1: Figure 14-1 is a simplified block diagram of the Timer3 module. Register 14-1 shows the Timer3 control register. This register controls the Operating mode of the Timer3 module and sets the CCP clock source. Register 12-1 shows the Timer1 control register. This register controls the Operating mode of the Timer1 module, as well as contains the Timer1 oscillator enable bit (T1OSCEN), which can be a clock source for Timer3. T3CON: TIMER3 CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON bit 7 bit 0 bit 7 RD16: 16-bit Read/Write Mode Enable bit 1 = Enables register Read/Write of Timer3 in one 16-bit operation 0 = Enables register Read/Write of Timer3 in two 8-bit operations bit 6, 3 T3CCP2:T3CCP1: Timer3 and Timer1 to CCPx Enable bits 1X = Timer3 is the clock source for compare/capture CCP modules 0X = Timer1 is the clock source for compare/capture CCP modules bit 5-4 T3CKPS1:T3CKPS0: Timer3 Input Clock Prescale Select bits 11 = 1:8 prescale value 10 = 1:4 prescale value 01 = 1:2 prescale value 00 = 1:1 prescale value bit 2 T3SYNC: Timer3 External Clock Input Synchronization Control bit (Not usable if the system clock comes from Timer1/Timer3.) When TMR3CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input When TMR3CS = 0: This bit is ignored. Timer3 uses the internal clock when TMR3CS = 0. bit 1 TMR3CS: Timer3 Clock Source Select bit 1 = External clock input from Timer1 oscillator or T1CKI (on the rising edge after the first falling edge) 0 = Internal clock (FOSC/4) bit 0 TMR3ON: Timer3 On bit 1 = Enables Timer3 0 = Stops Timer3 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR `1' = Bit is set `0' = Bit is cleared 2002 Microchip Technology Inc. Preliminary x = Bit is unknown DS39605B-page 113 PIC18F1220/1320 14.1 Timer3 Operation When TMR3CS = 0, Timer3 increments every instruction cycle. When TMR3CS = 1, Timer3 increments on every rising edge of the Timer1 external clock input or the Timer1 oscillator, if enabled. Timer3 can operate in one of these modes: * As a timer * As a synchronous counter * As an asynchronous counter When the Timer1 oscillator is enabled (T1OSCEN is set), the RB7/PGD/T1OSI/P1D/KBI3 and RB6/PGC/ T1OSO/T1CKI/P1C/KBI2 pins become inputs. That is, the TRISB7:TRISB6 value is ignored, and the pins are read as `0'. The Operating mode is determined by the clock select bit, TMR3CS (T3CON<1>). Timer3 also has an internal "RESET input". This RESET can be generated by the CCP module (see Section 15.4.4, "Special Event Trigger"). FIGURE 14-1: TIMER3 BLOCK DIAGRAM CCP Special Event Trigger T3CCPx TMR3IF Overflow Interrupt Flag bit TMR3H TMR3L 1 TMR3ON On/Off T1OSO/ T13CKI T1OSI Synchronized Clock Input 0 CLR T3SYNC T1OSC 1 T1OSCEN FOSC/4 Enable Internal Oscillator(1) Clock Prescaler 1, 2, 4, 8 Synchronize det 0 2 TMR3CS Peripheral Clocks T3CKPS1:T3CKPS0 Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain. DS39605B-page 114 Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 FIGURE 14-2: TIMER3 BLOCK DIAGRAM CONFIGURED IN 16-BIT READ/WRITE MODE Data Bus<7:0> 8 TMR3H 8 8 Write TMR3L Read TMR3L Set TMR3IF Flag bit on Overflow 8 TMR3 Timer3 High Byte TMR3L T1OSC T1OSI CLR 1 To Timer1 Clock Input T1OSO/ T13CKI CCP Special Event Trigger T3CCPx Synchronized 0 Clock Input TMR3ON On/Off T3SYNC 1 T1OSCEN Enable Oscillator(1) FOSC/4 Internal Clock Prescaler 1, 2, 4, 8 Synchronize det 0 2 T3CKPS1:T3CKPS0 TMR3CS Peripheral Clocks Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain. 2002 Microchip Technology Inc. Preliminary DS39605B-page 115 PIC18F1220/1320 14.2 Timer1 Oscillator 14.4 The Timer1 oscillator may be used as the clock source for Timer3. The Timer1 oscillator is enabled by setting the T1OSCEN (T1CON<3>) bit. The oscillator is a low power oscillator rated for 32 kHz crystals. See Section 12.2 for further details. 14.3 If the CCP module is configured in Compare mode to generate a "special event trigger" (CCP1M3:CCP1M0 = 1011), this signal will reset Timer3. See Section 15.4.4 for more information. Note: Timer3 Interrupt The TMR3 Register pair (TMR3H:TMR3L) increments from 0000h to FFFFh and rolls over to 0000h. The TMR3 Interrupt, if enabled, is generated on overflow, which is latched in interrupt flag bit, TMR3IF (PIR2<1>). This interrupt can be enabled/disabled by setting/clearing TMR3 interrupt enable bit, TMR3IE (PIE2<1>). TABLE 14-1: Resetting Timer3 Using a CCP Trigger Output The special event triggers from the CCP module will not set interrupt flag bit, TMR3IF (PIR1<0>). Timer3 must be configured for either Timer or Synchronized Counter mode to take advantage of this feature. If Timer3 is running in Asynchronous Counter mode, this RESET operation may not work. In the event that a write to Timer3 coincides with a special event trigger from CCP1, the write will take precedence. In this mode of operation, the CCPR1H:CCPR1L registers pair effectively becomes the period register for Timer3. REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER Value on all other RESETS Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR INTCON GIE/ GIEH PEIE/ GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u PIR2 OSCIF -- -- EEIF -- LVDIF TMR3IF -- 0--0 -00- 0--0 -00- PIE2 OSCIE -- -- EEIE -- LVDIE TMR3IE -- 0--0 -00- 0--0 -00- IPR2 OSCIP -- -- EEIP -- LVDIP TMR3IP -- 1--1 -11- 1--1 -11- TMR3L Holding Register for the Least Significant Byte of the 16-bit TMR3 Register xxxx xxxx uuuu uuuu TMR3H Holding Register for the Most Significant Byte of the 16-bit TMR3 Register xxxx xxxx uuuu uuuu T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 u0uu uuuu T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3SYNC TMR3CS TMR3ON 0000 0000 uuuu uuuu T3CCP1 Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Timer3 module. DS39605B-page 116 Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 15.0 ENHANCED CAPTURE/COMPARE/PWM (ECCP) MODULE The control register Register 15-1. The enhanced CCP module is implemented as a standard CCP module with enhanced PWM capabilities. These capabilities allow for 2 or 4 output channels, user selectable polarity, deadband control, and automatic shutdown and restart, and are discussed in detail in Section 15.5. REGISTER 15-1: bit 5-4 bit 3-0 CCP1 is shown in In addition to the expanded functions of the CCP1CON register, the ECCP module has two additional registers associated with enhanced PWM operation and auto shutdown features: * PWM1CON * ECCPAS CCP1CON REGISTER FOR ENHANCED CCP OPERATION R/W-0 P1M1 bit 7 bit 7-6 for R/W-0 P1M0 R/W-0 DC1B1 R/W-0 DC1B0 R/W-0 CCP1M3 R/W-0 CCP1M2 R/W-0 CCP1M1 R/W-0 CCP1M0 bit 0 P1M1:P1M0: PWM Output Configuration bits If CCP1M<3:2> = 00, 01, 10: xx = P1A assigned as Capture/Compare input; P1B, P1C, P1D assigned as port pins If CCP1M<3:2> = 11: 00 = Single output; P1A modulated; P1B, P1C, P1D assigned as port pins 01 = Full-bridge output forward; P1D modulated; P1A active; P1B, P1C inactive 10 = Half-bridge output; P1A, P1B modulated with deadband control; P1C, P1D assigned as port pins 11 = Full-bridge output reverse; P1B modulated; P1C active; P1A, P1D inactive DC1B1:DC1B0: PWM Duty Cycle Least Significant bits Capture mode: Unused Compare mode: Unused PWM mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPR1L. CCP1M3:CCP1M0: ECCP1 Mode Select bits 0000 = Capture/Compare/PWM off (resets ECCP module) 0001 = Unused (reserved) 0010 = Compare mode, toggle output on match (ECCP1IF bit is set) 0011 = Unused (reserved) 0100 = Capture mode, every falling edge 0101 = Capture mode, every rising edge 0110 = Capture mode, every 4th rising edge 0111 = Capture mode, every 16th rising edge 1000 = Compare mode, set output on match (ECCP1IF bit is set) 1001 = Compare mode, clear output on match (ECCP1IF bit is set) 1010 = Compare mode, generate software interrupt on match (ECCP1IF bit is set, ECCP1 pin is unaffected) 1011 = Compare mode, trigger special event (ECCP1IF bit is set; ECCP resets TMR1 or TMR2 and starts an A/D conversion, if the A/D module is enabled) 1100 = PWM mode; P1A, P1C active high; P1B, P1D active high 1101 = PWM mode; P1A, P1C active high; P1B, P1D active low 1110 = PWM mode; P1A, P1C active low; P1B, P1D active high 1111 = PWM mode; P1A, P1C active low; P1B, P1D active low Legend: R = Readable bit - n = Value at POR 2002 Microchip Technology Inc. W = Writable bit `1' = Bit is set Preliminary U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown DS39605B-page 117 PIC18F1220/1320 15.1 ECCP Outputs The enhanced CCP module may have up to four outputs, depending on the selected operating mode. These outputs, designated P1A through P1D, are multiplexed with I/O pins on PORTB. The pin assignments are summarized in Table 15-1. TABLE 15-1: To configure I/O pins as PWM outputs, the proper PWM mode must be selected by setting the P1Mn and CCP1Mn bits (CCP1CON<7:6> and <3:0>, respectively). The appropriate TRISB direction bits for the port pins must also be set as outputs. PIN ASSIGNMENTS FOR VARIOUS ECCP MODES CCP1CON Configuration RB3 RB2 RB6 RB7 Compatible CCP 00xx11xx CCP1 RB2/INT2 RB6/PGC/T1OSO/T1CKI/KBI2 RB7/PGD/T1OSI/KBI3 Dual PWM 10xx11xx P1A P1B RB6/PGC/T1OSO/T1CKI/KBI2 RB7/PGD/T1OSI/KBI3 Quad PWM x1xx11xx P1A P1B P1C P1D ECCP Mode Legend: x = Don't care. Shaded cells indicate pin assignments not used by ECCP in a given mode. Note 1: TRIS register values must be configured appropriately. 15.2 CCP Module 15.3.1 Capture/Compare/PWM Register 1 (CCPR1) is comprised of two 8-bit registers: CCPR1L (low byte) and CCPR1H (high byte). The CCP1CON register controls the operation of CCP1. All are readable and writable. TABLE 15-2: 15.3 CCP MODE - TIMER RESOURCE CCP Mode Timer Resource Capture Compare PWM Timer1 or Timer3 Timer1 or Timer3 Timer2 In Capture mode, the RB3/CCP1 pin should be configured as an input by setting the TRISB<3> bit. Note: 15.3.2 If the RB3/CCP1 is configured as an output, a write to the port can cause a capture condition. TIMER1/TIMER3 MODE SELECTION The timers that are to be used with the capture feature (either Timer1 and/or Timer3) must be running in Timer mode or Synchronized Counter mode. In Asynchronous Counter mode, the capture operation may not work. The timer to be used with each CCP module is selected in the T3CON register. Capture Mode In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 or TMR3 registers when an event occurs on pin RC2/CCP1. An event is defined as one of the following: * * * * CCP PIN CONFIGURATION every falling edge every rising edge every 4th rising edge every 16th rising edge 15.3.3 SOFTWARE INTERRUPT When the Capture mode is changed, a false capture interrupt may be generated. The user should keep bit CCP1IE (PIE1<2>) clear to avoid false interrupts and should clear the flag bit, CCP1IF, following any such change in Operating mode. The event is selected by control bits CCP1M3:CCP1M0 (CCP1CON<3:0>). When a capture is made, the interrupt request flag bit CCP1IF (PIR1<2>) is set; it must be cleared in software. If another capture occurs before the value in register CCPR1 is read, the old captured value is overwritten by the new captured value. DS39605B-page 118 Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 15.3.4 CCP PRESCALER There are four prescaler settings, specified by bits CCP1M3:CCP1M0. Whenever the CCP module is turned off or the CCP module is not in Capture mode, the prescaler counter is cleared. This means that any RESET will clear the prescaler counter. Switching from one capture prescaler to another may generate an interrupt. Also, the prescaler counter will not be cleared; therefore, the first capture may be from a non-zero prescaler. Example 15-1 shows the recom- FIGURE 15-1: mended method for switching between capture prescalers. This example also clears the prescaler counter and will not generate the "false" interrupt. EXAMPLE 15-1: CHANGING BETWEEN CAPTURE PRESCALERS CLRF MOVLW CCP1CON, F NEW_CAPT_PS MOVWF CCP1CON ; ; ; ; ; ; Turn CCP module off Load WREG with the new prescaler mode value and CCP ON Load CCP1CON with this value CAPTURE MODE OPERATION BLOCK DIAGRAM TMR3H Set Flag bit CCP1IF T3CCP2 Prescaler / 1, 4, 16 CCP1 pin TMR3 Enable CCPR1H and Edge Detect T3CCP2 TMR3L CCPR1L TMR1 Enable TMR1H TMR1L CCP1CON<3:0> Q's 15.4 Compare Mode 15.4.2 TIMER1/TIMER3 MODE SELECTION In Compare mode, the 16-bit CCPR1 register value is constantly compared against either the TMR1 register pair value, or the TMR3 register pair value. When a match occurs, the RC2/CCP1 pin: Timer1 and/or Timer3 must be running in Timer mode or Synchronized Counter mode, if the CCP module is using the compare feature. In Asynchronous Counter mode, the compare operation may not work. * * * * 15.4.3 Is driven High Is driven Low Toggles output (High to Low or Low to High) Remains unchanged (interrupt only) The action on the pin is based on the value of control bits CCP1M3:CCP1M0 (CCP2M3:CCP2M0). At the same time, interrupt flag bit CCP1IF (CCP2IF) is set. 15.4.1 CCP PIN CONFIGURATION The user must configure the CCPx pin as an output by clearing the appropriate TRISB bit. Note: Clearing the CCP1CON register will force the RB3/CCP1/P1A compare output latch to the default low level. This is not the PORTB I/O data latch. 2002 Microchip Technology Inc. SOFTWARE INTERRUPT MODE When generate software interrupt is chosen, the CCP1 pin is not affected. Only a CCP interrupt is generated (if enabled). 15.4.4 SPECIAL EVENT TRIGGER In this mode, an internal hardware trigger is generated, which may be used to initiate an action. The special event trigger output of CCP1 resets the TMR1 register pair. This allows the CCPR1 register to effectively be a 16-bit programmable period register for Timer1. Preliminary DS39605B-page 119 PIC18F1220/1320 FIGURE 15-2: COMPARE MODE OPERATION BLOCK DIAGRAM Special Event Trigger will: Reset Timer1 or Timer3, but do not set Timer1 or Timer3 interrupt flag bit, and set bit GO/DONE (ADCON0<2>), which starts an A/D conversion. Special Event Trigger Set Flag bit CCP1IF CCPR1H CCPR1L Q RB3/CCP1/P1A pin S Output Logic R TRISB<3> Output Enable Comparator Match CCP1CON<3:0> Mode Select TMR1H FIGURE 15-3: Name INTCON Bit 7 0 T3CCP2 TMR1L 1 TMR3H TMR3L REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3 Bit 6 GIE/GIEH PEIE/GIEL Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Value on all other RESETS Bit 0 Value on POR, BOR RBIF 0000 000x 0000 000u TMR0IE INT0IE RBIE TMR0IF INT0IF PIR1 -- ADIF RCIF TXIF -- CCP1IF TMR2IF TMR1IF -000 -000 -000 -000 PIE1 -- ADIE RCIE TXIE -- CCP1IE TMR2IE TMR1IE -000 -000 -000 -000 -- ADIP RCIP TXIP -- CCP1IP TMR2IP TMR1IP -000 -000 -000 -000 IPR1 TRISB PORTB Data Direction Register 1111 1111 1111 1111 TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 uuuu uuuu CCPR1L Capture/Compare/PWM Register1 (LSB) CCPR1H Capture/Compare/PWM Register1 (MSB) CCP1CON -- -- DC1B1 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 TMR3L Holding Register for the Least Significant Byte of the 16-bit TMR3 Register xxxx xxxx uuuu uuuu TMR3H Holding Register for the Most Significant Byte of the 16-bit TMR3 Register xxxx xxxx uuuu uuuu T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 uuuu uuuu Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by Capture and Timer1. DS39605B-page 120 Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 15.5 Enhanced PWM Mode 15.5.2 PWM DUTY CYCLE The Enhanced PWM Mode provides additional PWM output options for a broader range of control applications. The module is an upwardly compatible version of the standard CCP module, and offers up to four outputs, designated P1A through P1D. Users are also able to select the polarity of the signal (either active high or active low). The module's Output mode and polarity are configured by setting the P1M1:P1M0 and CCP1M3CCP1M0 bits of the CCP1CON register (CCP1CON<7:6> and CCP1CON<3:0>, respectively). The PWM duty cycle is specified by writing to the CCPR1L register and to the CCP1CON<5:4> bits. Up to 10-bit resolution is available. The CCPR1L contains the eight MSbs and the CCP1CON<5:4> contains the two LSbs. This 10-bit value is represented by CCPR1L:CCP1CON<5:4>. The PWM duty cycle is calculated by the equation: Figure 15-4 shows a simplified block diagram of PWM operation. All control registers are double-buffered, and are loaded at the beginning of a new PWM cycle (the period boundary when Timer2 resets), in order to prevent glitches on any of the outputs. The exception is the PWM delay register ECCP1DEL, which is loaded at either the duty cycle boundary, or the boundary period (whichever comes first). Because of the buffering, the module waits until the assigned timer resets, instead of starting immediately. This means that enhanced PWM waveforms do not exactly match the standard PWM waveforms, but are instead offset by one full instruction cycle (4 TOSC). CCPR1L and CCP1CON<5:4> can be written to at any time, but the duty cycle value is not copied into CCPR1H until a match between PR2 and TMR2 occurs (i.e., the period is complete). In PWM mode, CCPR1H is a read only register. PWM Duty Cycle = (CCPR1L:CCP1CON<5:4>) * TOSC * (TMR2 Prescale Value) The CCPR1H register and a 2-bit internal latch are used to double-buffer the PWM duty cycle. This double buffering is essential for glitchless PWM operation. When the CCPR1H and 2-bit latch match TMR2, concatenated with an internal 2-bit Q clock or two bits of the TMR2 prescaler, the CCP1 pin is cleared. The maximum PWM resolution (bits) for a given PWM frequency is given by the equation: As before, the user must manually configure the appropriate TRIS bits for output. 15.5.1 ( log FOSC FPWM PWM Resolution (max) = log(2) PWM PERIOD The PWM period is specified by writing to the PR2 register. The PWM period can be calculated using the equation: Note: PWM Period = [(PR2) + 1] * 4 * TOSC * (TMR2 Prescale Value) PWM frequency is defined as 1 / [PWM period]. When TMR2 is equal to PR2, the following three events occur on the next increment cycle: 15.5.3 * TMR2 is cleared * The CCP1 pin is set (if PWM duty cycle = 0%, the CCP1 pin will not be set) * The PWM duty cycle is copied from CCPR1L into CCPR1H * * * * Note: The Timer2 postscaler (see Section 13.0) is not used in the determination of the PWM frequency. The postscaler could be used to have a servo update rate at a different frequency than the PWM output. TABLE 15-3: ) bits If the PWM duty cycle value is longer than the PWM period, the CCP1 pin will not be cleared. PWM OUTPUT CONFIGURATIONS The P1M1:P1M0 bits in the CCP1CON register allow one of four configurations: Single Output Half-Bridge Output Full-Bridge Output, Forward mode Full-Bridge Output, Reverse mode The Single Output mode is the Standard PWM mode discussed in Section 15.5. The Half-Bridge and Full-Bridge Output modes are covered in detail in the sections that follow. The general relationship of the outputs in all configurations is summarized in Figure 15-5. EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz PWM Frequency Timer Prescaler (1, 4, 16) PR2 Value Maximum Resolution (bits) 2002 Microchip Technology Inc. 2.44 kHz 9.77 kHz 39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz 16 4 1 1 1 1 FFh FFh FFh 3Fh 1Fh 17h 10 10 10 8 7 6.58 Preliminary DS39605B-page 121 PIC18F1220/1320 FIGURE 15-4: SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODULE CCP1CON<5:4> Duty Cycle Registers CCP1M<3:0> 4 P1M1<1:0> 2 CCPR1L CCP1/P1A RB3/CCP1/P1A TRISB<3> CCPR1H (Slave) P1B R Comparator Output Controller Q RB2/P1B/INT2 TRISB<2> RB6/PGC/T1OSO/T1CKI/ P1C/KBI2 P1C TMR2 (Note 1) Comparator PR2 Note: P1D Clear Timer, set CCP1 pin and latch D.C. RB7/PGD/T1OSI/P1D/KBI3 TRISB<7> CCP1DEL The 8-bit timer TMR2 register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler to create the 10-bit time-base. FIGURE 15-5: PWM OUTPUT RELATIONSHIPS (ACTIVE HIGH STATE) CCP1CON <7:6> 00 TRISB<6> S (Single Output) SIGNAL 0 PR2+1 Duty Cycle Period P1A Modulated Delay(1) Delay(1) P1A Modulated 10 (Half-Bridge) P1B Modulated P1A Active 01 (Full-Bridge, Forward) P1B Inactive P1C Inactive P1D Modulated P1A Inactive 11 (Full-Bridge, Reverse) P1B Modulated P1C Active P1D Inactive DS39605B-page 122 Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 FIGURE 15-6: PWM OUTPUT RELATIONSHIPS (ACTIVE LOW STATE) CCP1CON <7:6> 00 (Single Output) SIGNAL 0 Period P1A Modulated P1A Modulated 10 (Half-Bridge) PR2+1 Duty Cycle Delay(1) Delay(1) P1B Modulated P1A Active 01 (Full-Bridge, Forward) P1B Inactive P1C Inactive P1D Modulated P1A Inactive 11 (Full-Bridge, Reverse) P1B Modulated P1C Active P1D Inactive Relationships: * Period = 4 * TOSC * (PR2 + 1) * (TMR2 prescale value) * Duty Cycle = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 prescale value) * Delay = 4 * TOSC * (PWM1CON<6:0>) Note 1: Deadband delay is programmed using the PWM1CON register (Section 15.5.6). 2002 Microchip Technology Inc. Preliminary DS39605B-page 123 PIC18F1220/1320 15.5.4 HALF-BRIDGE MODE FIGURE 15-7: In the Half-Bridge Output mode, two pins are used as outputs to drive push-pull loads. The PWM output signal is output on the RB3/CCP1/P1A pin, while the complementary PWM output signal is output on the RB2/P1B/INT2 pin (Figure 15-7). This mode can be used for half-bridge applications, as shown in Figure 15-8, or for full-bridge applications, where four power switches are being modulated with two PWM signals. HALF-BRIDGE PWM OUTPUT Period Period Duty Cycle P1A(2) td td P1B(2) In Half-Bridge Output mode, the programmable deadband delay can be used to prevent shoot-through current in half-bridge power devices. The value of bits PDC6:PDC0 sets the number of instruction cycles before the output is driven active. If the value is greater than the duty cycle, the corresponding output remains inactive during the entire cycle. See Section 15.5.6 for more details of the deadband delay operations. (1) (1) (1) td = Deadband Delay Note 1: At this time, the TMR2 register is equal to the PR2 register. 2: Output signals are shown as active high. Since the P1A and P1B outputs are multiplexed with the PORTB<3> and PORTB<2> data latches, the TRISB<3> and TRISB<2> bits must be cleared to configure P1A and P1B as outputs. FIGURE 15-8: EXAMPLES OF HALF-BRIDGE OUTPUT MODE APPLICATIONS V+ Standard Half-Bridge Circuit ("Push-Pull") PIC18F1220/1320 FET Driver + V - P1A Load FET Driver + V - P1B V- Half-Bridge Output Driving a Full-Bridge Circuit V+ PIC18F1220/1320 FET Driver FET Driver P1A FET Driver Load FET Driver P1B V- DS39605B-page 124 Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 15.5.5 FULL-BRIDGE MODE In Full-Bridge Output mode, four pins are used as outputs; however, only two outputs are active at a time. In the Forward mode, pin RB3/CCP1/P1A is continuously active, and pin RB7/PGD/T1OSI/P1D/KBI3 is modulated. In the Reverse mode, pin RB6/PGC/T1OSO/T1CKI/P1C/KBI2 is continuously active, and pin RB2/P1B/INT2 is modulated. These are illustrated in Figure 15-9. FIGURE 15-9: P1A, P1B, P1C and P1D outputs are multiplexed with the PORTB<3:2> and PORTB<7:6> data latches. The TRISB<3:2> and TRISB<7:6> bits must be cleared to make the P1A, P1B, P1C, and P1D pins output. FULL-BRIDGE PWM OUTPUT Forward Mode Period P1A (2) Duty Cycle P1B(2) P1C(2) P1D(2) (1) (1) Reverse Mode Period Duty Cycle P1A(2) P1B(2) P1C(2) P1D(2) (1) (1) Note 1: At this time, the TMR2 register is equal to the PR2 register. Note 2: Output signal is shown as active high. 2002 Microchip Technology Inc. Preliminary DS39605B-page 125 PIC18F1220/1320 FIGURE 15-10: EXAMPLE OF FULL-BRIDGE APPLICATION V+ PIC18F1220/1320 FET Driver QC QA FET Driver P1A Load P1B FET Driver P1C FET Driver QD QB VP1D 15.5.5.1 Direction Change in Full-Bridge Mode In the Full-Bridge Output mode, the P1M1 bit in the CCP1CON register allows user to control the Forward/Reverse direction. When the application firmware changes this direction control bit, the module will assume the new direction on the next PWM cycle. Just before the end of the current PWM period, the modulated outputs (P1B and P1D) are placed in their inactive state, while the unmodulated outputs (P1A and P1C) are switched to drive in the opposite direction. This occurs in a time interval of (4 TOSC * (Timer2 Prescale value) before the next PWM period begins. The Timer2 prescaler will be either 1,4 or 16, depending on the value of the T2CKPS bit (T2CON<1:0>). During the interval from the switch of the unmodulated outputs to the beginning of the next period, the modulated outputs (P1B and P1D) remain inactive. This relationship is shown in Figure 15-11. Note that in the Full-Bridge Output mode, the ECCP module does not provide any deadband delay. In general, since only one output is modulated at all times, deadband delay is not required. However, there is a situation where a deadband delay might be required. This situation occurs when both of the following conditions are true: 1. 2. Figure 15-12 shows an example where the PWM direction changes from forward to reverse, at a near 100% duty cycle. At time t1, the output P1A and P1D become inactive, while output P1C becomes active. In this example, since the turn off time of the power devices is longer than the turn on time, a shoot-through current may flow through power devices QC and QD (see Figure 15-10) for the duration of `t'. The same phenomenon will occur to power devices QA and QB for PWM direction change from reverse to forward. If changing PWM direction at high duty cycle is required for an application, one of the following requirements must be met: 1. 2. Reduce PWM for a PWM period before changing directions. Use switch drivers that can drive the switches off faster than they can drive them on. Other options to prevent shoot-through current may exist. The direction of the PWM output changes when the duty cycle of the output is at or near 100%. The turn off time of the power switch, including the power device and driver circuit, is greater than the turn on time. DS39605B-page 126 Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 FIGURE 15-11: PWM DIRECTION CHANGE Period(1) SIGNAL Period P1A (Active High) P1B (Active High) DC P1C (Active High) (Note 2) P1D (Active High) DC Note 1: The direction bit in the CCP1 Control Register (CCP1CON<7>) is written any time during the PWM cycle. 2: When changing directions, the P1A and P1C signals switch before the end of the current PWM cycle at intervals of 4 TOSC, 16 TOSC or 64 TOSC, depending on the Timer2 prescaler value. The modulated P1B and P1D signals are inactive at this time. FIGURE 15-12: PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE Forward Period t1 Reverse Period P1A P1B DC P1C P1D DC tON External Switch C tOFF External Switch D Potential Shoot-Through Current t = tOFF - tON Note 1: All signals are shown as active high. 2: tON is the turn on delay of power switch QC and its driver. 3: tOFF is the turn off delay of power switch QD and its driver. 2002 Microchip Technology Inc. Preliminary DS39605B-page 127 PIC18F1220/1320 15.5.6 PROGRAMMABLE DEADBAND DELAY In half-bridge applications where all power switches are modulated at the PWM frequency at all times, the power switches normally require more time to turn off than to turn on. If both the upper and lower power switches are switched at the same time (one turned on, and the other turned off), both switches may be on for a short period of time until one switch completely turns off. During this brief interval, a very high current (shoot-through current) may flow through both power switches, shorting the bridge supply. To avoid this potentially destructive shoot-through current from flowing during switching, turning on either of the power switches is normally delayed to allow the other switch to completely turn off. In the Half-Bridge Output mode, a digitally programmable deadband delay is available to avoid shoot-through current from destroying the bridge power switches. The delay occurs at the signal transition from the non-active state to the active state. See Figure 15-7 for illustration. The lower seven bits of the PWM1CON register (Register 15-2) sets the delay period in terms of microcontroller instruction cycles (TCY or 4 TOSC). 15.5.7 ENHANCED PWM AUTO SHUTDOWN When the ECCP is programmed for any of the enhanced PWM modes, the active output pins may be configured for Auto Shutdown. Auto shutdown immediately places the enhanced PWM output pins into a defined shutdown state, when a shutdown event occurs. REGISTER 15-2: A shutdown event can be caused by either of the two comparator modules, or the INT0 pin (or any combination of these three sources). The comparators may be used to monitor a voltage input proportional to a current being monitored in the bridge circuit. If the voltage exceeds a threshold, the comparator switches state and triggers a shutdown. Alternatively, a digital signal on the INT0 pin can also trigger a shutdown. The auto shutdown feature can be disabled by not selecting any auto shutdown sources. The auto shutdown sources to be used are selected using the ECCPAS2:ECCPAS0 bits (bits <6:4> of the ECCPAS register). When a shutdown occurs, the output pins are asynchronously placed in their shutdown states, specified by the PSSAC1:PSSAC0 and PSSBD1:PSSBD0 bits (ECCPAS<3:0>). Each pin pair (P1A/P1C and P1B/P1D) may be set to drive high, drive low, or be tri-stated (not driving). The ECCPASE bit (ECCPAS<7>) is also set to hold the enhanced PWM outputs in their shutdown states. The ECCPASE bit is set by hardware when a shutdown event occurs. If automatic restarts are not enabled, the ECCPASE bit is cleared by firmware when the cause of the shutdown clears. If automatic restarts are enabled, the ECCPASE bit is automatically cleared when the cause of the auto shutdown has cleared. If the ECCPASE bit is set when a PWM period begins, the PWM outputs remain in their shutdown state for that entire PWM period. When the ECCPASE bit is cleared, the PWM outputs will return to normal operation at the beginning of the next PWM period. Note: Writing to the ECCPASE bit is disabled while a shutdown condition is active. PWM1CON: PWM CONFIGURATION REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PRSEN PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 bit 7 bit 0 bit 7 PRSEN: PWM Restart Enable bit 1 = Upon auto shutdown, the ECCPASE bit clears automatically once the shutdown event goes away; the PWM restarts automatically 0 = Upon auto shutdown, ECCPASE must be cleared in software to restart the PWM bit 6-0 PDC<6:0>: PWM Delay Count bits Number of FOSC/4 (4*TOSC) cycles between the scheduled time when a PWM signal should transition active, and the actual time it transitions active. Legend: DS39605B-page 128 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR `1' = Bit is set `0' = Bit is cleared Preliminary x = Bit is unknown 2002 Microchip Technology Inc. PIC18F1220/1320 REGISTER 15-3: ECCPAS: ENHANCED CAPTURE/COMPARE/PWM/AUTO SHUTDOWN CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 R/W-0 R/W-0 R/W-0 R/W-0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 bit 7 bit 0 bit 7 ECCPASE: ECCP Auto Shutdown Event Status bit 0 = ECCP outputs are operating 1 = A shutdown event has occurred; ECCP outputs are in shutdown state bit 6-4 ECCPAS<2:0>: ECCP Auto Shutdown Source Select bits 000 = Auto shutdown is disabled 001 = Comparator 1 output 010 = Comparator 2 output 011 = Either Comparator 1 or 2 100 = INT0 101 = INT0 or Comparator 1 110 = INT0 or Comparator 2 111 = INT0 or Comparator 1 or Comparator 2 bit 3-2 PSSACn: Pin A and C Shutdown State Control bits 00 = Drive Pins A and C to `0' 01 = Drive Pins A and C to `1' 1x = Pins A and C tri-state bit 1-0 PSSBDn: Pin B and D Shutdown State Control bits 00 = Drive Pins B and D to `0' 01 = Drive Pins B and D to `1' 1x = Pins B and D tri-state Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR `1' = Bit is set `0' = Bit is cleared 2002 Microchip Technology Inc. Preliminary x = Bit is unknown DS39605B-page 129 PIC18F1220/1320 15.5.7.1 Auto Shutdown and Automatic Restart 15.5.8 The auto shutdown feature can be configured to allow automatic restarts of the module, following a shutdown event. This is enabled by setting the PRSEN bit of the PWM1CON register (PWM1CON<7>). In Shutdown mode with PRSEN = 1 (Figure 15-13), the ECCPASE bit will remain set for as long as the cause of the shutdown continues. When the shutdown condition clears, the ECCPASE bit is cleared. If PRSEN = 0 (Figure 15-14), once a shutdown condition occurs, the ECCPASE bit will remain set until it is cleared by firmware. Once ECCPASE is cleared, the enhanced PWM will resume at the beginning of the next PWM period. Note: When the ECCP module is used in the PWM mode, the application hardware must use the proper external pull-up and/or pull-down resistors on the PWM output pins. When the microcontroller is released from RESET, all of the I/O pins are in the high-impedance state. The external circuits must keep the power switch devices in the off state, until the microcontroller drives the I/O pins with the proper signal levels, or activates the PWM output(s). The CCP1M1:CCP1M0 bits (CCP1CON<1:0>) allow the user to choose whether the PWM output signals are active high or active low for each pair of PWM output pins (P1A/P1C and P1B/P1D). The PWM output polarities must be selected before the PWM pins are configured as outputs. Changing the polarity configuration while the PWM pins are configured as outputs is not recommended, since it may result in damage to the application circuits. Writing to the ECCPASE bit is disabled while a shutdown condition is active. Independent of the PRSEN bit setting, if the auto shutdown source is one of the comparators, the shutdown condition is a level. The ECCPASE bit cannot be cleared as long as the cause of the shutdown persists. The Auto Shutdown mode can be forced by writing a '1' to the ECCPASE bit. FIGURE 15-13: START-UP CONSIDERATIONS The P1A, P1B, P1C and P1D output latches may not be in the proper states when the PWM module is initialized. Enabling the PWM pins for output at the same time as the ECCP module may cause damage to the application circuit. The ECCP module must be enabled in the proper Output mode and complete a full PWM cycle, before configuring the PWM pins as outputs. The completion of a full PWM cycle is indicated by the TMR2IF bit being set as the second PWM period begins. PWM AUTO SHUTDOWN (PRSEN = 1, AUTO RESTART ENABLED) PWM Period Shutdown Event ECCPASE bit PWM Activity Normal PWM Start of PWM Period FIGURE 15-14: Shutdown Shutdown Event Occurs Event Clears PWM Resumes PWM AUTO SHUTDOWN (PRSEN = 0, AUTO RESTART DISABLED) PWM Period Shutdown Event ECCPASE bit PWM Activity Normal PWM Start of PWM Period DS39605B-page 130 ECCPASE Cleared by Shutdown Shutdown Firmware PWM Event Occurs Event Clears Resumes Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 15.5.9 SETUP FOR PWM OPERATION 15.5.10 The following steps should be taken when configuring the ECCP1 module for PWM operation: 1. 2. 3. 4. 5. 6. 7. 8. 9. Configure the PWM pins P1A and P1B (and P1C and P1D, if used) as inputs by setting the corresponding TRISB bits. Set the PWM period by loading the PR2 register. Configure the ECCP module for the desired PWM mode and configuration by loading the CCP1CON register with the appropriate values: * Select one of the available output configurations and direction with the P1M1:P1M0 bits. * Select the polarities of the PWM output signals with the CCP1M3:CCP1M0 bits. Set the PWM duty cycle by loading the CCPR1L register and CCP1CON<5:4> bits. For Half-Bridge Output mode, set the deadband delay by loading PWM1CON<6:0> with the appropriate value. If auto shutdown operation is required, load the ECCPAS register: * Select the auto shutdown sources using the ECCPAS<2:0> bits. * Select the shutdown states of the PWM output pins using PSSAC1:PSSAC0 and PSSBD1:PSSBD0 bits. * Set the ECCPASE bit (ECCPAS<7>). * Configure the comparators using the CMCON register. * Configure the comparator inputs as analog inputs. If auto restart operation is required, set the PRSEN bit (PWM1CON<7>). Configure and start TMR2: * Clear the TMR2 interrupt flag bit by clearing the TMR2IF bit (PIR1<1>). * Set the TMR2 prescale value by loading the T2CKPS bits (T2CON<1:0>). * Enable Timer2 by setting the TMR2ON bit (T2CON<2>). Enable PWM outputs after a new PWM cycle has started: * Wait until TMR2 overflows (TMR2IF bit is set). * Enable the CCP1/P1A, P1B, P1C and/or P1D pin outputs by clearing the respective TRISB bits. * Clear the ECCPASE bit (ECCPAS<7>). 2002 Microchip Technology Inc. OPERATION IN LOW POWER MODES In the low power SLEEP mode, all clock sources are disabled. Timer2 will not increment and the state of the module will not change. If the ECCP pin is driving a value, it will continue to drive that value. When the device wakes up, it will continue from this state. If Two-Speed Start-ups are enabled, the initial start-up frequency may not be stable if the INTOSC is being used. In PRI_IDLE mode, the primary clock will continue to clock the ECCP module without change. In all other Low Power modes, the selected Low Power mode clock will clock Timer2. Other Low Power mode clocks will most likely be different than the primary clock frequency. 15.5.10.1 Operation with Fail-Safe Clock Monitor If the Fail-Safe Clock Monitor is enabled (CONFIG1H<6> is programmed), a clock failure will force the device into the RC_RUN Low Power mode, and the OSCFIF bit (PIR2<7>) will be set. The ECCP will then be clocked from the INTRC clock source, which may have a different clock frequency than the primary clock. By loading the IRCF2:IRCF0 bits on RESETS, the user can enable the INTOSC at a high clock speed in the event of a clock failure. See the previous section for additional details. 15.5.11 EFFECTS OF A RESET Both power-on and subsequent RESETS will force all ports to Input mode and the CCP registers to their RESET states. This forces the Enhanced CCP module to reset to a state compatible with the standard CCP module. Preliminary DS39605B-page 131 PIC18F1220/1320 TABLE 15-4: Name INTCON RCON REGISTERS ASSOCIATED WITH ENHANCED PWM AND TIMER2 Bit 7 Bit 6 GIE/GIEH PEIE/GIEL IPEN -- Value on POR, BOR Value on all other RESETS Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u -- RI TO PD POR BOR 0--1 11qq 0--q qquu PIR1 -- ADIF RCIF TXIF -- CCP1IF TMR2IF TMR1IF -000 -000 -000 -000 PIE1 -- ADIE RCIE TXIE -- CCP1IE TMR2IE TMR1IE -000 -000 -000 -000 -- ADIP RCIP TXIP -- CCP1IP TMR2IP TMR1IP -111 -111 -111 -111 IPR1 TMR2 Timer2 Module Register PR2 Timer2 Module Period Register T2CON -- TOUTPS3 0000 0000 0000 0000 1111 1111 1111 1111 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 TRISB PORTB Data Direction Register 1111 1111 1111 1111 CCPR1H Enhanced Capture/Compare/PWM Register1 High Byte xxxx xxxx uuuu uuuu CCPR1L Enhanced Capture/Compare/PWM Register1 Low Byte CCP1CON ECCPAS P1M1 P1M0 DC1B1 DC1B0 xxxx xxxx uuuu uuuu CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 0000 0000 ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSBD0 0000 0000 0000 0000 PSSAC0 PSSBD1 PWM1CON PRSEN PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 0000 0000 uuuu uuuu OSCCON IDLEN IRCF2 IRCF1 IRCF0 OSTS FLTS SCS1 SCS0 0000 q000 uuuu uuqu Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the ECCP module in enhanced PWM mode. DS39605B-page 132 Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 16.0 ENHANCED UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (USART) The Universal Synchronous Asynchronous Receiver Transmitter (USART) module is one of the two serial I/O modules. (USART is also known as a Serial Communications Interface or SCI.) The USART can be configured as a full-duplex asynchronous system that can communicate with peripheral devices, such as CRT terminals and personal computers. It can also be configured as a half-duplex synchronous system that can communicate with peripheral devices, such as A/D or D/A integrated circuits, serial EEPROMs, etc. The Enhanced USART module implements additional features, including automatic baud rate detection and calibration, automatic wake-up on Sync Break reception and 12-bit Break character transmit. These make it ideally suited for use in Local Interconnect Network bus (LIN bus) systems. The USART can be configured in the following modes: * Asynchronous (full-duplex) with: - Auto wake-up on character reception - Auto baud calibration - 12-bit Break character transmission * Synchronous - Master (half-duplex) with selectable clock polarity * Synchronous - Slave (half-duplex) with selectable clock polarity In order to configure pins RB1/AN5/TX/CK/INT1 and RB4/AN6/RX/DT as the Universal Synchronous Asynchronous Receiver Transmitter: * * * * SPEN (RCSTA<7>) bit must be set (= 1), PCFG6:PCFG5 (ADCON1<5:6>) must be set (= 1), TRISB<4> bit must be set (= 1), and TRISB<1> bit must be set (= 1). Note: The USART control will automatically reconfigure the pin from input to output as needed. The operation of the Enhanced USART module is controlled through three registers: * Transmit Status and Control (TXSTA) * Receive Status and Control (RCSTA) * Baud Rate Control (BAUDCTL) These are detailed in on the following pages in Register 16-1, Register 16-2 and Register 16-3, respectively. 16.1 Asynchronous Operation in Power Managed Modes The USART may operate in Asynchronous mode while the peripheral clocks are being provided by the internal oscillator block. This makes it possible to remove the crystal or resonator that is commonly connected as the primary clock on the OSC1 and OSC2 pins. The factory calibrates the internal oscillator block output (INTOSC) for 8 MHz (see Table 22.5). However, this frequency may drift as VDD or temperature changes, and this directly affects the asynchronous baud rate. Two methods may be used to adjust the baud rate clock, but both require a reference clock source of some kind. The first (preferred) method uses the OSCTUNE register to adjust the INTOSC output back to 8 MHz. Adjusting the value in the OSCTUNE register allows for fine resolution changes to the system clock source (see Section 3.6 for more information). The other method adjusts the value in the baud rate generator. There may not be fine enough resolution when adjusting the Baud Rate Generator to compensate for a gradual change in the peripheral clock frequency. 2002 Microchip Technology Inc. Preliminary DS39605B-page 133 PIC18F1220/1320 REGISTER 16-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER R/W-0 CSRC bit 7 R/W-0 TX9 R/W-0 TXEN R/W-0 SYNC U-0 SENDB bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don't care Synchronous mode: 1 = Master mode (clock generated internally from BRG) 0 = Slave mode (clock from external source) bit 6 TX9: 9-bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission bit 5 TXEN: Transmit Enable bit 1 = Transmit enabled 0 = Transmit disabled Note: R/W-0 BRGH R-1 TRMT R/W-0 TX9D bit 0 SREN/CREN overrides TXEN in Sync mode. bit 4 SYNC: USART Mode Select bit 1 = Synchronous mode 0 = Asynchronous mode bit 3 SENDB: Send Break Character bit Asynchronous mode: 1 = Send Sync Break on next transmission (cleared by hardware upon completion) 0 = Sync Break transmission completed Synchronous mode: Don't care bit 2 BRGH: High Baud Rate Select bit Asynchronous mode: 1 = High speed 0 = Low speed Synchronous mode: Unused in this mode bit 1 TRMT: Transmit Shift Register Status bit 1 = TSR empty 0 = TSR full bit 0 TX9D: 9th bit of Transmit Data Can be address/data bit or a parity bit. Legend: DS39605B-page 134 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR `1' = Bit is set `0' = Bit is cleared Preliminary x = Bit is unknown 2002 Microchip Technology Inc. PIC18F1220/1320 REGISTER 16-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER R/W-0 SPEN bit 7 R/W-0 RX9 R/W-0 SREN R/W-0 CREN R/W-0 ADDEN R-0 FERR R-0 OERR R-x RX9D bit 0 bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins) 0 = Serial port disabled (held in RESET) bit 6 RX9: 9-bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception bit 5 SREN: Single Receive Enable bit Asynchronous mode: Don't care Synchronous mode - Master: 1 = Enables single receive 0 = Disables single receive This bit is cleared after reception is complete. Synchronous mode - Slave: Don't care bit 4 CREN: Continuous Receive Enable bit Asynchronous mode: 1 = Enables receiver 0 = Disables receiver Synchronous mode: 1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN) 0 = Disables continuous receive bit 3 ADDEN: Address Detect Enable bit Asynchronous mode 9-bit (RX9 = 1): 1 = Enables address detection, enable interrupt and load the receive buffer when RSR<8> is set 0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit Asynchronous mode 9-bit (RX9 = 0): Don't care bit 2 FERR: Framing Error bit 1 = Framing error (can be updated by reading RCREG register and receive next valid byte) 0 = No framing error bit 1 OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit CREN) 0 = No overrun error bit 0 RX9D: 9th bit of Received Data This can be address/data bit or a parity bit and must be calculated by user firmware. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR `1' = Bit is set `0' = Bit is cleared 2002 Microchip Technology Inc. Preliminary x = Bit is unknown DS39605B-page 135 PIC18F1220/1320 REGISTER 16-3: BAUDCTL: BAUD RATE CONTROL REGISTER U-0 R-1 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 -- RCIDL -- SCKP BRG16 -- WUE ABDEN bit 7 bit 0 bit 7 Unimplemented: Read as '0' bit 6 RCIDL: Receive Operation IDLE Status bit 1 = Receive operation is IDLE 0 = Receive operation is active bit 5 Unimplemented: Read as '0' bit 4 SCKP: Synchronous Clock Polarity Select bit Asynchronous mode: Unused in this mode Synchronous mode: 1 = IDLE state for clock (CK) is a high level 0 = IDLE state for clock (CK) is a low level bit 3 BRG16: 16-bit Baud Rate Register Enable bit 1 = 16-bit baud rate generator - SPBRGH and SPBRG 0 = 8-bit baud rate generator - SPBRG only (Compatible mode), SPBRGH value ignored bit 2 Unimplemented: Read as '0' bit 1 WUE: Wake-up Enable bit Asynchronous mode: 1 = USART will continue to sample the RX pin - interrupt generated on falling edge; bit cleared in hardware on following rising edge 0 = RX pin not monitored or rising edge detected Synchronous mode: Unused in this mode bit 0 ABDEN: Auto Baud Detect Enable bit Asynchronous mode: 1 = Enable baud rate measurement on the next character - requires reception of a Sync field (55h); cleared in hardware upon completion 0 = Baud rate measurement disabled or completed Synchronous mode: Unused in this mode Legend: DS39605B-page 136 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR `1' = Bit is set `0' = Bit is cleared Preliminary x = Bit is unknown 2002 Microchip Technology Inc. PIC18F1220/1320 16.2 USART Baud Rate Generator (BRG) The BRG is a dedicated 8-bit or 16-bit generator, that supports both the Asynchronous and Synchronous modes of the USART. By default, the BRG operates in 8-bit mode; setting the BRG16 bit (BAUDCTL<3>) selects 16-bit mode. The SPBRGH:SPBRG register pair controls the period of a free running timer. In Asynchronous mode, bits BRGH (TXSTA<2>) and BRG16 also control the baud rate. In Synchronous mode, bit BRGH is ignored. Table 16-1 shows the formula for computation of the baud rate for different USART modes, which only apply in Master mode (internally generated clock). Given the desired baud rate and FOSC, the nearest integer value for the SPBRGH:SPBRG registers can be calculated using the formulas in Table 16-1. From this, the error in baud rate can be determined. An example calculation is shown in Example 16-1. Typical baud rates and error values for the various asynchronous modes are shown in Table 16-2. It may be advantageous to use the high baud rate (BRGH = 1), or the 16-bit BRG to reduce the baud rate error, or achieve a slow baud rate for a fast oscillator frequency. 16.2.1 POWER MANAGED MODE OPERATION The system clock is used to generate the desired baud rate; however, when a Power Managed mode is entered, the clock source may be operating at a different frequency than in PRI_RUN mode. In SLEEP mode, no clocks are present and in PRI_IDLE, the primary clock source continues to provide clocks to the baud rate generator; however, in other Power Managed modes, the clock frequency will probably change. This may require the value in SPBRG to be adjusted. If the system clock is changed during an active receive operation, a receive error or data loss may result. To avoid this problem, check the status of the RCIDL bit and make sure that the receive operation is IDLE before changing the system clock. 16.2.2 SAMPLING The data on the RB4/RX/DT pin is sampled three times by a majority detect circuit to determine if a high or a low level is present at the RX pin. Writing a new value to the SPBRGH:SPBRG registers causes the BRG timer to be reset (or cleared). This ensures the BRG does not wait for a timer overflow before outputting the new baud rate. TABLE 16-1: BAUD RATE FORMULAS Configuration Bits BRG/USART Mode Baud Rate Formula 0 8-bit/Asynchronous FOSC / [64 (n+1)] 0 1 8-bit/Asynchronous 0 1 0 16-bit/Asynchronous 0 1 1 16-bit/Asynchronous 1 0 x 8-bit/Synchronous 1 1 x 16-bit/Synchronous SYNC BRG16 BRGH 0 0 0 FOSC / [16 (n+1)] FOSC / [4 (n+1)] Legend: x = Don't care, n = value of SPBRGH:SPBRG register pair 2002 Microchip Technology Inc. Preliminary DS39605B-page 137 PIC18F1220/1320 EXAMPLE 16-1: CALCULATING BAUD RATE ERROR For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG: Desired Baud Rate = FOSC / (64 ([SPBRGH:SPBRG] + 1)) Solving for SPBRGH:SPBRG: X = ((FOSC / Desired Baud Rate)/64) - 1 = ((16000000 / 9600) / 64) - 1 = [25.042] = 25 Calculated Baud Rate= 16000000 / (64 (25 + 1)) = 9615 Error = (Calculated Baud Rate - Desired Baud Rate) / Desired Baud Rate = (9615 - 9600) / 9600 = 0.16% TABLE 16-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other RESETS TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 -010 0000 -010 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 -00x 0000 -00x -- RCIDL -- SCKP BRG16 -- WUE ABDEN -1-1 0-00 -1-1 0-00 Name BAUDCTL SPBRGH Baud Rate Generator Register, High Byte 0000 0000 0000 0000 SPBRG Baud Rate Generator Register, Low Byte 0000 0000 0000 0000 Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used by the BRG. TABLE 16-3: BAUD RATES FOR ASYNCHRONOUS MODES SYNC = 0, BRGH = 0, BRG16 = 0 BAUD RATE (K) FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz (decimal) % Error -- -- -- -- -- 1.221 2.441 1.73 255 9.615 0.16 64 19.531 1.73 31 57.6 56.818 -1.36 10 62.500 8.51 4 52.083 -9.58 2 -- -- -- 115.2 125.000 8.51 4 104.167 -9.58 2 78.125 -32.18 1 -- -- -- % Error 0.3 1.2 -- -- 2.4 9.6 19.2 SPBRG value (decimal) Actual Rate (K) % Error -- 1.73 -- 255 -- 1.202 2.404 0.16 129 9.766 1.73 31 19.531 1.73 15 FOSC = 8.000 MHz Actual Rate (K) Actual Rate (K) SPBRG value (decimal) Actual Rate (K) % Error -- 0.16 -- 129 -- 1201 -- -0.16 -- 103 2.404 0.16 64 2403 -0.16 51 9.766 1.73 15 9615 -0.16 12 19.531 1.73 7 -- -- -- SPBRG value SPBRG value (decimal) SYNC = 0, BRGH = 0, BRG16 = 0 BAUD RATE (K) FOSC = 4.000 MHz FOSC = 2.000 MHz Actual Rate (K) % Error 207 300 -0.16 51 1201 -0.16 25 2403 -0.16 FOSC = 1.000 MHz Actual Rate (K) % Error 103 300 -0.16 51 25 1201 -0.16 12 12 -- -- -- Actual Rate (K) % Error 0.3 0.300 0.16 1.2 1.202 0.16 2.4 2.404 0.16 9.6 8.929 -6.99 6 -- -- -- -- -- -- 19.2 20.833 8.51 2 -- -- -- -- -- -- SPBRG value (decimal) SPBRG value (decimal) SPBRG value (decimal) 57.6 62.500 8.51 0 -- -- -- -- -- -- 115.2 62.500 -45.75 0 -- -- -- -- -- -- DS39605B-page 138 Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 TABLE 16-3: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1, BRG16 = 0 BAUD RATE (K) FOSC = 40.000 MHz Actual Rate (K) % Error FOSC = 20.000 MHz SPBRG value (decimal) Actual Rate (K) % Error SPBRG value (decimal) FOSC = 10.000 MHz Actual Rate (K) % Error SPBRG value (decimal) FOSC = 8.000 MHz Actual Rate (K) % Error SPBRG value (decimal) 2.4 -- -- -- -- -- -- 2.441 1.73 255 2403 -0.16 9.6 9.766 1.73 255 9.615 0.16 129 9.615 0.16 64 9615 -0.16 207 51 19.2 19.231 0.16 129 19.231 0.16 64 19.531 1.73 31 19230 -0.16 25 57.6 58.140 0.94 42 56.818 -1.36 21 56.818 -1.36 10 55555 3.55 8 115.2 113.636 -1.36 21 113.636 -1.36 10 125.000 8.51 4 -- -- -- SYNC = 0, BRGH = 1, BRG16 = 0 BAUD RATE (K) FOSC = 4.000 MHz FOSC = 2.000 MHz (decimal) Actual Rate (K) % Error -- 0.16 -- 207 -- 1201 -- -0.16 2.404 0.16 103 2403 9.615 0.16 25 9615 19.2 19.231 0.16 12 -- 57.6 62.500 8.51 3 -- 115.2 125.000 8.51 1 -- Actual Rate (K) % Error 0.3 1.2 -- 1.202 2.4 9.6 SPBRG value FOSC = 1.000 MHz (decimal) Actual Rate (K) % Error -- 103 300 1201 -0.16 -0.16 207 51 -0.16 51 2403 -0.16 25 -0.16 12 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- SPBRG value SPBRG value (decimal) SYNC = 0, BRGH = 0, BRG16 = 1 BAUD RATE (K) FOSC = 40.000 MHz FOSC = 20.000 MHz (decimal) Actual Rate (K) % Error 8332 0.300 0.02 0.02 2082 1.200 -0.03 2.402 0.06 1040 2.399 9.615 0.16 259 9.615 19.2 19.231 0.16 129 57.6 58.140 0.94 115.2 113.636 -1.36 Actual Rate (K) % Error 0.3 0.300 0.00 1.2 1.200 2.4 9.6 FOSC = 10.000 MHz (decimal) Actual Rate (K) % Error 4165 0.300 0.02 1041 1.200 -0.03 520 0.16 129 19.231 0.16 42 56.818 21 113.636 SPBRG value FOSC = 8.000 MHz (decimal) Actual Rate (K) % Error 2082 300 -0.04 1665 -0.03 520 1201 -0.16 415 2.404 0.16 259 2403 -0.16 207 9.615 0.16 64 9615 -0.16 51 64 19.531 1.73 31 19230 -0.16 25 -1.36 21 56.818 -1.36 10 55555 3.55 8 -1.36 10 125.000 8.51 4 -- -- -- SPBRG value SPBRG value SPBRG value (decimal) SYNC = 0, BRGH = 0, BRG16 = 1 BAUD RATE (K) FOSC = 4.000 MHz FOSC = 2.000 MHz Actual Rate (K) FOSC = 1.000 MHz Actual Rate (K) Actual Rate (K) % Error 0.3 0.300 0.04 832 300 -0.16 415 300 -0.16 1.2 1.202 0.16 207 1201 -0.16 103 1201 -0.16 51 2.4 2.404 0.16 103 2403 -0.16 51 2403 -0.16 25 9.6 9.615 0.16 25 9615 -0.16 12 -- -- -- 19.2 19.231 0.16 12 -- -- -- -- -- -- SPBRG value (decimal) % Error SPBRG value (decimal) % Error SPBRG value (decimal) 207 57.6 62.500 8.51 3 -- -- -- -- -- -- 115.2 125.000 8.51 1 -- -- -- -- -- -- 2002 Microchip Technology Inc. Preliminary DS39605B-page 139 PIC18F1220/1320 TABLE 16-3: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD RATE (K) FOSC = 40.000 MHz FOSC = 20.000 MHz (decimal) Actual Rate (K) % Error (decimal) % Error 0.00 33332 0.300 0.00 8332 1.200 0.00 16665 0.300 0.00 0.02 4165 1.200 0.02 2.400 0.02 4165 2.400 0.02 2082 2.402 9.6 9.606 0.06 1040 9.596 -0.03 520 19.2 19.193 -0.03 520 19.231 0.16 259 % Error 0.3 0.300 1.2 1.200 2.4 SPBRG value SPBRG value FOSC = 10.000 MHz Actual Rate (K) Actual Rate (K) FOSC = 8.000 MHz SPBRG value Actual Rate (K) % Error 8332 300 -0.01 6665 2082 1200 -0.04 1665 0.06 1040 2400 -0.04 832 9.615 0.16 259 9615 -0.16 207 19.231 0.16 129 19230 -0.16 103 (decimal) SPBRG value (decimal) 57.6 57.803 0.35 172 57.471 -0.22 86 58.140 0.94 42 57142 0.79 34 115.2 114.943 -0.22 86 116.279 0.94 42 113.636 -1.36 21 117647 -2.12 16 SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD RATE (K) FOSC = 4.000 MHz FOSC = 2.000 MHz (decimal) Actual Rate (K) % Error 0.01 0.04 3332 832 300 1201 2.404 0.16 415 9.615 0.16 103 19.2 19.231 0.16 57.6 58.824 2.12 115.2 111.111 -3.55 Actual Rate (K) % Error 0.3 1.2 0.300 1.200 2.4 9.6 DS39605B-page 140 FOSC = 1.000 MHz (decimal) Actual Rate (K) % Error -0.04 -0.16 1665 415 300 1201 -0.04 -0.16 832 207 2403 -0.16 207 2403 -0.16 103 9615 -0.16 51 9615 -0.16 25 51 19230 -0.16 25 19230 -0.16 12 16 55555 3.55 8 -- -- -- 8 -- -- -- -- -- -- SPBRG value SPBRG value Preliminary SPBRG value (decimal) 2002 Microchip Technology Inc. PIC18F1220/1320 16.2.3 AUTO BAUD RATE DETECT The Enhanced USART module supports the automatic detection and calibration of baud rate. This feature is active only in Asynchronous mode and while the WUE bit is clear. The automatic baud rate measurement sequence (Figure 16-1) begins whenever a START bit is received and the ABDEN bit is set. The calculation is self-averaging. carry occurred for 8-bit modes, by checking for 00h in the SPBRGH register. Refer to Table 16-4 for counter clock rates to the BRG. While the ABD sequence takes place, the USART state machine is held in IDLE. The RCIF interrupt is set once the fifth rising edge on RX is detected. The value in the RCREG needs to be read to clear the RCIF interrupt. RCREG content should be discarded. Note 1: If the WUE bit is set with the ABDEN bit, auto baud rate detection will occur on the byte following the Break character (see Section 16.3.4). In the Auto Baud Rate Detect (ABD) mode, the clock to the BRG is reversed. Rather than the BRG clocking the incoming RX signal, the RX signal is timing the BRG. In ABD mode, the internal Baud Rate Generator is used as a counter to time the bit period of the incoming serial byte stream. Once the ABDEN bit is set, the state machine will clear the BRG and look for a START bit. The Auto Baud Detect must receive a byte with the value 55h (ASCII "U", which is also the LIN bus Sync character), in order to calculate the proper bit rate. The measurement is taken over both a low and a high bit time in order to minimize any effects caused by asymmetry of the incoming signal. After a START bit, the SPBRG begins counting up using the preselected clock source on the first rising edge of RX. After eight bits on the RX pin, or the fifth rising edge, an accumulated value totalling the proper BRG period is left in the SPBRGH:SPBRG registers. Once the 5th edge is seen (should correspond to the STOP bit), the ABDEN bit is automatically cleared. 2: It is up to the user to determine that the incoming character baud rate is within the range of the selected BRG clock source. Some combinations of oscillator frequency and USART baud rates are not possible due to bit error rates. Overall system timing and communication baud rates must be taken into consideration when using the Auto Baud Rate Detection feature. TABLE 16-4: While calibrating the baud rate period, the BRG registers are clocked at 1/8th the pre-configured clock rate. Note that the BRG clock will be configured by the BRG16 and BRGH bits. Independent of the BRG16 bit setting, both the SPBRG and SPBRGH will be used as a 16-bit counter. This allows the user to verify that no FIGURE 16-1: BRG Value BRG COUNTER CLOCK RATES BRG16 BRGH BRG Counter Clock 0 0 FOSC/512 0 1 FOSC/128 1 0 FOSC/128 1 1 FOSC/32 Note: During the ABD sequence, SPBRG and SPBRGH are both used as a 16-bit counter, independent of BRG16 setting. AUTOMATIC BAUD RATE CALCULATION XXXXh RX pin 0000h 001Ch START Edge #1 Bit 1 Bit 0 Edge #2 Bit 3 Bit 2 Edge #3 Bit 5 Bit 4 Edge #4 Bit 7 Bit 6 Edge #5 STOP Bit BRG Clock Auto Cleared Set by User ABDEN bit RCIF bit (Interrupt) Read RCREG SPBRG XXXXh 1Ch SPBRGH XXXXh 00h Note 1: The ABD sequence requires the USART module to be configured in Asynchronous mode and WUE = 0. 2002 Microchip Technology Inc. Preliminary DS39605B-page 141 PIC18F1220/1320 16.3 USART Asynchronous Mode The Asynchronous mode of operation is selected by clearing the SYNC bit (TXSTA<4>). In this mode, the USART uses standard non-return-to-zero (NRZ) format (one START bit, eight or nine data bits and one STOP bit). The most common data format is 8 bits. An on-chip dedicated 8-bit/16-bit baud rate generator can be used to derive standard baud rate frequencies from the oscillator. The USART transmits and receives the LSb first. The USART's transmitter and receiver are functionally independent, but use the same data format and baud rate. The baud rate generator produces a clock, either x16 or x64 of the bit shift rate, depending on the BRGH and BRG16 bits (TXSTA<2> and BAUDCTL<3>). Parity is not supported by the hardware, but can be implemented in software and stored as the 9th data bit. Asynchronous mode is available in all Low Power modes; it is available in SLEEP mode only when Auto Wake-up on Sync Break is enabled. When in PRI_IDLE mode, no changes to the baud rate generator values are required; however, other Low Power mode clocks may operate at another frequency than the primary clock. Therefore, the baud rate generator values may need to be adjusted. Once the TXREG register transfers the data to the TSR register (occurs in one TCY), the TXREG register is empty and flag bit TXIF (PIR1<4>) is set. This interrupt can be enabled/disabled by setting/clearing enable bit TXIE (PIE1<4>). Flag bit TXIF will be set, regardless of the state of enable bit TXIE and cannot be cleared in software. Flag bit TXIF is not cleared immediately upon loading the transmit buffer register TXREG. TXIF becomes valid in the second instruction cycle following the load instruction. Polling TXIF immediately following a load of TXREG will return invalid results. While flag bit TXIF indicates the status of the TXREG register, another bit, TRMT (TXSTA<1>), shows the status of the TSR register. Status bit TRMT is a read only bit, which is set when the TSR register is empty. No interrupt logic is tied to this bit, so the user has to poll this bit in order to determine if the TSR register is empty. Note 1: The TSR register is not mapped in data memory, so it is not available to the user. 2: Flag bit TXIF is set when enable bit TXEN is set. To set up an Asynchronous Transmission: 1. When operating in Asynchronous mode, the USART module consists of the following important elements: * * * * * * * Baud Rate Generator Sampling Circuit Asynchronous Transmitter Asynchronous Receiver Auto Wake-up on Sync Break Character 12-bit Break Character Transmit Auto Baud Rate Detection 16.3.1 2. 3. 4. 5. 6. USART ASYNCHRONOUS TRANSMITTER 7. The USART transmitter block diagram is shown in Figure 16-2. The heart of the transmitter is the Transmit (serial) Shift Register (TSR). The shift register obtains its data from the read/write transmit buffer, TXREG. The TXREG register is loaded with data in software. The TSR register is not loaded until the STOP bit has been transmitted from the previous load. As soon as the STOP bit is transmitted, the TSR is loaded with new data from the TXREG register (if available). DS39605B-page 142 Initialize the SPBRGH:SPBRG registers for the appropriate baud rate. Set or clear the BRGH and BRG16 bits, as required, to achieve the desired baud rate. Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. If interrupts are desired, set enable bit TXIE. If 9-bit transmission is desired, set transmit bit TX9. Can be used as address/data bit. Enable the transmission by setting bit TXEN, which will also set bit TXIF. If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. Load data to the TXREG register (starts transmission). If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 FIGURE 16-2: USART TRANSMIT BLOCK DIAGRAM Data Bus TXIF TXREG Register TXIE 8 MSb LSb (8) 0 * * * RB1/AN5/TX/CK/INT1 pin Pin Buffer and Control TSR Register Interrupt Baud Rate CLK TXEN TRMT BRG16 SPBRGH SPEN SPBRG TX9 Baud Rate Generator TX9D FIGURE 16-3: Write to TXREG BRG Output (Shift Clock) ASYNCHRONOUS TRANSMISSION Word 1 RB1/AN5/TX/ CK/INT1 (pin) START bit FIGURE 16-4: bit 1 bit 7/8 STOP bit Word 1 TXIF bit (Transmit Buffer Reg. Empty Flag) TRMT bit (Transmit Shift Reg. Empty Flag) bit 0 1 TCY Word 1 Transmit Shift Reg ASYNCHRONOUS TRANSMISSION (BACK TO BACK) Write to TXREG BRG Output (Shift Clock) Word 1 RB1/AN5/TX/ CK/INT1 (pin) TXIF bit (Interrupt Reg. Flag) TRMT bit (Transmit Shift Reg. Empty Flag) Note: Word 2 START bit bit 0 1 TCY bit 1 Word 1 bit 7/8 STOP bit START bit bit 0 Word 2 1 TCY Word 1 Transmit Shift Reg. Word 2 Transmit Shift Reg. This timing diagram shows two consecutive transmissions. 2002 Microchip Technology Inc. Preliminary DS39605B-page 143 PIC18F1220/1320 TABLE 16-5: Name REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other RESETS 0000 000u GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x PIR1 -- ADIF RCIF TXIF -- CCP1IF TMR2IF TMR1IF -000 -000 -000 -000 PIE1 -- ADIE RCIE TXIE -- CCP1IE TMR2IE TMR1IE -000 -000 -000 -000 -- ADIP RCIP TXIP -- CCP1IP TMR2IP TMR1IP -000 -000 -000 -000 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 -00x 0000 -00x 0000 0000 0000 0000 INTCON IPR1 RCSTA TXREG TXSTA BAUDCTL USART Transmit Register CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010 -- RCIDL -- SCKP BRG16 -- WUE ABDEN -1-1 0-00 -1-1 0-00 SPBRGH Baud Rate Generator Register, High Byte 0000 0000 0000 0000 SPBRG Baud Rate Generator Register, Low Byte 0000 0000 0000 0000 Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for Asynchronous Transmission. DS39605B-page 144 Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 16.3.2 USART ASYNCHRONOUS RECEIVER 16.3.3 The receiver block diagram is shown in Figure 16-5. The data is received on the RB4/AN6/RX/DT/KBI0 pin and drives the data recovery block. The data recovery block is actually a high speed shifter operating at x16 times the baud rate, whereas the main receive serial shifter operates at the bit rate or at FOSC. This mode would typically be used in RS-232 systems. This mode would typically be used in RS-485 systems. To set up an Asynchronous Reception with Address Detect Enable: 1. Initialize the SPBRGH:SPBRG registers for the appropriate baud rate. Set or clear the BRGH and BRG16 bits, as required, to achieve the desired baud rate. 2. Enable the asynchronous serial port by clearing the SYNC bit and setting the SPEN bit. 3. If interrupts are required, set the RCEN bit and select the desired priority level with the RCIP bit. 4. Set the RX9 bit to enable 9-bit reception. 5. Set the ADDEN bit to enable address detect. 6. Enable reception by setting the CREN bit. 7. The RCIF bit will be set when reception is complete. The interrupt will be Acknowledged if the RCIE and GIE bits are set. 8. Read the RCSTA register to determine if any error occurred during reception, as well as read bit 9 of data (if applicable). 9. Read RCREG to determine if the device is being addressed. 10. If any error occurred, clear the CREN bit. 11. If the device has been addressed, clear the ADDEN bit to allow all received data into the receive buffer and interrupt the CPU. To set up an Asynchronous Reception: 1. Initialize the SPBRGH:SPBRG registers for the appropriate baud rate. Set or clear the BRGH and BRG16 bits, as required, to achieve the desired baud rate. 2. Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. 3. If interrupts are desired, set enable bit RCIE. 4. If 9-bit reception is desired, set bit RX9. 5. Enable the reception by setting bit CREN. 6. Flag bit RCIF will be set when reception is complete and an interrupt will be generated if enable bit RCIE was set. 7. Read the RCSTA register to get the 9th bit (if enabled) and determine if any error occurred during reception. 8. Read the 8-bit received data by reading the RCREG register. 9. If any error occurred, clear the error by clearing enable bit CREN. 10. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. FIGURE 16-5: SETTING UP 9-BIT MODE WITH ADDRESS DETECT USART RECEIVE BLOCK DIAGRAM CREN OERR FERR x64 Baud Rate CLK BRG16 SPBRGH SPBRG Baud Rate Generator / 64 or / 16 or /4 RSR Register MSb STOP (8) 7 * * * 1 LSb 0 START RX9 RB4/AN6/RX/DT/KBI0 Pin Buffer and Control Data Recovery RX9D RCREG Register FIFO SPEN 8 Interrupt RCIF Data Bus RCIE 2002 Microchip Technology Inc. Preliminary DS39605B-page 145 PIC18F1220/1320 To set up an Asynchronous Transmission: 1. 2. 3. 4. 5. Initialize the SPBRG register for the appropriate baud rate. If a high speed baud rate is desired, set bit BRGH (see Section 16.2). Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. If interrupts are desired, set enable bit TXIE. If 9-bit transmission is desired, set transmit bit TX9. Can be used as address/data bit. FIGURE 16-6: Enable the transmission by setting bit TXEN, which will also set bit TXIF. If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. Load data to the TXREG register (starts transmission). 6. 7. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. ASYNCHRONOUS RECEPTION START bit bit0 RX (pin) bit1 bit7/8 STOP bit Rcv Shift Reg Rcv Buffer Reg START bit bit0 bit7/8 STOP bit bit7/8 STOP bit Word 2 RCREG Word 1 RCREG Read Rcv Buffer Reg RCREG START bit RCIF (Interrupt Flag) OERR bit CREN Note: This timing diagram shows three words appearing on the RX input. causing the OERR (overrun) bit to be set. TABLE 16-6: Name INTCON The RCREG (receive buffer) is read after the third word, REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other RESETS 0000 000u GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x PIR1 -- ADIF RCIF TXIF -- CCP1IF TMR2IF TMR1IF -000 -000 -000 -000 PIE1 -- ADIE RCIE TXIE -- CCP1IE TMR2IE TMR1IE -000 -000 -000 -000 -- ADIP RCIP TXIP -- CCP1IP TMR2IP TMR1IP SPEN RX9 SREN CREN ADDEN FERR OERR RX9D IPR1 RCSTA RCREG TXSTA BAUDCTL USART Receive Register -000 -000 -000 -000 0000 -00x 0000 -00x 0000 0000 0000 0000 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010 -- RCIDL -- SCKP BRG16 -- WUE ABDEN -1-1 0-00 -1-1 0-00 SPBRGH Baud Rate Generator Register, High Byte 0000 0000 0000 0000 SPBRG Baud Rate Generator Register, Low Byte 0000 0000 0000 0000 Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for Asynchronous Reception. DS39605B-page 146 Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 16.3.4 AUTO WAKE-UP ON SYNC BREAK CHARACTER During SLEEP mode, all clocks to the USART are suspended. Because of this, the baud rate generator is inactive and a proper byte reception cannot be performed. The Auto Wake-up feature allows the controller to wake-up due to activity on the RX/DT line, while the USART is operating in Asynchronous mode. The Auto Wake-up feature is enabled by setting the WUE bit (BAUDCTL<1>). Once set, the typical receive sequence on RX/DT is disabled, and the USART remains in an IDLE state, monitoring for a wake-up event independent of the CPU mode. A wake-up event consists of a high-to-low transition on the RX/DT line. (This coincides with the start of a Sync Break or a Wake-up Signal character for the LIN protocol.) and cause data or framing errors. To work properly, therefore, the initial character in the transmission must be all `0's. This can be 00h (8 bytes) for standard RS-232 devices, or 000h (12 bits) for LIN bus. Oscillator start-up time must also be considered, especially in applications using oscillators with longer start-up intervals (i.e., XT or HS mode). The Sync Break (or Wake-up Signal) character must be of sufficient length, and be followed by a sufficient interval, to allow enough time for the selected oscillator to start and provide proper initialization of the USART. 16.3.4.2 Special Considerations Using the WUE Bit Following a wake-up event, the module generates an RCIF interrupt. The interrupt is generated synchronously to the Q clocks in normal Operating modes (Figure 16-7), and asynchronously if the device is in SLEEP mode (Figure 16-8). The interrupt condition is cleared by reading the RCREG register. The timing of WUE and RCIF events may cause some confusion when it comes to determining the validity of received data. As noted, setting the WUE bit places the USART in an IDLE mode. The wake-up event causes a receive interrupt by setting the RCIF bit. The WUE bit is cleared after this when a rising edge is seen on RX/DT. The interrupt condition is then cleared by reading the RCREG register. Ordinarily, the data in RCREG will be dummy data and should be discarded. The WUE bit is automatically cleared once a low-to-high transition is observed on the RX line, following the wake-up event. At this point, the USART module is in IDLE mode and returns to normal operation. This signals to the user that the Sync Break event is over. The fact that the WUE bit has been cleared (or is still set) and the RCIF flag is set should not be used as an indicator of the integrity of the data in RCREG. Users should consider implementing a parallel method in firmware to verify received data integrity. 16.3.4.1 To assure that no actual data is lost, check the RCIDL bit to verify that a receive operation is not in process. If a receive operation is not occurring, the WUE bit may then be set just prior to entering the SLEEP mode. Special Considerations Using Auto Wake-up Since Auto Wake-up functions by sensing rising edge transitions on RX/DT, information with any state changes before the STOP bit may signal a false end-of-character FIGURE 16-7: AUTO WAKE-UP BIT (WUE) TIMINGS DURING NORMAL OPERATION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Auto Cleared Bit Set by User WUE bit RX/DT Line RCIF Note 1: Cleared due to User Read of RCREG The USART remains in IDLE while the WUE bit is set. FIGURE 16-8: AUTO WAKE-UP BIT (WUE) TIMINGS DURING SLEEP Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Auto Cleared Bit Set by User WUE bit RX/DT Line Note 1 RCIF SLEEP Command Executed Note 1: 2: SLEEP Ends Cleared due to User Read of RCREG If the wake-up event requires long oscillator warm-up time, the auto clear of the WUE bit can occur while the stposc signal is still active. This sequence should not depend on the presence of Q clocks. The USART remains in IDLE while the WUE bit is set. 2002 Microchip Technology Inc. Preliminary DS39605B-page 147 PIC18F1220/1320 16.3.5 BREAK CHARACTER SEQUENCE The Enhanced USART module has the capability of sending the special Break character sequences that are required by the LIN bus standard. The Break character transmit consists of a START bit, followed by 12 `0' bits and a STOP bit. The frame Break character is sent whenever the SENDB and TXEN bits (TXSTA<3> and TXSTA<5>) are set, while the transmit shift register is loaded with data. Note that the value of data written to TXREG will be ignored and all `0's will be transmitted. The SENDB bit is automatically reset by hardware after the corresponding STOP bit is sent. This allows the user to preload the transmit FIFO with the next transmit byte following the Break character (typically, the Sync character in the LIN specification). Note that the data value written to the TXREG for the Break character is ignored. The write simply serves the purpose of initiating the proper sequence. The TRMT bit indicates when the transmit operation is active or IDLE, just as it does during normal transmission. See Figure 16-9 for the timing of the Break character sequence. 16.3.5.1 Break and Sync Transmit Sequence The following sequence will send a message frame header made up of a Break, followed by an auto baud Sync byte. This sequence is typical of a LIN bus master. 1. 2. 3. 4. 5. Configure the USART for the desired mode. Set the TXEN and SENDB bits to setup the Break character. Load the TXREG with a dummy character to initiate transmission (the value is ignored). Write `55h' to TXREG to load the Sync character into the transmit FIFO buffer. After the Break has been sent, the SENDB bit is reset by hardware. The Sync character now transmits in the Pre-Configured mode. When the TXREG becomes empty, as indicated by the TXIF, the next data byte can be written to TXREG. 16.3.6 RECEIVING A BREAK CHARACTER The Enhanced USART module can receive a Break character in two ways. The first method forces to configure the baud rate at a frequency of 9/13 the typical speed. This allows for the STOP bit transition to be at the correct sampling location (13 bits for Break versus START bit and 8 data bits for typical data). The second method uses the Auto Wake-up feature described in Section 16.3.4. By enabling this feature, the USART will sample the next two transitions on RX/DT, cause an RCIF interrupt, and receive the next data byte followed by another interrupt. Note that following a Break character, the user will typically want to enable the Auto Baud Rate detect feature. For both methods, the user can set the ABD bit once the TXIF interrupt is observed. FIGURE 16-9: Write to TXREG SEND BREAK CHARACTER SEQUENCE Dummy Write BRG Output (Shift Clock) TX (pin) START Bit Bit 0 Bit 1 Bit 11 STOP Bit Break TXIF bit (Transmit Buffer Reg. Empty Flag) TRMT bit (Transmit Shift Reg. Empty Flag) SENDB Sampled Here Auto Cleared SENDB (Transmit Shift Reg. Empty Flag) DS39605B-page 148 Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 16.4 USART Synchronous Master Mode Once the TXREG register transfers the data to the TSR register (occurs in one TCYCLE), the TXREG is empty and interrupt bit TXIF (PIR1<4>) is set. The interrupt can be enabled/disabled by setting/clearing enable bit TXIE (PIE1<4>). Flag bit TXIF will be set, regardless of the state of enable bit TXIE, and cannot be cleared in software. It will reset only when new data is loaded into the TXREG register. The Synchronous Master mode is entered by setting the CSRC bit (TXSTA<7>). In this mode, the data is transmitted in a half-duplex manner (i.e., transmission and reception do not occur at the same time). When transmitting data, the reception is inhibited and vice versa. Synchronous mode is entered by setting bit SYNC (TXSTA<4>). In addition, enable bit SPEN (RCSTA<7>) is set in order to configure the RB1/AN5/TX/CK/INT1 and RB4/AN6/RX/DT/KBI0 I/O pins to CK (clock) and DT (data) lines, respectively. While flag bit TXIF indicates the status of the TXREG register, another bit, TRMT (TXSTA<1>), shows the status of the TSR register. TRMT is a read only bit, which is set when the TSR is empty. No interrupt logic is tied to this bit, so the user has to poll this bit in order to determine if the TSR register is empty. The TSR is not mapped in data memory, so it is not available to the user. The Master mode indicates that the processor transmits the master clock on the CK line. Clock polarity is selected with the SCKP bit (BAUDCTL<5>); setting SCKP sets the IDLE state on CK as high, while clearing the bit sets the IDLE state is low. This option is provided to support Microwire(R) devices with this module. 16.4.1 To set up a Synchronous Master Transmission: 1. USART SYNCHRONOUS MASTER TRANSMISSION 2. The USART transmitter block diagram is shown in Figure 16-2. The heart of the transmitter is the Transmit (serial) Shift Register (TSR). The shift register obtains its data from the read/write transmit buffer register TXREG. The TXREG register is loaded with data in software. The TSR register is not loaded until the last bit has been transmitted from the previous load. As soon as the last bit is transmitted, the TSR is loaded with new data from the TXREG (if available). 3. 4. 5. 6. 7. 8. FIGURE 16-10: Initialize the SPBRGH:SPBRG registers for the appropriate baud rate. Set or clear the BRGH and BRG16 bits, as required, to achieve the desired baud rate. Enable the synchronous master serial port by setting bits SYNC, SPEN, and CSRC. If interrupts are desired, set enable bit TXIE. If 9-bit transmission is desired, set bit TX9. Enable the transmission by setting bit TXEN. If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. Start transmission by loading data to the TXREG register. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. SYNCHRONOUS TRANSMISSION Q1 Q2 Q3Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 RB4/AN6/RX/ DT/KBI0 pin bit 0 bit 1 bit 2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 bit 7 RB1/AN5/TX/ CK/INT1 pin (SCKP = 0) RB1/AN5/TX/ CK/INT1 pin (SCKP = 1) Write to TXREG Reg Write Word 1 bit 0 bit 1 bit 7 Word 2 Word 1 Write Word 2 TXIF bit (Interrupt Flag) TRMT bit TXEN bit Note: '1' '1' Sync Master mode, SPBRG = '0', continuous transmission of two 8-bit words. 2002 Microchip Technology Inc. Preliminary DS39605B-page 149 PIC18F1220/1320 FIGURE 16-11: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RB4/AN6/RX/DT/KBI0 pin bit0 bit2 bit1 bit6 bit7 RB1/AN5/TX/CK/INT1 pin Write to TXREG reg TXIF bit TRMT bit TXEN bit TABLE 16-7: Name INTCON REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Bit 7 Bit 6 Bit 5 GIE/GIEH PEIE/GIEL TMR0IE Bit 4 Bit 3 Bit 2 Bit 1 Value on POR, BOR Bit 0 Value on all other RESETS INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u PIR1 -- ADIF RCIF TXIF -- CCP1IF TMR2IF TMR1IF -000 -000 -000 -000 PIE1 -- ADIE RCIE TXIE -- CCP1IE TMR2IE TMR1IE -000 -000 -000 -000 IPR1 -- ADIP RCIP TXIP -- CCP1IP TMR2IP TMR1IP -000 -000 -000 -000 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 -00x 0000 -00x 0000 0000 0000 0000 RCSTA TXREG TXSTA BAUDCTL USART Transmit Register CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010 -- RCIDL -- SCKP BRG16 -- WUE ABDEN -1-1 0-00 -1-1 0-00 SPBRGH Baud Rate Generator Register, High Byte 0000 0000 0000 0000 SPBRG Baud Rate Generator Register, Low Byte 0000 0000 0000 0000 Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for Synchronous Master Transmission. DS39605B-page 150 Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 16.4.2 USART SYNCHRONOUS MASTER RECEPTION 3. 4. 5. 6. Ensure bits CREN and SREN are clear. If interrupts are desired, set enable bit RCIE. If 9-bit reception is desired, set bit RX9. If a single reception is required, set bit SREN. For continuous reception, set bit CREN. 7. Interrupt flag bit RCIF will be set when reception is complete and an interrupt will be generated if the enable bit RCIE was set. 8. Read the RCSTA register to get the 9th bit (if enabled) and determine if any error occurred during reception. 9. Read the 8-bit received data by reading the RCREG register. 10. If any error occurred, clear the error by clearing bit CREN. 11. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. Once Synchronous mode is selected, reception is enabled by setting either the Single Receive Enable bit SREN (RCSTA<5>), or the Continuous Receive Enable bit CREN (RCSTA<4>). Data is sampled on the RB4/AN6/RX/DT/KBI0 pin on the falling edge of the clock. If enable bit SREN is set, only a single word is received. If enable bit CREN is set, the reception is continuous until CREN is cleared. If both bits are set, then CREN takes precedence. To set up a Synchronous Master Reception: 1. 2. Initialize the SPBRGH:SPBRG registers for the appropriate baud rate. Set or clear the BRGH and BRG16 bits, as required, to achieve the desired baud rate. Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC. FIGURE 16-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 RB4/AN6/RX/ DT/KBI0 pin bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 RB1/AN5/TX/ CK/INT1 pin (SCKP = 0) RB1/AN5/TX/ CK/INT1 pin (SCKP = 1) Write to bit SREN SREN bit CREN bit '0' '0' RCIF bit (Interrupt) Read RXREG Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0. 2002 Microchip Technology Inc. Preliminary DS39605B-page 151 PIC18F1220/1320 TABLE 16-8: Name REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other RESETS TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u PIR1 -- ADIF RCIF TXIF -- CCP1IF TMR2IF TMR1IF -000 -000 -000 -000 PIE1 -- ADIE RCIE TXIE -- CCP1IE TMR2IE TMR1IE -000 -000 -000 -000 IPR1 -- ADIP RCIP TXIP -- CCP1IP TMR2IP TMR1IP -000 -000 -000 -000 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 -00x 0000 -00x 0000 0000 0000 0000 INTCON RCSTA RCREG TXSTA BAUDCTL GIE/GIEH PEIE/GIEL USART Receive Register CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010 -- RCIDL -- SCKP BRG16 -- WUE ABDEN -1-1 0-00 -1-1 0-00 SPBRGH Baud Rate Generator Register, High Byte 0000 0000 0000 0000 SPBRG Baud Rate Generator Register, Low Byte 0000 0000 0000 0000 Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for Synchronous Master Reception. DS39605B-page 152 Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 16.5 USART Synchronous Slave Mode To set up a Synchronous Slave Transmission: 1. Synchronous Slave mode is entered by clearing bit CSRC (TXSTA<7>). This mode differs from the Synchronous Master mode in that the shift clock is supplied externally at the RB1/AN5/TX/CK/INT1 pin (instead of being supplied internally in Master mode). This allows the device to transfer or receive data while in any Low Power mode. 16.5.1 Enable the synchronous slave serial port by setting bits SYNC and SPEN and clearing bit CSRC. Clear bits CREN and SREN. If interrupts are desired, set enable bit TXIE. If 9-bit transmission is desired, set bit TX9. Enable the transmission by setting enable bit TXEN. If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. Start transmission by loading data to the TXREG register. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. 2. 3. 4. 5. USART SYNCHRONOUS SLAVE TRANSMIT 6. The operation of the Synchronous Master and Slave modes are identical, except in the case of the SLEEP mode. 7. 8. If two words are written to the TXREG and then the SLEEP instruction is executed, the following will occur: a) b) c) d) e) The first word will immediately transfer to the TSR register and transmit. The second word will remain in TXREG register. Flag bit TXIF will not be set. When the first word has been shifted out of TSR, the TXREG register will transfer the second word to the TSR and flag bit TXIF will now be set. If enable bit TXIE is set, the interrupt will wake the chip from SLEEP. If the global interrupt is enabled, the program will branch to the interrupt vector. TABLE 16-9: Name INTCON REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other RESETS GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u PIR1 -- ADIF RCIF TXIF -- CCP1IF TMR2IF TMR1IF -000 -000 -000 -000 PIE1 -- ADIE RCIE TXIE -- CCP1IE TMR2IE TMR1IE -000 -000 -000 -000 IPR1 -- ADIP RCIP TXIP -- CCP1IP TMR2IP TMR1IP -000 -000 -000 -000 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 -00x 0000 -00x 0000 0000 0000 0000 RCSTA TXREG TXSTA BAUDCTL USART Transmit Register CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010 -- RCIDL -- SCKP BRG16 -- WUE ABDEN -1-1 0-00 -1-1 0-00 SPBRGH Baud Rate Generator Register, High Byte 0000 0000 0000 0000 SPBRG Baud Rate Generator Register, Low Byte 0000 0000 0000 0000 Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for Synchronous Slave Transmission. 2002 Microchip Technology Inc. Preliminary DS39605B-page 153 PIC18F1220/1320 16.5.2 USART SYNCHRONOUS SLAVE RECEPTION To set up a Synchronous Slave Reception: 1. The operation of the Synchronous Master and Slave modes is identical, except in the case of SLEEP, or any IDLE mode and bit SREN, which is a "don't care" in Slave mode. Enable the synchronous master serial port by setting bits SYNC and SPEN and clearing bit CSRC. If interrupts are desired, set enable bit RCIE. If 9-bit reception is desired, set bit RX9. To enable reception, set enable bit CREN. Flag bit RCIF will be set when reception is complete. An interrupt will be generated if enable bit RCIE was set. Read the RCSTA register to get the 9th bit (if enabled) and determine if any error occurred during reception. Read the 8-bit received data by reading the RCREG register. If any error occurred, clear the error by clearing bit CREN. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. 2. 3. 4. 5. If receive is enabled by setting the CREN bit prior to entering SLEEP or any IDLE mode, then a word may be received while in this Low Power mode. Once the word is received, the RSR register will transfer the data to the RCREG register; if the RCIE enable bit is set, the interrupt generated will wake the chip from Low Power mode. If the global interrupt is enabled, the program will branch to the interrupt vector. 6. 7. 8. 9. TABLE 16-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other RESETS 0000 000u GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x PIR1 -- ADIF RCIF TXIF -- CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 -- ADIE RCIE TXIE -- CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 -- ADIP RCIP TXIP -- CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 -00x 0000 -00x INTCON RCSTA RCREG TXSTA BAUDCTL USART Receive Register 0000 0000 0000 0000 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010 -- RCIDL -- SCKP BRG16 -- WUE ABDEN -1-1 0-00 -1-1 0-00 SPBRGH Baud Rate Generator Register, High Byte 0000 0000 0000 0000 SPBRG Baud Rate Generator Register, Low Byte 0000 0000 0000 0000 Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for Synchronous Slave Reception. DS39605B-page 154 Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 17.0 10-BIT ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE The module has five registers: * * * * * The Analog-to-Digital (A/D) converter module has 7 inputs for the PIC18F1220/1320 devices. This module allows conversion of an analog input signal to a corresponding 10-bit digital number. A new feature for the A/D converter is the addition of programmable acquisition time. This feature allows the user to select a new channel for conversion and setting the GO/DONE bit immediately. When the GO/DONE bit is set, the selected channel is sampled for the programmed acquisition time before a conversion is actually started. This removes the firmware overhead that may have been required to allow for an acquisition (sampling) period (see Register 17-3 and Section 17.3). REGISTER 17-1: A/D Result High Register (ADRESH) A/D Result Low Register (ADRESL) A/D Control Register 0 (ADCON0) A/D Control Register 1 (ADCON1) A/D Control Register 2 (ADCON2) The ADCON0 register, shown in Register 17-1, controls the operation of the A/D module. The ADCON1 register, shown in Register 17-2, configures the functions of the port pins. The ADCON2 register, shown in Register 17-3, configures the A/D clock source, programmed acquisition time and justification. ADCON0 REGISTER R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 VCFG1 VCFG0 -- CHS2 CHS1 CHS0 GO/DONE ADON bit 7 bit 7-6 bit 0 VCFG<1:0>: Voltage Reference Configuration bits A/D VREF+ A/D VREF- 00 AVDD AVSS 01 External VREF+ AVSS 10 AVDD External VREF- 11 External VREF+ External VREF- bit 5 Unimplemented: Read as '0' bit 4-3 CHS2:CHS0: Analog Channel Select bits 000 = Channel 0 (AN0) 001 = Channel 1 (AN1) 010 = Channel 2 (AN2) 011 = Channel 3 (AN3) 100 = Channel 4 (AN4) 101 = Channel 5 (AN5) 110 = Channel 6 (AN6) 111 = Unimplemented(1) bit 1 GO/DONE: A/D Conversion Status bit When ADON = 1: 1 = A/D conversion in progress 0 = A/D IDLE bit 0 ADON: A/D On bit 1 = A/D converter module is enabled 0 = A/D converter module is disabled Note 1: Performing a conversion on unimplemented channels returns full scale results. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR `1' = Bit is set `0' = Bit is cleared 2002 Microchip Technology Inc. Preliminary x = Bit is unknown DS39605B-page 155 PIC18F1220/1320 REGISTER 17-2: ADCON1 - A/D CONTROL REGISTER 1 U-0 -- bit 7 R/W-0 PCFG6 R/W-0 PCFG5 R/W-0 PCFG4 R/W-0 PCFG3 R/W-0 PCFG2 R/W-0 PCFG1 bit 7 Unimplemented: Read as `0' bit 6 PCFG6: A/D Port Configuration bit - AN6 1 = Pin configured as a digital port 0 = Pin configured as an analog channel - digital input disabled and reads `0' bit 5 PCFG5: A/D Port Configuration bit - AN5 1 = Pin configured as a digital port 0 = Pin configured as an analog channel - digital input disabled and reads `0' bit 4 PCFG4: A/D Port Configuration bit - AN4 1 = Pin configured as a digital port 0 = Pin configured as an analog channel - digital input disabled and reads `0' bit 3 PCFG3: A/D Port Configuration bit - AN3 1 = Pin configured as a digital port 0 = Pin configured as an analog channel - digital input disabled and reads `0' bit 2 PCFG2: A/D Port Configuration bit - AN2 1 = Pin configured as a digital port 0 = Pin configured as an analog channel - digital input disabled and reads `0' bit 1 PCFG1: A/D Port Configuration bit - AN1 1 = Pin configured as a digital port 0 = Pin configured as an analog channel - digital input disabled and reads `0' bit 0 PCFG0: A/D Port Configuration bit - AN0 1 = Pin configured as a digital port 0 = Pin configured as an analog channel - digital input disabled and reads `0' R/W-0 PCFG0 bit 0 Legend: DS39605B-page 156 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared Preliminary x = Bit is unknown 2002 Microchip Technology Inc. PIC18F1220/1320 REGISTER 17-3: ADCON2 REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADFM -- ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 bit 7 bit 0 bit 7 ADFM: A/D Result Format Select bit 1 = Right justified 0 = Left justified bit 6 Unimplemented: Read as '0' bit 5-3 ACQT2:ACQT0: A/D Acquisition Time Select bits 000 = 0 TAD(1) 001 = 2 TAD 010 = 4 TAD 011 = 6 TAD 100 = 8 TAD 101 = 12 TAD 110 = 16 TAD 111 = 20 TAD bit 2-0 ADCS2:ADCS0: A/D Conversion Clock Select bits 000 = FOSC/2 001 = FOSC/8 010 = FOSC/32 011 = FRC (clock derived from A/D RC oscillator)(1) 100 = FOSC/4 101 = FOSC/16 110 = FOSC/64 111 = FRC (clock derived from A/D RC oscillator)(1) Note 1: If the A/D FRC clock source is selected, a delay of one TCY (instruction cycle) is added before the A/D clock starts. This allows the SLEEP instruction to be executed before starting a conversion. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR `1' = Bit is set `0' = Bit is cleared 2002 Microchip Technology Inc. Preliminary x = Bit is unknown DS39605B-page 157 PIC18F1220/1320 The analog reference voltage is software selectable to either the device's positive and negative supply voltage (AVDD and AVSS), or the voltage level on the RA3/AN3/VREF+ and RA2/AN2/VREF- pins. A device RESET forces all registers to their RESET state. This forces the A/D module to be turned off and any conversion in progress is aborted. Each port pin associated with the A/D converter can be configured as an analog input, or as a digital I/O. The ADRESH and ADRESL registers contain the result of the A/D conversion. When the A/D conversion is complete, the result is loaded into the ADRESH/ADRESL registers, the GO/DONE bit (ADCON0 register) is cleared, and A/D interrupt flag bit ADIF is set. The block diagram of the A/D module is shown in Figure 17-1. The A/D converter has a unique feature of being able to operate while the device is in SLEEP mode. To operate in SLEEP, the A/D conversion clock must be derived from the A/D's internal RC oscillator. The output of the sample and hold is the input into the converter, which generates the result via successive approximation. FIGURE 17-1: A/D BLOCK DIAGRAM CHS2:CHS0 AVDD 111 110 101 100 VAIN 011 (Input Voltage) 10-bit Converter A/D 010 001 VCFG1:VCFG0 000 AVDD Reference Voltage VREFH VREFL AN6(1) AN5 AN4 AN3/VREF+ AN2/VREFAN1 AN0 x0 x1 1x 0x AVSS Note 1: I/O pins have diode protection to VDD and VSS. DS39605B-page 158 Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 The following steps should be followed to do an A/D Conversion: The value in the ADRESH/ADRESL registers is not modified for a Power-on Reset. The ADRESH/ADRESL registers will contain unknown data after a Power-on Reset. 1. After the A/D module has been configured as desired, the selected channel must be acquired before the conversion is started. The analog input channels must have their corresponding TRIS bits selected as an input. To determine acquisition time, see Section 17.1. After this acquisition time has elapsed, the A/D conversion can be started. An acquisition time can be programmed to occur between setting the GO/DONE bit and the actual start of the conversion. 2. 3. 4. 5. Configure the A/D module: * Configure analog pins, voltage reference and digital I/O (ADCON1) * Select A/D input channel (ADCON0) * Select A/D acquisition time (ADCON2) * Select A/D conversion clock (ADCON2) * Turn on A/D module (ADCON0) Configure A/D interrupt (if desired): * Clear ADIF bit * Set ADIE bit * Set GIE bit Wait the required acquisition time (if required). Start conversion: * Set GO/DONE bit (ADCON0 register) Wait for A/D conversion to complete, by either: * Polling for the GO/DONE bit to be cleared OR 6. 7. FIGURE 17-2: * Waiting for the A/D interrupt Read A/D Result registers (ADRESH:ADRESL); clear bit ADIF, if required. For next conversion, go to step 1 or step 2, as required. The A/D conversion time per bit is defined as TAD. A minimum wait of 2 TAD is required before next acquisition starts. ANALOG INPUT MODEL VDD Rs VAIN ANx RIC 1k CPIN 5 pF Sampling Switch VT = 0.6V VT = 0.6V SS RSS I leakage 500 nA CHOLD = 120 pF VSS Legend: CPIN = input capacitance = threshold voltage VT I LEAKAGE = leakage current at the pin due to various junctions = interconnect resistance RIC = sampling switch SS = sample/hold capacitance (from DAC) CHOLD RSS = sampling switch resistance 2002 Microchip Technology Inc. Preliminary VDD 6V 5V 4V 3V 2V 5 6 7 8 9 10 11 Sampling Switch (k) DS39605B-page 159 PIC18F1220/1320 17.1 A/D Acquisition Requirements For the A/D converter to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The analog input model is shown in Figure 17-2. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD). The source impedance affects the offset voltage at the analog input (due to pin leakage current). The maximum recommended impedance for analog sources is 2.5k. After the analog input channel is selected (changed), the channel must be sampled for at least the minimum acquisition time before starting a conversion. Note: When the conversion is started, the holding capacitor is disconnected from the input pin. To calculate the minimum acquisition time, Equation 17-1 may be used. This equation assumes that 1/2 LSb error is used (1024 steps for the A/D). The 1/2 LSb error is the maximum error allowed for the A/D to meet its specified resolution. EQUATION 17-1: TACQ CHOLD Rs Conversion Error VDD Temperature VHOLD 17.2 = = = = = 120 pF 2.5 k 1/2 LSb 5V Rss = 7 k 50C (system max.) 0V @ time = 0 A/D VREF+ and VREF- References If external voltage references are used instead of the internal AVDD and AVSS sources, the source impedance of the VREF+ and VREF- voltage sources must be considered. During acquisition, currents supplied by these sources are insignificant. However, during conversion, the A/D module sinks and sources current through the reference sources. In order to maintain the A/D accuracy, the voltage reference source impedances should be kept low to reduce voltage changes. These voltage changes occur as reference currents flow through the reference source impedance. The maximum recommended impedance of the VREF+ and VREF- external reference voltage sources is 250. ACQUISITION TIME = Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient = TAMP + TC + TCOFF EQUATION 17-2: VHOLD or TC Example 17-1 shows the calculation of the minimum required acquisition time TACQ. This calculation is based on the following application system assumptions: A/D MINIMUM CHARGING TIME = (VREF - (VREF/2048)) * (1 - e(-Tc/CHOLD(RIC + RSS + RS))) = -(CHOLD)(RIC + RSS + RS) ln(1/2048) EXAMPLE 17-1: CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME TACQ = TAMP + TC + TCOFF TAMP = 5 s TCOFF = (Temp - 25C)(0.05 s/C) (50C - 25C)(0.05 s/C) 1.25 s Temperature coefficient is only required for temperatures > 25C. Below 25C, TCOFF = 0 s. TC = -(CHOLD)(RIC + RSS + RS) ln(1/2047) s -(120 pF) (1 k + 7 k + 2.5 k) ln(0.0004883) s 9.61 s TACQ = 5 s + 1.25 s + 9.61 s 12.86 s DS39605B-page 160 Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 17.3 Selecting and Configuring Automatic Acquisition Time 17.4 The ADCON2 register allows the user to select an acquisition time that occurs each time the GO/DONE bit is set. When the GO/DONE bit is set, sampling is stopped and a conversion begins. The user is responsible for ensuring the required acquisition time has passed between selecting the desired input channel and setting the GO/DONE bit. This occurs when the ACQT2:ACQT0 bits (ADCON2<5:3>) remain in their RESET state (`000'), and is compatible with devices that do not offer programmable acquisition times. If desired, the ACQT bits can be set to select a programmable acquisition time for the A/D module. When the GO/DONE bit is set, the A/D module continues to sample the input for the selected acquisition time, then automatically begins a conversion. Since the acquisition time is programmed, there may be no need to wait for an acquisition time between selecting a channel and setting the GO/DONE bit. In either case, when the conversion is completed, the GO/DONE bit is cleared, the ADIF flag is set, and the A/D begins sampling the currently selected channel again. If an acquisition time is programmed, there is nothing to indicate if the acquisition time has ended, or if the conversion has begun. TABLE 17-1: Selecting the A/D Conversion Clock The A/D conversion time per bit is defined as TAD. The A/D conversion requires 11 TAD per 10-bit conversion. The source of the A/D conversion clock is software selectable. There are seven possible options for TAD: * * * * * * * 2 TOSC 4 TOSC 8 TOSC 16 TOSC 32 TOSC 64 TOSC Internal RC oscillator For correct A/D conversions, the A/D conversion clock (TAD) must be as short as possible, but greater than the minimum TAD (approximately 2 s, see parameter 130 for more information). Table 17-1 shows the resultant TAD times derived from the device operating frequencies and the A/D clock source selected. TAD vs. DEVICE OPERATING FREQUENCIES AD Clock Source (TAD) Maximum Device Frequency PIC18LF1X20(4) Operation ADCS2:ADCS0 PIC18F1X20 2 TOSC 000 1.25 MHz 666 kHz 4 TOSC 100 2.50 MHz 1.33 MHz 8 TOSC 001 5.00 MHz 2.66 MHz 16 TOSC 101 10.0 MHz 5.33 MHz 32 TOSC 010 20.0 MHz 10.65 MHz 64 TOSC 110 40.0 MHz 21.33 MHz RC(3) 1.00 x11 MHz(1) 1.00 MHz(2) Note 1: The RC source has a typical TAD time of 4 s. 2: The RC source has a typical TAD time of 6 s. 3: For device frequencies above 1 MHz, the device must be in SLEEP for the entire conversion or the A/D accuracy may be out of specification. 4: Low power devices only. 2002 Microchip Technology Inc. Preliminary DS39605B-page 161 PIC18F1220/1320 17.5 Operation in Low Power Modes 17.6 The selection of the automatic acquisition time and A/D conversion clock is determined, in part, by the Low Power mode clock source and frequency while in a Low Power mode. If the A/D is expected to operate while the device is in a Low Power mode, the ACQT2:ACQT0 and ADCS2:ADCS0 bits in ADCON2 should be updated in accordance with the Low Power mode clock that will be used. After the Low Power mode is entered (either of the RUN modes), an A/D acquisition or conversion may be started. Once an acquisition or conversion is started, the device should continue to be clocked by the same Low Power mode clock source until the conversion has been completed. If desired, the device may be placed into the corresponding Low Power (ANY)_IDLE mode during the conversion. The ADCON1, TRISA, and TRISB registers all configure the A/D port pins. The port pins needed as analog inputs must have their corresponding TRIS bits set (input). If the TRIS bit is cleared (output), the digital output level (VOH or VOL) will be converted. The A/D operation is independent of the state of the CHS2:CHS0 bits and the TRIS bits. Note 1: When reading the port register, all pins configured as analog input channels will read as cleared (a low level). Pins configured as digital inputs will convert an analog input. Analog levels on a digitally configured input will be accurately converted. If the Low Power mode clock frequency is less than 1 MHz, the A/D RC clock source should be selected. Operation in the Low Power SLEEP mode requires the A/D RC clock to be selected. If bits ACQT2:ACQT0 are set to `000', and a conversion is started, the conversion will be delayed one instruction cycle to allow execution of the SLEEP instruction and entry to Low Power SLEEP mode. The IDLEN and SCS bits in the OSCCON register must have already been cleared prior to starting the conversion. DS39605B-page 162 Configuring Analog Port Pins Preliminary 2: Analog levels on any pin defined as a digital input may cause the digital input buffer to consume current out of the device's specification limits. 2002 Microchip Technology Inc. PIC18F1220/1320 17.7 A/D Conversions Figure 17-3 shows the operation of the A/D converter after the GO bit has been set and the ACQT2:ACQT0 bits are cleared. A conversion is started after the following instruction to allow entry into Low Power SLEEP mode before the conversion begins. Clearing the GO/DONE bit during a conversion will abort the current conversion. The A/D result register pair will NOT be updated with the partially completed A/D conversion sample. This means the ADRESH:ADRESL registers will continue to contain the value of the last completed conversion (or the last value written to the ADRESH:ADRESL registers). Figure 17-4 shows the operation of the A/D converter after the GO bit has been set and the ACQT2:ACQT0 bits are set to `010', and selecting a 4 TAD acquisition time before the conversion starts. After the A/D conversion is completed or aborted, a 2 TAD wait is required before the next acquisition can be started. After this wait, acquisition on the selected channel is automatically started. Note: FIGURE 17-3: The GO/DONE bit should NOT be set in the same instruction that turns on the A/D. A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0) TCY - TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11 b4 b1 b0 b6 b7 b2 b8 b9 b3 b5 Conversion Starts Holding capacitor is disconnected from analog input (typically 100 ns) Set GO bit Next Q4: ADRESH/ADRESL is loaded, GO bit is cleared, ADIF bit is set, holding capacitor is connected to analog input. A/D CONVERSION TAD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD) FIGURE 17-4: TAD Cycles TACQT Cycles 1 2 3 4 Automatic Acquisition Time 1 3 4 5 6 7 8 9 10 11 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Conversion Starts (Holding capacitor is disconnected) Set GO bit (Holding capacitor continues acquiring input) 2002 Microchip Technology Inc. 2 Next Q4: ADRESH:ADRESL is loaded, GO bit is cleared, ADIF bit is set, holding capacitor is reconnected to analog input. Preliminary DS39605B-page 163 PIC18F1220/1320 17.8 Use of the CCP1 Trigger desired location). The appropriate analog input channel must be selected and the minimum acquisition period is either timed by the user, or an appropriate TACQ time selected before the "special event trigger" sets the GO/DONE bit (starts a conversion). An A/D conversion can be started by the "special event trigger" of the CCP1 module. This requires that the CCP1M3:CCP1M0 bits (CCP1CON<3:0>) be programmed as `1011' and that the A/D module is enabled (ADON bit is set). When the trigger occurs, the GO/DONE bit will be set, starting the A/D acquisition and conversion, and the Timer1 (or Timer3) counter will be reset to zero. Timer1 (or Timer3) is reset to automatically repeat the A/D acquisition period with minimal software overhead (moving ADRESH/ADRESL to the TABLE 17-2: If the A/D module is not enabled (ADON is cleared), the "special event trigger" will be ignored by the A/D module, but will still reset the Timer1 (or Timer3) counter. SUMMARY OF A/D REGISTERS Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other RESETS INTCON GIE/ GIEH PEIE/ GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 0000 0000 0000 PIR1 -- ADIF RCIF TXIF -- CCP1IF TMR2IF TMR1IF -000 -000 -000 -000 -000 -000 PIE1 -- ADIE RCIE TXIE -- CCP1IE TMR2IE TMR1IE -000 -000 IPR1 -- ADIP RCIP TXIP -- CCP1IP TMR2IP TMR1IP -111 -111 -111 -111 PIR2 OSCFIF -- -- EEIF -- LVDIF TMR3IF -- 0--0 -00- 0--0 -00- PIE2 OSCFIE -- -- EEIE -- LVDIE TMR3IE -- 0--0 -00- 0--0 -00- IPR2 OSCFIP -- -- EEIP -- LVDIP TMR3IP -- ADRESH A/D Result Register High Byte ADRESL A/D Result Register Low Byte ADCON0 -- CHS2 CHS1 CHS0 GO/DONE ADON 1--1 -11- 1--1 -11- xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu 00-0 0000 00-0 0000 VCFG1 VCFG0 ADCON1 -- PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 -000 0000 -000 0000 ADCON2 ADFM -- ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 0-00 0000 0-00 0000 PORTA RA7 RA6 RA5(1) RA4 RA3 RA2 RA1 RA0 --0x 0000 --0u 0000 TRISA TRISA7 TRISA6 -- 11-1 1111 11-1 1111 PORTA Data Direction Register PORTB Read PORTB pins, Write LATB Latch xxxx xxxx uuuu uuuu TRISB PORTB Data Direction Register 1111 1111 1111 1111 LATB PORTB Output Data Latch xxxx xxxx uuuu uuuu Legend: x = unknown, u = unchanged, - = unimplemented, read as '0', q = value depends on condition. Shaded cells are not used for A/D conversion. Note 1: RA5 port bit is available only as an input pin when MCLRE bit in configuration register is `0'. DS39605B-page 164 Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 18.0 LOW VOLTAGE DETECT In many applications, the ability to determine if the device voltage (VDD) is below a specified voltage level is a desirable feature. A window of operation for the application can be created, where the application software can do "housekeeping tasks", before the device voltage exits the valid operating range. This can be done using the Low Voltage Detect module. This module is a software programmable circuitry, where a device voltage trip point can be specified. When the voltage of the device becomes lower then the specified point, an interrupt flag is set. If the interrupt is enabled, the program execution will branch to the interrupt vector address and the software can then respond to that interrupt source. The Low Voltage Detect circuitry is completely under software control. This allows the circuitry to be turned off by the software, which minimizes the current consumption for the device. The block diagram for the LVD module is shown in Figure 18-2 (following page). A comparator uses an internally generated reference voltage as the set point. When the selected tap output of the device voltage crosses the set point (is lower than), the LVDIF bit is set. Each node in the resistor divider represents a "trip point" voltage. The "trip point" voltage is the minimum supply voltage level at which the device can operate before the LVD module asserts an interrupt. When the supply voltage is equal to the trip point, the voltage tapped off of the resistor array is equal to the 1.2V internal reference voltage generated by the voltage reference module. The comparator then generates an interrupt signal setting the LVDIF bit. This voltage is software programmable to any one of 16 values (see Figure 18-2). The trip point is selected by programming the LVDL3:LVDL0 bits (LVDCON<3:0>). TYPICAL LOW VOLTAGE DETECT APPLICATION Voltage FIGURE 18-1: Figure 18-1 shows a possible application voltage curve (typically for batteries). Over time, the device voltage decreases. When the device voltage equals voltage VA, the LVD logic generates an interrupt. This occurs at time TA. The application software then has the time, until the device voltage is no longer in valid operating range, to shutdown the system. Voltage point VB is the minimum valid operating voltage specification. This occurs at time TB. The difference TB - TA is the total time for shutdown. VA VB Legend: VA = LVD trip point VB = Minimum valid device operating voltage Time 2002 Microchip Technology Inc. TA TB Preliminary DS39605B-page 165 PIC18F1220/1320 FIGURE 18-2: LOW VOLTAGE DETECT (LVD) BLOCK DIAGRAM LVDIN LVD Control Register 16 to 1 MUX VDD Internally Generated Reference Voltage 1.2V LVDEN The LVD module has an additional feature that allows the user to supply the trip voltage to the module from an external source. This mode is enabled when bits LVDL3:LVDL0 are set to `1111'. In this state, the comparator input is multiplexed from the external input pin, FIGURE 18-3: LVDIF LVDIN (Figure 18-3). This gives users flexibility, because it allows them to configure the Low Voltage Detect interrupt to occur at any voltage in the valid operating range. LOW VOLTAGE DETECT (LVD) WITH EXTERNAL INPUT BLOCK DIAGRAM VDD VDD 16 to 1 MUX LVD Control Register LVDIN Externally Generated Trip Point LVDEN LVD VxEN BODEN EN BGAP DS39605B-page 166 Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 18.1 Control Register The Low Voltage Detect Control register controls the operation of the Low Voltage Detect circuitry. REGISTER 18-1: LVDCON REGISTER U-0 U-0 R-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-1 -- -- IRVST LVDEN LVDL3 LVDL2 LVDL1 LVDL0 bit 7 bit 0 bit 7-6 Unimplemented: Read as '0' bit 5 IRVST: Internal Reference Voltage Stable Flag bit 1 = Indicates that the Low Voltage Detect logic will generate the interrupt flag at the specified voltage range 0 = Indicates that the Low Voltage Detect logic will not generate the interrupt flag at the specified voltage range and the LVD interrupt should not be enabled bit 4 LVDEN: Low Voltage Detect Power Enable bit 1 = Enables LVD, powers up LVD circuit 0 = Disables LVD, powers down LVD circuit bit 3-0 LVDL3:LVDL0: Low Voltage Detection Limit bits 1111 = External analog input is used (input comes from the LVDIN pin) 1110 = 4.50V - 4.78V 1101 = 4.20V - 4.46V 1100 = 4.00V - 4.26V 1011 = 3.80V - 4.04V 1010 = 3.60V - 3.84V 1001 = 3.50V - 3.72V 1000 = 3.30V - 3.52V 0111 = 3.00V - 3.20V 0110 = 2.80V - 2.98V 0101 = 2.70V - 2.86V 0100 = 2.50V - 2.66V 0011 = 2.40V - 2.55V 0010 = 2.20V - 2.34V 0001 = 2.00V - 2.12V 0000 = Reserved Note: LVDL3:LVDL0 modes, which result in a trip point below the valid operating voltage of the device, are not tested. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR `1' = Bit is set `0' = Bit is cleared 2002 Microchip Technology Inc. Preliminary x = Bit is unknown DS39605B-page 167 PIC18F1220/1320 18.2 Operation The following steps are needed to set up the LVD module: Depending on the power source for the device voltage, the voltage normally decreases relatively slowly. This means that the LVD module does not need to be constantly operating. To decrease the current requirements, the LVD circuitry only needs to be enabled for short periods, where the voltage is checked. After doing the check, the LVD module may be disabled. 1. 2. 3. Each time that the LVD module is enabled, the circuitry requires some time to stabilize. After the circuitry has stabilized, all status flags may be cleared. The module will then indicate the proper state of the system. 4. 5. 6. Write the value to the LVDL3:LVDL0 bits (LVDCON register), which selects the desired LVD Trip Point. Ensure that LVD interrupts are disabled (the LVDIE bit is cleared or the GIE bit is cleared). Enable the LVD module (set the LVDEN bit in the LVDCON register). Wait for the LVD module to stabilize (the IRVST bit to become set). Clear the LVD interrupt flag, which may have falsely become set until the LVD module has stabilized (clear the LVDIF bit). Enable the LVD interrupt (set the LVDIE and the GIE bits). Figure 18-4 shows typical waveforms that the LVD module may be used to detect. FIGURE 18-4: LOW VOLTAGE DETECT WAVEFORMS CASE 1: LVDIF may not be set. VDD VLVD LVDIF Enable LVD Internally Generated Reference Stable TIVRST LVDIF cleared in software. CASE 2: VDD VLVD LVDIF Enable LVD Internally Generated Reference Stable TIVRST LVDIF cleared in software. LVDIF cleared in software, LVDIF remains set since LVD condition still exists. DS39605B-page 168 Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 18.2.1 REFERENCE VOLTAGE SET POINT The Internal Reference Voltage of the LVD module may be used by other internal circuitry (the Programmable Brown-out Reset). If these circuits are disabled (lower current consumption), the reference voltage circuit requires a time to become stable before a low voltage condition can be reliably detected. This time is invariant of system clock speed. This start-up time is specified in electrical specification parameter 36. The low voltage interrupt flag will not be enabled until a stable reference voltage is reached. Refer to the waveform in Figure 18-4. 18.2.2 18.3 Operation During SLEEP When enabled, the LVD circuitry continues to operate during SLEEP. If the device voltage crosses the trip point, the LVDIF bit will be set and the device will wakeup from SLEEP. Device execution will continue from the interrupt vector address, if interrupts have been globally enabled. 18.4 Effects of a RESET A device RESET forces all registers to their RESET state. This forces the LVD module to be turned off. CURRENT CONSUMPTION When the module is enabled, the LVD comparator and voltage divider are enabled and will consume static current. The voltage divider can be tapped from multiple places in the resistor array. Total current consumption, when enabled, is specified in electrical specification parameter #D022B. 2002 Microchip Technology Inc. Preliminary DS39605B-page 169 PIC18F1220/1320 NOTES: DS39605B-page 170 Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 19.0 SPECIAL FEATURES OF THE CPU The inclusion of an internal RC oscillator also provides the additional benefits of a Fail-Safe Clock Monitor (FSCM) and Two-Speed Start-up. FSCM provides for background monitoring of the peripheral clock and automatic switchover in the event of its failure. Two-Speed Start-up enables code to be executed almost immediately on start-up, while the primary clock source completes its start-up delays. PIC18F1220/1320 devices include several features intended to maximize system reliability, minimize cost through elimination of external components and offer code protection. These are: * Oscillator Selection * RESETS: - Power-on Reset (POR) - Power-up Timer (PWRT) - Oscillator Start-up Timer (OST) - Brown-out Reset (BOR) * Interrupts * Watchdog Timer (WDT) * Fail-Safe Clock Monitor * Two-Speed Start-up * Code Protection * ID Locations * In-Circuit Serial Programming All of these features are enabled and configured by setting the appropriate configuration register bits. 19.1 The configuration bits can be programmed (read as '0'), or left unprogrammed (read as '1'), to select various device configurations. These bits are mapped starting at program memory location 300000h. The user will note that address 300000h is beyond the user program memory space. In fact, it belongs to the configuration memory space (300000h - 3FFFFFh), which can only be accessed using Table Reads and Table Writes. Programming the configuration registers is done in a manner similar to programming the FLASH memory. The EECON1 register WR bit starts a self-timed write to the configuration register. In normal Operation mode, a TBLWT instruction, with the TBLPTR pointing to the configuration register, sets up the address and the data for the configuration register write. Setting the WR bit starts a long write to the configuration register. The configuration registers are written a byte at a time. To write or erase a configuration cell, a TBLWT instruction can write a `1' or a `0' into the cell. For additional details on FLASH programming, refer to Section 6.5. Several oscillator options are available to allow the part to fit the application. The RC oscillator option saves system cost, while the LP crystal option saves power. These are discussed in detail in Section 2.0. A complete discussion of device RESETS and interrupts is available in previous sections of this data sheet. In addition to their Power-up and Oscillator Start-up Timers provided for RESETS, PIC18F1220/1320 devices have a Watchdog Timer, which is either permanently enabled via the configuration bits, or software controlled (if configured as disabled). TABLE 19-1: Configuration Bits CONFIGURATION BITS AND DEVICE IDS File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Default/ Unprogrammed Value Bit 0 300001h CONFIG1H IESO FCMEN -- -- FOSC3 FOSC2 FOSC1 FOSC0 11-- 1111 300002h CONFIG2L -- -- -- -- BORV1 BORV0 BODEN PWRTEN ---- 1111 300003h CONFIG2H -- -- -- 300005h CONFIG3H MCLRE -- -- -- -- -- 300006h CONFIG4L DEBUG -- -- -- -- 300008h CONFIG5L -- -- -- -- -- 300009h CONFIG5H CPD CPB -- -- -- -- 30000Ah CONFIG6L -- -- -- -- -- -- WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN ---1 1111 -- -- 1--- ---- LVP -- STVREN 1--- -1-1 -- CP1 CP0 ---- --11 -- -- 11-- ---- WRT1 WRT0 ---- --11 111- ---- 30000Bh CONFIG6H WRTD WRTB WRTC -- -- -- -- -- 30000Ch CONFIG7L -- -- -- -- -- -- EBTR1 EBTR0 ---- --11 30000Dh CONFIG7H -- EBTRB -- -- -- -- -- -- -1-- ---- DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 xxxx xxxx(1) DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 0000 0111 3FFFFEh DEVID1(1) 3FFFFFh (1) DEVID2 Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded cells are unimplemented, read as `0'. Note 1: See Register 19-14 for DEVID1 values. DEVID registers are read only and cannot be programmed by the user. 2002 Microchip Technology Inc. Preliminary DS39605B-page 171 PIC18F1220/1320 REGISTER 19-1: CONFIGURATION REGISTER 1 HIGH (CONFIG1H: BYTE ADDRESS 300001h) R/P-1 R/P-1 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 IESO FCMEN -- -- FOSC3 FOSC2 FOSC1 FOSC0 bit 7 bit 0 bit 7 IESO: Internal External Switch Over bit 1 = Internal External Switch Over mode enabled 0 = Internal External Switch Over mode disabled bit 6 FCMEN: Fail-Safe Clock Monitor Enable bit 1 = Fail-Safe Clock Monitor enabled 0 = Fail-Safe Clock Monitor disabled bit 5:4 Unimplemented: Read as `0' bit 3-0 FOSC<3:0>: Oscillator Selection bits 11xx = External RC oscillator, CLKO function on RA6 1001 = Internal RC oscillator, CLKO function on RA6, and port function on RA7 1000 = Internal RC oscillator, port function on RA6, and port function on RA7 0111 = External RC oscillator, port function on RA6 0110 = HS oscillator, PLL enabled (clock frequency = 4 x FOSC1) 0101 = EC oscillator, port function on RA6 0100 = EC oscillator, CLKO function on RA6 0010 = HS oscillator 0001 = XT oscillator 0000 = LP oscillator Legend: R = Readable bit P = Programmable bit - n = Value when device is unprogrammed DS39605B-page 172 Preliminary U = Unimplemented bit, read as `0' u = Unchanged from programmed state 2002 Microchip Technology Inc. PIC18F1220/1320 REGISTER 19-2: CONFIGURATION REGISTER 2 LOW (CONFIG2L: BYTE ADDRESS 300002h) U-0 U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 -- -- -- -- BORV1 BORV0 BOREN PWRTEN bit 7 bit 0 bit 7-4 Unimplemented: Read as `0' bit 3-2 BORV1:BORV0: Brown-out Reset Voltage bits 11 = VBOR set to 2.0V 10 = VBOR set to 2.7V 01 = VBOR set to 4.2V 00 = VBOR set to 4.5V bit 1 BOREN: Brown-out Reset Enable bit(1) 1 = Brown-out Reset enabled 0 = Brown-out Reset disabled bit 0 PWRTEN: Power-up Timer Enable bit(1) 1 = PWRT disabled 0 = PWRT enabled Note 1: The Power-up Timer is decoupled from Brown-out Reset, allowing these features to be independently controlled. Legend: R = Readable bit P = Programmable bit - n = Value when device is unprogrammed 2002 Microchip Technology Inc. Preliminary U = Unimplemented bit, read as `0' u = Unchanged from programmed state DS39605B-page 173 PIC18F1220/1320 REGISTER 19-3: CONFIGURATION REGISTER 2 HIGH (CONFIG2H: BYTE ADDRESS 300003h) U-0 -- bit 7 bit 7-5 bit 4-1 bit 0 U-0 -- U-0 -- R/P-1 WDTPS3 R/P-1 WDTPS1 R/P-1 WDTPS0 R/P-1 WDTEN bit 0 Unimplemented: Read as `0' WDPS<3:0>: Watchdog Timer Postscale Select bits 1111 = 1:32,768 1110 = 1:16,384 1101 = 1:8,192 1100 = 1:4,096 1011 = 1:2,048 1010 = 1:1,024 1001 = 1:512 1000 = 1:256 0111 = 1:128 0110 = 1:64 0101 = 1:32 0100 = 1:16 0011 = 1:8 0010 = 1:4 0001 = 1:2 0000 = 1:1 WDTEN: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled (control is placed on the SWDTEN bit) Legend: R = Readable bit P = Programmable bit - n = Value when device is unprogrammed DS39605B-page 174 R/P-1 WDTPS2 Preliminary U = Unimplemented bit, read as `0' u = Unchanged from programmed state 2002 Microchip Technology Inc. PIC18F1220/1320 REGISTER 19-4: CONFIGURATION REGISTER 3 HIGH (CONFIG3H: BYTE ADDRESS 300005h) R/P-1 U-0 U-0 U-0 U-0 U-0 U-0 U-0 MCLRE -- -- -- -- -- -- -- bit 7 bit 0 bit 7 MCLRE: MCLR Pin Enable bit 1 = MCLR pin enabled, RA5 input pin disabled 0 = RA5 input pin enabled, MCLR disabled bit 6-0 Unimplemented: Read as `0' Legend: R = Readable bit P = Programmable bit - n = Value when device is unprogrammed REGISTER 19-5: U = Unimplemented bit, read as `0' u = Unchanged from programmed state CONFIGURATION REGISTER 4 LOW (CONFIG4L: BYTE ADDRESS 300006h) R/P-1 U-0 U-0 U-0 U-0 R/P-1 U-0 R/P-1 DEBUG -- -- -- -- LVP -- STVREN bit 7 bit 0 bit 7 DEBUG: Background Debugger Enable bit 1 = Background Debugger disabled, RB6 and RB7 configured as general purpose I/O pins 0 = Background Debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug bit 6-3 Unimplemented: Read as `0' bit 2 LVP: Low Voltage ICSP Enable bit 1 = Low Voltage ICSP enabled 0 = Low Voltage ICSP disabled bit 1 Unimplemented: Read as `0' bit 0 STVREN: Stack Full/Underflow Reset Enable bit 1 = Stack Full/Underflow will cause RESET 0 = Stack Full/Underflow will not cause RESET Legend: R = Readable bit C = Clearable bit - n = Value when device is unprogrammed 2002 Microchip Technology Inc. Preliminary U = Unimplemented bit, read as `0' u = Unchanged from programmed state DS39605B-page 175 PIC18F1220/1320 REGISTER 19-6: CONFIGURATION REGISTER 5 LOW (CONFIG5L: BYTE ADDRESS 300008h) U-0 U-0 U-0 U-0 R/C-1 R/C-1 R/C-1 R/C-1 -- -- -- -- -- -- CP1 CP0 bit 7 bit 0 bit 7-2 Unimplemented: Read as `0' bit 1 CP1: Code Protection bit (PIC18F1320) 1 = Block 1 (001000-001FFFh) not code protected 0 = Block 1 (001000-001FFFh) code protected bit 0 CP0: Code Protection bit (PIC18F1320) 1 = Block 0 (00200-000FFFh) not code protected 0 = Block 0 (00200-000FFFh) code protected bit 1 CP1: Code Protection bit (PIC18F1220) 1 = Block 1 (000800-000FFFh) not code protected 0 = Block 1 (000800-000FFFh) code protected bit 0 CP0: Code Protection bit (PIC18F1220) 1 = Block 0 (000200-0007FFh) not code protected 0 = Block 0 (000200-0007FFh) code protected Legend: R = Readable bit C = Clearable bit - n = Value when device is unprogrammed REGISTER 19-7: U = Unimplemented bit, read as `0' u = Unchanged from programmed state CONFIGURATION REGISTER 5 HIGH (CONFIG5H: BYTE ADDRESS 300009h) R/C-1 R/C-1 U-0 U-0 U-0 U-0 U-0 U-0 CPD CPB -- -- -- -- -- -- bit 7 bit 0 bit 7 CPD: Data EEPROM Code Protection bit 1 = Data EEPROM not code protected 0 = Data EEPROM code protected bit 6 CPB: Boot Block Code Protection bit 1 = Boot Block (000000-0001FFh) not code protected 0 = Boot Block (000000-0001FFh) code protected bit 5-0 Unimplemented: Read as `0' Legend: R = Readable bit C = Clearable bit - n = Value when device is unprogrammed DS39605B-page 176 Preliminary U = Unimplemented bit, read as `0' u = Unchanged from programmed state 2002 Microchip Technology Inc. PIC18F1220/1320 REGISTER 19-8: CONFIGURATION REGISTER 6 LOW (CONFIG6L: BYTE ADDRESS 30000Ah) U-0 U-0 U-0 U-0 U-0 U-0 R/P-1 R/P-1 -- -- -- -- -- -- WRT1 WRT0 bit 7 bit 0 bit 7-2 Unimplemented: Read as `0' bit 1 WRT1: Write Protection bit (PIC18F1320) 1 = Block 1 (001000-001FFFh) not write protected 0 = Block 1 (001000-001FFFh) write protected bit 0 WRT0: Write Protection bit (PIC18F1320) 1 = Block 0 (00200-000FFFh) not write protected 0 = Block 0 (00200-000FFFh) write protected bit 1 WRT1: Write Protection bit (PIC18F1220) 1 = Block 1 (000800-000FFFh) not write protected 0 = Block 1 (000800-000FFFh) write protected bit 0 WRT0: Write Protection bit (PIC18F1220) 1 = Block 0 (000200-0007FFh) not write protected 0 = Block 0 (000200-0007FFh) write protected Legend: R = Readable bit P = Programmable bit - n = Value when device is unprogrammed REGISTER 19-9: U = Unimplemented bit, read as `0' u = Unchanged from programmed state CONFIGURATION REGISTER 6 HIGH (CONFIG6H: BYTE ADDRESS 30000Bh) R/P-1 R/P-1 R-1 U-0 U-0 U-0 U-0 U-0 WRTD WRTB WRTC -- -- -- -- -- bit 7 bit 0 bit 7 WRTD: Data EEPROM Write Protection bit 1 = Data EEPROM not write protected 0 = Data EEPROM write protected bit 6 WRTB: Boot Block Write Protection bit 1 = Boot Block (000000-0001FFh) not write protected 0 = Boot Block (000000-0001FFh) write protected bit 5 WRTC: Configuration Register Write Protection bit 1 = Configuration registers (300000-3000FFh) not write protected 0 = Configuration registers (300000-3000FFh) write protected Note: bit 4-0 This bit is read only in normal Execution mode; it can be written only in Program mode. Unimplemented: Read as `0' Legend: R = Readable bit P =Programmable bit - n = Value when device is unprogrammed 2002 Microchip Technology Inc. Preliminary U = Unimplemented bit, read as `0' u = Unchanged from programmed state DS39605B-page 177 PIC18F1220/1320 REGISTER 19-10: CONFIGURATION REGISTER 7 LOW (CONFIG7L: BYTE ADDRESS 30000Ch) U-0 U-0 U-0 U-0 U-0 U-0 R/P-1 R/P-1 -- -- -- -- -- -- EBTR1 EBTR0 bit 7 bit 0 bit 7-2 Unimplemented: Read as `0' bit 1 EBTR1: Table Read Protection bit (PIC18F1320) 1 = Block 1 (001000-001FFFh) not protected from Table Reads executed in other blocks 0 = Block 1 (001000-001FFFh) protected from Table Reads executed in other blocks bit 0 EBTR0: Table Read Protection bit (PIC18F1320) 1 = Block 0 (00200-000FFFh) not protected from Table Reads executed in other blocks 0 = Block 0 (00200-000FFFh) protected from Table Reads executed in other blocks bit 1 EBTR1: Table Read Protection bit (PIC18F1220) 1 = Block 1 (000800-000FFFh) not protected from Table Reads executed in other blocks 0 = Block 1 (000800-000FFFh) protected from Table Reads executed in other blocks bit 0 EBTR0: Table Read Protection bit (PIC18F1220) 1 = Block 0 (000200-0007FFh) not protected from Table Reads executed in other blocks 0 = Block 0 (000200-0007FFh) protected from Table Reads executed in other blocks Legend: R = Readable bit P = Programmable bit - n = Value when device is unprogrammed U = Unimplemented bit, read as `0' u = Unchanged from programmed state REGISTER 19-11: CONFIGURATION REGISTER 7 HIGH (CONFIG7H: BYTE ADDRESS 30000Dh) U-0 R/P-1 U-0 U-0 U-0 U-0 U-0 U-0 -- EBTRB -- -- -- -- -- -- bit 7 bit 0 bit 7 Unimplemented: Read as `0' bit 6 EBTRB: Boot Block Table Read Protection bit 1 = Boot Block (000000-0001FFh) not protected from Table Reads executed in other blocks 0 = Boot Block (000000-0001FFh) protected from Table Reads executed in other blocks bit 5-0 Unimplemented: Read as `0' Legend: R = Readable bit P =Programmable bit - n = Value when device is unprogrammed DS39605B-page 178 Preliminary U = Unimplemented bit, read as `0' u = Unchanged from programmed state 2002 Microchip Technology Inc. PIC18F1220/1320 REGISTER 19-12: DEVICE ID REGISTER 1 FOR PIC18F1220/1320 DEVICES R R R R R R R R DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 bit 7 bit 0 bit 7-5 DEV2:DEV0: Device ID bits 111 = PIC18F1220 110 = PIC18F1320 bit 4-0 REV4:REV0: Revision ID bits These bits are used to indicate the device revision Legend: R = Read only bit P =Programmable bit - n = Value when device is unprogrammed U = Unimplemented bit, read as `0' u = Unchanged from programmed state REGISTER 19-13: DEVICE ID REGISTER 2 FOR PIC18F1220/1320 DEVICES R R R R R R R R DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 bit 7 bit 7-0 bit 0 DEV10:DEV3: Device ID bits These bits are used with the DEV2:DEV0 bits in the Device ID Register 1 to identify the part number 0000 0111 = PIC18F1220/1320 devices Note: These values for DEV10:DEV3 may be shared with other devices. The specific device is always identified by using the entire DEV10:DEV0 bit sequence. Legend: R = Read only bit P =Programmable bit - n = Value when device is unprogrammed 2002 Microchip Technology Inc. Preliminary U = Unimplemented bit, read as `0' u = Unchanged from programmed state DS39605B-page 179 PIC18F1220/1320 19.2 Watchdog Timer (WDT) Note 1: The CLRWDT and SLEEP instructions clear the WDT and postscaler counts when executed. For PIC18F1220/1320 devices, the WDT is driven by the INTRC source. When the WDT is enabled, the clock source is also enabled. The nominal WDT period is 4 ms, and has the same stability as the INTRC oscillator. The 4 ms period of the WDT is multiplied by a 16-bit postscaler. Any output of the WDT postscaler is selected by a multiplexer, controlled by bits in Configuration Register 2H. Available periods range from 4 ms to 131.072 seconds (2.18 minutes). The WDT and postscaler are cleared when any of the following events occur: execute a SLEEP or CLRWDT instruction, the IRCF bits (OSCCON<6:4>) are changed, or a clock failure has occurred. Adjustments to the internal oscillator clock period using the OSCTUNE register also affect the period of the WDT by the same factor. For example, if the INTRC period is increased by 3%, then the WDT period is increased by 3%. 2: Changing the setting of the IRCF bits (OSCCON<6:4> clears the WDT and postscaler counts. 3: When a CLRWDT instruction is executed the postscaler count will be cleared. 19.2.1 CONTROL REGISTER Register 19-14 shows the WDTCON register. This is a readable and writable register, which contains a control bit that allows software to override the WDT enable configuration bit, only if the configuration bit has disabled the WDT. FIGURE 19-1: WDT BLOCK DIAGRAM Enable WDT SWDTEN WDTEN INTRC Control WDT Counter Wake-up from SLEEP /125 INTRC Oscillator (31 kHz) CLRWDT All Device RESETS WDT Reset Programmable Postscaler RESET 1:1 to 1:32,768 WDT 4 WDTPS<3:0> SLEEP REGISTER 19-14: WDTCON REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 -- -- -- -- -- -- -- SWDTEN bit 7 bit 0 bit 7-1 Unimplemented: Read as '0' bit 0 SWDTEN: Software Controlled Watchdog Timer Enable bit 1 = Watchdog Timer is on 0 = Watchdog Timer is off Note: This bit has no effect if the configuration bit WDTEN (CONFIG2H<0>) is enabled. Legend: DS39605B-page 180 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 TABLE 19-2: SUMMARY OF WATCHDOG TIMER REGISTERS Name CONFIG2H RCON WDTCON Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 -- -- -- WDTPS3 WDTPS2 WDTPS2 WDTPS0 WDTEN IPEN -- -- RI TO PD POR BOR -- -- -- -- -- -- -- SWDTEN Legend: Shaded cells are not used by the Watchdog Timer. 19.3 Two-Speed Start-up In all other Power Managed modes, Two-Speed Start-up is not used. The device will be clocked by the currently selected clock source until the primary clock source becomes available. The setting of the IESO bit is ignored. The Two-Speed Start-up feature helps to minimize the latency period from oscillator start-up to code execution, by allowing the microcontroller to use the INTRC oscillator as a clock source until the primary clock source is available. It is enabled by setting the IESO bit in Configuration Register 1H (CONFIG1H<7>). 19.3.1 Two-Speed Start-up is available only if the primary Oscillator mode is LP, XT, HS, or HSPLL (Crystal Based modes). Other sources do not require a OST start-up delay; for these, Two-Speed Start-up is disabled. While using the INTRC oscillator in Two-Speed Start-up, the device still obeys the normal command sequences for entering Power Managed modes, including serial SLEEP instructions (refer to "Multiple SLEEP Commands" in Section 3.1.3). In practice, this means that user code can change the SCS1:SCS0 bit settings and issue SLEEP commands before the OST times out. This would allow an application to briefly wake-up, perform routine "housekeeping" tasks and return to SLEEP before the device starts to operate from the primary oscillator. When enabled, RESETS and wake-ups from SLEEP mode cause the device to configure itself to run from the internal oscillator block as the clock source, following the time-out of the Power-up Timer after a POR RESET is enabled. This allows almost immediate code execution while the primary oscillator starts and the OST is running. Once the OST times out, the device automatically switches to PRI_RUN mode. User code can also check if the primary clock source is currently providing the system clocking by checking the status of the OSTS bit (OSCCON<3>). If the bit is set, the primary oscillator is providing the system clock. Otherwise, the internal oscillator block is providing the clock during wake-up from RESET or SLEEP mode. Because the OSCCON register is cleared on RESET events, the INTOSC (or postscaler) clock source is not initially available after a RESET event; the INTRC clock is used directly at its base frequency. To use a higher clock speed on wake-up, the INTOSC or postscaler clock sources can be selected to provide a higher clock speed by setting bits IFRC2:IFRC0 immediately after RESET. For wake-ups from SLEEP, the INTOSC or postscaler clock sources can be selected by setting IFRC2:IFRC0 prior to entering SLEEP mode. FIGURE 19-2: SPECIAL CONSIDERATIONS FOR USING TWO-SPEED START-UP TIMING TRANSITION FOR TWO-SPEED START-UP (INTOSC TO HSPLL) Q1 Q2 Q3 Q4 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 INTOSC Multiplexer OSC1 TOST(1) TPLL(1) PLL Clock Output 1 2 3 4 5 6 Clock Transition 7 8 CPU Clock Peripheral Clock Program Counter PC Wake from Interrupt Event Note PC + 4 PC + 2 PC + 6 OSTS bit Set 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale. 2002 Microchip Technology Inc. Preliminary DS39605B-page 181 PIC18F1220/1320 19.4 Fail-Safe Clock Monitor The Fail-Safe Clock Monitor (FSCM) allows the microcontroller to continue operation in the event of an external oscillator failure, by automatically switching the system clock to the internal oscillator block. The FSCM function is enabled by setting the Fail-Safe Clock Monitor Enable bit, FCMEN (CONFIG1H<6>). When FSCM is enabled, the INTRC oscillator runs at all times to monitor clocks to peripherals and provide an instant backup clock in the event of a clock failure. Clock monitoring (shown in Figure 19-1) is accomplished by creating a sample clock signal, which is the INTRC output divided by 64. This allows ample time between FSCM sample clocks for a peripheral clock edge to occur. The peripheral system clock and the sample clock are presented as inputs to the Clock Monitor latch (CM). The CM is set on the falling edge of the system clock source, but cleared on the rising edge of the sample clock. FIGURE 19-1: FSCM BLOCK DIAGRAM Clock Monitor Latch (CM) (edge-triggered) Peripheral Clock INTRC Source (32 s) S / 64 C To use a higher clock speed on wake-up, the INTOSC or postscaler clock sources can be selected to provide a higher clock speed by setting bits IFRC2:IFRC0 immediately after RESET. For wake-ups from SLEEP, the INTOSC or postscaler clock sources can be selected by setting IFRC2:IFRC0 prior to entering SLEEP mode. Adjustments to the internal oscillator block using the OSCTUNE register also affect the period of the FSCM by the same factor. This can usually be neglected, as the clock frequency being monitored is generally much higher than the sample clock frequency. The FSCM will detect failures of the primary or secondary clock sources only. If the internal oscillator block fails, no failure would be detected, nor would any action be possible. 19.4.1 Q FSCM AND THE WATCHDOG TIMER Both the FSCM and the WDT are clocked by the INTRC oscillator. Since the WDT operates with a separate divider and counter, disabling the WDT has no effect on the operation of the INTRC oscillator when the FSCM is enabled. Q 488 Hz (2.048 ms) Clock Failure Detected Clock failure is tested for on the falling edge of the sample clock. If a sample clock falling edge occurs while CM is still set, a clock failure has been detected (Figure 19-2). This causes the following: * the FSCM generates an oscillator fail interrupt by setting bit OSCFIF (PIR2<7>); * the system clock source is switched to the internal oscillator block (OSCCON is not updated to show the current clock source - this is the fail-safe condition); and * the WDT is reset. DS39605B-page 182 Since the postscaler frequency from the internal oscillator block may not be sufficiently stable, it may be desirable to select another clock configuration and enter an alternate Power Managed mode (see Sections 19.3.1 and 3.1.3 for more details). This can be done to attempt a partial recovery, or execute a controlled shutdown. As already noted, the clock source is switched to the INTOSC clock when a clock failure is detected. Depending on the frequency selected by the IRCF2:IRCF0 bits, this may mean a substantial change in the speed of code execution. If the WDT is enabled with a small prescale value, a decrease in clock speed allows a WDT time-out to occur, and a subsequent device RESET. For this reason, fail-safe clock events also reset the WDT and postscaler, allowing it to start timing from when execution speed was changed and decreasing the likelihood of an erroneous time-out. Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 19.4.2 EXITING FAIL-SAFE OPERATION The fail-safe condition is terminated by either a device RESET, or by entering a Power Managed mode. On RESET, the controller starts the primary clock source specified in Configuration Register 1H (with any required start-up delays that are required for the Oscillator mode, such as OST or PLL timer). The INTOSC multiplexer provides the system clock until the primary clock source becomes ready (similar to a Two-Speed Start-up). The clock system source is then switched to the primary clock (indicated by the OSTS bit in the OSCCON register becoming set). The Fail-Safe Clock Monitor then resumes monitoring the peripheral clock. The primary clock source may never become ready during start-up. In this case, operation is clocked by the INTOSC multiplexer. The OSCCON register will remain in its RESET state until a Power Managed mode is entered. Entering a Power Managed mode by loading the OSCCON register and executing a SLEEP instruction will clear the fail-safe condition. When the fail-safe condition is cleared, the clock monitor will resume monitoring the peripheral clock. FIGURE 19-2: 19.4.3 FSCM INTERRUPTS IN POWER MANAGED MODES As previously mentioned, entering a Power Managed mode clears the fail-safe condition. By entering a Power Managed mode, the clock multiplexer selects the clock source selected by the OSCCON register. Fail-safe monitoring of the Power Managed clock source resumes in the Power Managed mode. If an oscillator failure occurs during Power Managed operation, the subsequent events depend on whether or not the oscillator failure interrupt is enabled. If enabled (OSCFIF = 1), code execution will be clocked by the INTOSC multiplexer. An automatic transition back to the failed clock source will not occur. If the interrupt is disabled, the device will not exit the Power Managed mode on oscillator failure. Instead, the device will continue to operate as before, but clocked by the INTOSC multiplexer. While in IDLE mode, subsequent interrupts will cause the CPU to begin executing instructions while being clocked by the INTOSC multiplexer. The device will not transition to a different clock source until the fail-safe condition is cleared. FSCM TIMING DIAGRAM Sample Clock Oscillator Failure System Clock Output CM Output (Q) Failure Detected OSCFIF CM Test Note: CM Test CM Test The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity. 2002 Microchip Technology Inc. Preliminary DS39605B-page 183 PIC18F1220/1320 19.4.4 POR OR WAKE FROM SLEEP The FSCM is designed to detect oscillator failure at any point after the device has exited Power-on Reset (POR) or Low Power SLEEP mode. When the primary system clock is EC, RC or INTRC modes, monitoring can begin immediately following these events. For Oscillator modes involving a crystal or resonator (HS, HSPLL, LP or XT), the situation is somewhat different. Since the oscillator may require a start-up time considerably longer than the FCSM sample clock time, a false clock failure may be detected. To prevent this, the internal oscillator block is automatically configured as the system clock, and functions until the primary clock is stable (the OST and PLL timers have timed out). This is identical to Two-Speed Start-up mode. Once the primary clock is stable, the INTRC returns to its role as the FSCM source DS39605B-page 184 Note: The same logic that prevents false oscillator failure interrupts on POR or wake from SLEEP, will also prevent the detection of the oscillator's failure to start at all following these events. This can be avoided by monitoring the OSTS bit and using a timing routine to determine if the oscillator is taking too long to start. Even so, no oscillator failure interrupt will be flagged. As noted in Section 19.3.1, it is also possible to select another clock configuration and enter an alternate Power Managed mode while waiting for the primary system clock to become stable. When the new Powered Managed mode is selected, the primary clock is disabled. Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 19.5 Program Verification and Code Protection Each of the three blocks has three protection bits associated with them. They are: The overall structure of the code protection on the PIC18 FLASH devices differs significantly from other PICmicro(R) devices. * Code Protect bit (CPn) * Write Protect bit (WRTn) * External Block Table Read bit (EBTRn) The user program memory is divided into three blocks. One of these is a boot block of 512 bytes. The remainder of the memory is divided into two blocks on binary boundaries. Figure 19-3 shows the program memory organization for 4- and 8-Kbyte devices, and the specific code protection bit associated with each block. The actual locations of the bits are summarized in Table 19-3. FIGURE 19-3: CODE PROTECTED PROGRAM MEMORY FOR PIC18F1220/1320 Block Code Protection Controlled By: CPB, WRTB, EBTRB MEMORY SIZE / DEVICE Address Range 4 Kbytes (PIC18F1220) 8 Kbytes (PIC18F1320) 000000h 0001FFh Boot Block Boot Block Address Range Block Code Protection Controlled By: 000000h CPB, WRTB, EBTRB 0001FFh 000200h 000200h Block 0 CP0, WRT0, EBTR0 0007FFh CP0, WRT0, EBTR0 Block 0 000800h CP1, WRT1, EBTR1 Block 1 000FFFh 000FFFh 001000h 001000h Block 1 (Unimplemented Memory Space) Unimplemented Read 0's CP1, WRT1, EBTR1 001FFFh 002000h Unimplemented Read 0's 1FFFFFh 1FFFFFh TABLE 19-3: (Unimplemented Memory Space) SUMMARY OF CODE PROTECTION REGISTERS File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CP1 CP0 300008h CONFIG5L -- -- -- -- -- -- 300009h CONFIG5H CPD CPB -- -- -- -- -- -- 30000Ah CONFIG6L -- -- -- -- -- -- WRT1 WRT0 30000Bh CONFIG6H WRTD WRTB WRTC -- -- -- -- -- 30000Ch CONFIG7L -- -- -- -- -- -- EBTR1 EBTR0 30000Dh CONFIG7H -- EBTRB -- -- -- -- -- -- Legend: Shaded cells are unimplemented. 2002 Microchip Technology Inc. Preliminary DS39605B-page 185 PIC18F1220/1320 19.5.1 PROGRAM MEMORY CODE PROTECTION The program memory may be read to, or written from, any location using the Table Read and Table Write instructions. The device ID may be read with Table Reads. The configuration registers may be read and written with the Table Read and Table Write instructions. A Table Read instruction that executes from a location outside of that block is not allowed to read, and will result in reading `0's. Figures 19-4 through 19-6 illustrate Table Write and Table Read protection. Note: In normal Execution mode, the CPn bits have no direct effect. CPn bits inhibit external reads and writes. A block of user memory may be protected from Table Writes if the WRTn configuration bit is `0'. The EBTRn bits control Table Reads. For a block of user memory with the EBTRn bit set to `0', a Table Read instruction that executes from within that block is allowed to read. FIGURE 19-4: Code protection bits may only be written to a `0' from a `1' state. It is not possible to write a `1' to a bit in the `0' state. Code protection bits are only set to `1' by a full chip erase or block erase function. The full chip erase and block erase functions can only be initiated via ICSP or an external programmer. TABLE WRITE (WRTn) DISALLOWED PIC18F1320 Register Values Program Memory Configuration Bit Settings 000000h 0001FFh 000200h TBLPTR = 0002FFh PC = 0007FEh WRTB,EBTRB = 11 WRT0,EBTR0 = 01 TBLWT * 000FFFh 001000h PC = 0017FEh TBLWT * WRT1,EBTR1 = 11 001FFFh Results: All Table Writes disabled to Blockn whenever WRTn = `0'. DS39605B-page 186 Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 FIGURE 19-5: EXTERNAL BLOCK TABLE READ (EBTRn) DISALLOWED PIC18F1320 Register Values Program Memory Configuration Bit Settings 000000h 0001FFh 000200h TBLPTR = 0002FFh WRTB,EBTRB = 11 WRT0,EBTR0 = 10 000FFFh 001000h PC = 001FFEh WRT1,EBTR1 = 11 TBLRD * 001FFFh Results: All Table Reads from external blocks to Blockn are disabled whenever EBTRn = `0'. TABLAT register returns a value of `0'. FIGURE 19-6: EXTERNAL BLOCK TABLE READ (EBTRn) ALLOWED PIC18F1320 Register Values Program Memory Configuration Bit Settings 000000h 0001FFh 000200h TBLPTR = 0002FFh PC = 0007FEh WRTB,EBTRB = 11 WRT0,EBTR0 = 10 TBLRD * 000FFFh 001000h WRT1,EBTR1 = 11 001FFFh Results: Table Reads permitted within Blockn, even when EBTRBn = `0'. TABLAT register returns the value of the data at the location TBLPTR. 2002 Microchip Technology Inc. Preliminary DS39605B-page 187 PIC18F1220/1320 19.5.2 DATA EEPROM CODE PROTECTION The entire data EEPROM is protected from external reads and writes by two bits: CPD and WRTD. CPD inhibits external reads and writes of Data EEPROM. WRTD inhibits external writes to Data EEPROM. The CPU can continue to read and write Data EEPROM, regardless of the protection bit settings. 19.5.3 CONFIGURATION REGISTER PROTECTION The configuration registers can be write protected. The WRTC bit controls protection of the configuration registers. In normal Execution mode, the WRTC bit is readable only. WRTC can only be written via ICSP or an external programmer. 19.6 ID Locations Eight memory locations (200000h - 200007h) are designated as ID locations, where the user can store checksum, or other code identification numbers. These locations are both readable and writable during normal execution through the TBLRD and TBLWT instructions, or during program/verify. The ID locations can be read when the device is code protected. 19.7 19.9 In-Circuit Debugger When the DEBUG bit in configuration register CONFIG4L is programmed to a '0', the In-Circuit Debugger functionality is enabled. This function allows simple debugging functions when used with MPLAB(R) IDE. When the microcontroller has this feature enabled, some resources are not available for general use. Table 19-4 shows which resources are required by the background debugger. TABLE 19-4: Low Voltage ICSP Programming The LVP bit in configuration register CONFIG4L enables Low Voltage Programming (LVP). When LVP is enabled, the microcontroller can be programmed without requiring high voltage being applied to the MCLR/VPP pin, but the RB5/PGM pin is then dedicated to controlling Program mode entry and is not available as a general purpose I/O pin. LVP is enabled in erased devices. While programming using LVP, VDD is applied to the MCLR/VPP pin as in normal Execution mode. To enter Programming mode, VDD is applied to the PGM pin. Note 1: High voltage programming is always available, regardless of the state of the LVP bit or the PGM pin, by applying VIHH to the MCLR pin. 2: When Low Voltage Programming is enabled, the RB5 pin can no longer be used as a general purpose I/O pin. In-Circuit Serial Programming PIC18F1220/1320 microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data and three other lines for power, ground and the programming voltage. This allows customers to manufacture boards with unprogrammed devices, and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. 19.8 To use the In-Circuit Debugger function of the microcontroller, the design must implement In-Circuit Serial Programming connections to MCLR/VPP, VDD, VSS, RB7 and RB6. This will interface to the In-Circuit Debugger module available from Microchip, or one of the third party development tool companies. 3: When LVP is enabled, externally pull the PGM pin to VSS to allow normal program execution. If Low Voltage Programming mode will not be used, the LVP bit can be cleared and RB5/PGM becomes available as the digital I/O pin RB5. The LVP bit may be set or cleared only when using standard high voltage programming (VIHH applied to the MCLR/VPP pin). Once LVP has been disabled, only the standard high voltage programming is available and must be used to program the device. Memory that is not code protected can be erased, using either a block erase, or erased row by row, then written at any specified VDD. If code protected memory is to be erased, a block erase is required. If a block erase is to be performed when using low voltage programming, the device must be supplied with VDD of 4.5V to 5.5V. DEBUGGER RESOURCES I/O pins: Stack: RB6, RB7 2 levels Program Memory: 512 bytes Data Memory: 10 bytes DS39605B-page 188 Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 20.0 INSTRUCTION SET SUMMARY The PIC18 instruction set adds many enhancements to the previous PICmicro instruction sets, while maintaining an easy migration from these PICmicro instruction sets. Most instructions are a single program memory word (16 bits), but there are three instructions that require two program memory locations. Each single word instruction is a 16-bit word divided into an OPCODE, which specifies the instruction type and one or more operands, which further specify the operation of the instruction. The instruction set is highly orthogonal and is grouped into four basic categories: * * * * Byte-oriented operations Bit-oriented operations Literal operations Control operations The PIC18 instruction set summary in Table 20-2 lists byte-oriented, bit-oriented, literal and control operations. Table 20-1 shows the opcode field descriptions. Most byte-oriented instructions have three operands: 1. 2. 3. The file register (specified by `f') The destination of the result (specified by `d') The accessed memory (specified by `a') The file register designator 'f' specifies which file register is to be used by the instruction. The destination designator `d' specifies where the result of the operation is to be placed. If 'd' is zero, the result is placed in the WREG register. If 'd' is one, the result is placed in the file register specified in the instruction. All bit-oriented instructions have three operands: 1. 2. 3. The file register (specified by `f') The bit in the file register (specified by `b') The accessed memory (specified by `a') * A program memory address (specified by `n') * The mode of the CALL or RETURN instructions (specified by `s') * The mode of the Table Read and Table Write instructions (specified by `m') * No operand required (specified by `--') All instructions are a single word, except for three double-word instructions. These three instructions were made double-word instructions, so that all the required information is available in these 32 bits. In the second word, the 4 MSbs are 1's. If this second word is executed as an instruction (by itself), it will execute as a NOP. All single word instructions are executed in a single instruction cycle, unless a conditional test is true, or the program counter is changed as a result of the instruction. In these cases, the execution takes two instruction cycles, with the additional instruction cycle(s) executed as a NOP. The double-word instructions execute in two instruction cycles. One instruction cycle consists of four oscillator periods. Thus, for an oscillator frequency of 4 MHz, the normal instruction execution time is 1 s. If a conditional test is true, or the program counter is changed as a result of an instruction, the instruction execution time is 2 s. Two-word branch instructions (if true) would take 3 s. Figure 20-1 shows the general formats that the instructions can have. All examples use the format `nnh' to represent a hexadecimal number, where `h' signifies a hexadecimal digit. The Instruction Set Summary, shown in Table 20-2, lists the instructions recognized by the Microchip Assembler (MPASMTM). Section 20.2 provides a description of each instruction. 20.1 The bit field designator 'b' selects the number of the bit affected by the operation, while the file register designator 'f' represents the number of the file in which the bit is located. The literal instructions may use some of the following operands: * A literal value to be loaded into a file register (specified by `k') * The desired FSR register to load the literal value into (specified by `f') * No operand required (specified by `--') 2002 Microchip Technology Inc. The control instructions may use some of the following operands: READ-MODIFY-WRITE OPERATIONS Any instruction that specifies a file register as part of the instruction performs a Read-Modify-Write (R-M-W) operation. The register is read, the data is modified, and the result is stored according to either the instruction or the destination designator `d'. A read operation is performed on a register even if the instruction writes to that register. For example, a "BCF PORTB,1" instruction will read PORTB, clear bit 1 of the data, then write the result back to PORTB. The read operation would have the unintended result that any condition that sets the RBIF flag would be cleared. The R-M-W operation may also copy the level of an input pin to its corresponding output latch. Preliminary DS39605B-page 189 PIC18F1220/1320 TABLE 20-1: OPCODE FIELD DESCRIPTIONS Field Description a RAM access bit a = 0: RAM location in Access RAM (BSR register is ignored) a = 1: RAM bank is specified by BSR register bbb Bit address within an 8-bit file register (0 to 7) BSR Bank Select Register. Used to select the current RAM bank. d Destination select bit; d = 0: store result in WREG, d = 1: store result in file register f. dest Destination either the WREG register or the specified register file location f 8-bit Register file address (0x00 to 0xFF) fs 12-bit Register file address (0x000 to 0xFFF). This is the source address. fd 12-bit Register file address (0x000 to 0xFFF). This is the destination address. k Literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value) label Label name mm The mode of the TBLPTR register for the Table Read and Table Write instructions. Only used with Table Read and Table Write instructions: * No Change to register (such as TBLPTR with Table reads and writes) *+ Post-Increment register (such as TBLPTR with Table reads and writes) *- Post-Decrement register (such as TBLPTR with Table reads and writes) Pre-Increment register (such as TBLPTR with Table reads and writes) +* n The relative address (2's complement number) for relative branch instructions, or the direct address for Call/Branch and Return instructions PRODH Product of Multiply high byte PRODL Product of Multiply low byte s Fast Call/Return mode select bit s = 0: do not update into/from shadow registers s = 1: certain registers loaded into/from shadow registers (Fast mode) u Unused or Unchanged WREG Working register (accumulator) x Don't care (0 or 1) The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. TBLPTR 21-bit Table Pointer (points to a Program Memory location) TABLAT 8-bit Table Latch TOS Top-of-Stack PC Program Counter PCL Program Counter Low Byte PCH Program Counter High Byte PCLATH Program Counter High Byte Latch PCLATU Program Counter Upper Byte Latch GIE Global Interrupt Enable bit WDT Watchdog Timer TO Time-out bit PD Power-down bit C, DC, Z, OV, N ALU status bits Carry, Digit Carry, Zero, Overflow, Negative [ ] Optional ( ) Contents Assigned to < > Register bit field In the set of italics User defined term (font is Courier) DS39605B-page 190 Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 FIGURE 20-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations 15 10 9 8 7 OPCODE d a Example Instruction 0 ADDWF MYREG, W, B f (FILE #) d = 0 for result destination to be WREG register d = 1 for result destination to be file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Byte to Byte move operations (2-word) 15 12 11 OPCODE 15 0 f (Source FILE #) 12 11 MOVFF MYREG1, MYREG2 0 f (Destination FILE #) 1111 f = 12-bit file register address Bit-oriented file register operations 15 12 11 9 8 7 OPCODE b (BIT #) a 0 BSF MYREG, bit, B f (FILE #) b = 3-bit position of bit in file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Literal operations 15 8 7 OPCODE 0 MOVLW 0x7F k (literal) k = 8-bit immediate value Control operations CALL, GOTO and Branch operations 15 8 7 OPCODE 15 0 GOTO Label n<7:0> (literal) 12 11 0 n<19:8> (literal) 1111 n = 20-bit immediate value 15 8 7 OPCODE 15 S 0 CALL MYFUNC n<7:0> (literal) 12 11 0 n<19:8> (literal) S = Fast bit 15 OPCODE 15 OPCODE 2002 Microchip Technology Inc. 11 10 0 BRA MYFUNC n<10:0> (literal) 8 7 0 n<7:0> (literal) Preliminary BC MYFUNC DS39605B-page 191 PIC18F1220/1320 TABLE 20-2: PIC18FXXXX INSTRUCTION SET Mnemonic, Operands Description Cycles 16-Bit Instruction Word MSb LSb Status Affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF 1 f, d, a Add WREG and f 0010 01da ffff ffff C, DC, Z, OV, N 1, 2 ADDWFC f, d, a Add WREG and Carry bit to f 1 0010 00da ffff ffff C, DC, Z, OV, N 1, 2 ANDWF 1 f, d, a AND WREG with f 0001 01da ffff ffff Z, N 1,2 CLRF 1 Clear f f, a 0110 101a ffff ffff Z 2 COMF 1 f, d, a Complement f 0001 11da ffff ffff Z, N 1, 2 CPFSEQ f, a 1 (2 or 3) 0110 001a ffff ffff None Compare f with WREG, skip = 4 CPFSGT f, a 1 (2 or 3) 0110 010a ffff ffff None Compare f with WREG, skip > 4 CPFSLT f, a 1 (2 or 3) 0110 000a ffff ffff None Compare f with WREG, skip < 1, 2 DECF 1 f, d, a Decrement f 0000 01da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4 DECFSZ f, d, a Decrement f, Skip if 0 1 (2 or 3) 0010 11da ffff ffff None 1, 2, 3, 4 DCFSNZ f, d, a Decrement f, Skip if Not 0 1 (2 or 3) 0100 11da ffff ffff None 1, 2 INCF 1 f, d, a Increment f 0010 10da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4 INCFSZ 1 (2 or 3) 0011 11da ffff ffff None f, d, a Increment f, Skip if 0 4 INFSNZ 1 (2 or 3) 0100 10da ffff ffff None f, d, a Increment f, Skip if Not 0 1, 2 IORWF 1 f, d, a Inclusive OR WREG with f 0001 00da ffff ffff Z, N 1, 2 MOVF 1 f, d, a Move f 0101 00da ffff ffff Z, N 1 MOVFF 2 fs, fd Move fs (source) to 1st word 1100 ffff ffff ffff None fd (destination)2nd word 1111 ffff ffff ffff Move WREG to f MOVWF f, a 1 0110 111a ffff ffff None Multiply WREG with f f, a MULWF 1 0000 001a ffff ffff None Negate f f, a NEGF 1 0110 110a ffff ffff C, DC, Z, OV, N 1, 2 f, d, a Rotate Left f through Carry RLCF 1 0011 01da ffff ffff C, Z, N f, d, a Rotate Left f (No Carry) RLNCF 1 0100 01da ffff ffff Z, N 1, 2 f, d, a Rotate Right f through Carry RRCF 1 0011 00da ffff ffff C, Z, N f, d, a Rotate Right f (No Carry) RRNCF 1 0100 00da ffff ffff Z, N Set f f, a SETF 1 0110 100a ffff ffff None SUBFWB f, d, a Subtract f from WREG with 1 0101 01da ffff ffff C, DC, Z, OV, N 1, 2 borrow f, d, a Subtract WREG from f SUBWF 1 0101 11da ffff ffff C, DC, Z, OV, N SUBWFB f, d, a Subtract WREG from f with 1 0101 10da ffff ffff C, DC, Z, OV, N 1, 2 borrow f, d, a Swap nibbles in f SWAPF 1 0011 10da ffff ffff None 4 Test f, skip if 0 TSTFSZ f, a 1 (2 or 3) 0110 011a ffff ffff None 1, 2 XORWF f, d, a Exclusive OR WREG with f 1 0001 10da ffff ffff Z, N BIT-ORIENTED FILE REGISTER OPERATIONS BCF f, b, a Bit Clear f 1 1001 bbba ffff ffff None 1, 2 BSF f, b, a Bit Set f 1 1000 bbba ffff ffff None 1, 2 BTFSC f, b, a Bit Test f, Skip if Clear 1 (2 or 3) 1011 bbba ffff ffff None 3, 4 BTFSS f, b, a Bit Test f, Skip if Set 1 (2 or 3) 1010 bbba ffff ffff None 3, 4 BTG f, d, a Bit Toggle f 1 0111 bbba ffff ffff None 1, 2 Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external device, the data will be written back with a '0'. 2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if assigned. 3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 4: Some instructions are 2-word instructions. The second word of these instructions will be executed as a NOP, unless the first word of the instruction retrieves the information embedded in these 16-bits. This ensures that all program memory locations have a valid instruction. 5: If the Table Write starts the write cycle to internal memory, the write will continue until terminated. DS39605B-page 192 Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 TABLE 20-2: Mnemonic, Operands PIC18FXXXX INSTRUCTION SET (CONTINUED) Description CONTROL OPERATIONS BC n Branch if Carry BN n Branch if Negative BNC n Branch if Not Carry BNN n Branch if Not Negative BNOV n Branch if Not Overflow BNZ n Branch if Not Zero BOV n Branch if Overflow BRA n Branch Unconditionally BZ n Branch if Zero CALL n, s Call subroutine 1st word 2nd word CLRWDT -- Clear Watchdog Timer DAW -- Decimal Adjust WREG GOTO n Go to address 1st word 2nd word NOP -- No Operation NOP -- No Operation POP -- Pop top of return stack (TOS) PUSH -- Push top of return stack (TOS) RCALL n Relative Call RESET Software device RESET RETFIE s Return from interrupt enable Cycles 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 2 1 (2) 1 (2) 1 (2) 2 1 1 2 16-Bit Instruction Word MSb 1110 1110 1110 1110 1110 1110 1110 1101 1110 1110 1111 0000 0000 1110 1111 0000 1111 0000 0000 1101 0000 0000 LSb 0010 0110 0011 0111 0101 0001 0100 0nnn 0000 110s kkkk 0000 0000 1111 kkkk 0000 xxxx 0000 0000 1nnn 0000 0000 nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn kkkk kkkk 0000 0000 kkkk kkkk 0000 xxxx 0000 0000 nnnn 1111 0001 nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn kkkk kkkk 0100 0111 kkkk kkkk 0000 xxxx 0110 0101 nnnn 1111 000s Status Affected Notes None None None None None None None None None None TO, PD C None None 4 None None None None All GIE/GIEH, PEIE/GIEL RETLW k Return with literal in WREG 2 0000 1100 kkkk kkkk None RETURN s Return from Subroutine 2 0000 0000 0001 001s None SLEEP -- Go into Standby mode 1 0000 0000 0000 0011 TO, PD Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external device, the data will be written back with a '0'. 2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if assigned. 3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 4: Some instructions are 2-word instructions. The second word of these instructions will be executed as a NOP, unless the first word of the instruction retrieves the information embedded in these 16-bits. This ensures that all program memory locations have a valid instruction. 5: If the Table Write starts the write cycle to internal memory, the write will continue until terminated. 2002 Microchip Technology Inc. 1 1 1 1 2 1 2 Preliminary DS39605B-page 193 PIC18F1220/1320 TABLE 20-2: PIC18FXXXX INSTRUCTION SET (CONTINUED) Mnemonic, Operands Description Cycles 16-Bit Instruction Word MSb LSb Status Affected Notes LITERAL OPERATIONS ADDLW k Add literal and WREG 1 0000 1111 kkkk kkkk C, DC, Z, OV, N ANDLW k AND literal with WREG 1 0000 1011 kkkk kkkk Z, N IORLW k Inclusive OR literal with WREG 1 0000 1001 kkkk kkkk Z, N LFSR f, k Move literal (12-bit)2nd word 2 1110 1110 00ff kkkk None to FSRx 1st word 1111 0000 kkkk kkkk MOVLB k Move literal to BSR<3:0> 1 0000 0001 0000 kkkk None MOVLW k Move literal to WREG 1 0000 1110 kkkk kkkk None MULLW k Multiply literal with WREG 1 0000 1101 kkkk kkkk None RETLW k Return with literal in WREG 2 0000 1100 kkkk kkkk None SUBLW k Subtract WREG from literal 1 0000 1000 kkkk kkkk C, DC, Z, OV, N XORLW k Exclusive OR literal with WREG 1 0000 1010 kkkk kkkk Z, N DATA MEMORY PROGRAM MEMORY OPERATIONS TBLRD* Table Read 2 0000 0000 0000 1000 None TBLRD*+ Table Read with post-increment 0000 0000 0000 1001 None TBLRD*Table Read with post-decrement 0000 0000 0000 1010 None TBLRD+* Table Read with pre-increment 0000 0000 0000 1011 None TBLWT* Table Write 2 (5) 0000 0000 0000 1100 None TBLWT*+ Table Write with post-increment 0000 0000 0000 1101 None TBLWT*Table Write with post-decrement 0000 0000 0000 1110 None TBLWT+* Table Write with pre-increment 0000 0000 0000 1111 None Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external device, the data will be written back with a '0'. 2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if assigned. 3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 4: Some instructions are 2-word instructions. The second word of these instructions will be executed as a NOP, unless the first word of the instruction retrieves the information embedded in these 16-bits. This ensures that all program memory locations have a valid instruction. 5: If the Table Write starts the write cycle to internal memory, the write will continue until terminated. DS39605B-page 194 Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 20.2 Instruction Set ADDLW ADD literal to W Syntax: [ label ] ADDLW Operands: 0 k 255 Operation: (W) + k W Status Affected: N, OV, C, DC, Z Encoding: 0000 Description: 1111 kkkk kkkk The contents of W are added to the 8-bit literal 'k' and the result is placed in W. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Decode Example: Q2 Q3 Q4 Read literal 'k' Process Data Write to W ADDLW 0x15 Before Instruction W k = ADDWF ADD W to f Syntax: [ label ] ADDWF Operands: 0 f 255 d [0,1] a [0,1] Operation: (W) + (f) dest Status Affected: N, OV, C, DC, Z Encoding: 0010 01da f [,d [,a]] ffff ffff Description: Add W to register 'f'. If 'd' is 0, the result is stored in W. If 'd' is 1, the result is stored back in register 'f' (default). If `a' is 0, the Access Bank will be selected. If `a' is 1, the BSR is used. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Decode 0x10 Q2 Q3 Q4 Read register 'f' Process Data Write to destination After Instruction W = 0x25 Example: ADDWF REG, W Before Instruction W REG = = 0x17 0xC2 After Instruction W REG 2002 Microchip Technology Inc. Preliminary = = 0xD9 0xC2 DS39605B-page 195 PIC18F1220/1320 ADDWFC ADD W and Carry bit to f ANDLW AND literal with W Syntax: [ label ] ADDWFC Syntax: [ label ] ANDLW Operands: 0 f 255 d [0,1] a [0,1] f [,d [,a]] Operation: (W) + (f) + (C) dest Status Affected: N,OV, C, DC, Z Encoding: 0010 Description: 1 Cycles: 1 0 k 255 Operation: (W) .AND. k W Status Affected: N,Z Encoding: ffff ffff Add W, the Carry Flag and data memory location 'f'. If 'd' is 0, the result is placed in W. If 'd' is 1, the result is placed in data memory location 'f'. If `a' is 0, the Access Bank will be selected. If `a' is 1, the BSR will not be overridden. Words: 0000 kkkk kkkk The contents of W are ANDed with the 8-bit literal 'k'. The result is placed in W. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Decode Q2 Q3 Q4 Read literal 'k' Process Data Write to W ANDLW 0x5F Before Instruction Q2 Q3 Q4 Read register 'f' Process Data Write to destination ADDWFC REG, W W = 0xA3 After Instruction W Example: 1011 Description: Example: Q Cycle Activity: Q1 Decode 00da Operands: k = 0x03 Before Instruction Carry bit = REG = W = 1 0x02 0x4D After Instruction Carry bit = REG = W = DS39605B-page 196 0 0x02 0x50 Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 ANDWF AND W with f Syntax: [ label ] ANDWF Operands: 0 f 255 d [0,1] a [0,1] f [,d [,a]] Operation: (W) .AND. (f) dest Status Affected: N,Z Encoding: 0001 ffff ffff [ label ] BC Operands: -128 n 127 Operation: if carry bit is '1' (PC) + 2 + 2n PC Status Affected: None nnnn nnnn Words: 1 1 Cycles: 1(2) Q Cycle Activity: Q1 Q2 Q3 Q4 Read register 'f' Process Data Write to destination ANDWF = = Q Cycle Activity: If Jump: Q1 REG, W Before Instruction 0x17 0xC2 0x02 0xC2 Q2 Q3 Q4 Decode Read literal 'n' Process Data Write to PC No operation No operation No operation No operation If No Jump: Q1 Decode After Instruction = = 0010 1 Cycles: W REG 1110 n If the Carry bit is `1', then the program will branch. The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC+2+2n. This instruction is then a two-cycle instruction. Words: W REG Syntax: Description: The contents of W are AND'ed with register 'f'. If 'd' is 0, the result is stored in W. If 'd' is 1, the result is stored back in register 'f' (default). If `a' is 0, the Access Bank will be selected. If `a' is 1, the BSR will not be overridden (default). Example: Branch if Carry Encoding: 01da Description: Decode BC Example: Q2 Q3 Q4 Read literal 'n' Process Data No operation HERE BC JUMP Before Instruction PC = address (HERE) = = = = 1; address (JUMP) 0; address (HERE+2) After Instruction If Carry PC If Carry PC 2002 Microchip Technology Inc. Preliminary DS39605B-page 197 PIC18F1220/1320 BCF Bit Clear f Syntax: [ label ] BCF Operands: 0 f 255 0b7 a [0,1] Operation: 0 f<b> Status Affected: None Encoding: 1001 Description: Branch if Negative Syntax: [ label ] BN Operands: -128 n 127 Operation: if negative bit is '1' (PC) + 2 + 2n PC Status Affected: None Encoding: bbba ffff ffff 1110 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Read register 'f' Process Data Write register 'f' Example: BCF FLAG_REG, FLAG_REG = 0xC7 FLAG_REG = 0x47 0110 nnnn nnnn If the Negative bit is '1', then the program will branch. The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC+2+2n. This instruction is then a two-cycle instruction. Words: 1 Cycles: 1(2) Q Cycle Activity: If Jump: Q1 Q2 Q3 Q4 Decode Read literal 'n' Process Data Write to PC No operation No operation No operation No operation 7 Before Instruction After Instruction n Description: Bit 'b' in register 'f' is cleared. If `a' is 0, the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). Words: Decode f,b[,a] BN If No Jump: Q1 Decode Q2 Q3 Q4 Read literal 'n' Process Data No operation Example: HERE BN Jump Before Instruction PC = address (HERE) = = = = 1; address (Jump) 0; address (HERE+2) After Instruction If Negative PC If Negative PC DS39605B-page 198 Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 BNC Branch if Not Carry BNN Branch if Not Negative Syntax: [ label ] BNC Syntax: [ label ] BNN Operands: -128 n 127 Operands: -128 n 127 Operation: if carry bit is '0' (PC) + 2 + 2n PC Operation: if negative bit is '0' (PC) + 2 + 2n PC Status Affected: None Status Affected: None Encoding: 1110 n 0011 nnnn nnnn Encoding: 1110 n 0111 nnnn nnnn Description: If the Carry bit is '0', then the program will branch. The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC+2+2n. This instruction is then a two-cycle instruction. Description: If the Negative bit is '0', then the program will branch. The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC+2+2n. This instruction is then a two-cycle instruction. Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Q Cycle Activity: If Jump: Q1 Q Cycle Activity: If Jump: Q1 Q2 Q3 Q4 Q2 Q3 Q4 Decode Read literal 'n' Process Data Write to PC Decode Read literal 'n' Process Data Write to PC No operation No operation No operation No operation No operation No operation No operation No operation Q2 Q3 Q4 Read literal 'n' Process Data No operation If No Jump: Q1 Decode Example: HERE BNC Jump If No Jump: Q1 Decode Q4 No operation HERE BNN Jump Before Instruction = address (HERE) PC After Instruction If Carry PC If Carry PC Q3 Process Data Example: Before Instruction PC Q2 Read literal 'n' = address (HERE) = = = = 0; address (Jump) 1; address (HERE+2) After Instruction = = = = 0; address (Jump) 1; address (HERE+2) 2002 Microchip Technology Inc. If Negative PC If Negative PC Preliminary DS39605B-page 199 PIC18F1220/1320 BNOV Branch if Not Overflow BNZ Branch if Not Zero Syntax: [ label ] BNOV Syntax: [ label ] BNZ Operands: -128 n 127 Operands: -128 n 127 Operation: if overflow bit is '0' (PC) + 2 + 2n PC Operation: if zero bit is '0' (PC) + 2 + 2n PC Status Affected: None Status Affected: None Encoding: 1110 n 0101 nnnn nnnn Encoding: 1110 n 0001 nnnn nnnn Description: If the Overflow bit is `0', then the program will branch. The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC+2+2n. This instruction is then a two-cycle instruction. Description: If the Zero bit is `0', then the program will branch. The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC+2+2n. This instruction is then a two-cycle instruction. Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Q Cycle Activity: If Jump: Q1 Q Cycle Activity: If Jump: Q1 Q2 Q3 Q4 Q2 Q3 Q4 Decode Read literal 'n' Process Data Write to PC Decode Read literal 'n' Process Data Write to PC No operation No operation No operation No operation No operation No operation No operation No operation Q2 Q3 Q4 Read literal 'n' Process Data No operation If No Jump: Q1 Decode Example: HERE BNOV Jump If No Jump: Q1 Decode Example: Before Instruction PC DS39605B-page 200 Q3 Q4 Process Data No operation HERE BNZ Jump Before Instruction = address (HERE) PC After Instruction If Overflow PC If Overflow PC Q2 Read literal 'n' = address (HERE) = = = = 0; address (Jump) 1; address (HERE+2) After Instruction = = = = 0; address (Jump) 1; address (HERE+2) If Zero PC If Zero PC Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 BRA Unconditional Branch BSF Bit Set f Syntax: [ label ] BRA Syntax: [ label ] BSF Operands: -1024 n 1023 Operands: Operation: (PC) + 2 + 2n PC Status Affected: None 0 f 255 0b7 a [0,1] Operation: 1 f<b> Status Affected: None Encoding: Description: 1101 1 Cycles: 2 Q Cycle Activity: Q1 No operation 0nnn nnnn nnnn Add the 2's complement number `2n' to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC+2+2n. This instruction is a two-cycle instruction. Words: Decode n Q2 Q3 Q4 Read literal 'n' Process Data Write to PC No operation No operation No operation Encoding: HERE BRA 1 Cycles: 1 Q Cycle Activity: Q1 Decode Q3 Q4 Process Data Write register 'f' BSF = address (Jump) 2002 Microchip Technology Inc. FLAG_REG, 7 Before Instruction = 0x0A = 0x8A After Instruction FLAG_REG After Instruction PC Q2 Read register 'f' FLAG_REG address (HERE) ffff Words: Jump = ffff Bit 'b' in register 'f' is set. If `a' is 0, Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value. Before Instruction PC bbba Description: Example: Example: 1000 f,b[,a] Preliminary DS39605B-page 201 PIC18F1220/1320 BTFSC Bit Test File, Skip if Clear BTFSS Bit Test File, Skip if Set Syntax: [ label ] BTFSC f,b[,a] Syntax: [ label ] BTFSS f,b[,a] Operands: 0 f 255 0b7 a [0,1] Operands: 0 f 255 0b<7 a [0,1] Operation: skip if (f<b>) = 0 Operation: skip if (f<b>) = 1 Status Affected: None Status Affected: None Encoding: 1011 bbba ffff ffff Encoding: 1010 bbba ffff ffff Description: If bit 'b' in register 'f' is 0, then the next instruction is skipped. If bit 'b' is 0, then the next instruction fetched during the current instruction execution is discarded, and a NOP is executed instead, making this a two-cycle instruction. If `a' is 0, the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). Description: If bit 'b' in register 'f' is 1, then the next instruction is skipped. If bit 'b' is 1, then the next instruction fetched during the current instruction execution, is discarded and a NOP is executed instead, making this a two-cycle instruction. If `a' is 0, the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). Words: 1 Words: 1 Cycles: 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Cycles: 1(2) Note: Q Cycle Activity: Q1 Decode Q2 Q3 Q4 Read register 'f' Process Data No operation If skip: Q Cycle Activity: Q1 Decode 3 cycles if skip and followed by a 2-word instruction. Q2 Q3 Q4 Read register 'f' Process Data No operation If skip: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation Example: HERE FALSE TRUE BTFSC : : FLAG, 1 Example: Before Instruction PC DS39605B-page 202 BTFSS : : FLAG, 1 Before Instruction = address (HERE) PC After Instruction If FLAG<1> PC If FLAG<1> PC HERE FALSE TRUE = address (HERE) = = = = 0; address (FALSE) 1; address (TRUE) After Instruction = = = = 0; address (TRUE) 1; address (FALSE) If FLAG<1> PC If FLAG<1> PC Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 BTG Bit Toggle f BOV Branch if Overflow Syntax: [ label ] BTG f,b[,a] Syntax: [ label ] BOV Operands: 0 f 255 0b<7 a [0,1] Operands: -128 n 127 Operation: if overflow bit is '1' (PC) + 2 + 2n PC Status Affected: None Operation: (f<b>) f<b> Status Affected: None Encoding: Description: bbba ffff ffff 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Read register 'f' Process Data Write register 'f' Example: BTG PORTB, = 0111 0101 [0x75] PORTB = 0110 0101 [0x65] nnnn nnnn If the Overflow bit is `1', then the program will branch. The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC+2+2n. This instruction is then a two-cycle instruction. Words: 1 Cycles: 1(2) Q Cycle Activity: If Jump: Q1 Q2 Q3 Q4 Decode Read literal 'n' Process Data Write to PC No operation No operation No operation No operation 4 After Instruction: 0100 Description: Before Instruction: PORTB 1110 Bit 'b' in data memory location 'f' is inverted. If `a' is 0, the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). Words: Decode Encoding: 0111 n If No Jump: Q1 Decode Q2 Q3 Q4 Read literal 'n' Process Data No operation Example: HERE BOV JUMP Before Instruction PC = address (HERE) = = = = 1; address (JUMP) 0; address (HERE+2) After Instruction If Overflow PC If Overflow PC 2002 Microchip Technology Inc. Preliminary DS39605B-page 203 PIC18F1220/1320 BZ Branch if Zero CALL Subroutine Call Syntax: [ label ] BZ Syntax: [ label ] CALL k [,s] Operands: -128 n 127 Operands: Operation: if Zero bit is '1' (PC) + 2 + 2n PC 0 k 1048575 s [0,1] Operation: (PC) + 4 TOS, k PC<20:1>, if s = 1 (W) WS, (STATUS) STATUSS, (BSR) BSRS Status Affected: None Status Affected: n None Encoding: 1110 Description: 0000 nnnn nnnn If the Zero bit is `1', then the program will branch. The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC+2+2n. This instruction is then a two-cycle instruction. Words: 1 Cycles: 1(2) Q Cycle Activity: If Jump: Q1 Q2 Q3 Q4 Decode Read literal 'n' Process Data Write to PC No operation No operation No operation No operation Q2 Q3 Q4 Read literal 'n' Process Data No operation If No Jump: Q1 Decode Example: HERE BZ Encoding: 1st word (k<7:0>) 2nd word(k<19:8>) 1110 1111 110s k19kkk k7kkk kkkk Description: Subroutine call of entire 2 Mbyte memory range. First, return address (PC+ 4) is pushed onto the return stack. If `s' = 1, the W, STATUS and BSR registers are also pushed into their respective shadow registers, WS, STATUSS and BSRS. If 's' = 0, no update occurs (default). Then, the 20-bit value `k' is loaded into PC<20:1>. CALL is a two-cycle instruction. Words: 2 Cycles: 2 Q Cycle Activity: Q1 Jump Q2 Q3 Q4 Decode Read literal 'k'<7:0>, Push PC to stack Read literal 'k'<19:8>, Write to PC No operation No operation No operation No operation Before Instruction PC = address (HERE) = = = = 1; address (Jump) 0; address (HERE+2) After Instruction If Zero PC If Zero PC kkkk0 kkkk8 Example: HERE CALL THERE,FAST Before Instruction PC = address (HERE) After Instruction PC = TOS = WS = BSRS = STATUSS= DS39605B-page 204 Preliminary address (THERE) address (HERE + 4) W BSR STATUS 2002 Microchip Technology Inc. PIC18F1220/1320 CLRF Clear f Syntax: [ label ] CLRF Operands: 0 f 255 a [0,1] Operation: 000h f 1Z Status Affected: Z Encoding: Description: 0110 f [,a] 101a ffff ffff CLRWDT Clear Watchdog Timer Syntax: [ label ] CLRWDT Operands: None Operation: 000h WDT, 000h WDT postscaler, 1 TO, 1 PD Status Affected: TO, PD Encoding: 0000 0000 0000 0100 Clears the contents of the specified register. If `a' is 0, the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). Description: CLRWDT instruction resets the Watchdog Timer. It also resets the postscaler of the WDT. Status bits TO and PD are set. Words: 1 Words: 1 Cycles: 1 Cycles: 1 Q Cycle Activity: Q1 Decode Q Cycle Activity: Q1 Q2 Q3 Q4 Read register 'f' Process Data Write register 'f' Decode Example: Example: CLRF FLAG_REG Q4 No operation CLRWDT WDT Counter = 0x5A = 0x00 2002 Microchip Technology Inc. = ? = = = = 0x00 0 1 1 After Instruction After Instruction FLAG_REG Q3 Process Data Before Instruction Before Instruction FLAG_REG Q2 No operation WDT Counter WDT Postscaler TO PD Preliminary DS39605B-page 205 PIC18F1220/1320 COMF Complement f Syntax: [ label ] COMF Operands: 0 f 255 d [0,1] a [0,1] Operation: ( f ) dest Status Affected: N, Z Encoding: 0001 Description: 1 Cycles: 1 Q Cycle Activity: Q1 Syntax: [ label ] CPFSEQ Operands: 0 f 255 a [0,1] Operation: (f) - (W), skip if (f) = (W) (unsigned comparison) Status Affected: None Encoding: 0110 001a f [,a] ffff ffff Description: Compares the contents of data memory location 'f' to the contents of W by performing an unsigned subtraction. If 'f' = W, then the fetched instruction is discarded and a NOP is executed instead, making this a two-cycle instruction. If `a' is 0, the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). Q2 Q3 Q4 Words: 1 Process Data Write to destination Cycles: 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. COMF Before Instruction = 0x13 After Instruction REG W ffff Compare f with W, skip if f = W Read register 'f' Example: REG ffff The contents of register 'f' are complemented. If 'd' is 0, the result is stored in W. If 'd' is 1, the result is stored back in register 'f' (default). If `a' is 0, the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). Words: Decode 11da f [,d [,a] CPFSEQ = = 0x13 0xEC REG, W Q Cycle Activity: Q1 Decode Q2 Q3 Q4 Read register 'f' Process Data No operation If skip: Q1 Q2 Q3 Q4 No operation No operation No operation No operation If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation Example: HERE NEQUAL EQUAL CPFSEQ REG : : Before Instruction PC Address W REG = = = HERE ? ? = = = W; Address (EQUAL) W; Address (NEQUAL) After Instruction If REG PC If REG PC DS39605B-page 206 Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 CPFSGT Compare f with W, skip if f > W CPFSLT Compare f with W, skip if f < W Syntax: [ label ] CPFSGT Syntax: [ label ] CPFSLT Operands: 0 f 255 a [0,1] Operands: 0 f 255 a [0,1] Operation: (f) - (W), skip if (f) > (W) (unsigned comparison) Operation: (f) - (W), skip if (f) < (W) (unsigned comparison) Status Affected: None Status Affected: None Encoding: Description: 0110 010a f [,a] ffff ffff Compares the contents of data memory location 'f' to the contents of the W by performing an unsigned subtraction. If the contents of 'f' are greater than the contents of WREG, then the fetched instruction is discarded and a NOP is executed instead, making this a two-cycle instruction. If `a' is 0, the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). Words: 1 Cycles: 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q1 Decode Encoding: Q2 Q3 Q4 Process Data No operation Q2 Q3 Q4 No operation No operation No operation No operation If skip and followed by 2-word instruction: Q1 Q2 Q3 Words: 1 Cycles: 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q1 Q4 No operation If skip: Q1 Q2 Q3 Q4 No operation No operation No operation No operation If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 Q4 No operation No operation No operation No operation No operation HERE NLESS LESS CPFSLT REG : : No operation No operation No operation No operation No operation HERE NGREATER GREATER CPFSGT REG : : Example: Before Instruction PC W Before Instruction = = Address (HERE) ? > = = W; Address (GREATER) W; Address (NGREATER) = = Address (HERE) ? < = = W; Address (LESS) W; Address (NLESS) After Instruction If REG PC If REG PC After Instruction 2002 Microchip Technology Inc. Q3 Process Data No operation No operation If REG PC If REG PC Q2 Read register 'f' No operation No operation PC W ffff No operation No operation Example: ffff Compares the contents of data memory location 'f' to the contents of W by performing an unsigned subtraction. If the contents of 'f' are less than the contents of W, then the fetched instruction is discarded and a NOP is executed instead, making this a two-cycle instruction. If `a' is 0, the Access Bank will be selected. If `a' is 1, the BSR will not be overridden (default). If skip: Q1 000a Description: Decode Read register 'f' 0110 f [,a] Preliminary DS39605B-page 207 PIC18F1220/1320 DAW Decimal Adjust W Register DECF Decrement f Syntax: [ label ] DAW Syntax: [ label ] DECF f [,d [,a]] Operands: None Operands: Operation: If [W<3:0> >9] or [DC = 1] then (W<3:0>) + 6 W<3:0>; else (W<3:0>) W<3:0>; 0 f 255 d [0,1] a [0,1] Operation: (f) - 1 dest Status Affected: C, DC, N, OV, Z Encoding: If [W<7:4> >9] or [C = 1] then (W<7:4>) + 6 W<7:4>; else (W<7:4>) W<7:4>; Status Affected: Encoding: 0000 0000 0000 Words: 1 Cycles: 1 Q Cycle Activity: Q1 1 Cycles: 1 Decode Q2 Q3 Q4 Process Data Write W Example1: DAW = = = Q2 Q3 Q4 Read register 'f' Process Data Write to destination Example: DECF CNT, Before Instruction CNT Z Before Instruction W C DC ffff Words: Q Cycle Activity: Q1 Read register W ffff Decrement register 'f'. If 'd' is 0, the result is stored in W. If 'd' is 1, the result is stored back in register 'f' (default). If 'a' is 0, the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). 0111 DAW adjusts the eight-bit value in W, resulting from the earlier addition of two variables (each in packed BCD format) and produces a correct packed BCD result. 01da Description: C Description: Decode 0000 = = 0x01 0 After Instruction 0xA5 0 0 CNT Z = = 0x00 1 After Instruction W C DC Example 2: = = = 0x05 1 0 Before Instruction W C DC = = = 0xCE 0 0 After Instruction W C DC = = = DS39605B-page 208 0x34 1 0 Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 DECFSZ Decrement f, skip if 0 DCFSNZ Decrement f, skip if not 0 Syntax: [ label ] DECFSZ f [,d [,a]] Syntax: [ label ] DCFSNZ Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 f 255 d [0,1] a [0,1] Operation: (f) - 1 dest, skip if result = 0 Operation: (f) - 1 dest, skip if result 0 Status Affected: None Status Affected: None Encoding: 0010 11da ffff ffff Encoding: 0100 11da f [,d [,a]] ffff ffff Description: The contents of register 'f' are decremented. If 'd' is 0, the result is placed in W. If 'd' is 1, the result is placed back in register 'f' (default). If the result is 0, the next instruction, which is already fetched, is discarded and a NOP is executed instead, making it a two-cycle instruction. If `a' is 0, the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). Description: The contents of register 'f' are decremented. If 'd' is 0, the result is placed in W. If 'd' is 1, the result is placed back in register 'f' (default). If the result is not 0, the next instruction, which is already fetched, is discarded, and a NOP is executed instead, making it a two-cycle instruction. If `a' is 0, the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). Words: 1 Words: 1 Cycles: 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Cycles: 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q1 Decode Q Cycle Activity: Q1 Q2 Q3 Q4 Read register 'f' Process Data Write to destination If skip: Decode Q2 Q3 Q4 Read register 'f' Process Data Write to destination If skip: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation If skip and followed by 2-word instruction: Q1 Q2 Q3 If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 Q4 No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation Example: HERE DECFSZ GOTO CNT LOOP Example: CONTINUE Before Instruction PC = = = = = DCFSNZ : : TEMP Before Instruction Address (HERE) TEMP After Instruction CNT If CNT PC If CNT PC HERE ZERO NZERO = ? = = = = TEMP - 1, 0; Address (ZERO) 0; Address (NZERO) After Instruction CNT - 1 0; Address (CONTINUE) 0; Address (HERE+2) 2002 Microchip Technology Inc. TEMP If TEMP PC If TEMP PC Preliminary DS39605B-page 209 PIC18F1220/1320 GOTO Unconditional Branch INCF Increment f Syntax: [ label ] Syntax: [ label ] Operands: 0 k 1048575 Operands: Operation: k PC<20:1> Status Affected: None 0 f 255 d [0,1] a [0,1] Operation: (f) + 1 dest Status Affected: C, DC, N, OV, Z Encoding: 1st word (k<7:0>) 2nd word(k<19:8>) Description: 1110 1111 GOTO k 1111 k19kkk k7kkk kkkk kkkk0 kkkk8 GOTO allows an unconditional branch anywhere within entire 2 Mbyte memory range. The 20-bit value `k' is loaded into PC<20:1>. GOTO is always a two-cycle instruction. Words: 2 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal 'k'<7:0>, No operation Read literal 'k'<19:8>, Write to PC No operation No operation No operation No operation Example: GOTO THERE Encoding: f [,d [,a]] 10da ffff ffff Description: The contents of register 'f' are incremented. If 'd' is 0, the result is placed in W. If 'd' is 1, the result is placed back in register 'f' (default). If `a' is 0, the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). Words: 1 Cycles: 1 Q Cycle Activity: Q1 Decode Q2 Q3 Q4 Read register 'f' Process Data Write to destination Example: After Instruction PC = 0010 INCF INCF CNT, Before Instruction Address (THERE) CNT Z C DC = = = = 0xFF 0 ? ? After Instruction CNT Z C DC DS39605B-page 210 Preliminary = = = = 0x00 1 1 1 2002 Microchip Technology Inc. PIC18F1220/1320 INCFSZ Increment f, skip if 0 INFSNZ Increment f, skip if not 0 Syntax: [ label ] Syntax: [ label ] Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 f 255 d [0,1] a [0,1] Operation: (f) + 1 dest, skip if result = 0 Operation: (f) + 1 dest, skip if result 0 Status Affected: None Status Affected: None Encoding: 0011 INCFSZ 11da f [,d [,a]] ffff ffff Encoding: 0100 INFSNZ 10da f [,d [,a]] ffff ffff Description: The contents of register 'f' are incremented. If 'd' is 0, the result is placed in W. If 'd' is 1, the result is placed back in register 'f' (default). If the result is 0, the next instruction, which is already fetched, is discarded and a NOP is executed instead, making it a two-cycle instruction. If `a' is 0, the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). Description: The contents of register 'f' are incremented. If 'd' is 0, the result is placed in W. If 'd' is 1, the result is placed back in register 'f' (default). If the result is not 0, the next instruction, which is already fetched, is discarded and a NOP is executed instead, making it a two-cycle instruction. If `a' is 0, the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). Words: 1 Words: 1 Cycles: 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Cycles: 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q1 Decode Q Cycle Activity: Q1 Q2 Q3 Q4 Read register 'f' Process Data Write to destination If skip: Decode Q2 Q3 Q4 Read register 'f' Process Data Write to destination If skip: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation If skip and followed by 2-word instruction: Q1 Q2 Q3 If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 Q4 No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation Example: HERE NZERO ZERO INCFSZ : : CNT Example: Before Instruction PC = = = = = INFSNZ REG Before Instruction Address (HERE) PC After Instruction CNT If CNT PC If CNT PC HERE ZERO NZERO = Address (HERE) After Instruction CNT + 1 0; Address (ZERO) 0; Address (NZERO) 2002 Microchip Technology Inc. REG If REG PC If REG PC Preliminary = = = = REG + 1 0; Address (NZERO) 0; Address (ZERO) DS39605B-page 211 PIC18F1220/1320 IORLW Inclusive OR literal with W IORWF Inclusive OR W with f Syntax: [ label ] Syntax: [ label ] Operands: 0 f 255 d [0,1] a [0,1] Operation: (W) .OR. (f) dest Status Affected: N, Z IORLW k Operands: 0 k 255 Operation: (W) .OR. k W Status Affected: N, Z Encoding: 0000 Description: kkkk kkkk The contents of W are OR'ed with the eight-bit literal 'k'. The result is placed in W. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Decode Example: Q2 Q3 Q4 Read literal 'k' Process Data Write to W IORLW Before Instruction W 1001 = 0x9A 0x35 Encoding: = 00da f [,d [,a]] ffff ffff Description: Inclusive OR W with register 'f'. If 'd' is 0, the result is placed in W. If 'd' is 1, the result is placed back in register 'f' (default). If `a' is 0, the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). Words: 1 Cycles: 1 Q Cycle Activity: Q1 After Instruction W 0001 IORWF Decode 0xBF Q2 Q3 Q4 Read register 'f' Process Data Write to destination Example: IORWF RESULT, W Before Instruction RESULT = W = 0x13 0x91 After Instruction RESULT = W = DS39605B-page 212 Preliminary 0x13 0x93 2002 Microchip Technology Inc. PIC18F1220/1320 LFSR Load FSR MOVF Move f Syntax: [ label ] Syntax: [ label ] Operands: 0f2 0 k 4095 Operands: Operation: k FSRf 0 f 255 d [0,1] a [0,1] Status Affected: None Operation: f dest Status Affected: N, Z Encoding: LFSR f,k 1110 1111 1110 0000 00ff k7kkk k11kkk kkkk Description: The 12-bit literal 'k' is loaded into the file select register pointed to by 'f'. Words: 2 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal 'k' MSB Process Data Write literal 'k' MSB to FSRfH Decode Read literal 'k' LSB Process Data Write literal 'k' to FSRfL Example: LFSR 2, 0x3AB After Instruction FSR2H FSR2L = = Encoding: MOVF 0101 00da f [,d [,a]] ffff ffff Description: The contents of register 'f' are moved to a destination dependent upon the status of 'd'. If 'd' is 0, the result is placed in W. If 'd' is 1, the result is placed back in register 'f' (default). Location 'f' can be anywhere in the 256-byte bank. If `a' is 0, the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). Words: 1 Cycles: 1 Q Cycle Activity: Q1 Decode 0x03 0xAB Example: Q2 Q3 Q4 Read register 'f' Process Data Write W MOVF REG, W Before Instruction REG W = = 0x22 0xFF = = 0x22 0x22 After Instruction REG W 2002 Microchip Technology Inc. Preliminary DS39605B-page 213 PIC18F1220/1320 MOVFF Move f to f MOVLB Move literal to low nibble in BSR Syntax: [ label ] Syntax: [ label ] Operands: 0 fs 4095 0 fd 4095 Operands: 0 k 255 Operation: k BSR None MOVFF fs,fd Operation: (fs) fd Status Affected: Status Affected: None Encoding: Encoding: 1st word (source) 2nd word (destin.) 1100 1111 Description: ffff ffff ffff ffff ffffs ffffd The contents of source register 'fs' are moved to destination register 'fd'. Location of source 'fs' can be anywhere in the 4096 byte data space (000h to FFFh) and location of destination 'fd' can also be anywhere from 000h to FFFh. Either source or destination can be W (a useful special situation). MOVFF is particularly useful for transferring a data memory location to a peripheral register (such as the transmit buffer or an I/O port). MOVLB k 0000 0001 kkkk kkkk Description: The 8-bit literal 'k' is loaded into the Bank Select Register (BSR). Words: 1 Cycles: 1 Q Cycle Activity: Q1 Decode Example: The MOVFF instruction cannot use the PCL, TOSU, TOSH or TOSL as the destination register. Q2 Q3 Q4 Read literal 'k' Process Data Write literal 'k' to BSR MOVLB 5 Before Instruction BSR register = 0x02 = 0x05 After Instruction BSR register The MOVFF instruction should not be used to modify interrupt settings while any interrupt is enabled (see Page 75). Words: 2 Cycles: 2 (3) Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register 'f' (src) Process Data No operation Decode No operation No operation Write register 'f' (dest) No dummy read Example: MOVFF REG1, REG2 Before Instruction REG1 REG2 = = 0x33 0x11 = = 0x33, 0x33 After Instruction REG1 REG2 DS39605B-page 214 Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 MOVLW Move literal to W MOVWF Move W to f Syntax: [ label ] Syntax: [ label ] Operands: 0 k 255 Operands: Operation: kW 0 f 255 a [0,1] Status Affected: None Operation: (W) f Status Affected: None Encoding: 0000 Description: MOVLW k 1110 kkkk Encoding: The eight-bit literal 'k' is loaded into W. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Decode Example: Q2 Q3 Q4 Process Data Write to W MOVLW 0x5A = 0110 Description: Read literal 'k' After Instruction W kkkk 1 Cycles: 1 Q Cycle Activity: Q1 Decode 111a f [,a] ffff ffff Move data from W to register 'f'. Location 'f' can be anywhere in the 256 byte bank. If `a' is 0, the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). Words: 0x5A MOVWF Q2 Q3 Q4 Read register 'f' Process Data Write register 'f' Example: MOVWF REG Before Instruction W REG = = 0x4F 0xFF After Instruction W REG 2002 Microchip Technology Inc. Preliminary = = 0x4F 0x4F DS39605B-page 215 PIC18F1220/1320 MULLW Multiply Literal with W MULWF Multiply W with f Syntax: [ label ] Syntax: [ label ] Operands: 0 f 255 a [0,1] Operation: (W) x (f) PRODH:PRODL Status Affected: None MULLW k Operands: 0 k 255 Operation: (W) x k PRODH:PRODL Status Affected: None Encoding: Description: 0000 1 Cycles: 1 Q Cycle Activity: Q1 Example: kkkk kkkk An unsigned multiplication is carried out between the contents of W and the 8-bit literal 'k'. The 16-bit result is placed in PRODH:PRODL register pair. PRODH contains the high byte. W is unchanged. None of the status flags are affected. Note that neither overflow nor carry is possible in this operation. A zero result is possible but not detected. Words: Decode 1101 Q2 Q3 Q4 Read literal 'k' Process Data Write registers PRODH: PRODL MULLW 0xC4 Encoding: 0xE2 ? ? = = = 0xE2 0xAD 0x08 After Instruction W PRODH PRODL 001a ffff ffff An unsigned multiplication is carried out between the contents of W and the register file location 'f'. The 16-bit result is stored in the PRODH:PRODL register pair. PRODH contains the high byte. Both W and 'f' are unchanged. None of the status flags are affected. Note that neither overflow nor carry is possible in this operation. A zero result is possible, but not detected. If `a' is 0, the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). Words: 1 Cycles: 1 Q Cycle Activity: Q1 Decode = = = 0000 f [,a] Description: Before Instruction W PRODH PRODL MULWF Example: Q2 Q3 Q4 Read register 'f' Process Data Write registers PRODH: PRODL MULWF REG Before Instruction W REG PRODH PRODL = = = = 0xC4 0xB5 ? ? = = = = 0xC4 0xB5 0x8A 0x94 After Instruction W REG PRODH PRODL DS39605B-page 216 Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 NEGF Negate f Syntax: [ label ] Operands: 0 f 255 a [0,1] NEGF Operation: (f)+1f Status Affected: N, OV, C, DC, Z Encoding: 0110 Description: 1 Cycles: 1 Q Cycle Activity: Q1 Syntax: [ label ] NOP Operands: None Operation: No operation Status Affected: None 0000 1111 ffff Description: 1 Cycles: 1 Decode 0000 xxxx 0000 xxxx No operation. Words: Q Cycle Activity: Q1 0000 xxxx Q2 Q3 Q4 No operation No operation No operation Example: Q2 Q3 Q4 Read register 'f' Process Data Write register 'f' Example: No Operation Encoding: ffff Location `f' is negated using two's complement. The result is placed in the data memory location 'f'. If `a' is 0, the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value. Words: Decode 110a f [,a] NOP NEGF None. REG, 1 Before Instruction REG = 0011 1010 [0x3A] After Instruction REG = 1100 0110 [0xC6] 2002 Microchip Technology Inc. Preliminary DS39605B-page 217 PIC18F1220/1320 POP Pop Top of Return Stack PUSH Push Top of Return Stack Syntax: [ label ] Syntax: [ label ] Operands: None Operands: None Operation: (TOS) bit bucket Operation: (PC+2) TOS Status Affected: None Status Affected: None Encoding: 0000 Description: 0000 0000 0110 The TOS value is pulled off the return stack and is discarded. The TOS value then becomes the previous value that was pushed onto the return stack. This instruction is provided to enable the user to properly manage the return stack to incorporate a software stack. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Decode POP Encoding: Q3 Q4 POP TOS value No operation 1 Cycles: 1 = = DS39605B-page 218 = = Q3 Q4 No operation No operation PUSH TOS PC 0x0031A2 0x014332 = = 0x00345A 0x000124 = = = 0x000126 0x000126 0x00345A After Instruction PC TOS Stack (1 level down) After Instruction TOS PC Q2 PUSH PC+2 onto return stack Before Instruction NEW Before Instruction TOS Stack (1 level down) 0101 Words: Example: POP GOTO 0000 The PC+2 is pushed onto the top of the return stack. The previous TOS value is pushed down on the stack. This instruction allows implementing a software stack by modifying TOS, and then pushing it onto the return stack. Decode Q2 0000 Description: Q Cycle Activity: Q1 No operation Example: 0000 PUSH 0x014332 NEW Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 RCALL Relative Call RESET Reset Syntax: [ label ] RCALL Syntax: [ label ] Operands: Operation: -1024 n 1023 Operands: None (PC) + 2 TOS, (PC) + 2 + 2n PC Operation: Reset all registers and flags that are affected by a MCLR Reset. Status Affected: None Status Affected: All Encoding: Description: 1101 nnnn nnnn Subroutine call with a jump up to 1K from the current location. First, return address (PC+2) is pushed onto the stack. Then, add the 2's complement number `2n' to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC+2+2n. This instruction is a two-cycle instruction. Words: 1 Cycles: 2 Q Cycle Activity: Q1 Decode 1nnn n Encoding: 0000 RESET 0000 1111 1111 Description: This instruction provides a way to execute a MCLR Reset in software. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Decode Example: Q2 Q3 Q4 Start reset No operation No operation RESET After Instruction Registers = Flags* = Q2 Q3 Q4 Read literal 'n' Process Data Write to PC No operation No operation Reset Value Reset Value Push PC to stack No operation Example: No operation HERE RCALL Jump Before Instruction PC = Address (HERE) After Instruction PC = TOS = Address (Jump) Address (HERE+2) 2002 Microchip Technology Inc. Preliminary DS39605B-page 219 PIC18F1220/1320 RETFIE Return from Interrupt RETLW Return Literal to W Syntax: [ label ] Syntax: [ label ] RETFIE [s] RETLW k Operands: s [0,1] Operands: 0 k 255 Operation: (TOS) PC, 1 GIE/GIEH or PEIE/GIEL, if s = 1 (WS) W, (STATUSS) STATUS, (BSRS) BSR, PCLATU, PCLATH are unchanged. Operation: k W, (TOS) PC, PCLATU, PCLATH are unchanged Status Affected: None Status Affected: 0000 Description: 0000 0001 1 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 No operation pop PC from stack Set GIEH or GIEL No operation kkkk W is loaded with the eight-bit literal `k'. The program counter is loaded from the top of the stack (the return address). The high address latch (PCLATH) remains unchanged. Words: 1 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal 'k' Process Data pop PC from stack, Write to W No operation No operation No operation No operation RETFIE No operation No operation 1 CALL TABLE ; ; ; ; : TABLE ADDWF PCL ; RETLW k0 ; RETLW k1 ; : : RETLW kn ; After Interrupt PC W BSR STATUS GIE/GIEH, PEIE/GIEL DS39605B-page 220 kkkk Example: No operation Example: 1100 Description: 000s Return from interrupt. Stack is popped and Top-of-Stack (TOS) is loaded into the PC. Interrupts are enabled by setting either the high or low priority global interrupt enable bit. If `s' = 1, the contents of the shadow registers WS, STATUSS and BSRS are loaded into their corresponding registers, W, STATUS and BSR. If `s' = 0, no update of these registers occurs (default). Words: No operation 0000 GIE/GIEH, PEIE/GIEL. Encoding: Decode Encoding: = = = = = W contains table offset value W now has table value W = offset Begin table End of table Before Instruction TOS WS BSRS STATUSS 1 W = 0x07 After Instruction W Preliminary = value of kn 2002 Microchip Technology Inc. PIC18F1220/1320 RETURN Return from Subroutine RLCF Rotate Left f through Carry Syntax: [ label ] Syntax: [ label ] Operands: 0 f 255 d [0,1] a [0,1] Operation: (f<n>) dest<n+1>, (f<7>) C, (C) dest<0> Status Affected: C, N, Z RETURN [s] Operands: s [0,1] Operation: (TOS) PC, if s = 1 (WS) W, (STATUSS) STATUS, (BSRS) BSR, PCLATU, PCLATH are unchanged Status Affected: None Encoding: 0000 Encoding: 0000 0001 001s Description: Return from subroutine. The stack is popped and the top of the stack (TOS) is loaded into the program counter. If `s'= 1, the contents of the shadow registers, WS, STATUSS and BSRS are loaded into their corresponding registers, W, STATUS and BSR. If `s' = 0, no update of these registers occurs (default). Words: 1 Cycles: 2 Q Cycle Activity: Q1 0011 Description: 01da Q3 Q4 Decode No operation Process Data pop PC from stack No operation No operation No operation No operation Words: 1 Cycles: 1 Q Cycle Activity: Q1 Decode ffff register f Q2 Q3 Q4 Process Data Write to destination RLCF REG, W Before Instruction REG C After Interrupt PC = TOS = = 1110 0110 0 After Instruction REG W C 2002 Microchip Technology Inc. ffff Read register 'f' Example: RETURN f [,d [,a]] The contents of register 'f' are rotated one bit to the left through the Carry Flag. If 'd' is 0, the result is placed in W. If 'd' is 1, the result is stored back in register 'f' (default). If `a' is 0, the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). C Q2 Example: RLCF Preliminary = = = 1110 0110 1100 1100 1 DS39605B-page 221 PIC18F1220/1320 RLNCF Rotate Left f (no carry) RRCF Rotate Right f through Carry Syntax: [ label ] Syntax: [ label ] Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 f 255 d [0,1] a [0,1] Operation: (f<n>) dest<n+1>, (f<7>) dest<0> Operation: Status Affected: N, Z (f<n>) dest<n-1>, (f<0>) C, (C) dest<7> Status Affected: C, N, Z Encoding: 0100 Description: RLNCF 01da f [,d [,a]] ffff ffff The contents of register `f' are rotated one bit to the left. If `d' is 0, the result is placed in W. If `d' is 1, the result is stored back in register `f' (default). If `a' is 0, the Access Bank will be selected, overriding the BSR value. If `a' is 1, then the bank will be selected as per the BSR value (default). Encoding: 0011 Description: 1 Cycles: 1 Q Cycle Activity: Q1 Decode Q3 Q4 Read register 'f' Process Data Write to destination Words: 1 Cycles: 1 Q Cycle Activity: Q1 Decode RLNCF REG Before Instruction REG = 1010 1011 REG = ffff Q2 Q3 Q4 Read register 'f' Process Data Write to destination Example: After Instruction ffff register f C Q2 Example: 00da f [,d [,a]] The contents of register `f' are rotated one bit to the right through the Carry Flag. If `d' is 0, the result is placed in W. If `d' is 1, the result is placed back in register 'f' (default). If `a' is 0, the Access Bank will be selected, overriding the BSR value. If `a' is 1, then the bank will be selected as per the BSR value (default). register f Words: RRCF RRCF REG, W Before Instruction REG C 0101 0111 = = 1110 0110 0 After Instruction REG W C DS39605B-page 222 Preliminary = = = 1110 0110 0111 0011 0 2002 Microchip Technology Inc. PIC18F1220/1320 RRNCF Rotate Right f (no carry) SETF Set f Syntax: [ label ] Syntax: [ label ] SETF Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 f 255 a [0,1] (f<n>) dest<n-1>, (f<0>) dest<7> Operation: FFh f Operation: Status Affected: None Status Affected: N, Z Encoding: 0100 Description: RRNCF 00da f [,d [,a]] Encoding: ffff ffff The contents of register `f' are rotated one bit to the right. If `d' is 0, the result is placed in W. If `d' is 1, the result is placed back in register `f' (default). If `a' is 0, the Access Bank will be selected, overriding the BSR value. If `a' is 1, then the bank will be selected as per the BSR value (default). 1 Cycles: 1 ffff ffff The contents of the specified register are set to FFh. If `a' is 0, the Access Bank will be selected, overriding the BSR value. If `a' is 1, then the bank will be selected as per the BSR value (default). Words: 1 Cycles: 1 Q Cycle Activity: Q1 Decode Example: Q2 Q3 Q4 Read register 'f' Process Data Write register 'f' SETF REG Before Instruction Q Cycle Activity: Q1 Decode 100a Description: register f Words: 0110 f [,a] REG Q2 Q3 Q4 Read register 'f' Process Data Write to destination Example 1: RRNCF = 0x5A = 0xFF After Instruction REG REG, 1, 0 Before Instruction REG = 1101 0111 After Instruction REG = Example 2: 1110 1011 RRNCF REG, W Before Instruction W REG = = ? 1101 0111 After Instruction W REG = = 1110 1011 1101 0111 2002 Microchip Technology Inc. Preliminary DS39605B-page 223 PIC18F1220/1320 SLEEP Enter SLEEP mode SUBFWB Subtract f from W with borrow Syntax: [ label ] SLEEP Syntax: [ label ] SUBFWB Operands: None Operands: Operation: 00h WDT, 0 WDT postscaler, 1 TO, 0 PD 0 f 255 d [0,1] a [0,1] Operation: (W) - (f) - (C) dest Status Affected: N, OV, C, DC, Z TO, PD Encoding: Status Affected: Encoding: 0000 0000 0000 0011 Description: The power-down status bit (PD) is cleared. The time-out status bit (TO) is set. Watchdog Timer and its postscaler are cleared. The processor is put into SLEEP mode with the oscillator stopped. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Decode Q2 Q3 Q4 No operation Process Data Go to sleep TO = PD = ffff Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Read register 'f' Process Data Write to destination Example 1: ? ? SUBFWB REG Before Instruction REG W C After Instruction TO = PD = ffff Subtract register 'f' and carry flag (borrow) from W (2's complement method). If `d' is 0, the result is stored in W. If `d' is 1, the result is stored in register `f' (default). If `a' is 0, the Access Bank will be selected, overriding the BSR value. If `a' is 1, then the bank will be selected as per the BSR value (default). SLEEP Before Instruction 01da Description: Decode Example: 0101 f [,d [,a]] 1 0 = = = 0x03 0x02 0x01 After Instruction If WDT causes wake-up, this bit is cleared. REG W C Z N = = = = = Example 2: 0xFF 0x02 0x00 0x00 0x01 SUBFWB ; result is negative REG, 0, 0 Before Instruction REG W C = = = 2 5 1 After Instruction REG W C Z N = = = = = Example 3: 2 3 1 0 0 ; result is positive SUBFWB REG, 1, 0 Before Instruction REG W C = = = 1 2 0 After Instruction REG W C Z N DS39605B-page 224 Preliminary = = = = = 0 2 1 1 0 ; result is zero 2002 Microchip Technology Inc. PIC18F1220/1320 SUBLW Subtract W from literal SUBWF Subtract W from f Syntax: [ label ] SUBLW k Syntax: [ label ] SUBWF Operands: 0 k 255 Operands: Operation: k - (W) W Status Affected: N, OV, C, DC, Z 0 f 255 d [0,1] a [0,1] Operation: (f) - (W) dest Status Affected: N, OV, C, DC, Z Encoding: 0000 Description: 1000 kkkk W is subtracted from the eight-bit literal `k'. The result is placed in W. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Decode Q2 Q3 Q4 Read literal 'k' Process Data Write to W Example 1: SUBLW 0x02 Before Instruction W C = = 1 ? = = = = Example 2: 1 1 0 0 SUBLW Encoding: = = Example 3: 0 1 1 0 SUBLW 1 Cycles: 1 Decode ; result is positive = = = = = = Q3 Q4 Process Data Write to destination SUBWF REG Before Instruction 0x02 REG W C = = = 3 2 ? After Instruction REG W C Z N ; result is zero 0x02 = = = = = Example 2: 1 2 1 0 0 ; result is positive SUBWF REG, W Before Instruction REG W C 3 ? After Instruction W C Z N Q2 Read register 'f' Example 1: Before Instruction W C ffff Words: 2 ? = = = = ffff Subtract W from register `f' (2's complement method). If `d' is 0, the result is stored in W. If `d' is 1, the result is stored back in register `f' (default). If `a' is 0, the Access Bank will be selected, overriding the BSR value. If `a' is 1, then the bank will be selected as per the BSR value (default). After Instruction W C Z N 11da Description: Before Instruction W C 0101 Q Cycle Activity: Q1 After Instruction W C Z N kkkk f [,d [,a]] = = = 2 2 ? After Instruction FF ; (2's complement) 0 ; result is negative 0 1 REG W C Z N = = = = = Example 3: 2 0 1 1 0 ; result is zero SUBWF REG Before Instruction REG W C = = = 0x01 0x02 ? After Instruction REG W C Z N 2002 Microchip Technology Inc. Preliminary = = = = = 0xFFh ;(2's complement) 0x02 0x00 ; result is negative 0x00 0x01 DS39605B-page 225 PIC18F1220/1320 SUBWFB Subtract W from f with Borrow SWAPF Swap f Syntax: [ label ] SUBWFB Syntax: [ label ] SWAPF f [,d [,a]] Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 f 255 d [0,1] a [0,1] Operation: (f) - (W) - (C) dest Operation: Status Affected: N, OV, C, DC, Z (f<3:0>) dest<7:4>, (f<7:4>) dest<3:0> Status Affected: None Encoding: Description: 0101 ffff ffff Subtract W and the carry flag (borrow) from register `f' (2's complement method). If `d' is 0, the result is stored in W. If `d' is 1, the result is stored back in register `f' (default). If `a' is 0, the Access Bank will be selected, overriding the BSR value. If `a' is 1, then the bank will be selected as per the BSR value (default). Words: 1 Cycles: 1 Q Cycle Activity: Q1 Decode 10da f [,d [,a]] Q2 Q3 Q4 Read register 'f' Process Data Write to destination Example 1: SUBWFB = = = 1 Cycles: 1 Q Cycle Activity: Q1 Decode (0001 1001) (0000 1101) = = = = = 0x0C 0x0D 0x01 0x00 0x00 (0000 1011) (0000 1101) Example 2: ffff ffff Q2 Q3 Q4 Read register 'f' Process Data Write to destination Example: 0x19 0x0D 0x01 10da The upper and lower nibbles of register 'f' are exchanged. If `d' is 0, the result is placed in W. If `d' is 1, the result is placed in register `f' (default). If `a' is 0, the Access Bank will be selected, overriding the BSR value. If `a' is 1, then the bank will be selected as per the BSR value (default). Words: SWAPF REG Before Instruction REG = 0x53 After Instruction After Instruction REG W C Z N 0011 Description: REG, 1, 0 Before Instruction REG W C Encoding: REG = 0x35 ; result is positive SUBWFB REG, 0, 0 Before Instruction REG W C = = = 0x1B 0x1A 0x00 (0001 1011) (0001 1010) 0x1B 0x00 0x01 0x01 0x00 (0001 1011) After Instruction REG W C Z N = = = = = Example 3: SUBWFB ; result is zero REG, 1, 0 Before Instruction REG W C = = = 0x03 0x0E 0x01 (0000 0011) (0000 1101) (1111 0100) ; [2's comp] (0000 1101) After Instruction REG = 0xF5 W C Z N = = = = 0x0E 0x00 0x00 0x01 DS39605B-page 226 ; result is negative Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 TBLRD Table Read TBLRD Table Read (Continued) Syntax: [ label ] Example1: TBLRD Operands: None Operation: if TBLRD *, (Prog Mem (TBLPTR)) TABLAT; TBLPTR - No Change; if TBLRD *+, (Prog Mem (TBLPTR)) TABLAT; (TBLPTR) +1 TBLPTR; if TBLRD *-, (Prog Mem (TBLPTR)) TABLAT; (TBLPTR) -1 TBLPTR; if TBLRD +*, (TBLPTR) +1 TBLPTR; (Prog Mem (TBLPTR)) TABLAT; TBLRD ( *; *+; *-; +*) Before Instruction TABLAT TBLPTR MEMORY(0x00A356) 0000 0000 0000 TABLAT TBLPTR Example2: 10nn nn=0 * =1 *+ =2 *=3 +* Description: This instruction is used to read the contents of Program Memory (P.M.). To address the program memory, a pointer called Table Pointer (TBLPTR) is used. The TBLPTR (a 21-bit pointer) points to each byte in the program memory. TBLPTR has a 2 Mbyte address range. TBLPTR[0] = 0: Least Significant Byte of Program Memory Word TBLPTR[0] = 1: Most Significant Byte of Program Memory Word The TBLRD instruction can modify the value of TBLPTR as follows: * no change * post-increment * post-decrement * pre-increment Words: 1 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No operation No operation No operation No operation No operation (Read Program Memory) 2002 Microchip Technology Inc. = = = 0x55 0x00A356 0x34 = = 0x34 0x00A357 After Instruction Status Affected:None Encoding: *+ ; TBLRD +* ; Before Instruction TABLAT TBLPTR MEMORY(0x01A357) MEMORY(0x01A358) = = = = 0xAA 0x01A357 0x12 0x34 = = 0x34 0x01A358 After Instruction TABLAT TBLPTR No No operation operation (Write TABLAT) Preliminary DS39605B-page 227 PIC18F1220/1320 TBLWT Table Write TBLWT Syntax: [ label ] Words: 1 TBLWT ( *; *+; *-; +*) Table Write (Continued) Operands: None Cycles: 2 Operation: if TBLWT*, (TABLAT) Holding Register; TBLPTR - No Change; if TBLWT*+, (TABLAT) Holding Register; (TBLPTR) +1 TBLPTR; if TBLWT*-, (TABLAT) Holding Register; (TBLPTR) -1 TBLPTR; if TBLWT+*, (TBLPTR) +1 TBLPTR; (TABLAT) Holding Register; Q Cycle Activity: Description: 0000 Q3 Q4 Decode No operation No operation No operation No operation No operation (Read TABLAT) No operation No operation (Write to Holding Register ) TBLWT *+; Before Instruction 0000 0000 TABLAT TBLPTR HOLDING REGISTER (0x00A356) 11nn nn=0 * =1 *+ =2 *=3 +* This instruction uses the 3 LSBs of TBLPTR to determine which of the 8 holding registers the TABLAT is written to. The holding registers are used to program the contents of Program Memory (P.M.). (Refer to Section 6.0 for additional details on programming FLASH memory.) The TBLPTR (a 21-bit pointer) points to each byte in the program memory. TBLPTR has a 2 MBtye address range. The LSb of the TBLPTR selects which byte of the program memory location to access. TBLPTR[0] = 0: Least Significant Byte of Program Memory Word TBLPTR[0] = 1: Most Significant Byte of Program Memory Word The TBLWT instruction can modify the value of TBLPTR as follows: * no change * post-increment * post-decrement * pre-increment DS39605B-page 228 Q2 Example1: Status Affected: None Encoding: Q1 = = 0x55 0x00A356 = 0xFF After Instructions (table write completion) TABLAT TBLPTR HOLDING REGISTER (0x00A356) Example 2: Preliminary TBLWT = = 0x55 0x00A357 = 0x55 +*; Before Instruction TABLAT TBLPTR HOLDING REGISTER (0x01389A) HOLDING REGISTER (0x01389B) = = 0x34 0x01389A = 0xFF = 0xFF After Instruction (table write completion) TABLAT TBLPTR HOLDING REGISTER (0x01389A) HOLDING REGISTER (0x01389B) = = 0x34 0x01389B = 0xFF = 0x34 2002 Microchip Technology Inc. PIC18F1220/1320 TSTFSZ Test f, skip if 0 XORLW Exclusive OR literal with W Syntax: [ label ] TSTFSZ f [,a] Syntax: [ label ] XORLW k Operands: 0 f 255 a [0,1] Operands: 0 k 255 Operation: skip if f = 0 Operation: (W) .XOR. k W Status Affected: None Status Affected: N, Z Encoding: Description: Encoding: 0110 011a ffff ffff If `f' = 0, the next instruction, fetched during the current instruction execution is discarded and a NOP is executed, making this a two-cycle instruction. If `a' is 0, the Access Bank will be selected, overriding the BSR value. If `a' is 1, then the bank will be selected as per the BSR value (default). Words: 1 Cycles: 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q1 Decode 0000 1010 kkkk kkkk Description: The contents of W are XORed with the 8-bit literal 'k'. The result is placed in W. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Decode Q2 Q3 Q4 Read literal 'k' Process Data Write to W Example: XORLW 0xAF Before Instruction W = 0xB5 After Instruction Q2 Q3 Q4 Read register 'f' Process Data No operation W = 0x1A If skip: Q1 Q2 Q3 Q4 No operation No operation No operation No operation If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation Example: HERE NZERO ZERO TSTFSZ : CNT : Before Instruction PC = Address (HERE) After Instruction If CNT PC If CNT PC = = = 0x00, Address (ZERO) 0x00, Address (NZERO) 2002 Microchip Technology Inc. Preliminary DS39605B-page 229 PIC18F1220/1320 XORWF Exclusive OR W with f Syntax: [ label ] XORWF Operands: 0 f 255 d [0,1] a [0,1] Operation: (W) .XOR. (f) dest Status Affected: N, Z Encoding: 0001 10da f [,d [,a]] ffff ffff Description: Exclusive OR the contents of W with register `f'. If `d' is 0, the result is stored in W. If `d' is 1, the result is stored back in the register `f' (default). If `a' is 0, the Access Bank will be selected, overriding the BSR value. If `a' is 1, then the bank will be selected as per the BSR value (default). Words: 1 Cycles: 1 Q Cycle Activity: Q1 Decode Q2 Q3 Q4 Read register 'f' Process Data Write to destination Example: XORWF REG Before Instruction REG W = = 0xAF 0xB5 After Instruction REG W = = DS39605B-page 230 0x1A 0xB5 Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 21.0 DEVELOPMENT SUPPORT The MPLAB IDE allows you to: The PICmicro(R) microcontrollers are supported with a full range of hardware and software development tools: * Integrated Development Environment - MPLAB(R) IDE Software * Assemblers/Compilers/Linkers - MPASMTM Assembler - MPLAB C17 and MPLAB C18 C Compilers - MPLINKTM Object Linker/ MPLIBTM Object Librarian * Simulators - MPLAB SIM Software Simulator * Emulators - MPLAB ICE 2000 In-Circuit Emulator - ICEPICTM In-Circuit Emulator * In-Circuit Debugger - MPLAB ICD * Device Programmers - PRO MATE(R) II Universal Device Programmer - PICSTART(R) Plus Entry-Level Development Programmer * Low Cost Demonstration Boards - PICDEMTM 1 Demonstration Board - PICDEM 2 Demonstration Board - PICDEM 3 Demonstration Board - PICDEM 17 Demonstration Board - KEELOQ(R) Demonstration Board 21.1 The ability to use MPLAB IDE with multiple debugging tools allows users to easily switch from the costeffective simulator to a full-featured emulator with minimal retraining. 21.2 The MPASM assembler has a command line interface and a Windows shell. It can be used as a stand-alone application on a Windows 3.x or greater system, or it can be used through MPLAB IDE. The MPASM assembler generates relocatable object files for the MPLINK object linker, Intel(R) standard HEX files, MAP files to detail memory usage and symbol reference, an absolute LST file that contains source lines and generated machine code, and a COD file for debugging. The MPASM assembler features include: The MPLAB IDE software brings an ease of software development previously unseen in the 8-bit microcontroller market. The MPLAB IDE is a Windows(R)-based application that contains: 2002 Microchip Technology Inc. MPASM Assembler The MPASM assembler is a full-featured universal macro assembler for all PICmicro MCU's. MPLAB Integrated Development Environment Software * An interface to debugging tools - simulator - programmer (sold separately) - emulator (sold separately) - in-circuit debugger (sold separately) * A full-featured editor * A project manager * Customizable toolbar and key mapping * A status bar * On-line help * Edit your source files (either assembly or `C') * One touch assemble (or compile) and download to PICmicro emulator and simulator tools (automatically updates all project information) * Debug using: - source files - absolute listing file - machine code * Integration into MPLAB IDE projects. * User-defined macros to streamline assembly code. * Conditional assembly for multi-purpose source files. * Directives that allow complete control over the assembly process. 21.3 MPLAB C17 and MPLAB C18 C Compilers The MPLAB C17 and MPLAB C18 Code Development Systems are complete ANSI `C' compilers for Microchip's PIC17CXXX and PIC18CXXX family of microcontrollers, respectively. These compilers provide powerful integration capabilities and ease of use not found with other compilers. For easier source level debugging, the compilers provide symbol information that is compatible with the MPLAB IDE memory display. Preliminary DS39605B-page 231 PIC18F1220/1320 21.4 MPLINK Object Linker/ MPLIB Object Librarian 21.6 The MPLINK object linker combines relocatable objects created by the MPASM assembler and the MPLAB C17 and MPLAB C18 C compilers. It can also link relocatable objects from pre-compiled libraries, using directives from a linker script. The MPLIB object librarian is a librarian for precompiled code to be used with the MPLINK object linker. When a routine from a library is called from another source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The MPLIB object librarian manages the creation and modification of library files. The MPLINK object linker features include: * Integration with MPASM assembler and MPLAB C17 and MPLAB C18 C compilers. * Allows all memory areas to be defined as sections to provide link-time flexibility. The MPLIB object librarian features include: * Easier linking because single libraries can be included instead of many smaller files. * Helps keep code maintainable by grouping related modules together. * Allows libraries to be created and modules to be added, listed, replaced, deleted or extracted. 21.5 The MPLAB ICE universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PICmicro microcontrollers (MCUs). Software control of the MPLAB ICE in-circuit emulator is provided by the MPLAB Integrated Development Environment (IDE), which allows editing, building, downloading and source debugging from a single environment. The MPLAB ICE 2000 is a full-featured emulator system with enhanced trace, trigger and data monitoring features. Interchangeable processor modules allow the system to be easily reconfigured for emulation of different processors. The universal architecture of the MPLAB ICE in-circuit emulator allows expansion to support new PICmicro microcontrollers. The MPLAB ICE in-circuit emulator system has been designed as a real-time emulation system, with advanced features that are generally found on more expensive development tools. The PC platform and Microsoft(R) Windows environment were chosen to best make these features available to you, the end user. 21.7 MPLAB SIM Software Simulator The MPLAB SIM software simulator allows code development in a PC-hosted environment by simulating the PICmicro series microcontrollers on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a file, or user-defined key press, to any of the pins. The execution can be performed in single step, execute until break, or trace mode. MPLAB ICE High Performance Universal In-Circuit Emulator with MPLAB IDE ICEPIC In-Circuit Emulator The ICEPIC low cost, in-circuit emulator is a solution for the Microchip Technology PIC16C5X, PIC16C6X, PIC16C7X and PIC16CXXX families of 8-bit OneTime-Programmable (OTP) microcontrollers. The modular system can support different subsets of PIC16C5X or PIC16CXXX products through the use of interchangeable personality modules, or daughter boards. The emulator is capable of emulating without target application circuitry being present. The MPLAB SIM simulator fully supports symbolic debugging using the MPLAB C17 and the MPLAB C18 C compilers and the MPASM assembler. The software simulator offers the flexibility to develop and debug code outside of the laboratory environment, making it an excellent multiproject software development tool. DS39605B-page 232 Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 21.8 MPLAB ICD In-Circuit Debugger Microchip's In-Circuit Debugger, MPLAB ICD, is a powerful, low cost, run-time development tool. This tool is based on the FLASH PICmicro MCUs and can be used to develop for this and other PICmicro microcontrollers. The MPLAB ICD utilizes the in-circuit debugging capability built into the FLASH devices. This feature, along with Microchip's In-Circuit Serial ProgrammingTM protocol, offers cost-effective in-circuit FLASH debugging from the graphical user interface of the MPLAB Integrated Development Environment. This enables a designer to develop and debug source code by watching variables, single-stepping and setting break points. Running at full speed enables testing hardware in realtime. 21.9 PRO MATE II Universal Device Programmer The PRO MATE II universal device programmer is a full-featured programmer, capable of operating in stand-alone mode, as well as PC-hosted mode. The PRO MATE II device programmer is CE compliant. The PRO MATE II device programmer has programmable VDD and VPP supplies, which allow it to verify programmed memory at VDD min and VDD max for maximum reliability. It has an LCD display for instructions and error messages, keys to enter commands and a modular detachable socket assembly to support various package types. In stand-alone mode, the PRO MATE II device programmer can read, verify, or program PICmicro devices. It can also set code protection in this mode. 21.10 PICSTART Plus Entry Level Development Programmer The PICSTART Plus development programmer is an easy-to-use, low cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus development programmer supports all PICmicro devices with up to 40 pins. Larger pin count devices, such as the PIC16C92X and PIC17C76X, may be supported with an adapter socket. The PICSTART Plus development programmer is CE compliant. 2002 Microchip Technology Inc. 21.11 PICDEM 1 Low Cost PICmicro Demonstration Board The PICDEM 1 demonstration board is a simple board which demonstrates the capabilities of several of Microchip's microcontrollers. The microcontrollers supported are: PIC16C5X (PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X, PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All necessary hardware and software is included to run basic demo programs. The user can program the sample microcontrollers provided with the PICDEM 1 demonstration board on a PRO MATE II device programmer, or a PICSTART Plus development programmer, and easily test firmware. The user can also connect the PICDEM 1 demonstration board to the MPLAB ICE incircuit emulator and download the firmware to the emulator for testing. A prototype area is available for the user to build some additional hardware and connect it to the microcontroller socket(s). Some of the features include an RS-232 interface, a potentiometer for simulated analog input, push button switches and eight LEDs connected to PORTB. 21.12 PICDEM 2 Low Cost PIC16CXX Demonstration Board The PICDEM 2 demonstration board is a simple demonstration board that supports the PIC16C62, PIC16C64, PIC16C65, PIC16C73 and PIC16C74 microcontrollers. All the necessary hardware and software is included to run the basic demonstration programs. The user can program the sample microcontrollers provided with the PICDEM 2 demonstration board on a PRO MATE II device programmer, or a PICSTART Plus development programmer, and easily test firmware. The MPLAB ICE in-circuit emulator may also be used with the PICDEM 2 demonstration board to test firmware. A prototype area has been provided to the user for adding additional hardware and connecting it to the microcontroller socket(s). Some of the features include a RS-232 interface, push button switches, a potentiometer for simulated analog input, a serial EEPROM to demonstrate usage of the I2CTM bus and separate headers for connection to an LCD module and a keypad. Preliminary DS39605B-page 233 PIC18F1220/1320 21.13 PICDEM 3 Low Cost PIC16CXXX Demonstration Board The PICDEM 3 demonstration board is a simple demonstration board that supports the PIC16C923 and PIC16C924 in the PLCC package. It will also support future 44-pin PLCC microcontrollers with an LCD Module. All the necessary hardware and software is included to run the basic demonstration programs. The user can program the sample microcontrollers provided with the PICDEM 3 demonstration board on a PRO MATE II device programmer, or a PICSTART Plus development programmer with an adapter socket, and easily test firmware. The MPLAB ICE in-circuit emulator may also be used with the PICDEM 3 demonstration board to test firmware. A prototype area has been provided to the user for adding hardware and connecting it to the microcontroller socket(s). Some of the features include a RS-232 interface, push button switches, a potentiometer for simulated analog input, a thermistor and separate headers for connection to an external LCD module and a keypad. Also provided on the PICDEM 3 demonstration board is a LCD panel, with 4 commons and 12 segments, that is capable of displaying time, temperature and day of the week. The PICDEM 3 demonstration board provides an additional RS-232 interface and Windows software for showing the demultiplexed LCD signals on a PC. A simple serial interface allows the user to construct a hardware demultiplexer for the LCD signals. DS39605B-page 234 21.14 PICDEM 17 Demonstration Board The PICDEM 17 demonstration board is an evaluation board that demonstrates the capabilities of several Microchip microcontrollers, including PIC17C752, PIC17C756A, PIC17C762 and PIC17C766. All necessary hardware is included to run basic demo programs, which are supplied on a 3.5-inch disk. A programmed sample is included and the user may erase it and program it with the other sample programs using the PRO MATE II device programmer, or the PICSTART Plus development programmer, and easily debug and test the sample code. In addition, the PICDEM 17 demonstration board supports downloading of programs to and executing out of external FLASH memory on board. The PICDEM 17 demonstration board is also usable with the MPLAB ICE in-circuit emulator, or the PICMASTER emulator and all of the sample programs can be run and modified using either emulator. Additionally, a generous prototype area is available for user hardware. 21.15 KEELOQ Evaluation and Programming Tools KEELOQ evaluation and programming tools support Microchip's HCS Secure Data Products. The HCS evaluation kit includes a LCD display to show changing codes, a decoder to decode transmissions and a programming interface to program test transmitters. Preliminary 2002 Microchip Technology Inc. Software Tools Programmers Debugger Emulators PIC12CXXX PIC14000 PIC16C5X PIC16C6X PIC16CXXX PIC16F62X PIC16C7X 9 9 9 9 9 9 2002 Microchip Technology Inc. Preliminary 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 MCP2510 * Contact the Microchip Technology Inc. web site at www.microchip.com for information on how to use the MPLAB(R) ICD In-Circuit Debugger (DV164001) with PIC16C62, 63, 64, 65, 72, 73, 74, 76, 77. ** Contact Microchip Technology Inc. for availability date. Development tool is available on select devices. MCP2510 CAN Developer's Kit 9 13.56 MHz Anticollision microIDTM Developer's Kit 9 125 kHz Anticollision microIDTM Developer's Kit 9 125 kHz microIDTM Developer's Kit MCRFXXX microIDTM Programmer's Kit 9 9** 9 9* 9 9 9 9 9 9 9 9 9** 9** PIC18FXXX 9 24CXX/ 25CXX/ 93CXX KEELOQ(R) Transponder Kit 9 9 9 9 9 9 9 9 9 HCSXXX KEELOQ(R) Evaluation Kit PICDEMTM 17 Demonstration Board PICDEMTM 14A Demonstration Board PICDEMTM 3 Demonstration Board PICDEMTM 2 Demonstration Board PICDEMTM 1 Demonstration Board 9 9 PRO MATE(R) II Universal Device Programmer 9 9 9 9 PICSTART(R) Plus Entry Level Development Programmer 9 9 9* 9 9 MPLAB(R) ICD In-Circuit Debugger 9 9 9 9 9 9 9 9 ICEPICTM In-Circuit Emulator 9 9 PIC16C7XX 9 9 9 PIC16C8X/ PIC16F8X 9 9 9 PIC16F8XX 9 9 9 PIC16C9XX MPLAB(R) ICE In-Circuit Emulator 9 9 PIC17C4X 9 9 9 PIC17C7XX MPASMTM Assembler/ MPLINKTM Object Linker 9 PIC18CXX2 MPLAB(R) C18 C Compiler MPLAB(R) C17 C Compiler TABLE 21-1: Demo Boards and Eval Kits MPLAB(R) Integrated Development Environment PIC18F1220/1320 DEVELOPMENT TOOLS FROM MICROCHIP DS39605B-page 235 PIC18F1220/1320 NOTES: DS39605B-page 236 Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 22.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings () Ambient temperature under bias.............................................................................................................-55C to +125C Storage temperature .............................................................................................................................. -65C to +150C Voltage on any pin with respect to VSS (except VDD, MCLR, and RA4) ......................................... -0.3V to (VDD + 0.3V) Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +7.5V Voltage on MCLR with respect to VSS (Note 2) ......................................................................................... 0V to +13.25V Voltage on RA4 with respect to Vss ............................................................................................................... 0V to +8.5V Total power dissipation (Note 1) ...............................................................................................................................1.0W Maximum current out of VSS pin ...........................................................................................................................300 mA Maximum current into VDD pin ..............................................................................................................................250 mA Input clamp current, IIK (VI < 0 or VI > VDD)...................................................................................................................... 20 mA Output clamp current, IOK (VO < 0 or VO > VDD) .............................................................................................................. 20 mA Maximum output current sunk by any I/O pin..........................................................................................................25 mA Maximum output current sourced by any I/O pin ....................................................................................................25 mA Maximum current sunk by all ports .......................................................................................................................200 mA Maximum current sourced by all ports ..................................................................................................................200 mA Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - IOH} + {(VDD-VOH) x IOH} + (VOl x IOL) 2: Voltage spikes below VSS at the MCLR/VPP pin, inducing currents greater than 80 mA, may cause latchup. Thus, a series resistor of 50-100 should be used when applying a "low" level to the MCLR/VPP pin, rather than pulling this pin directly to VSS. NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2002 Microchip Technology Inc. Preliminary DS39605B-page 237 PIC18F1220/1320 FIGURE 22-1: PIC18F1220/1320 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 6.0V 5.5V 5.0V PIC18F1X20 Voltage 4.5V 4.2V 4.0V 3.5V 3.0V 2.5V 2.0V 40 MHz Frequency FIGURE 22-2: PIC18LF1220/1320 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 6.0V 5.5V Voltage 5.0V PIC18LF1X20 4.5V 4.2V 4.0V 3.5V 3.0V 2.5V 2.0V 40 MHz 4 MHz Frequency FMAX = (16.36 MHz/V) (VDDAPPMIN - 2.0V) + 4 MHz Note: VDDAPPMIN is the minimum voltage of the PICmicro(R) device in the application. DS39605B-page 238 Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 22.1 DC Characteristics: Supply Voltage PIC18F1220/1320 (Industrial) PIC18LF1220/1320 (Industrial) PIC18LF1220/1320 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial PIC18F1220/1320 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Param No. Symbol VDD D001 Characteristic Min Typ Max Units PIC18LF1220/1320 2.0 -- 5.5 V PIC18F1220/1320 Conditions Supply Voltage 4.2 -- 5.5 V D002 VDR RAM Data Retention Voltage(1) 1.5 -- -- V D003 VPOR VDD Start Voltage to ensure internal Power-on Reset signal -- -- 0.7 V D004 SVDD VDD Rise Rate to ensure internal Power-on Reset signal 0.05 -- -- VBOR Brown-out Reset Voltage BORV1:BORV0 = 11 2.00 -- 2.16 V BORV1:BORV0 = 10 2.70 -- 2.86 V BORV1:BORV0 = 01 4.20 -- 4.46 V BORV1:BORV0 = 00 4.50 -- 4.78 V BORV1:BORV0 = 1x NA -- NA V BORV1:BORV0 = 01 4.20 -- 4.46 V BORV1:BORV0 = 00 4.50 -- 4.78 V HS, XT, RC and LP Osc mode See Section 4.1, "Power-on Reset (POR)" for details. V/ms See Section 4.1, "Power-on Reset (POR)" for details. PIC18LF1220/1320 D005 D005 PIC18F1220/1320 Not in operating voltage range of device Legend: Shading of rows is to assist in readability of the table. Note 1: This is the limit to which VDD can be lowered in SLEEP mode, or during a device RESET, without losing RAM data. 2002 Microchip Technology Inc. Preliminary DS39605B-page 239 PIC18F1220/1320 22.2 DC Characteristics: Power-Down and Supply Current PIC18F1220/1320 (Industrial) PIC18LF1220/1320 (Industrial) PIC18LF1220/1320 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial PIC18F1220/1320 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Param No. Device Typ Max Units Conditions 0.1 TBD A -40C 0.1 TBD A 25C 0.2 TBD A 85C 0.1 TBD A -40C 0.1 TBD A 25C 0.3 TBD A 85C 0.1 TBD A -40C 0.1 TBD A 25C 0.4 TBD A 85C Power-down Current (IPD)(1) PIC18LF1220/1320 PIC18LF1220/1320 All devices VDD = 2.0V, (SLEEP mode) VDD = 3.0V, (SLEEP mode) VDD = 5.0V, (SLEEP mode) Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in k. 4: Standard low cost 32 kHz crystals have an operating temperature range of -10C to +70C. Extended temperature crystals are available at a much higher cost. DS39605B-page 240 Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 22.2 DC Characteristics: Power-Down and Supply Current PIC18F1220/1320 (Industrial) PIC18LF1220/1320 (Industrial) (Continued) PIC18LF1220/1320 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial PIC18F1220/1320 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Param No. Device Typ Max Units Conditions 11 TBD A -40C 13 TBD A 25C Supply Current (IDD)(2,3) PIC18LF1220/1320 PIC18LF1220/1320 All devices PIC18LF1220/1320 PIC18LF1220/1320 All devices PIC18LF1220/1320 PIC18LF1220/1320 All devices 14 TBD A 85C 34 TBD A -40C 28 TBD A 25C 25 TBD A 85C 77 TBD A -40C 62 TBD A 25C 53 TBD A 85C 100 TBD A -40C 110 TBD A 25C 120 TBD A 85C 180 TBD A -40C 180 TBD A 25C 170 TBD A 85C 340 TBD A -40C 330 TBD A 25C 310 TBD A 85C 350 TBD A -40C 360 TBD A 25C 370 TBD A 85C 580 TBD A -40C 580 TBD A 25C 560 TBD A 85C 1.1 TBD mA -40C 1.1 TBD mA 25C 1.0 TBD mA 85C VDD = 2.0V VDD = 3.0V FOSC = 31 kHz (RC_RUN mode, Internal oscillator source) VDD = 5.0V VDD = 2.0V VDD = 3.0V FOSC = 1 MHz (RC_RUN mode, Internal oscillator source) VDD = 5.0V VDD = 2.0V VDD = 3.0V FOSC = 4 MHz (RC_RUN mode, Internal oscillator source) VDD = 5.0V Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in k. 4: Standard low cost 32 kHz crystals have an operating temperature range of -10C to +70C. Extended temperature crystals are available at a much higher cost. 2002 Microchip Technology Inc. Preliminary DS39605B-page 241 PIC18F1220/1320 22.2 DC Characteristics: Power-Down and Supply Current PIC18F1220/1320 (Industrial) PIC18LF1220/1320 (Industrial) (Continued) PIC18LF1220/1320 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial PIC18F1220/1320 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Param No. Device Typ Max Units Conditions 4.7 TBD A -40C 4.6 TBD A 25C Supply Current (IDD)(2,3) PIC18LF1220/1320 PIC18LF1220/1320 All devices PIC18LF1220/1320 PIC18LF1220/1320 All devices PIC18LF1220/1320 PIC18LF1220/1320 All devices 5.1 TBD A 85C 6.9 TBD A -40C 6.3 TBD A 25C 6.8 TBD A 85C 12 TBD A -40C 10 TBD A 25C 10 TBD A 85C 49 TBD A -40C 52 TBD A 25C 56 TBD A 85C 73 TBD A -40C 77 TBD A 25C 77 TBD A 85C 130 TBD A -40C 130 TBD A 25C 130 TBD A 85C 140 TBD A -40C 140 TBD A 25C 150 TBD A 85C 220 TBD A -40C 220 TBD A 25C 210 TBD A 85C 390 TBD A -40C 400 TBD A 25C 380 TBD A 85C VDD = 2.0V VDD = 3.0V FOSC = 31 kHz (RC_IDLE mode, Internal oscillator source) VDD = 5.0V VDD = 2.0V VDD = 3.0V FOSC = 1 MHz (RC_IDLE mode, Internal oscillator source) VDD = 5.0V VDD = 2.0V VDD = 3.0V FOSC = 4 MHz (RC_IDLE mode, Internal oscillator source) VDD = 5.0V Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in k. 4: Standard low cost 32 kHz crystals have an operating temperature range of -10C to +70C. Extended temperature crystals are available at a much higher cost. DS39605B-page 242 Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 22.2 DC Characteristics: Power-Down and Supply Current PIC18F1220/1320 (Industrial) PIC18LF1220/1320 (Industrial) (Continued) PIC18LF1220/1320 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial PIC18F1220/1320 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Param No. Device Typ Max Units Conditions 150 TBD A -40C 150 TBD A 25C 160 TBD A 85C 340 TBD A -40C 300 TBD A 25C 280 TBD A 85C Supply Current (IDD)(2,3) PIC18LF1220/1320 PIC18LF1220/1320 All devices PIC18LF1220/1320 PIC18LF1220/1320 All devices All devices All devices 720 TBD A -40C 630 TBD A 25C 570 TBD A 85C 440 TBD A -40C 450 TBD A 25C 460 TBD A 85C 800 TBD A -40C 780 TBD A 25C 770 TBD A 85C 1.6 TBD mA -40C 1.5 TBD mA 25C 1.5 TBD mA 85C 9.5 TBD mA -40C 9.7 TBD mA 25C 9.9 TBD mA 85C -40C 11.9 TBD mA 12.1 TBD mA 25C 12.3 TBD mA 85C VDD = 2.0V VDD = 3.0V FOSC = 1 MHZ (PRI_RUN, EC oscillator) VDD = 5.0V VDD = 2.0V VDD = 3.0V FOSC = 4 MHz (PRI_RUN, EC oscillator) VDD = 5.0V VDD = 4.2V FOSC = 40 MHZ (PRI_RUN, EC oscillator) VDD = 5.0V Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in k. 4: Standard low cost 32 kHz crystals have an operating temperature range of -10C to +70C. Extended temperature crystals are available at a much higher cost. 2002 Microchip Technology Inc. Preliminary DS39605B-page 243 PIC18F1220/1320 22.2 DC Characteristics: Power-Down and Supply Current PIC18F1220/1320 (Industrial) PIC18LF1220/1320 (Industrial) (Continued) PIC18LF1220/1320 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial PIC18F1220/1320 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Param No. Device Typ Max Units Conditions 37 TBD A -40C 37 TBD A 25C Supply Current (IDD)(2,3) PIC18LF1220/1320 PIC18LF1220/1320 All devices PIC18LF1220/1320 PIC18LF1220/1320 All devices All devices All devices 38 TBD A 85C 58 TBD A -40C 59 TBD A 25C 60 TBD A 85C 110 TBD A -40C 110 TBD A 25C 110 TBD A 85C 140 TBD A -40C 140 TBD A 25C 140 TBD A 85C 220 TBD A -40C 230 TBD A 25C 230 TBD A 85C 410 TBD A -40C 420 TBD A 25C 430 TBD A 85C -40C 3.1 TBD mA 3.2 TBD mA 25C 3.3 TBD mA 85C -40C 4.4 TBD mA 4.6 TBD mA 25C 4.6 TBD mA 85C VDD = 2.0V VDD = 3.0V FOSC = 1 MHz (PRI_IDLE mode, EC oscillator) VDD = 5.0V VDD = 2.0V VDD = 3.0V FOSC = 4 MHz (PRI_IDLE mode, EC oscillator) VDD = 5.0V VDD = 4.2 V FOSC = 40 MHz (PRI_IDLE mode, EC oscillator) VDD = 5.0V Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in k. 4: Standard low cost 32 kHz crystals have an operating temperature range of -10C to +70C. Extended temperature crystals are available at a much higher cost. DS39605B-page 244 Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 22.2 DC Characteristics: Power-Down and Supply Current PIC18F1220/1320 (Industrial) PIC18LF1220/1320 (Industrial) (Continued) PIC18LF1220/1320 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial PIC18F1220/1320 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Param No. Device Typ Max Units Conditions 13 TBD A -10C 14 TBD A 25C Supply Current (IDD)(2,3) PIC18LF1220/1320 PIC18LF1220/1320 All devices 16 TBD A 70C 34 TBD A -10C 31 TBD A 25C 28 TBD A 70C 72 TBD A -10C 65 TBD A 25C 59 TBD A 70C 5.5 TBD A -10C 5.8 TBD A 25C VDD = 2.0V VDD = 3.0V FOSC = 32 kHz(4) (SEC_RUN mode, Timer1 as clock) VDD = 5.0V Supply Current (IDD)(2,3) PIC18LF1220/1320 PIC18LF1220/1320 All devices 6.1 TBD A 70C 8.2 TBD A -10C 8.6 TBD A 25C 8.8 TBD A 70C 13 TBD A -10C 13 TBD A 25C 13 TBD A 70C VDD = 2.0V VDD = 3.0V FOSC = 32 kHz(4) (SEC_IDLE mode, Timer1 as clock) VDD = 5.0V Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in k. 4: Standard low cost 32 kHz crystals have an operating temperature range of -10C to +70C. Extended temperature crystals are available at a much higher cost. 2002 Microchip Technology Inc. Preliminary DS39605B-page 245 PIC18F1220/1320 22.2 DC Characteristics: Power-Down and Supply Current PIC18F1220/1320 (Industrial) PIC18LF1220/1320 (Industrial) (Continued) PIC18LF1220/1320 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial PIC18F1220/1320 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Param No. Device Typ Max Units Conditions Module Differential Currents (IWDT, IBOR, ILVD, IOSCB, IAD) D022 (IWDT) D022A Watchdog Timer Brown-out Reset (IBOR) D022B Low Voltage Detect (ILVD) D025 Timer1 Oscillator (IOSCB) D026 (IAD) A/D Converter 1.7 TBD A -40C 2.1 TBD A 25C 2.6 TBD A 85C 2.2 TBD A -40C 2.4 TBD A 25C 2.8 TBD A 85C 2.9 TBD A -40C 3.1 TBD A 25C 3.3 TBD A 85C 17 TBD A -40C to +85C VDD = 3.0V VDD = 2.0V VDD = 3.0V VDD = 5.0V 47 TBD A -40C to +85C VDD = 5.0V 14 TBD A -40C to +85C VDD = 2.0V 18 TBD A -40C to +85C VDD = 3.0V 21 TBD A -40C to +85C VDD = 5.0V 1.0 TBD A -10C 1.1 TBD A 25C 1.1 TBD A 70C 1.2 TBD A -10C 1.3 TBD A 25C 1.2 TBD A 70C 1.8 TBD A -10C 1.9 TBD A 25C 70C VDD = 2.0V 32 kHz on Timer1(4) VDD = 3.0V 32 kHz on Timer1(4) VDD = 5.0V 32 kHz on Timer1(4) 1.9 TBD A 1.0 TBD A VDD = 2.0V 1.0 TBD A VDD = 3.0V 1.0 TBD A VDD = 5.0V A/D on, not converting Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in k. 4: Standard low cost 32 kHz crystals have an operating temperature range of -10C to +70C. Extended temperature crystals are available at a much higher cost. DS39605B-page 246 Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 22.3 DC Characteristics: PIC18F1220/1320 (Industrial) PIC18LF1220/1320 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial DC CHARACTERISTICS Param Symbol No. VIL D030 D030A D031 D032 D032A D033 VIH D040 Characteristic Input Low Voltage I/O ports: with TTL buffer with Schmitt Trigger buffer RC3 and RC4 MCLR OSC1 (in XT, HS and LP modes) and T1OSI OSC1 (in RC and EC mode)(1) Input High Voltage I/O ports: with TTL buffer D040A D041 D042 D042A D043 IIL D060 with Schmitt Trigger buffer RC3 and RC4 MCLR, OSC1 (EC mode) OSC1 (in XT, HS and LP modes) and T1OSI OSC1 (RC mode)(1) Input Leakage Current(2,3) I/O ports Min Max Units Conditions VSS -- VSS VSS VSS VSS 0.15 VDD 0.8 0.2 VDD 0.3 VDD 0.2 VDD 0.3 VDD V V V V V V VSS 0.2 VDD V 0.25 VDD + 0.8V 2.0 VDD V VDD < 4.5V VDD V 4.5V VDD 5.5V 0.8 VDD 0.7 VDD 0.8 VDD 0.7 VDD VDD VDD VDD VDD V V V V 0.9 VDD VDD V -- 1 A VDD < 4.5V 4.5V VDD 5.5V VSS VPIN VDD, Pin at hi-impedance VSS VPIN VDD VSS VPIN VDD -- 5 A MCLR OSC1 -- 5 A IPU Weak Pull-up Current D070 IPURB PORTB weak pull-up current 50 400 A VDD = 5V, VPIN = VSS Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the PICmicro device be driven with an external clock while in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. 4: Parameter is characterized but not tested. D061 D063 2002 Microchip Technology Inc. Preliminary DS39605B-page 247 PIC18F1220/1320 22.3 DC Characteristics: PIC18F1220/1320 (Industrial) PIC18LF1220/1320 (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial DC CHARACTERISTICS Param Symbol No. VOL D080 D083 VOH D090 D092 D150 VOD D100(4) COSC2 Characteristic Output Low Voltage I/O ports OSC2/CLKO (RC mode) Output High Voltage(3) I/O ports OSC2/CLKO (RC mode) Open Drain High Voltage Capacitive Loading Specs on Output Pins OSC2 pin Min Max Units -- 0.6 V -- 0.6 V VDD - 0.7 -- V VDD - 0.7 -- V -- 8.5 V 15 pF Conditions IOL = 8.5 mA, VDD = 4.5V, -40C to +85C IOL = 1.6 mA, VDD = 4.5V, -40C to +85C IOH = -3.0 mA, VDD = 4.5V, -40C to +85C IOH = -1.3 mA, VDD = 4.5V, -40C to +85C RA4 pin In XT, HS and LP modes when external clock is used to drive OSC1 D101 CIO All I/O pins and OSC2 -- 50 pF To meet the AC Timing (in RC mode) Specifications D102 CB SCL, SDA -- 400 pF In I2C mode Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the PICmicro device be driven with an external clock while in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. 4: Parameter is characterized but not tested. DS39605B-page 248 -- Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 TABLE 22-1: MEMORY PROGRAMMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial DC Characteristics Param No. Sym Characteristic Min Typ Max Units Conditions Internal Program Memory Programming Specifications(1) D110 VPP Voltage on MCLR/VPP pin 9.00 -- 13.25 V (Note 2) D112 IPP Current into MCLR/VPP pin -- -- 5 A D113 IDDP Supply current during programming -- -- 10 mA E/W -40C to +85C Data EEPROM Memory D120 ED Byte Endurance 100K 1M -- D121 VDRW VDD for read/write VMIN -- 5.5 V D122 TDEW Erase/Write cycle time -- 4 -- ms D123 TRETD Characteristic Retention 40 -- -- Year Provided no other specifications are violated D124 TREF 1M 10M -- E/W -40C to +85C E/W -40C to +85C Number of total erase/write cycles before refresh(3) Using EECON to read/write VMIN = Minimum operating voltage Program FLASH Memory D130 EP Cell Endurance 10K 100K -- D131 VPR VDD for read VMIN -- 5.5 V VMIN = Minimum operating voltage D132 VIE VDD for Block Erase 4.5 -- 5.5 V Using ICSP port D132A VIW VDD for externally timed erase or write 4.5 -- 5.5 V Using ICSP port D132B VPEW VDD for self-timed write VMIN -- 5.5 V VMIN = Minimum operating voltage D133 ICSP Block Erase cycle time -- 4 -- ms VDD > 4.5V D133A TIW ICSP Erase or Write cycle time (externally timed) 1 -- -- ms VDD > 4.5V D133A TIW Self-timed Write cycle time -- 2 -- ms 40 -- -- TIE D134 TRETD Characteristic Retention Year Provided no other specifications are violated Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: These specifications are for programming the on-chip program memory through the use of Table Write instructions. 2: The pin may be kept in this range at times other than programming, but it is not recommended. 3: Refer to Section 7.8 for a more detailed discussion on data EEPROM endurance. 2002 Microchip Technology Inc. Preliminary DS39605B-page 249 PIC18F1220/1320 FIGURE 22-1: LOW VOLTAGE DETECT CHARACTERISTICS VDD (LVDIF can be cleared in software) VLVD (LVDIF set by hardware) LVDIF TABLE 22-2: LOW VOLTAGE DETECT CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Param Symbol No. Characteristic Min Typ Max Units Conditions D420 LVD Voltage on LVV = 0000 1.80 1.86 1.91 V VDD transition high LVV = 0001 2.00 2.06 2.12 V to low LVV = 0010 2.20 2.27 2.34 V LVV = 0011 2.40 2.47 2.55 V LVV = 0100 2.50 2.58 2.66 V LVV = 0101 2.70 2.78 2.86 V LVV = 0110 2.80 2.89 2.98 V LVV = 0111 3.00 3.10 3.20 V LVV = 1000 3.30 3.41 3.52 V LVV = 1001 3.50 3.61 3.72 V LVV = 1010 3.60 3.72 3.84 V LVV = 1011 3.80 3.92 4.04 V LVV = 1100 4.00 4.13 4.26 V LVV = 1101 4.20 4.33 4.46 V LVV = 1110 4.50 4.64 4.78 V Production tested at TAMB = 25C. Specifications over temp. limits ensured by characterization. DS39605B-page 250 Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 22.4 22.4.1 AC (Timing) Characteristics TIMING PARAMETER SYMBOLOGY The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase letters (pp) and their meanings: pp cc CCP1 ck CLKO cs CS di SDI do SDO dt Data in io I/O port mc MCLR Uppercase letters and their meanings: S F Fall H High I Invalid (Hi-Impedance) L Low I2C only AA output access BUF Bus free TCC:ST (I2C specifications only) CC HD Hold ST DAT DATA input hold STA START condition 2002 Microchip Technology Inc. 3. TCC:ST 4. Ts (I2C specifications only) (I2C specifications only) T Time osc rd rw sc ss t0 t1 wr OSC1 RD RD or WR SCK SS T0CKI T1CKI WR P R V Z Period Rise Valid Hi-Impedance High Low High Low SU Setup STO STOP condition Preliminary DS39605B-page 251 PIC18F1220/1320 22.4.2 TIMING CONDITIONS The temperature and voltages specified in Table 22-3 apply to all timing specifications unless otherwise noted. Figure 22-2 specifies the load conditions for the timing specifications. TABLE 22-3: TEMPERATURE AND VOLTAGE SPECIFICATIONS - AC AC CHARACTERISTICS FIGURE 22-2: Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Operating voltage VDD range as described in DC spec Section 22.1 and Section 22.3. LC parts operate for industrial temperatures only. LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 2 Load Condition 1 VDD/2 RL CL Pin VSS CL Pin RL = 464 VSS DS39605B-page 252 CL = 50 pF Preliminary for all pins except OSC2/CLKO 2002 Microchip Technology Inc. PIC18F1220/1320 22.4.3 TIMING DIAGRAMS AND SPECIFICATIONS FIGURE 22-3: EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL) Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 4 3 4 2 CLKO TABLE 22-4: Param. No. 1A EXTERNAL CLOCK TIMING REQUIREMENTS Symbol FOSC Characteristic Min Max Units External CLKI Frequency(1) DC 40 MHz EC, ECIO DC 4 MHz RC osc 0.1 4 MHz XT osc 4 25 MHz HS osc 4 10 MHz HS + PLL osc 5 200 kHz LP osc mode 25 -- ns Oscillator Frequency 1 TOSC External CLKI (1) Period(1) (1) Oscillator Period Time(1) 2 TCY Instruction Cycle 3 TosL, TosH External Clock in (OSC1) High or Low Time 4 TosR, TosF External Clock in (OSC1) Rise or Fall Time Conditions EC, ECIO 250 -- ns RC osc 250 10,000 ns XT osc 25 100 250 250 ns ns HS osc HS + PLL osc 5 -- s LP osc 100 -- ns TCY = 4/FOSC 30 -- ns XT osc 2.5 -- s LP osc 10 -- ns HS osc -- 20 ns XT osc -- 50 ns LP osc -- 7.5 ns HS osc Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period for all configurations except PLL. All specified values are based on characterization data for that particular oscillator type under standard operating conditions, with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the "max." cycle time limit is "DC" (no clock) for all devices. 2002 Microchip Technology Inc. Preliminary DS39605B-page 253 PIC18F1220/1320 TABLE 22-5: Param No. PLL CLOCK TIMING SPECIFICATIONS (VDD = 4.2 TO 5.5V) Sym Characteristic Min Typ Max Units F10 F11 FOSC Oscillator Frequency Range FSYS On-Chip VCO System Frequency 4 16 -- -- 10 40 F12 tRC PLL Start-up Time (Lock Time) -- -- 2 ms CLK CLKO Stability (Jitter) -2 -- +2 % F13 Conditions MHz HS mode only MHz HS mode only Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. 22.5 DC Characteristics: Internal RC Accuracy PIC18F1220/1320 (Industrial) PIC18LF1220/1320 (Industrial) PIC18LF1220/1320 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial PIC18F1220/1320 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Param No. Device Min Typ Max Units Conditions INTOSC Accuracy @ Freq = 8 MHz, 4 MHz, 2 MHz, 1 MHz, 500 kHz, 250 kHz, 125 kHz(1) F1 PIC18LF1220/1320 TBD TBD All devices TBD 28.125 F2 F3 +/-1 TBD % 25C VDD = 2.0V +/-1 TBD % 25C VDD = 3.0V +/-1 TBD % 25C VDD = 5.0V -- 34.375 kHz 25C VDD = 2.0V 28.125 -- 34.375 kHz 25C VDD = 3.0V 28.125 -- 34.375 kHz 25C VDD = 5.0V TBD 1 TBD % 25C VDD = 2.0V TBD 1 TBD % 25C VDD = 3.0V TBD 1 TBD % 25C VDD = 5.0V INTRC Accuracy @ Freq = 31.25 kHz(2) F4 PIC18LF1220/1320 F5 F6 All devices INTRC Stability(3) F7 PIC18LF1220/1320 F8 F9 Legend: Note 1: 2: 3: All devices Shading of rows is to assist in readability of the table. Frequency calibrated at 25C. OSCTUNE register can be used to compensate for temperature drift. INTRC frequency after calibration. Change of INTRC frequency as VDD changes. DS39605B-page 254 Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 FIGURE 22-4: CLKO AND I/O TIMING Q1 Q4 Q2 Q3 OSC1 11 10 CLKO 13 19 14 12 18 16 I/O pin (Input) 15 17 I/O pin (Output) New Value Old Value 20, 21 Note: Refer to Figure 22-2 for load conditions. TABLE 22-6: CLKO AND I/O TIMING REQUIREMENTS Param. Symbol No. Characteristic Min Typ Max Units Conditions 10 TosH2ckL OSC1 to CLKO -- 75 200 ns (1) 11 TosH2ckH OSC1 to CLKO -- 75 200 ns (1) 12 TckR CLKO rise time -- 35 100 ns (1) 13 TckF CLKO fall time -- 35 100 ns (1) 14 TckL2ioV CLKO to Port out valid -- -- 0.5 TCY + 20 ns (1) 15 TioV2ckH Port in valid before CLKO 0.25 TCY + 25 -- -- ns (1) (1) 16 TckH2ioI 17 TosH2ioV OSC1 (Q1 cycle) to Port out valid 18 TosH2ioI 18A Port in hold after CLKO OSC1 (Q2 cycle) to Port PIC18FXX20 input invalid (I/O in hold time) PIC18LFXX20 0 -- -- ns -- 50 150 ns 100 -- -- ns 200 -- -- ns 19 TioV2osH Port input valid to OSC1 (I/O in setup time) 0 -- -- ns 20 TioR Port output rise time PIC18FXX20 -- 10 25 ns PIC18LFXX20 -- -- 60 ns TioF Port output fall time PIC18FXX20 -- 10 25 ns -- -- 60 ns 22 TINP INT pin high or low time TCY -- -- ns 23 TRBP RB7:RB4 change INT high or low time TCY -- -- ns 24 TRCP RC7:RC4 change INT high or low time 20 -- -- ns 20A 21 21A PIC18LFXX20 These parameters are asynchronous events not related to any internal clock edges. Note 1: Measurements are taken in RC mode, where CLKO output is 4 x TOSC. 2002 Microchip Technology Inc. Preliminary DS39605B-page 255 PIC18F1220/1320 FIGURE 22-5: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal RESET Watchdog Timer Reset 31 34 34 I/O Pins Note: Refer to Figure 22-2 for load conditions. FIGURE 22-6: BROWN-OUT RESET TIMING BVDD VDD 35 VBGAP = 1.2V VIRVST Enable Internal Reference Voltage Internal Reference Voltage Stable DS39605B-page 256 36 Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 TABLE 22-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET REQUIREMENTS Param. Symbol No. Characteristic Min Typ Max Units 30 TmcL MCLR Pulse Width (low) 2 -- -- s 31 TWDT Watchdog Timer Time-out Period (No Postscaler) -- 4.0 TBD ms 32 TOST Oscillation Start-up Timer Period 1024 TOSC -- 1024 TOSC -- 33 TPWRT Power up Timer Period -- 65.5 132 ms 34 TIOZ I/O Hi-Impedance from MCLR Low or Watchdog Timer Reset -- 2 -- s 35 TBOR Brown-out Reset Pulse Width 200 -- -- s 36 TIVRST Time for Internal Reference Voltage to become stable -- 20 50 s 37 TLVD Low Voltage Detect Pulse Width 200 -- -- s FIGURE 22-7: Conditions TOSC = OSC1 period VDD BVDD (see D005) VDD VLVD TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 41 40 42 T1OSO/T1CKI 46 45 47 48 TMR0 or TMR1 Note: Refer to Figure 22-2 for load conditions. 2002 Microchip Technology Inc. Preliminary DS39605B-page 257 PIC18F1220/1320 TABLE 22-8: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param Symbol No. Characteristic 40 Tt0H T0CKI High Pulse Width 41 Tt0L T0CKI Low Pulse Width 42 Tt0P T0CKI Period No Prescaler With Prescaler No Prescaler With Prescaler No Prescaler With Prescaler 45 Tt1H T1CKI High Time Synchronous, no prescaler Synchronous, PIC18FXX20 with prescaler PIC18LFXX20 Asynchronous 46 Tt1L PIC18FXX20 PIC18LFXX20 T1CKI Low Time Synchronous, no prescaler Synchronous, PIC18FXX20 with prescaler PIC18LFXX20 Asynchronous PIC18FXX20 PIC18LFXX20 47 Tt1P T1CKI Input Period Synchronous Ft1 T1CKI Oscillator Input Frequency Range Asynchronous 48 Tcke2tmrI Delay from External T1CKI Clock Edge to Timer Increment DS39605B-page 258 Preliminary Min Max Units 0.5 TCY + 20 -- ns 10 -- ns 0.5 TCY + 20 -- ns 10 -- ns TCY + 10 -- ns Greater of: 20 ns or TCY + 40 N -- ns 0.5 TCY + 20 -- ns 10 -- ns 25 -- ns 30 -- ns 50 -- ns 0.5 TCY + 5 -- ns 10 -- ns 25 -- ns 30 -- ns TBD TBD ns Greater of: 20 ns or TCY + 40 N -- ns 60 -- ns DC 50 kHz 2 TOSC 7 TOSC -- Conditions N = prescale value (1, 2, 4,..., 256) N = prescale value (1, 2, 4, 8) 2002 Microchip Technology Inc. PIC18F1220/1320 FIGURE 22-8: CAPTURE/COMPARE/PWM TIMINGS (ALL CCP MODULES) CCPx (Capture Mode) 50 51 52 CCPx (Compare or PWM Mode) 54 53 Note: TABLE 22-9: Refer to Figure 22-2 for load conditions. CAPTURE/COMPARE/PWM REQUIREMENTS (ALL CCP MODULES) Param. Symbol No. 50 51 TccL TccH Characteristic CCPx input low time No Prescaler With Prescaler TccP CCPx input period 53 TccR CCPx output fall time 54 TccF CCPx output fall time 2002 Microchip Technology Inc. Max Units 0.5 TCY + 20 -- ns 10 -- ns PIC18FXX20 PIC18LFXX20 CCPx input high No Prescaler time With PIC18FXX20 Prescaler PIC18LFXX20 52 Min 20 -- ns 0.5 TCY + 20 -- ns 10 -- ns 20 -- ns 3 TCY + 40 N -- ns PIC18FXX20 -- 25 ns PIC18LFXX20 -- 45 ns PIC18FXX20 -- 25 ns PIC18LFXX20 -- 45 ns Preliminary Conditions N = prescale value (1,4 or 16) DS39605B-page 259 PIC18F1220/1320 FIGURE 22-9: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING RB1/AN5/TX/ CK/INT1 pin 121 121 RB4/AN6/RX/ DT/KBI0 pin 120 Note: 122 Refer to Figure 22-2 for load conditions. TABLE 22-10: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS Param. Symbol No. 120 Characteristic TckH2dtV SYNC XMIT (MASTER & SLAVE) Clock high to data out valid PIC18FXX20 Min Max Units -- 40 ns PIC18LFXX20 -- 100 ns 121 Tckrf Clock out rise time and fall time (Master mode) PIC18FXX20 -- 20 ns PIC18LFXX20 -- 50 ns 122 Tdtrf Data out rise time and fall time PIC18FXX20 -- 20 ns PIC18LFXX20 -- 50 ns FIGURE 22-10: RB1/AN5/TX/ CK/INT1 pin Conditions USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING 125 RB4/AN6/RX/ DT/KBI0 pin 126 Note: Refer to Figure 22-2 for load conditions. TABLE 22-11: USART SYNCHRONOUS RECEIVE REQUIREMENTS Param. No. 125 126 Symbol TdtV2ckl TckL2dtl DS39605B-page 260 Characteristic Min Max Units SYNC RCV (MASTER & SLAVE) Data hold before CK (DT hold time) 10 -- ns Data hold after CK (DT hold time) 15 -- ns Preliminary Conditions 2002 Microchip Technology Inc. PIC18F1220/1320 TABLE 22-12: A/D CONVERTER CHARACTERISTICS: PIC18F1220/1320 (INDUSTRIAL) PIC18LF1220/1320 (INDUSTRIAL) Param Symbol No. Characteristic Min Typ Max Units bit Conditions VREF 3.0V A01 NR Resolution -- -- 10 A03 EIL Integral linearity error -- -- <1 LSb VREF 3.0V A04 EDL Differential linearity error -- -- <1 LSb VREF 3.0V A06 EOFF Offset error -- -- <1 LSb VREF 3.0V A07 EGN Gain error -- -- <1 LSb VREF 3.0V guaranteed(2) -- A10 -- Monotonicity A20 VREF Reference voltage range (VREFH - VREFL) 3 -- AVDD - AVSS V For 10-bit resolution A21 VREFH Reference voltage High AVSS + 3.0V -- AVDD + 0.3V V For 10-bit resolution A22 VREFL Reference voltage Low AVSS - 0.3V -- AVDD - 3.0V V For 10-bit resolution A25 VAIN Analog input voltage VREFL -- VREFH V A28 AVDD Analog supply voltage VDD - 0.3 -- VDD + 0.3 V A29 AVSS Analog supply voltage VSS - 0.3 -- VSS + 0.3 V A30 ZAIN Recommended impedance of analog voltage source -- -- 2.5 k A40 IAD A/D conversion PIC18FXX20 current (VDD) PIC18LFXX2 0 A50 IREF VREF input current (Note 3) -- 180 -- A -- 90 -- A -- -- -- -- 5 150 A A Average current consumption when A/D is on (Note 1) During VAIN acquisition. During A/D conversion cycle. Note 1: When A/D is off, it will not consume any current other than minor leakage current. The power-down current spec includes any such leakage from the A/D module. 2: The A/D conversion result never decreases with an increase in the input voltage, and has no missing codes. 3: VREFH current is from RA3/AN3/VREF+ pin or AVDD, whichever is selected as the VREFH source. VREFL current is from RA2/AN2/VREF- pin or AVSS, whichever is selected as the VREFL source. 2002 Microchip Technology Inc. Preliminary DS39605B-page 261 PIC18F1220/1320 FIGURE 22-11: A/D CONVERSION TIMING BSF ADCON0, GO (Note 2) 131 Q4 A/D CLK 130 132 9 A/D DATA 8 7 ... ... 2 1 0 NEW_DATA OLD_DATA ADRES TCY ADIF GO DONE SAMPLING STOPPED SAMPLE Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. 2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input. TABLE 22-13: A/D CONVERSION REQUIREMENTS Param Symbol No. 130 TAD Characteristic A/D Clock Period Min Max Units Conditions PIC18FXX20 1.6 20(5) s TOSC based, VREF 3.0V PIC18LFXX20 3.0 20(5) s TOSC based, VREF full range PIC18FXX20 2.0 6.0 s A/D RC mode PIC18LFXX20 3.0 9.0 s A/D RC mode 131 TCNV Conversion Time (not including acquisition time) (Note 1) 11 12 TAD 132 TACQ Acquisition Time (Note 3) 15 10 -- -- s s -40C Temp +125C 0C Temp +125C 135 TSWC Switching Time from convert sample -- (Note 4) 136 TAMP Amplifier Settling Time (Note 2) 1 -- s This may be used if the "new" input voltage has not changed by more than 1 LSb (i.e., 5 mV @ 5.12V) from the last sampled voltage (as stated on CHOLD). Note 1: ADRES register may be read on the following TCY cycle. 2: See Section 17.0 for minimum conditions, when input voltage has changed more than 1 LSb. 3: The time for the holding capacitor to acquire the "New" input voltage, when the voltage changes full scale after the conversion (AVDD to AVSS, or AVSS to AVDD). The source impedance (RS) on the input channels is 50. 4: On the next Q4 cycle of the device clock. 5: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider. DS39605B-page 262 Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 23.0 PRELIMINARY DC AND AC CHARACTERISTICS GRAPHS AND TABLES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range. "Typical" represents the mean of the distribution at 25C. "Maximum" or "minimum" represents (mean + 3) or (mean - 3) respectively, where is a standard deviation, over the whole temperature range. FIGURE 23-1: TYPICAL IDD vs. FOSC OVER VDD (EC MODE) 16 14 5 .5 V 5 .0 V 12 4 .5 V 10 IDD (mA) 4 .0 V 3 .5 V 8 3 .0 V 6 2 .5 V 4 2 2 .0 V 0 0 5 10 15 20 25 30 35 40 F O S C (M H z) FIGURE 23-2: TYPICAL TOTAL IPD vs. VDD (SLEEP MODE, WDT ENABLED) 4 .0 3 .5 3 .0 Typ T y p(25C) (2 5 C ) IPD ( A) 2 .5 2 .0 1 .5 1 .0 0 .5 0 .0 2 .0 2 .5 3 .0 3 .5 4 .0 4 .5 5 .0 5 .5 V D D (V ) 2002 Microchip Technology Inc. Preliminary DS39605B-page 263 PIC18F1220/1320 FIGURE 23-3: TYPICAL IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED) IPD ( A) 1 0.1 C) Typ (25C) 0.01 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) DS39605B-page 264 Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 FIGURE 23-4: TYPICAL TOTAL IDD vs. VDD OVER TEMPERATURE (-40C TO +85C, INTOSC AT 2 MHz, BOR ENABLED AT 2.70 - 2.86V) 0.35 0.30 Held in RESET Reset 0.25 IPD (mA) 0.20 Typ 0.15 0.10 SLEEP Mode 0.05 Typ 0.00 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) 2002 Microchip Technology Inc. Preliminary DS39605B-page 265 PIC18F1220/1320 FIGURE 23-5: TYPICAL TOTAL IPD vs. VDD (-10C TO +70C, SLEEP MODE, TIMER1 OSCILLATOR ENABLED) 10 IPD (A) Typ Typ(25C) (25C) 1 0.1 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 23-6: TYPICAL TOTAL IPD vs. VDD (SLEEP MODE, TIMER1 AND OSCILLATOR ENABLED) IPD (A) 10 Typ Typ(25C) (25C) 1 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) DS39605B-page 266 Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 24.0 PACKAGING INFORMATION 24.1 Package Marking Information 18-Lead PDIP Example PIC18F1320-I/SP XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN 0217017 18-Lead SOIC Example XXXXXXXXXXXX XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN PIC18F1220E/SO 0210017 20-Lead SSOP Example XXXXXXXXXXX XXXXXXXXXXX YYWWNNN PIC18F1220E/SS 0210017 28-Lead QFN Example XXXXXXXX XXXXXXXX YYWWNNN Legend: XX...X Y YY WW NNN Note: * PIC18F13 20-I/ML 0210017 Customer specific information* Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. Standard PICmicro device marking consists of Microchip part number, year code, week code, and traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. 2002 Microchip Technology Inc. Preliminary DS39605B-page 267 PIC18F1220/1320 24.2 Package Details The following sections give the technical details of the packages. 18-Lead Plastic Dual In-line (P) - 300 mil (PDIP) E1 D 2 n 1 E A2 A L c A1 B1 p B eB Units Dimension Limits n p MIN INCHES* NOM 18 .100 .155 .130 MAX MILLIMETERS NOM 18 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 22.61 22.80 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40 5 10 5 10 MIN Number of Pins Pitch Top to Seating Plane A .140 .170 Molded Package Thickness A2 .115 .145 Base to Seating Plane .015 A1 Shoulder to Shoulder Width E .300 .313 .325 Molded Package Width E1 .240 .250 .260 Overall Length D .890 .898 .905 Tip to Seating Plane L .125 .130 .135 c Lead Thickness .008 .012 .015 Upper Lead Width B1 .045 .058 .070 Lower Lead Width B .014 .018 .022 Overall Row Spacing eB .310 .370 .430 Mold Draft Angle Top 5 10 15 Mold Draft Angle Bottom 5 10 15 * Controlling Parameter Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-007 DS39605B-page 268 Preliminary MAX 4.32 3.68 8.26 6.60 22.99 3.43 0.38 1.78 0.56 10.92 15 15 2002 Microchip Technology Inc. PIC18F1220/1320 18-Lead Plastic Small Outline (SO) - Wide, 300 mil (SOIC) E p E1 D 2 B n 1 h 45 c A2 A L Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom A A2 A1 E E1 D h L c B MIN .093 .088 .004 .394 .291 .446 .010 .016 0 .009 .014 0 0 A1 INCHES* NOM 18 .050 .099 .091 .008 .407 .295 .454 .020 .033 4 .011 .017 12 12 MAX .104 .094 .012 .420 .299 .462 .029 .050 8 .012 .020 15 15 MILLIMETERS NOM 18 1.27 2.36 2.50 2.24 2.31 0.10 0.20 10.01 10.34 7.39 7.49 11.33 11.53 0.25 0.50 0.41 0.84 0 4 0.23 0.27 0.36 0.42 0 12 0 12 MIN MAX 2.64 2.39 0.30 10.67 7.59 11.73 0.74 1.27 8 0.30 0.51 15 15 * Controlling Parameter Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-013 Drawing No. C04-051 2002 Microchip Technology Inc. Preliminary DS39605B-page 269 PIC18F1220/1320 20-Lead Plastic Shrink Small Outline (SS) - 209 mil, 5.30 mm (SSOP) E E1 p D B 2 1 n c A2 A L A1 Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Foot Length Lead Thickness Foot Angle Lead Width Mold Draft Angle Top Mold Draft Angle Bottom A A2 A1 E E1 D L c B MIN .068 .064 .002 .299 .201 .278 .022 .004 0 .010 0 0 INCHES* NOM 20 .026 .073 .068 .006 .309 .207 .284 .030 .007 4 .013 5 5 MAX .078 .072 .010 .322 .212 .289 .037 .010 8 .015 10 10 MILLIMETERS NOM 20 0.65 1.73 1.85 1.63 1.73 0.05 0.15 7.59 7.85 5.11 5.25 7.06 7.20 0.56 0.75 0.10 0.18 0.00 101.60 0.25 0.32 0 5 0 5 MIN MAX 1.98 1.83 0.25 8.18 5.38 7.34 0.94 0.25 203.20 0.38 10 10 * Controlling Parameter Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MO-150 Drawing No. C04-072 DS39605B-page 270 Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 28-Lead Plastic Quad Flat No Lead Package (ML) 6x6 mm Body (QFN) EXPOSED METAL PADS E E1 Q D1 D D2 p 2 1 B n R E2 CH x 45 TOP VIEW L BOTTOM VIEW A2 A A1 A3 Units Dimension Limits MILLIMETERS* INCHES MIN NOM MIN MAX MAX NOM Number of Pins n Pitch p Overall Height A .033 .039 0.85 1.00 Molded Package Thickness A2 .026 .031 0.65 0.80 Standoff A1 .0004 .002 0.01 0.05 Base Thickness A3 .008 REF. 0.20 REF. 6.00 BSC .000 E .236 BSC E1 .226 BSC Exposed Pad Width E2 Overall Length 0.65 BSC .026 BSC Molded Package Width Overall Width 28 28 .140 D .146 0.00 5.75 BSC .152 3.55 .236 BSC 3.70 3.85 6.00 BSC Molded Package Length D1 Exposed Pad Length D2 .140 .146 .152 3.55 3.70 Lead Width B .009 .011 .014 0.23 0.28 0.35 Lead Length L .020 .024 .030 0.50 0.60 0.75 Tie Bar Width R .005 .007 .010 0.13 0.17 0.23 Tie Bar Length Q .012 .016 .026 0.30 0.40 0.65 CH .009 .017 .024 0.24 0.42 0.60 Chamfer Mold Draft Angle Top .226 BSC 5.75 BSC 12 3.85 12 *Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC equivalent: M0-220 Drawing No. C04-114 2002 Microchip Technology Inc. Preliminary DS39605B-page 271 PIC18F1220/1320 28-Lead Plastic Quad Flat No Lead Package (ML) 6x6 mm Body (QFN) Land Pattern and Solder Mask M B L M p PACKAGE EDGE SOLDER MASK Pitch Pad Width Pad Length Pad to Solder Mask Units Dimension Limits p B L M MIN .009 .020 .005 INCHES NOM .026 BSC .011 .024 MAX .014 .030 .006 MILLIMETERS* NOM 0.65 BSC 0.23 0.28 0.50 0.60 0.13 MIN MAX 0.35 0.75 0.15 *Controlling Parameter Drawing No. C04-2114 DS39605B-page 272 Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 APPENDIX A: REVISION HISTORY Revision A (August 2002) APPENDIX B: DEVICE DIFFERENCES The differences between the devices listed in this data sheet are shown in Table B-1. Original data sheet for PIC18F1220/1320 devices. Revision B (November 2002) This revision includes significant changes to Section 2.0, Section 3.0, and Section 19.0, as well as updates to the Electrical Specifications in Section 22.0, and includes minor corrections to the data sheet text. TABLE B-1: DEVICE DIFFERENCES Features PIC18F1220 PIC18F1320 Program Memory (Bytes) 4096 8192 Program Memory (Instructions) 2048 4096 Interrupt Sources I/O Ports Enhanced Capture/Compare/PWM Modules 10-bit Analog-to-Digital Module Packages 2002 Microchip Technology Inc. 15 15 Ports A, B Ports A, B 1 1 7 input channels 7 input channels 18-pin SDIP 18-pin SOIC 20-pin SSOP 28-pin QFN 18-pin SDIP 18-pin SOIC 20-pin SSOP 28-pin QFN Preliminary DS39605B-page 273 PIC18F1220/1320 APPENDIX C: CONVERSION CONSIDERATIONS APPENDIX D: This appendix discusses the considerations for converting from previous versions of a device to the ones listed in this data sheet. Typically, these changes are due to the differences in the process technology used. An example of this type of conversion is from a PIC16C74A to a PIC16C74B. Not Applicable DS39605B-page 274 MIGRATION FROM BASELINE TO ENHANCED DEVICES This section discusses how to migrate from a Baseline device (i.e., PIC16C5X) to an Enhanced MCU device (i.e., PIC18FXXX). The following are the list of modifications over the PIC16C5X microcontroller family: Not Currently Available Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 APPENDIX E: MIGRATION FROM MID-RANGE TO ENHANCED DEVICES A detailed discussion of the differences between the mid-range MCU devices (i.e., PIC16CXXX) and the enhanced devices (i.e., PIC18FXXX) is provided in AN716, "Migrating Designs from PIC16C74A/74B to PIC18F442". The changes discussed, while device specific, are generally applicable to all mid-range to enhanced device migrations. APPENDIX F: MIGRATION FROM HIGH-END TO ENHANCED DEVICES A detailed discussion of the migration pathway and differences between the high-end MCU devices (i.e., PIC17CXXX) and the enhanced devices (i.e., PIC18FXXX) is provided in AN726, "PIC17CXXX to PIC18FXXX Migration". This Application Note is available as Literature Number DS00726. This Application Note is available as Literature Number DS00716. 2002 Microchip Technology Inc. Preliminary DS39605B-page 275 PIC18F1220/1320 NOTES: DS39605B-page 276 Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 INDEX A A/D ................................................................................... 155 A/D Converter Interrupt, Configuring ....................... 159 Acquisition Requirements ........................................ 160 ADCON0 Register .................................................... 155 ADCON1 Register .................................................... 155 ADCON2 Register .................................................... 155 ADRESH Register .................................................... 155 ADRESH/ADRESL Registers .................................. 158 ADRESL Register .................................................... 155 Analog Port Pins, Configuring .................................. 162 Configuring the Module ............................................ 159 Conversion Clock (TAD) ........................................... 161 Conversion Requirements ....................................... 262 Conversion Status (GO/DONE Bit) .......................... 158 Conversions ............................................................. 163 Converter Characteristics ........................................ 261 Operation in Low Power Modes ............................... 162 Registers Summary ................................................. 164 Selecting, Configuring Automatic Acquisition Time ............................................... 161 Special Event Trigger (CCP) .................................... 119 Special Event Trigger (CCP1) .................................. 164 Use of the CCP1 Trigger .......................................... 164 VREF+ and VREF- References .................................. 160 Absolute Maximum Ratings ............................................. 237 AC (Timing) Characteristics ............................................. 251 Conditions ................................................................ 252 Load Conditions for Device Timing Specifications ................................................... 252 Parameter Symbology ............................................. 251 Temperature and Voltage Specifications ................. 252 ADCON0 Register ............................................................ 155 GO/DONE Bit ........................................................... 158 ADCON1 Register ............................................................ 155 ADCON2 Register ............................................................ 155 ADDLW ............................................................................ 195 ADDWF ............................................................................ 195 ADDWFC ......................................................................... 196 ADRESH Register ............................................................ 155 ADRESH/ADRESL Registers ........................................... 158 ADRESL Register ............................................................ 155 Analog-to-Digital Converter. See A/D ANDLW ............................................................................ 196 ANDWF ............................................................................ 197 Assembler MPASM Assembler .................................................. 231 Auto Wake-up on Sync Break Character ......................... 147 B BC .................................................................................... 197 BCF .................................................................................. 198 Block Diagrams A/D ........................................................................... 158 Analog Input Model .................................................. 159 Capture Mode Operation ......................................... 119 Compare Mode Operation ....................................... 120 Enhanced PWM ....................................................... 122 Fail-Safe Clock Monitor ............................................ 182 Generic I/O Port Operation ........................................ 89 Low Voltage Detect (LVD) ....................................... 166 Low Voltage Detect (LVD) with External Input ......... 166 On-Chip Reset Circuit ................................................ 33 2002 Microchip Technology Inc. PIC18F1220/1320 ....................................................... 7 PLL ............................................................................ 12 PORTA MCLR/RA5 Pin .................................................. 91 OSC1/CLKI/RA7 Pin .......................................... 90 OSC2/CLKO/RA6 Pin ........................................ 90 RA3:RA0 Port Pins ............................................ 90 RA4/T0CKI Pin .................................................. 90 PORTB RB0/AN4/INT0 Pin ............................................. 92 RB1/AN5/INT1/TX/CK Pin ................................. 93 RB2/P1B/INT2 Pin ............................................. 94 RB3/CCP1/P1A Pin ........................................... 95 RB4/AN6/RX/DT/KBI0 Pin ................................. 96 RB5/PGM/KBI1 Pin ........................................... 97 RB6/PGC/T1OSO/T1CKI/P1C/KBI2 Pin ........... 98 RB7/PGD/T1OSI/P1D/KBI3 Pin ........................ 99 Reads from FLASH Program Memory ....................... 63 System Clock ............................................................. 16 Table Read Operation ............................................... 59 Table Write Operation ................................................ 60 Table Writes to FLASH Program Memory ................. 65 Timer0 in 16-bit Mode .............................................. 102 Timer0 in 8-bit Mode ................................................ 102 Timer1 ..................................................................... 106 Timer1 (16-bit Read/Write Mode) ............................ 106 Timer2 ..................................................................... 112 Timer3 ..................................................................... 114 Timer3 (16-bit R/W Mode) ....................................... 115 USART Receive ....................................................... 145 USART Transmit ...................................................... 143 WDT ........................................................................ 180 BN .................................................................................... 198 BNC ................................................................................. 199 BNN ................................................................................. 199 BNOV ............................................................................... 200 BNZ .................................................................................. 200 BOR. See Brown-out Reset BOV ................................................................................. 203 BRA ................................................................................. 201 Break Character (12-bit) Transmit and Receive .............. 148 Brown-out Reset (BOR) ..............................................34, 171 BSF .................................................................................. 201 BTFSC ............................................................................. 202 BTFSS ............................................................................. 202 BTG ................................................................................. 203 BZ .................................................................................... 204 C CALL ................................................................................ 204 Capture (CCP Module) .................................................... 118 CCP Pin Configuration ............................................. 118 CCPR1H:CCPR1L Registers ................................... 118 Software Interrupt .................................................... 118 Timer1/Timer3 Mode Selection ................................ 118 Capture, Compare, Timer1 and Timer3 Associated Registers ............................................... 120 Capture/Compare/PWM (CCP) Capture Mode. See Capture CCP1 ....................................................................... 118 CCPR1H Register ........................................... 118 CCPR1L Register ............................................ 118 Compare Mode. See Compare Timer Resources ..................................................... 118 Preliminary DS39605B-page 277 PIC18F1220/1320 Clock Sources .................................................................... 15 Selection Using OSCCON Register ........................... 16 Clocking Scheme ............................................................... 47 CLRF ................................................................................ 205 CLRWDT .......................................................................... 205 Code Examples 16 x 16 Signed Multiply Routine ................................. 74 16 x 16 Unsigned Multiply Routine ............................. 74 8 x 8 Signed Multiply Routine ..................................... 73 8 x 8 Unsigned Multiply Routine ................................. 73 Changing Between Capture Prescalers ................... 119 Computed GOTO Using an Offset Value ................... 49 Data EEPROM Read ................................................. 71 Data EEPROM Refresh Routine ................................ 72 Data EEPROM Write .................................................. 71 Erasing a FLASH Program Memory Row .................. 64 Fast Register Stack .................................................... 46 How to Clear RAM (Bank1) Using Indirect Addressing ............................................ 55 Implementing a Real-Time Clock Using a Timer1 Interrupt Service .................................. 109 Initializing PORTA ...................................................... 89 Initializing PORTB ...................................................... 92 Reading a FLASH Program Memory Word ................ 63 Saving STATUS, WREG and BSR Registers in RAM ............................................................... 87 Writing to FLASH Program Memory ..................... 66-67 Code Protection ............................................................... 171 COMF ............................................................................... 206 Compare (CCP Module) ................................................... 119 CCP Pin Configuration ............................................. 119 CCPR1 Register ....................................................... 119 Software Interrupt ..................................................... 119 Special Event Trigger ....................................... 116, 119 Timer1/Timer3 Mode Selection ................................ 119 Compare (CCP1 Module) Special Event Trigger ............................................... 164 Computed GOTO ............................................................... 49 Configuration Bits ............................................................. 171 Context Saving During Interrupts ....................................... 87 Conversion Considerations .............................................. 274 CPFSEQ .......................................................................... 206 CPFSGT ........................................................................... 207 CPFSLT ........................................................................... 207 D Data EEPROM Memory ..................................................... 69 Associated Registers ................................................. 72 EEADR Register ........................................................ 69 EECON1 Register ...................................................... 69 EECON2 Register ...................................................... 69 Operation During Code Protect .................................. 72 Protection Against Spurious Write ............................. 71 Reading ...................................................................... 71 Using .......................................................................... 72 Write Verify ................................................................. 71 Writing ........................................................................ 71 Data Memory ...................................................................... 49 General Purpose Registers ........................................ 49 Map for PIC18F1220/1320 Devices ........................... 50 Special Function Registers ........................................ 51 DAW ................................................................................. 208 DC and AC Characteristics Graphs and Tables (Preliminary) ............................. 263 DS39605B-page 278 DC Characteristics ........................................................... 247 Power-Down and Supply Current ............................ 240 Supply Voltage ......................................................... 239 DCFSNZ .......................................................................... 209 DECF ............................................................................... 208 DECFSZ .......................................................................... 209 Details on Individual Family Members ................................. 6 Development Support ...................................................... 231 Device Differences ........................................................... 273 Direct Addressing ............................................................... 56 E Effects of Power Managed Modes on Various Clock Sources .............................................. 18 Electrical Characteristics .................................................. 237 Enhanced Capture/Compare/PWM (ECCP) .................... 117 Outputs .................................................................... 118 PWM Mode. See PWM (ECCP Module) Enhanced PWM Mode. See PWM (ECCP Module) ......... 121 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (USART) ................................ 133 Equations 16 x 16 Signed Multiplication Algorithm ..................... 74 16 x 16 Unsigned Multiplication Algorithm ................. 74 A/D Minimum Charging Time ................................... 160 Acquisition Time ...................................................... 160 Errata ................................................................................... 4 F Fail-Safe Clock Monitor .................................................... 171 Exiting Operation ..................................................... 183 Interrupts in Power Managed Modes ....................... 183 POR or Wake from SLEEP ...................................... 184 WDT During Oscillator Failure ................................. 182 Fail-Safe Clock Monitor (FSCM) ...................................... 182 Fast Register Stack ............................................................ 46 Firmware Instructions ....................................................... 189 FLASH Program Memory ................................................... 59 Associated Registers ................................................. 67 Control Registers ....................................................... 60 Erase Sequence ........................................................ 64 Erasing ....................................................................... 64 Operation During Code Protect ................................. 67 Reading ..................................................................... 63 TABLAT Register ....................................................... 62 Table Pointer ............................................................. 62 Boundaries Based on Operation ........................ 62 Table Pointer Boundaries .......................................... 62 Table Reads and Table Writes .................................. 59 Write Sequence ......................................................... 65 Writing to .................................................................... 65 Unexpected Termination .................................... 67 Write Verify ........................................................ 67 G GOTO .............................................................................. 210 H Hardware Multiplier ............................................................ 73 Introduction ................................................................ 73 Operation ................................................................... 73 Performance Comparison .......................................... 73 Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 I I/O Ports ............................................................................. 89 ICEPIC In-Circuit Emulator .............................................. 232 ID Locations ............................................................. 171, 188 INCF ................................................................................. 210 INCFSZ ............................................................................ 211 In-Circuit Debugger .......................................................... 188 In-Circuit Serial Programming (ICSP) ...................... 171, 188 Indirect Addressing ............................................................ 56 INDF and FSR Registers ........................................... 55 Operation ................................................................... 55 Indirect Addressing Operation ............................................ 56 Indirect File Operand .......................................................... 49 INFSNZ ............................................................................ 211 Initialization Conditions for All Registers ............................ 36 Instruction Cycle ................................................................. 47 Instruction Flow/Pipelining ................................................. 47 Instruction Format ............................................................ 191 Instruction Set .................................................................. 189 ADDLW .................................................................... 195 ADDWF .................................................................... 195 ADDWFC ................................................................. 196 ANDLW .................................................................... 196 ANDWF .................................................................... 197 BC ............................................................................ 197 BCF .......................................................................... 198 BN ............................................................................ 198 BNC ......................................................................... 199 BNN ......................................................................... 199 BNOV ....................................................................... 200 BNZ .......................................................................... 200 BOV ......................................................................... 203 BRA .......................................................................... 201 BSF .......................................................................... 201 BTFSC ..................................................................... 202 BTFSS ..................................................................... 202 BTG .......................................................................... 203 BZ ............................................................................ 204 CALL ........................................................................ 204 CLRF ........................................................................ 205 CLRWDT .................................................................. 205 COMF ...................................................................... 206 CPFSEQ .................................................................. 206 CPFSGT .................................................................. 207 CPFSLT ................................................................... 207 DAW ......................................................................... 208 DCFSNZ .................................................................. 209 DECF ....................................................................... 208 DECFSZ ................................................................... 209 GOTO ...................................................................... 210 INCF ......................................................................... 210 INCFSZ .................................................................... 211 INFSNZ .................................................................... 211 IORLW ..................................................................... 212 IORWF ..................................................................... 212 LFSR ........................................................................ 213 MOVF ....................................................................... 213 MOVFF .................................................................... 214 MOVLB .................................................................... 214 MOVLW ................................................................... 215 MOVWF ................................................................... 215 MULLW .................................................................... 216 MULWF .................................................................... 216 NEGF ....................................................................... 217 NOP ......................................................................... 217 2002 Microchip Technology Inc. POP ......................................................................... 218 PUSH ....................................................................... 218 RCALL ..................................................................... 219 RESET ..................................................................... 219 RETFIE .................................................................... 220 RETLW .................................................................... 220 RETURN .................................................................. 221 RLCF ....................................................................... 221 RLNCF ..................................................................... 222 RRCF ....................................................................... 222 RRNCF .................................................................... 223 SETF ....................................................................... 223 SLEEP ..................................................................... 224 SUBFWB ................................................................. 224 SUBLW .................................................................... 225 SUBWF .................................................................... 225 SUBWFB ................................................................. 226 SWAPF .................................................................... 226 TBLRD ..................................................................... 227 TBLWT .................................................................... 228 TSTFSZ ................................................................... 229 XORLW ................................................................... 229 XORWF ................................................................... 230 Summary Table ....................................................... 192 INTCON Register RBIF Bit ..................................................................... 92 INTCON Registers ............................................................. 77 Internal Oscillator Block ..................................................... 14 Adjustment ................................................................. 14 INTIO Modes ............................................................. 14 INTRC Output Frequency .......................................... 14 OSCTUNE Register ................................................... 14 Internal RC Oscillator Use with WDT .......................................................... 180 Interrupt Sources ............................................................. 171 A/D Conversion Complete ....................................... 159 Capture Complete (CCP) ......................................... 118 Compare Complete (CCP) ....................................... 119 Interrupt-on-Change (RB7:RB4) ................................ 92 INTn Pin ..................................................................... 87 PORTB, Interrupt-on-Change .................................... 87 TMR0 ......................................................................... 87 TMR0 Overflow ........................................................ 103 TMR1 Overflow ........................................................ 105 TMR2 to PR2 Match ................................................ 112 TMR2 to PR2 Match (PWM) .............................111, 121 TMR3 Overflow .................................................113, 116 Interrupts ............................................................................ 75 Enable Bits (CCP1IE Bit) .................................................... 118 Flag Bits CCP1 Flag (CCP1IF Bit) .................................. 118 CCP1IF Flag (CCP1IF Bit) .............................. 119 Interrupt-on-Change (RB7:RB4) Flag (RBIF Bit) ................................................... 92 Logic .......................................................................... 76 INTOSC Frequency Drift .................................................... 30 IORLW ............................................................................. 212 IORWF ............................................................................. 212 IPR Registers ..................................................................... 84 K KEELOQ Evaluation and Programming Tools ................... 234 Preliminary DS39605B-page 279 PIC18F1220/1320 L LFSR ................................................................................ 213 Low Voltage Detect .......................................................... 165 Characteristics ......................................................... 250 Effects of a RESET .................................................. 169 Operation ................................................................. 168 Current Consumption ....................................... 169 Reference Voltage Set Point ............................ 169 Operation During SLEEP ......................................... 169 LVD. See Low Voltage Detect. ......................................... 165 M Memory Organization ......................................................... 43 Data Memory .............................................................. 49 Program Memory ....................................................... 43 Memory Programming Requirements .............................. 249 Migration from Baseline to Enhanced Devices ................ 274 Migration from High-End to Enhanced Devices ............... 275 Migration from Mid-Range to Enhanced Devices ............. 275 MOVF ............................................................................... 213 MOVFF ............................................................................. 214 MOVLB ............................................................................. 214 MOVLW ............................................................................ 215 MOVWF ........................................................................... 215 MPLAB C17 and MPLAB C18 C Compilers ..................... 231 MPLAB ICD In-Circuit Debugger ...................................... 233 MPLAB ICE High Performance Universal In-Circuit Emulator with MPLAB IDE ........................ 232 MPLAB Integrated Development Environment Software .............................................. 231 MPLINK Object Linker/MPLIB Object Librarian ............... 232 MULLW ............................................................................ 216 MULWF ............................................................................ 216 N NEGF ............................................................................... 217 New Core Features Multiple Oscillator Options and Features ..................... 5 Nanowatt Technology .................................................. 5 NOP ................................................................................. 217 O OPCODE Field Descriptions ............................................ 190 OPTION_REG Register PSA Bit ..................................................................... 103 T0CS Bit ................................................................... 103 T0PS2:T0PS0 Bits ................................................... 103 T0SE Bit ................................................................... 103 Oscillator Configuration ...................................................... 11 Crystal/Ceramic Resonator ........................................ 11 EC .............................................................................. 11 ECIO .......................................................................... 11 External Clock Input ................................................... 13 HS .............................................................................. 11 HSPLL .................................................................. 11, 12 INTIO1 ........................................................................ 11 INTIO2 ........................................................................ 11 LP ............................................................................... 11 RC ........................................................................ 11, 13 RCIO .......................................................................... 11 XT ............................................................................... 11 Oscillator Selection .......................................................... 171 Oscillator Start-up Timer (OST) ........................... 18, 34, 171 DS39605B-page 280 Oscillator Switching ............................................................ 15 Oscillator Transitions ......................................................... 18 Oscillator, Timer1 ......................................................105, 116 Oscillator, Timer3 ............................................................. 113 Other Special Features ........................................................ 5 P Packaging ........................................................................ 267 Details ...................................................................... 268 Marking Information ................................................. 267 PICDEM 1 Low Cost PICmicro Demonstration Board ............................................... 233 PICDEM 17 Demonstration Board ................................... 234 PICDEM 2 Low Cost PIC16CXX Demonstration Board ............................................... 233 PICDEM 3 Low Cost PIC16CXXX Demonstration Board ............................................... 234 PICSTART Plus Entry Level Development Programmer ....................................... 233 PIE Registers ..................................................................... 82 Pin Functions MCLR/VPP/RA5 ........................................................... 8 OSC1/CLKI/RA7 .......................................................... 8 OSC2/CLKO/RA6 ........................................................ 8 RA0/AN0 ...................................................................... 8 RA1/AN1/LVDIN .......................................................... 8 RA2/AN2/VREF- ........................................................... 8 RA3/AN3/VREF+ ........................................................... 8 RA4/T0CKI ................................................................... 8 RB0/AN4/INT0 ............................................................. 9 RB1/AN5/TX/CK/INT1 ................................................. 9 RB2/P1B/INT2 ............................................................. 9 RB3/CCP1/P1A ........................................................... 9 RB4/AN6/RX/DT/KBI0 ................................................. 9 RB5/PGM/KBI1 ............................................................ 9 RB6/PGC/T1OSO/T1CKI/P1C/KBI2 ............................ 9 RB7/PGD/T1OSI/P1D/KBI3 ......................................... 9 VDD .............................................................................. 9 VSS ............................................................................... 9 Pinout I/O Descriptions PIC18F1220/1320 ........................................................ 8 PIR Registers ..................................................................... 80 PLL Lock Time-out ............................................................. 34 Pointer, FSR ...................................................................... 55 POP ................................................................................. 218 POR. See Power-on Reset PORTA Associated Registers ................................................. 91 Functions ................................................................... 91 LATA Register ........................................................... 89 PORTA Register ........................................................ 89 TRISA Register .......................................................... 89 PORTB Associated Registers ............................................... 100 Functions ................................................................. 100 LATB Register ........................................................... 92 PORTB Register ........................................................ 92 RB7:RB4 Interrupt-on-Change Flag (RBIF Bit) .......... 92 TRISB Register .......................................................... 92 Postscaler Timer2 ...................................................................... 111 WDT Assignment (PSA Bit) ...................................... 103 Rate Select (T0PS2:T0PS0 Bits) ..................... 103 Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 Power Managed Modes ..................................................... 19 Entering ...................................................................... 20 IDLE Modes ............................................................... 21 RUN Modes ............................................................... 26 Selecting .................................................................... 19 SLEEP Mode ............................................................. 21 Summary (table) ........................................................ 19 Wake from .................................................................. 28 Power-on Reset (POR) .............................................. 34, 171 Power-up Delays ................................................................ 18 Power-up Timer (PWRT) .......................................18, 34, 171 Prescaler Capture .................................................................... 119 Timer0 ...................................................................... 103 Assignment (PSA Bit) ...................................... 103 Rate Select (T0PS2:T0PS0 Bits) ..................... 103 Timer2 ...................................................................... 121 PRO MATE II Universal Device Programmer .................. 233 Product Identification System ........................................... 287 Program Counter PCL Register .............................................................. 46 PCLATH Register ...................................................... 46 PCLATU Register ...................................................... 46 Program Memory Instructions in ............................................................. 48 Interrupt Vector .......................................................... 43 Map and Stack for PIC18F1220 ................................. 43 Map and Stack for PIC18F1320 ................................. 43 RESET Vector ............................................................ 43 Program Verification and Code Protection ....................... 185 Associated Registers ............................................... 185 Configuration Register ............................................. 188 Data EEPROM ......................................................... 188 Program Memory ..................................................... 186 Programming, Device Instructions ................................... 189 PUSH ............................................................................... 218 PUSH and POP Instructions .............................................. 45 PWM (CCP Module) CCPR1H:CCPR1L Registers ................................... 121 Duty Cycle ................................................................ 121 Example Frequencies/Resolutions .......................... 121 Period ....................................................................... 121 TMR2 to PR2 Match ........................................ 111, 121 PWM (ECCP Module) ...................................................... 121 Associated Registers ............................................... 132 Direction Change in Full-Bridge Output Mode .................................................... 126 Effects of a RESET .................................................. 131 Enhanced PWM Auto Shutdown .............................. 128 Full-Bridge Application Example .............................. 126 Full-Bridge PWM Output Diagram ........................... 125 Half-Bridge Output Diagram ..................................... 124 Half-Bridge Output Mode Applications Example ....................................... 124 Operation in Low Power Modes ............................... 131 Output Configurations .............................................. 121 Output Relationships (Active High) .......................... 122 Output Relationships (Active Low) ........................... 123 Programmable Deadband Delay .............................. 128 PWM Direction Change at Near 100% Duty Cycle Diagram ......................................... 127 PWM Direction Change Diagram ............................. 127 Setup for PWM Operation ........................................ 131 Start-up Considerations ........................................... 130 2002 Microchip Technology Inc. Q Q Clock ............................................................................ 121 R RAM. See Data Memory RCALL ............................................................................. 219 RCIO Oscillator .................................................................. 13 RCON Register Bit Status During Initialization .................................... 35 RCSTA Register SPEN Bit .................................................................. 133 Register File ....................................................................... 49 Register File Summary ...................................................... 52 Registers ADCON0 (A/D Control 0) ......................................... 155 ADCON1 (A/D Control 1) ......................................... 156 ADCON2 (A/D Control 2) ......................................... 157 BAUDCTL (Baud Rate Control) ............................... 136 CCP1CON (Enhanced CCP1 Control) .................... 117 CONFIG1H (Configuration 1 High) .......................... 172 CONFIG2H (Configuration 2 High) .......................... 174 CONFIG2L (Configuration 2 Low) ........................... 173 CONFIG3H (Configuration 3 High) .......................... 175 CONFIG4L (Configuration 4 Low) ........................... 175 CONFIG5H (Configuration 5 High) .......................... 176 CONFIG5L (Configuration 5 Low) ........................... 176 CONFIG6H (Configuration 6 High) .......................... 177 CONFIG6L (Configuration 6 Low) ........................... 177 CONFIG7H (Configuration 7 High) .......................... 178 CONFIG7L (Configuration 7 Low) ........................... 178 DEVID1 (Device ID 1) .............................................. 179 DEVID2 (Device ID 2) .............................................. 179 ECCPAS (ECCP Auto Shutdown Control) ............... 129 EECON1 (Data EEPROM Control 1) ....................61, 70 INTCON (Interrupt Control) ........................................ 77 INTCON2 (Interrupt Control 2) ................................... 78 INTCON3 (Interrupt Control 3) ................................... 79 IPR1 (Peripheral Interrupt Priority 1) ......................... 84 IPR2 (Peripheral Interrupt Priority 2) ......................... 85 LVDCON (LVD Control) ........................................... 167 OSCCON (Oscillator Control) .................................... 17 OSCTUNE (Oscillator Tuning) ................................... 15 PIE1 (Peripheral Interrupt Enable 1) .......................... 82 PIE2 (Peripheral Interrupt Enable 2) .......................... 83 PIR1 (Peripheral Interrupt Request (Flag) 1) ............. 80 PIR2 (Peripheral Interrupt Request (Flag) 2) ............. 81 PWM1CON (PWM Configuration) ........................... 128 RCON (Register Control) ........................................... 86 RCON (RESET Control) ............................................ 58 RCSTA (Receive Status and Control) ..................... 135 STATUS .................................................................... 57 STKPTR (Stack Pointer) ............................................ 45 T0CON (Timer0 Control) ......................................... 101 T1CON (Timer 1 Control) ........................................ 105 T2CON (Timer 2 Control) ........................................ 111 T3CON (Timer3 Control) ......................................... 113 TXSTA (Transmit Status and Control) ..................... 134 WDTCON (Watchdog Timer Control) ...................... 180 RESET ................................................................ 33, 171, 219 RETFIE ............................................................................ 220 RETLW ............................................................................ 220 RETURN .......................................................................... 221 Preliminary DS39605B-page 281 PIC18F1220/1320 Return Address Stack ........................................................ 44 and Associated Registers .......................................... 44 Return Stack Pointer (STKPTR) ........................................ 44 Revision History ............................................................... 273 RLCF ................................................................................ 221 RLNCF ............................................................................. 222 RRCF ............................................................................... 222 RRNCF ............................................................................. 223 S SETF ................................................................................ 223 SLEEP .............................................................................. 224 OSC1 and OSC2 Pin States ...................................... 18 Software Simulator (MPLAB SIM) .................................... 232 Special Event Trigger. See Compare Special Features of the CPU ............................................ 171 Configuration Registers .................................... 172-178 Special Function Registers ................................................ 51 Map ............................................................................ 51 SSP TMR2 Output for Clock Shift .................................... 112 Stack Full/Underflow Resets .............................................. 45 SUBFWB .......................................................................... 224 SUBLW ............................................................................ 225 SUBWF ............................................................................ 225 SUBWFB .......................................................................... 226 SWAPF ............................................................................ 226 T TABLAT Register ............................................................... 62 Table Pointer Operations (table) ........................................ 62 TBLPTR Register ............................................................... 62 TBLRD ............................................................................. 227 TBLWT ............................................................................. 228 Time-out Sequence ............................................................ 34 Timer0 .............................................................................. 101 16-bit Mode Timer Reads and Writes ...................... 103 Associated Registers ............................................... 103 Clock Source Edge Select (T0SE Bit) ...................... 103 Clock Source Select (T0CS Bit) ............................... 103 Operation ................................................................. 103 Overflow Interrupt ..................................................... 103 Prescaler. See Prescaler, Timer0 Switching Prescaler Assignment .............................. 103 Timer1 .............................................................................. 105 16-bit Read/Write Mode ........................................... 108 Associated Registers ............................................... 109 Interrupt .................................................................... 107 Operation ................................................................. 106 Oscillator .......................................................... 105, 107 Oscillator Layout Considerations ............................. 107 Overflow Interrupt ..................................................... 105 Resetting, Using a Special Event Trigger Output (CCP) ....................................... 108 Special Event Trigger (CCP) .................................... 119 TMR1H Register ...................................................... 105 TMR1L Register ....................................................... 105 Use as a Real-Time Clock ....................................... 108 DS39605B-page 282 Timer2 .............................................................................. 111 Associated Registers ............................................... 112 Operation ................................................................. 111 Postscaler. See Postscaler, Timer2 PR2 Register ....................................................111, 121 Prescaler. See Prescaler, Timer2 SSP Clock Shift ....................................................... 112 TMR2 Register ......................................................... 111 TMR2 to PR2 Match Interrupt ...................111, 112, 121 Timer3 .............................................................................. 113 Associated Registers ............................................... 116 Operation ................................................................. 114 Oscillator ...........................................................113, 116 Overflow Interrupt .............................................113, 116 Special Event Trigger (CCP) ................................... 116 TMR3H Register ...................................................... 113 TMR3L Register ....................................................... 113 Timing Diagrams A/D Conversion ........................................................ 262 Asynchronous Reception ......................................... 146 Asynchronous Transmission .................................... 143 Asynchronous Transmission (Back to Back) ........... 143 Auto Wake-up Bit (WUE) During Normal Operation 147 Auto Wake-up Bit (WUE) During SLEEP ................. 147 Brown-out Reset (BOR) ........................................... 256 Capture/Compare/PWM (All CCP Modules) ............ 259 CLKO and I/O .......................................................... 255 Clock/Instruction Cycle .............................................. 47 External Clock (All Modes except PLL) ................... 253 Fail-Safe Clock Monitor ........................................... 183 Low Voltage Detect .................................................. 168 PWM Auto Shutdown (PRSEN = 0, Auto Restart Disabled) ..................................... 130 PWM Auto Shutdown (PRSEN = 1, Auto Restart Enabled) ..................................... 130 RESET, Watchdog Timer (WDT), Oscillator Start-up Timer (OST) and Power-up Timer (PWRT) ................................. 256 Send Break Character Sequence ............................ 148 Slow Rise Time (MCLR Tied to VDD, VDD Rise > TPWRT) ............................................ 41 Synchronous Reception (Master Mode, SREN) ...... 151 Synchronous Transmission ..................................... 149 Synchronous Transmission (Through TXEN) .......... 150 Time-out Sequence on POR w/ PLL Enabled (MCLR Tied to VDD) ........................................... 41 Time-out Sequence on Power-up (MCLR Not Tied to VDD) Case 1 ........................ 40 Time-out Sequence on Power-up (MCLR Not Tied to VDD) Case 2 ........................ 40 Time-out Sequence on Power-up (MCLR Tied to VDD, VDD Rise TPWRT) .............. 40 Timer0 and Timer1 External Clock .......................... 257 Transition for Entry to SEC_IDLE Mode .................... 24 Transition for Entry to SEC_RUN Mode .................... 26 Transition for Entry to SLEEP Mode .......................... 22 Transition for Two-Speed Start-up (INTOSC to HSPLL) ........................................ 181 Transition for Wake from RC_RUN Mode (RC_RUN to PRI_RUN) ..................................... 25 Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 Transition for Wake from SEC_RUN Mode (Secondary Clock to HSPLL) ............................. 24 Transition for Wake from SLEEP (HSPLL) ................ 22 Transition Timing For Wake from PRI_IDLE Mode ................................................. 23 Transition Timing to PRI_IDLE Mode ........................ 23 Transition to RC_IDLE Mode ..................................... 25 Transition to RC_RUN Mode ..................................... 27 USART Synchronous Receive (Master/Slave) .................................................. 260 USART SynchronousTransmission (Master/Slave) .................................................. 260 Timing Diagrams and Specifications ................................ 253 Capture/Compare/PWM Requirements (All CCP Modules) ........................................... 259 CLKO and I/O Requirements ................................... 255 DC Characteristics - Internal RC Accuracy .............. 254 External Clock Requirements .................................. 253 PLL Clock (VDD = 4.2 to 5.5V) ................................. 254 RESET, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-out Reset Requirements ....................... 257 Timer0 and Timer1 External Clock Requirements ................................................... 258 USART Synchronous Receive Requirements ......... 260 USART Synchronous Transmission Requirements ................................................... 260 Top-of-Stack Access .......................................................... 44 TSTFSZ ............................................................................ 229 Two-Speed Start-up ................................................. 171, 181 Two-Word Instructions ....................................................... 48 Example Cases .......................................................... 48 TXSTA Register BRGH Bit ................................................................. 137 U USART Asynchronous Mode ................................................ 142 12-bit Break Transmit and Receive ................. 148 Associated Registers, Receive ........................ 146 Associated Registers, Transmit ....................... 144 Auto Wake-up on Sync Break ......................... 147 Receiver .......................................................... 145 Setting up 9-bit Mode with Address Detect ..... 145 Transmitter ...................................................... 142 Baud Rate Generator (BRG) ................................... 137 Associated Registers ....................................... 138 Auto Baud Rate Detect .................................... 141 Baud Rate Error, Calculating ........................... 138 Baud Rates, Asynchronous Modes ................. 138 High Baud Rate Select (BRGH Bit) ................. 137 Power Managed Mode Operation .................... 137 Sampling .......................................................... 137 Serial Port Enable (SPEN Bit) ................................. 133 Synchronous Master Mode ...................................... 149 Associated Registers, Reception ..................... 152 Associated Registers, Transmit ....................... 150 Reception ........................................................ 151 Transmission ................................................... 149 Synchronous Slave Mode ........................................ 153 Associated Registers, Receive ........................ 154 Associated Registers, Transmit ....................... 153 Reception ........................................................ 154 Transmission ................................................... 153 W Watchdog Timer (WDT) ............................................171, 180 Associated Registers ............................................... 181 Control Register ....................................................... 180 During Oscillator Failure .......................................... 182 Programming Considerations .................................. 180 WWW, On-Line Support ...................................................... 4 X XORLW ............................................................................ 229 XORWF ........................................................................... 230 2002 Microchip Technology Inc. Preliminary DS39605B-page 283 PIC18F1220/1320 NOTES: DS39605B-page 284 Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 ON-LINE SUPPORT Microchip provides on-line support on the Microchip World Wide Web site. The web site is used by Microchip as a means to make files and information easily available to customers. To view the site, the user must have access to the Internet and a web browser, such as Netscape(R) or Microsoft(R) Internet Explorer. Files are also available for FTP download from our FTP site. Connecting to the Microchip Internet Web Site SYSTEMS INFORMATION AND UPGRADE HOT LINE The Systems Information and Upgrade Line provides system users a listing of the latest versions of all of Microchip's development systems software products. Plus, this line provides information on how customers can receive the most current upgrade kits.The Hot Line Numbers are: 1-800-755-2345 for U.S. and most of Canada, and 1-480-792-7302 for the rest of the world. The Microchip web site is available at the following URL: 092002 www.microchip.com The file transfer site is available by using an FTP service to connect to: ftp://ftp.microchip.com The web site and file transfer site provide a variety of services. Users may download files for the latest Development Tools, Data Sheets, Application Notes, User's Guides, Articles and Sample Programs. A variety of Microchip specific business information is also available, including listings of Microchip sales offices, distributors and factory representatives. Other data available for consideration is: * Latest Microchip Press Releases * Technical Support Section with Frequently Asked Questions * Design Tips * Device Errata * Job Postings * Microchip Consultant Program Member Listing * Links to other useful web sites related to Microchip Products * Conferences for products, Development Systems, technical information and more * Listing of seminars and events 2002 Microchip Technology Inc. Preliminary DS39605B-page 285 PIC18F1220/1320 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: Technical Publications Manager RE: Reader Response Total Pages Sent ________ From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Device: PIC18F1220/1320 Y N Literature Number: DS39605B Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS39605B-page 286 Preliminary 2002 Microchip Technology Inc. PIC18F1220/1320 PIC18F1220/1320 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. - PART NO. Device Device X Temperature Range /XX XXX Package Pattern PIC18F1220/1320(1), PIC18F1220/1320(2); VDD range 4.2V to 5.5V Examples: a) b) PIC18LF1320 - I/P 301 = Industrial temp., PDIP package, Extended VDD limits, QTP pattern #301. PIC18LF1220 - I/SO = Industrial temp., SOIC package, Extended VDD limits. PIC18LF1220/1320(1), PIC18LF1220/1320(2); VDD range 2.5V to 5.5V Temperature Range I = -40C to +85C (Industrial) Package SO = SOIC P = PDIP SS = SSOP ML = QFN Pattern QTP, SQTP, Code or Special Requirements (blank otherwise) Note 1: F = Standard Voltage range LF = Wide Voltage Range 2: T = in tape and reel - SOIC package only Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. 2. 3. Your local Microchip sales office The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products. 2002 Microchip Technology Inc. Preliminary DS39605B-page 287 WORLDWIDE SALES AND SERVICE AMERICAS ASIA/PACIFIC Corporate Office Australia 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: 480-792-7627 Web Address: http://www.microchip.com Microchip Technology Australia Pty Ltd Suite 22, 41 Rawson Street Epping 2121, NSW Australia Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 Rocky Mountain China - Beijing 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7966 Fax: 480-792-4338 Atlanta 500 Sugar Mill Road, Suite 200B Atlanta, GA 30350 Tel: 770-640-0034 Fax: 770-640-0307 Boston 2 Lan Drive, Suite 120 Westford, MA 01886 Tel: 978-692-3848 Fax: 978-692-3821 Chicago 333 Pierce Road, Suite 180 Itasca, IL 60143 Tel: 630-285-0071 Fax: 630-285-0075 Dallas 4570 Westgrove Drive, Suite 160 Addison, TX 75001 Tel: 972-818-7423 Fax: 972-818-2924 Detroit Tri-Atria Office Building 32255 Northwestern Highway, Suite 190 Farmington Hills, MI 48334 Tel: 248-538-2250 Fax: 248-538-2260 Kokomo 2767 S. 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No. 6 Chaoyangmen Beidajie Beijing, 100027, No. China Tel: 86-10-85282100 Fax: 86-10-85282104 China - Chengdu Microchip Technology Consulting (Shanghai) Co., Ltd., Chengdu Liaison Office Rm. 2401, 24th Floor, Ming Xing Financial Tower No. 88 TIDU Street Chengdu 610016, China Tel: 86-28-86766200 Fax: 86-28-86766599 China - Fuzhou Microchip Technology Consulting (Shanghai) Co., Ltd., Fuzhou Liaison Office Unit 28F, World Trade Plaza No. 71 Wusi Road Fuzhou 350001, China Tel: 86-591-7503506 Fax: 86-591-7503521 China - Shanghai Microchip Technology Consulting (Shanghai) Co., Ltd. Room 701, Bldg. B Far East International Plaza No. 317 Xian Xia Road Shanghai, 200051 Tel: 86-21-6275-5700 Fax: 86-21-6275-5060 China - Shenzhen Microchip Technology Consulting (Shanghai) Co., Ltd., Shenzhen Liaison Office Rm. 1315, 13/F, Shenzhen Kerry Centre, Renminnan Lu Shenzhen 518001, China Tel: 86-755-82350361 Fax: 86-755-82366086 China - Hong Kong SAR Microchip Technology Hongkong Ltd. Unit 901-6, Tower 2, Metroplaza 223 Hing Fong Road Kwai Fong, N.T., Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 India Microchip Technology Inc. India Liaison Office Divyasree Chambers 1 Floor, Wing A (A3/A4) No. 11, O'Shaugnessey Road Bangalore, 560 025, India Tel: 91-80-2290061 Fax: 91-80-2290062 Japan Microchip Technology Japan K.K. Benex S-1 6F 3-18-20, Shinyokohama Kohoku-Ku, Yokohama-shi Kanagawa, 222-0033, Japan Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Korea Microchip Technology Korea 168-1, Youngbo Bldg. 3 Floor Samsung-Dong, Kangnam-Ku Seoul, Korea 135-882 Tel: 82-2-554-7200 Fax: 82-2-558-5934 Singapore Microchip Technology Singapore Pte Ltd. 200 Middle Road #07-02 Prime Centre Singapore, 188980 Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan Microchip Technology (Barbados) Inc., Taiwan Branch 11F-3, No. 207 Tung Hua North Road Taipei, 105, Taiwan Tel: 886-2-2717-7175 Fax: 886-2-2545-0139 EUROPE Austria Microchip Technology Austria GmbH Durisolstrasse 2 A-4600 Wels Austria Tel: 43-7242-2244-399 Fax: 43-7242-2244-393 Denmark Microchip Technology Nordic ApS Regus Business Centre Lautrup hoj 1-3 Ballerup DK-2750 Denmark Tel: 45 4420 9895 Fax: 45 4420 9910 France Microchip Technology SARL Parc d'Activite du Moulin de Massy 43 Rue du Saule Trapu Batiment A - ler Etage 91300 Massy, France Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany Microchip Technology GmbH Steinheilstrasse 10 D-85737 Ismaning, Germany Tel: 49-89-627-144 0 Fax: 49-89-627-144-44 Italy Microchip Technology SRL Centro Direzionale Colleoni Palazzo Taurus 1 V. Le Colleoni 1 20041 Agrate Brianza Milan, Italy Tel: 39-039-65791-1 Fax: 39-039-6899883 United Kingdom Microchip Ltd. 505 Eskdale Road Winnersh Triangle Wokingham Berkshire, England RG41 5TU Tel: 44 118 921 5869 Fax: 44-118 921-5820 10/18/02 DS39605B-page 288 Preliminary 2002 Microchip Technology Inc.