Simplified Application Diagram
33580
HS0
HS1
GND
GND FSI
CSNS
HS2
HS3
MCU
SCLK
LOAD 0
LOAD 1
LOAD 2
LOAD 3
SCLK
IN0I/O
IN1
IN2
IN3
I/O
SI
SI SO
SO
I/O
A/D
VPWR
VDD
VDD VPWR
WAKE
I/O
I/O
VDD
VDD
CS
CS
RST
I/O FS
I/O
VPWR
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
This document contains information on a product under development.
Motorola reserves the right to change or discontinue this product without notice.
© Motorola, Inc. 2004
Document order number: MC33580
Rev 1.0, 09/2004
33580
Preliminary Information
Quad High-Side Switch
(Quad 15 mΩ)
The 33580 is one in a family of devices designed for low-voltage automotive
and industrial lighting and motor control applications. Its four low RDS(ON)
MOSFETs (four 15 mΩ) can control the high sides of four separate resistive or
inductive loads.
Programming, control, and diagnostics are accomplished using a 16-bit SPI
interface. Additionally, each output has its own parallel input for pulse-width
modulation (PWM) control if desired. The 33580 allows the user to program
via the SPI the fault current trip levels and duration of acceptable lamp inrush
or motor stall intervals. Such programmability allows tight control of fault
currents and can protect wiring harnesses and circuit boards as well as loads.
The 33580 is packaged in a power-enhanced 12x 12 nonleaded Power
QFN package with exposed tabs.
Features
•Quad 15 mΩ High-Side Switches (at 25°C)
• Operating Voltage Range of 6.0 V to 27 V with Standby Current < 5.0 µA
• SPI Control of Overcurrent Limit, Overcurrent Fault Blanking Time,
Output OFF Open Load Detection, Output ON/OFF Control, Watchdog
Timeout, Slew Rates, and Fault Status Reporting
• SPI Status Reporting of Overcurrent, Open and Shorted Loads,
Overtemperature, Undervoltage and Overvoltage Shutdown, Fail-Safe
Terminal Status, and Program Status
• Analog Current Feedback with Selectable Ratio
• Enhanced -16 V Reverse Polarity VPWR Protection
33580 Simplified Application Diagram
ORDERING INFORMATION
Device Temperature
Range (TA)Package
PC33580PNA/R2 -40°C to 125°C24 PQFN
QUAD HIGH-SIDE SWITCH
15 mΩ
PNA SUFFIX
CASE 1593-02
24-TERMINAL PQFN (12 x 12)
Bottom View
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33580 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
2
Figure 1. 33580 Simplified Internal Block Diagram
GND
Programmable
Watchdog
310 ms–2500 ms
Overtemperature
Detection
Logic
SPI
3.0 MHz
Selectable Over-
HS[0:3]: 4.8 A–18.2 A
Selectable Overcurrent
Internal
Regulator
Selectable Slew
Rate Gate Drive
Over/Undervoltage
Protection
HS0
VPWR
VDD
CS
SCLK
SO
SI
RST
WAKE
FS
IN0
FSI
IN3
HS1
HS0
HS1
HS2
HS3
HS2
HS3
IN1
IN2
current Low Detection
HS[0:3]: 70 A or 100 A
Selectable Output Current
HS[0:3]: 1/13000 or 1/40000
CSNS
Recopy (Analog MUX)
VIC
VIC
IDWN
IUP
IDWN
RDWN
Open Load
Detection
High Detection
Selectable Over-
current Low Detection
0.15 ms–155 ms
Blanking Time
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33580
3
Transparent Top View of Package
13
24
12 1098 7654 32111
23
22
19 20 21
16
17
18
15
14
SO
GND
HS3
HS1 NC HS0
HS2
GND
FSI
VDD
SI
SCLK
CS
RST
WAKE
FS
IN3
IN2
NC
IN1
IN0
CSNS
GND
VPWR
TERMINAL DEFINITIONS
Functional descriptions of many of these terminals can be found in the System/Application Information section beginning on
page 16.
Terminal Terminal Name Formal Name Definition
1 CSNS Output Current
Monitoring
The Current Sense terminal sources a current proportional to the designated
HS0:HS3 output. That current is fed into a ground-referenced resistor and its voltage
is monitored by an MCU's A/D. The output to be monitored is selected via the SPI. This
terminal can be tri-stated through SPI.
2
3
5
6
IN0
IN1
IN2
IN3
Serial Inputs The IN0:IN3 high-side input terminals are used to directly control HS0:HS3 high-side
output terminals, respectively. An SPI register determines if each input is activated or
if the input logic state is ORed or ANDed with the SPI instruction. These terminals are
to be driven with 5.0 V CMOS levels, and they have an active internal pulldown current
source.
4, 20 NC No Connect These terminals may not be connected.
7FS Fault Status
(Active Low)
This terminal is an open drain configured output requiring an external pullup resistor
to VDD for fault reporting. If a device fault condition is detected, this terminal is active
LOW. Specific device diagnostic faults are reported via the SPI SO terminal.
8 WAKE Wake This input terminal controls the device mode and watchdog timeout feature if enabled.
An internal clamp protects this terminal from high damaging voltages when the output
is current limited with an external resistor. This input has a passive internal pulldown.
9RST Reset This input terminal is used to initialize the device configuration and fault registers, as
well as place the device in a low-current sleep mode. The terminal also starts the
watchdog timer when transitioning from logic [0] to logic [1]. This terminal should not
be allowed to be logic [1] until VDD is in regulation. This terminal has a passive internal
pulldown.
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33580 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
4
10 CS Chip Select
(Active Low)
This input terminal is connected to a chip select output of a master microcontroller
(MCU). The MCU determines which device is addressed (selected) to receive data by
pulling the CS terminal of the selected device logic LOW, thereby enabling SPI
communication with the device. Other unselected devices on the serial link having
their CS terminals pulled up logic HIGH disregard the SPI communication data sent.
This terminal has an active internal pullup current source and requires CMOS logic
levels.
11 SCLK Serial Clock This input terminal is connected to the MCU providing the required bit shift clock for
SPI communication. It transitions one time per bit transferred at an operating
frequency, fSPI, defined by the communication interface. The 50 percent duty cycle
CMOS level serial clock signal is idle between command transfers. The signal is used
to shift data into and out-of the device. This terminal has an active internal pulldown
current source.
12 SI Serial Input This terminal is a command data input terminal connected to the SPI Serial Data
Output of the MCU or to the SO terminal of the previous device of a daisy-chain of
devices. The input requires CMOS logic level signals and incorporates an internal
active pulldown. Device control is facilitated by the input's receiving the MSB first of a
serial 8-bit control command. The MCU ensures data is available upon the falling edge
of SCLK. The logic state of SI present upon the rising edge of SCLK loads that bit
command into the internal command shift register. This terminal has an active internal
pulldown current source.
13 VDD Digital Drain Voltage
(Power)
This terminal is an external voltage input terminal used to supply power to the SPI
circuit. In the event VDD is lost, an internal supply provides power to a portion of the
logic, ensuring limited functionality of the device.
14, 17, 23 GND Ground These terminals are the ground for the logic and analog circuitry of the device.
15 VPWR Positive Power Supply This terminal connects to the positive power supply and is the source of operational
power for the device. The VPWR contact is the backside surface mount tab of the
package.
16 SO Serial Output This output terminal is connected to the SPI Serial Data Input terminal of the MCU or
to the SI terminal of the next device of a daisy-chain of devices. This output will remain
tri-stated (high-impedance OFF condition) so long as the CS terminal of the device is
logic HIGH. SO is only active when the CS terminal of the device is asserted logic
LOW. The generated SO output signals are CMOS logic levels. SO output data is
available on the falling edge of SCLK and transitions immediately on the rising edge
of SCLK.
18
19
21
22
HS3
HS1
HS0
HS2
High-Side Outputs Protected 15 mΩ high-side power output terminals to the load.
24 FSI Fail-Safe Input The value of the resistance connected between this terminal and ground determines
the state of the outputs after a Watchdog timeout occurs. Depending on the resistance
value, either all outputs are OFF or the output HSO only is ON. If the FSI terminal is
left to float up to a logic [1] level, then the outputs HS0 and HS2 will turn ON when in
the Fail-Safe state. When the FSI terminal is connected to GND, the Watchdog circuit
and Fail-Safe operation are disabled. This terminal incorporates an active internal
pullup current source.
TERMINAL DEFINITIONS (continued)
Functional descriptions of many of these terminals can be found in the System/Application Information section beginning on
page 16.
Terminal Terminal Name Formal Name Definition
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33580
5
MAXIMUM RATINGS
All voltages are with respect to ground unless otherwise noted.
Rating Symbol Value Unit
ELECTRICAL RATINGS
Operating Voltage Range
Steady-State
VPWR(SS)
-16 to 41
V
VDD Supply Voltage VDD 0 to 5.5 V
Input/Output Voltage (Note 1) VIN[0:3], RST, FSI,
CSNS, SI, SCLK,
CS, FS
-0.3 to 7.0 V
SO Output Voltage (Note 1) VSO -0.3 to VDD+0.3 V
WAKE Input Clamp Current ICL(WAKE) 2.5 mA
CSNS Input Clamp Current ICL(CSNS) 10 mA
Output Current (Note 2) I
HS[0:3] 22.8 A
Output Clamp Energy (Note 3) E
CL[0:3] TBD J
ESD Voltage
Human Body Model (Note 4)
Machine Model (Note 5)
VESD1
VESD2
±2000
±200
V
THERMAL RATINGS
Operating Temperature
Ambient
Junction
TA
TJ
-40 to 125
-40 to 150
°C
Storage Temperature TSTG -55 to 150 °C
Thermal Resistance (Note 6)
Junction to Case
Junction to Ambient
RθJC
RθJA
<1.0
TBD
°C/W
Peak Terminal Reflow Temperature During Solder Mounting (Note 7) T
SOLDER 240 °C
Notes
1. Exceeding voltage limits on IN[0:3], RST, FSI, CSNS, SI, SO, SCLK, CS, or FS terminals may cause a malfunction or permanent damage
to the device.
2. Continuous high-side output current rating so long as maximum junction temperature is not exceeded. Calculation of maximum output
current using package thermal resistance is required.
3. Active clamp energy using single-pulse method (L = 16 mH, RL = 0 Ω, VPWR = 12 V, TJ = 150°C).
4. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω).
5. ESD2 testing is performed in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 Ω) and in accordance with the system module
specification with a capacitor > 0.01 µF connected from high-side outputs to GND.
6. Device mounted on a 2s2p test board per JEDEC JESD51-2.
7. Terminal soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits
may cause malfunction or permanent damage to the device.
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33580 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
6
STATIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5V, 6.0V ≤ VPWR ≤ 27 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical
values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic Symbol Min Typ Max Unit
POWER INPUT
Battery Supply Voltage Range
Fully Operational
VPWR
6.0 – 27
V
VPWR Operating Supply Current
Outputs ON, HS[0:3] open
IPWR(ON)
––20
mA
VPWR Supply Current
Outputs OFF, Open Load Detection Disabled, WAKE > 0.7 VDD,
RST = VLOGIC HIGH
IPWR(SBY)
––5.0
mA
Sleep State Supply Current (VPWR < 14 V, RST < 0.5 V, WAKE < 0.5 V)
TJ = 25°C
TJ = 85°C
IPWR(SLEEP)
–
–
–
–
10
50
µA
VDD Supply Voltage VDD(ON) 4.5 5.0 5.5 V
VDD Supply Current
No SPI Communication
3.0 MHz SPI Communication
IDD(ON)
–
–
–
–
1.0
5.0
mA
VDD Sleep State Current IDD(SLEEP) ––5.0µA
Overvoltage Shutdown Threshold VPWR(OV) 28 32 36 V
Overvoltage Shutdown Hysteresis VPWR(OVHYS) 0.2 0.8 1.5 V
Undervoltage Shutdown Threshold (Note 8) V
PWR(UV) 4.75 5.25 5.75 V
Undervoltage Hysteresis (Note 9) VPWR(UVHYS) –0.25–V
Undervoltage Power-ON Reset VPWR(UVPOR) ––5.0V
Notes
8. Output will automatically recover to instructed state when VPWR voltage is restored to normal so long as the VPWR degradation level did not
go below the undervoltage power-ON reset threshold. This applies to all internal device logic that is supplied by VPWR and assumes that the
external VDD supply is within specification.
9. This applies when the undervoltage fault is not latched (IN = 0).
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33580
7
STATIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted.
Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic Symbol Min Typ Max Unit
OUTPUTS HS0 TO HS3
Output Drain-to-Source ON Resistance (IHS = 10 A, TJ = 25°C)
VPWR = 6.0 V
VPWR = 10 V
VPWR = 13 V
RDS(ON)
–
–
–
–
–
–
23
15
15
mΩ
Output Drain-to-Source ON Resistance (IHS = 10 A A, TJ = 150°C)
VPWR = 6.0 V
VPWR = 10 V
VPWR = 13 V
RDS(ON)
–
–
–
–
–
–
38
25.5
25.5
mΩ
Output Source-to-Drain ON Resistance (Note 10)
IHS = 10 A, TJ = 25°C, VPWR = -12 V
RDS(ON)
––30
mΩ
Output Overcurrent High Detection Levels (9.0 V < VPWR < 16 V)
SOCH = 0
SOCH = 1
IOCH0
IOCH1
80
56
100
70
120
84
A
Overcurrent Low Detection Levels (SOCL[2:0], 9.0 V < VPWR < 16 V)
000
001
010
011
100
101
110
111
IOCL0
IOCL1
IOCL2
IOCL3
IOCL4
IOCL5
IOCL6
IOCL7
14.6
13
11.5
10
8.4
6.9
5.4
3.8
18.2
16.3
14.4
12.5
10.5
8.6
6.7
4.8
22.8
20.4
18
15.7
13.2
10.8
8.4
6
A
Current Sense Ratio (9.0 V < VPWR < 16 V, CSNS < 4.5 V)
DICR D2 = 0
DICR D2 = 1
CSR0
CSR1
–
–
1/13000
1/40000
–
–
–
Current Sense Ratio (CSR0) Accuracy
Output Current
2.0 A
5.0 A
10 A
12.5 A
15 A
20 A
CSR0_ACC
-20
-14
-13
-12
-13
-13
–
–
–
–
–
–
20
14
13
12
13
13
%
Notes
10. Source-Drain ON Resistance (Reverse Drain-to-Source ON Resistance) with negative polarity VPWR.
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33580 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
8
STATIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5V, 6.0V ≤ VPWR ≤ 27 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted.
Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic Symbol Min Typ Max Unit
OUTPUTS HS0 TO HS3 (continued)
Current Sense Ratio (CSR1) Accuracy
Output Current
5.0 A
10 A
12.5 A
15 A
20 A
25 A
CSR1_ACC
-25
-19
-18
-17
-18
-18
–
–
–
–
–
–
25
19
18
17
18
18
%
Current Sense Clamp Voltage
CSNS Open; IHS[0:3] =22 A
VCL(CSNS)
4.5 6.0 7.0
V
Open Load Detection Current (Note 11) IOLDC 30 – 100 µA
Output Fault Detection Threshold
Output Programmed OFF
VOFD(THRES)
2.0 3.0 4.0
V
Output Negative Clamp Voltage
0.5 A < IHS[0:3] < 2.0 A, Output OFF
VCL
-20 – –
V
Overtemperature Shutdown (Note 12) TSD 155 175 190 °C
Overtemperature Shutdown Hysteresis (Note 12) TSD(HYS) 5.0 – 20 °C
Notes
11. Output OFF Open Load Detection Current is the current required to flow through the load for the purpose of detecting the existence of an
open load condition when the specific output is commanded OFF.
12. Guaranteed by process monitoring. Not production tested.
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33580
9
STATIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6 V ≤ VPWR ≤ 27 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical
values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic Symbol Min Typ Max Unit
CONTROL INTERFACE
Input Logic High Voltage (Note 13) VIH 0.7 VDD – – V
Input Logic Low Voltage (Note 13) VIL – – 0.2 VDD V
Input Logic Voltage Hysteresis (Note 13) VIN(HYS) 100 350 750 mV
Input Logic Pulldown Current (SCLK, SI, IN[0:3]) IDWN 5.0 –20 µA
RST Input Voltage Range VRST 4.5 5.0 5.5 V
SO, FS Tri-State Capacitance (Note 14) CSO – – 20 pF
Input Logic Pulldown Resistor (RST) and WAKE RDWN 100 200 400 kΩ
Input Capacitance (Note 15) CIN –4.0 12 pF
Wake Input Clamp Voltage (Note 16)
ICL(WAKE) < 2.5 mA
VCL(WAKE)
7.0 –14
V
Wake Input Forward Voltage
ICL(WAKE) = -2.5 mA
VF(WAKE)
-2.0 –-0.3
V
SO High-State Output Voltage
IOH = 1.0 mA
VSOH
0.8 VDD – –
V
FS, SO Low-State Output Voltage
IOL = -1.6 mA
VSOL
–0.2 0.4
V
SO Tri-State Leakage Current
CS > 0.7 VDD
ISO(LEAK)
-5.0 05.0
µA
Input Logic Pullup Current (Note 17)
CS, VIN > 0.7VDD
IUP
5.0 –20
µA
FSI Input terminal External Pulldown Resistance (Note 18)
FSI Disabled, HS[0:3] Indeterminate
FSI Enabled, HS[0:3] OFF
FSI Enabled, HS0 ON, HS[1:3] OFF
FSI Enabled, HS0 and HS2 ON, HS1 and HS3 OFF
RFS
RFSdis
RFSoffoff
RFSonoff
RFSonon
–
6.0
15
40
0
6.5
17
Infinite
1.0
7.0
19
–
kΩ
Notes
13. Upper and lower logic threshold voltage range applies to SI, CS, SCLK, RST, IN[0:3], and WAKE input signals. The WAKE and RST signals
may be supplied by a derived voltage referenced to VPWR.
14. Parameter is guaranteed by process monitoring but is not production tested.
15. Input capacitance of SI, CS, SCLK, RST, and WAKE. This parameter is guaranteed by process monitoring but is not production tested.
16. The current must be limited by a series resistance when using voltages > 7.0 V.
17. Pullup current is with CS OPEN. CS has an active internal pullup to VDD.
18. The selection of the RFS must take into consideration the tolerance, temperature coefficient and lifetime duration to assure that the
resistance value will always be within the desired (specified) range.
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33580 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
10
DYNAMIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical
values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic Symbol Min Typ Max Unit
POWER OUTPUT TIMING HS0 TO HS3
Output Rising Slow Slew Rate A (DICR D3 = 0) (Note 19)
9.0 V < VPWR < 16 V
SRRA_SLOW
0.15 0.45 0.75
V/µs
Output Rising Slow Slew Rate B (DICR D3 = 0) (Note 20)
9.0 V < VPWR < 16 V
SRRB_SLOW
0.025 0.075 0.225
V/µs
Output Rising Fast Slew Rate A (DICR D3 = 1) (Note 19)
9.0 V < VPWR < 16 V
SRRA_FAST
0.3 0.75 2.25
V/µs
Output Rising Fast Slew Rate B (DICR D3 = 1) (Note 20)
9.0 V < VPWR < 16 V
SRRB_FAST
0.025 0.075 0.225
V/µs
Output Falling Slow Slew Rate A (DICR D3 = 0) (Note 19)
9.0 V < VPWR < 16 V
SRFA_SLOW
0.15 0.45 0.75
V/µs
Output Falling Slow Slew Rate B (DICR D3 = 0) (Note 20)
9.0 V < VPWR < 16 V
SRFB_SLOW
0.025 0.075 0.225
V/µs
Output Falling Fast Slew Rate A (DICR D3 = 1) (Note 19)
9.0 V < VPWR < 16 V
SRFA_FAST
0.7 1.5 3.0
V/µs
Output Falling Fast Slew Rate B (DICR D3 = 1) (Note 20)
9.0 V < VPWR < 16 V
SRFB_FAST
0.05 0.262 1.4
V/µs
Output Turn-ON Delay Time in Fast/Slow Slew Rate (Note 21)
DICR = 0, DICR = 1
tDLY(ON)
2.0 20 130
µs
Output Turn-OFF Delay Time in Slow Slew Rate Mode (Note 22)
DICR = 0
tDLY_SLOW(OFF)
25 300 650
µs
Output Turn-OFF Delay Time in Fast Slew Rate Mode (Note 22)
DICR = 1
tDLY_FAST(OFF)
15 80 250
µs
Overcurrent Low Detection Blanking Time (OCLT[1:0])
00
01 (Note 23)
10
11
tOCL0
tOCL1
tOCL2
tOCL3
108
–
55
0.08
155
–
75
0.15
202
–
95
0.25
ms
Notes
19. Rise and Fall Slew Rates A measured across a 5.0 Ω resistive load at high-side output = 0.5 V to VPWR-3.5 V (see Figure 2, page 13). These
parameters are guaranteed by process monitoring.
20. Rise and Fall Slew Rates B measured across a 5.0 Ω resistive load at high-side output = 0.5 V to VPWR-3.5 V (see Figure 2). These
parameters are guaranteed by process monitoring.
21. Turn-ON delay time measured from rising edge of any signal (IN[0:3], SCLK, CS) that would turn the output ON to VHS[0:3] = 0.5 V with
RL=5.0Ω resistive load.
22. Turn-OFF delay time measured from falling edge of any signal (IN[0:3], SCLK, CS) that would turn the output OFF to VHS[0:3] = VPWR-0.5 V
with RL=5.0Ω resistive load.
23. This logical bit is not defined. Do not use.
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33580
11
POWER OUTPUT TIMING HS0 TO HS3 (continued)
Overcurrent High Detection Blanking Time tOCH 1.0 10 20 µs
CS to CSNS Valid Time (Note 24) tCNSVAL – – 10 µs
Watchdog Timeout (WD[1:0]) (Note 25)
00
01
10
11
tWDTO0
tWDTO1
tWDTO2
tWDTO3
496
248
2000
1000
620
310
2500
1250
806
403
3250
1625
ms
Notes
24. Time necessary for the CSNS to be with ±5% of the targeted value.
25. Watchdog timeout delay measured from the rising edge of WAKE or RST from a sleep state condition, to output turn-ON with the output
driven OFF and FSI floating. The values shown are for WDR setting of [00]. The accuracy of tWDTO is consistent for all configured watchdog
timeouts.
DYNAMIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical
values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic Symbol Min Typ Max Unit
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33580 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
12
DYNAMIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical
values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic Symbol Min Typ Max Unit
SPI INTERFACE CHARACTERISTICS
Maximum Frequency of SPI Operation fSPI – – 3.0 MHz
Required Low State Duration for RST (Note 26) tWRST –50 350 ns
Rising Edge of CS to Falling Edge of CS (Required Setup Time) (Note 27) tCS – – 300 ns
Rising Edge of RST to Falling Edge of CS (Required Setup Time) (Note 27) tENBL – – 5.0 µs
Falling Edge of CS to Rising Edge of SCLK (Required Setup Time) (Note 27) tLEAD –50 167 ns
Required High State Duration of SCLK (Required Setup Time) (Note 27) tWSCLKh – – 167 ns
Required Low State Duration of SCLK (Required Setup Time) (Note 27) tWSCLKl – – 167 ns
Falling Edge of SCLK to Rising Edge of CS (Required Setup Time) (Note 27) tLAG –50 167 ns
SI to Falling Edge of SCLK (Required Setup Time) (Note 28) tSI(SU) –25 83 ns
Falling Edge of SCLK to SI (Required Setup Time) (Note 28) tSI(HOLD) –25 83 ns
SO Rise Time
CL = 200 pF
tRSO
–25 50
ns
SO Fall Time
CL = 200 pF
tFSO
–25 50
ns
SI, CS, SCLK, Incoming Signal Rise Time (Note 28) tRSI – – 50 ns
SI, CS, SCLK, Incoming Signal Fall Time (Note 28) tFSI – – 50 ns
Time from Falling Edge of CS to SO Low Impedance (Note 29) tSO(EN) – – 145 ns
Time from Rising Edge of CS to SO High Impedance (Note 30) tSO(DIS) –65 145 ns
Time from Rising Edge of SCLK to SO Data Valid (Note 31)
0.2 VDD ≤ SO ≥ 0.8 VDD, CL = 200 pF
tVALID
–65 105
ns
Notes
26. RST low duration measured with outputs enabled and going to OFF or disabled condition.
27. Maximum setup time required for the 33580 is the minimum guaranteed time needed from the microcontroller.
28. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
29. Time required for output status data to be available for use at SO. 1.0 kΩ on pullup on CS.
30. Time required for output status data to be terminated at SO. 1.0 kΩ on pullup on CS.
31. Time required to obtain valid data out from SO following the rise of SCLK.
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33580
13
Timing Diagrams
Figure 2. Output Slew Rate and Time Delays
Figure 3. Overcurrent Shutdown
VPWR
VPWR - 0.5V
VPWR - 3V
0.5V
Tdly(off)
SRrA
SRrB
SRfA
SRfB
CS
Tdly
(on)
VPWR
VPWR-0.5 V
VPWR-3.5 V
0.5 V
tDLY(ON) tDLY(OFF)
SRRB
SRFB
SRFA
SRRA
Load
Current
IOCHx
IOCLx
tOCLx
Time
tOCH
ILOAD1
ILOAD2
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33580 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
14
Figure 4. Overcurrent Low and High Detection
Figure 5. Input Timing Switching Characteristics
IOCH0
tOCL0
tOCL2
tOCL3
tOCH
Time
Load
Current
IOCH1
IOCL0
IOCL2
IOCL3
IOCL4
IOCL5
IOCL6
IOCL7
IOCL1
SI
RSTB
CSB
SCLK
Don’t Care Don’t Care Don’t Care
Valid Valid
VIH
VIL
VIH
VIH
VIH
VIL
VIL
VIL
TwRSTB
Tlead TwSCLKh TrSI
Tlag
TSIsu TwSCLKl
TSI(hold) TfSI
0.7 VDD
0.2 VDD
0.7VDD
0.2VDD
0.2VDD
0.7VDD
0.7VDD
TCSB
TENBL
RST
SCLK
SI
CS
0.2 VDD
tWRST tENBL
0.7 VDD
tLEAD
tWSCLKh
tRSI
0.7 VDD
0.2 VDD
0.7 VDD
0.2 VDD
tSI(SU)
t
WSCLKl
tSI(HOLD) tFSI
0.7 VDD
tCS
tLAG
VIH
VIH
VIL
V
IL
VIH
VIL
VIH
VIH
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33580
15
Figure 6. SCLK Waveform and Valid SO Data Delay Time
SO
SO
SCLK
VOH
VOL
VOH
VOL
VOH
VOL
TfSI
TdlyLH
TdlyHL
TVALID
TrSO
TfSO
3.5V
50%
TrSI
High-to-Low
1.0V
0.7 VDD
0.2VDD
0.2 VDD
0.7 VDD
Low-to-High
tRSI tFSI
0.7 VDD
SCLK
SO
SO
VOH
VOL
VOH
VOL
VOH
VOL
1.0 V
0.2 VDD
0.7 VDD
tRSO
tFSO
0.2 VDD
tSO(EN)
tSO(DIS)
3.5 V
Low to High
High to Low
tVALID
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33580 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
16
SYSTEM/APPLICATION INFORMATION
INTRODUCTION
The 33580 is one in a family of devices designed for low-
voltage automotive and industrial lighting and motor control
applications. Its four low RDS(ON) MOSFETs (15 mΩ) can
control the high sides of four separate resistive or inductive
loads.
Programming, control, and diagnostics are accomplished
using a 16-bit SPI interface. Additionally, each output has its
own parallel input for PWM control if desired. The 33580 allows
the user to program via the SPI the fault current trip levels and
duration of acceptable lamp inrush or motor stall intervals. Such
programmability allows tight control of fault currents and can
protect wiring harnesses and circuit boards as well as loads.
The 33580 is packaged in a power-enhanced 12 x 12
nonleaded PQFN package with exposed tabs.
FUNCTIONAL DESCRIPTION
SPI Protocol Description
The SPI interface has a full duplex, three-wire synchronous
data transfer with four I/O lines associated with it: Serial Input
(SI), Serial Output (SO), Serial Clock (SCLK), and Chip Select
(CS).
The SI/SO terminals of the 33580 follow a first-in first-out
(D15 to D0) protocol, with both input and output words
transferring the most significant bit (MSB) first. All inputs are
compatible with 5.0 V CMOS logic levels.
The SPI lines perform the following functions:
Serial Input (SI)
This is a serial interface (SI) command data input terminal.
Each SI bit is read on the falling edge of SCLK. A 16-bit stream
of serial data is required on the SI terminal, starting with D15 to
D0. The internal registers of the 33580 are configured and
controlled using a 5-bit addressing scheme described in
Table 1, page 17. Register addressing and configuration are
described in Table 2, page 18. The SI input has an active
internal pulldown, IDWN.
Serial Output (SO)
The SO data terminal is a tri-stateable output from the shift
register. The SO terminal remains in a high-impedance state
until the CS terminal is put into a logic [0] state. The SO data is
capable of reporting the status of the output, the device
configuration, and the state of the key inputs. The SO terminal
changes state on the rising edge of SCLK and reads out on the
falling edge of SCLK. Fault and input status descriptions are
provided in Tab l e 9, page 21.
Serial Clock (SCLK)
The SCLK terminal clocks the internal shift registers of the
33580 device. The serial input (SI) terminal accepts data into
the input shift register on the falling edge of the SCLK signal
while the serial output (SO) terminal shifts data information out
of the SO line driver on the rising edge of the SCLK signal. It is
important the SCLK terminal be in a logic low state whenever
CS makes any transition. For this reason, it is recommended the
SCLK terminal be in a logic [0] whenever the device is not
accessed (CS logic [1] state). SCLK has an active internal
pulldown. When CS is logic [1], signals at the SCLK and SI
terminals are ignored and SO is tri-stated (high impedance)
(see Figure 7, page 17).
Chip Select (CS)
The CS terminal enables communication with the master
microcontroller (MCU). When this terminal is in a logic [0] state,
the device is capable of transferring information to, and
receiving information from, the MCU. The 33580 latches in data
from the Input Shift registers to the addressed registers on the
rising edge of CS. The device transfers status information from
the power output to the Shift register on the falling edge of CS.
The SO output driver is enabled when CS is logic [0]. CS should
transition from a logic [1] to a logic [0] state only when SCLK is
a logic [0]. CS has an active internal pullup, IUP.
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33580
17
Figure 7. Single 16-Bit Word SPI Communication
Serial Input Communication
SPI communication is accomplished using 16-bit
messages. A message is transmitted by the MCU starting with
the MSB D15 and ending with the LSB, D0 (Table 1). Each
incoming command message on the SI terminal can be
interpreted using the following bit assignments: the MSB, D15,
is the watchdog bit. In some cases, output selection is done
with bits D12:D11. The next three bits, D10:D8, are used to
select the command register. The remaining five bits, D4:D0,
are used to configure and control the outputs and their
protection features.
Multiple messages can be transmitted in succession to
accommodate those applications where daisy-chaining is
desirable, or to confirm transmitted data, as long as the
messages are all multiples of 16 bits. Any attempt made to
latch in a message that is not 16 bits will be ignored.
The 33580 has defined registers, which are used to
configure the device and to control the state of the outputs.
Table 2, page 18, summarizes the SI registers.
CS
CSB
SI
SCLK
SO
D15 D1 D2 D3 D4 D5 D6 D7 D8 D9 D14 D13 D12 D11 D10
OD12
D0
OD13 OD14 OD15 OD6OD7OD8OD9OD10OD11 OD1 OD2 OD3 OD4OD5
1. RSTB is in a logic H state during the above operation.
2. DO, D1, D2, ... , and D15 relate to the most recent ordered entry of program data into the LUX IC
3. OD0, OD1, OD2, ..., and OD15 relate to the first 16 bits of ordered fault and status data out of the LUX IC
NOTES:
OD0
CS
device.
device.
1.
RST
is a logic [1] state during the above operation.
2. D15
:
D0 relate to the most recent ordered entry of data into the device.
3. OD15
:
OD0 relate to the first 16 bits of ordered fault and status data out of the device.
Notes
Table 1. SI Message Bit Assignment
Bit Sig SI Msg Bit Message Bit Description
MSB D15 Watchdog in: toggled to satisfy watchdog
requirements.
D14:D15 Not used.
D12:D11 Register address bits used in some cases for
output selection.
D10:D8 Register address bits.
D7:D5 Not used.
D4:D1 Used to configure the inputs, outputs, and the
device protection features and SO status
content.
LSB D0 Used to configure the inputs, outputs, and the
device protection features and SO status
content.
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33580 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
18
Device Register Addressing
The following section describes the possible register
addresses and their impact on device operation.
Address xx000—Status Register (STATR)
The STATR register is used to read the device status and the
various configuration register contents without disrupting the
device operation or the register contents. The register bits
D[4:0] determine the content of the first sixteen bits of SO data.
In addition to the device status, this feature provides the ability
to read the content of the OCR0, OCR1, SOCHLR, CDTOLR,
DICR, UOVR, WDR, and NAR registers. (Refer to the section
entitled Serial Output Communication (Device Status Return
Data) beginning on page 20.)
Address x0001—Output Control Register (OCR0)
The OCR0 register allows the MCU to control the ON/OFF
state of four outputs through the SPI. Incoming message bit
D3:D0 reflects the desired states of the four high-side outputs
(INx_SPI), respectively. A logic [1] enables the corresponding
output switch and a logic [0] turns it OFF.
Address x1001—Output Control Register (OCR1)
Incoming message bits D3:D0 reflect the desired output that
will be mirrored on the Current Sense (CSNS) terminal. A
logic [1] on message bits D3:D0 enables the CSNS terminal for
outputs HS3:HS0, respectively. In the event the current sense
is enabled for multiple outputs, the current will be summed. In
the event that bits D3:D0 are all logic [0], the output CSNS will
be tri-stated. This is useful when several CSNS terminals of
several devices share the same A/D converter.
Address A1A0010—Select Overcurrent High and Low
Register (SOCHLR_s)
The SOCHLR_s register allows the MCU to configure the
output overcurrent low and high detection levels, respectively.
Each output “s” is independently selected for configuration
based on the state of the D12:D11 bits (Table 3).
Each output can be configured to different levels. In addition
to protecting the device, this slow blow fuse emulation feature
can be used to optimize the load requirements matching system
characteristics. Bits D2:D0 set the overcurrent low detection
level to one of eight possible levels, as shown in Table 4,
page 19. Bit D3 sets the overcurrent high detection level to one
of two levels, as outlined in Table 5, page 19.
Table 2. Serial Input Address and Configuration Bit Map
SI Register
SI Data
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
STATR WDIN x x x x 0 0 0 x x x SOA4 SOA3 SOA2 SOA1 SOA0
OCR0 WDIN x x x 0 0 0 1 x x x x IN3_SPI IN2_SPI IN1_SPI IN0_SPI
OCR1 WDIN x x x 1 0 0 1 x x x x CSNS3 EN CSNS2 EN CSNS1 EN CSNS0 EN
SOCHLR_s WDIN x x A1A00 1 0 x x x x SOCH_s SOCL2_s SOCL1_s SOCL0_s
CDTOLR_s WDIN x x A1A00 1 1 x x x x OL_DIS_s OCL_DIS_s OCLT1_s OCLT0_s
DICR_s WDIN x x A1A01 0 0 x x x x FAST_SR_s CSNS_high_s DIR_DIS_s A/O_s
UOVR WDIN x x x 0 1 0 1 x x x x x x UV_DIS OV_DIS
WDR WDIN x x x 1 1 0 1 x x x x x x WD1 WD0
NAR WDIN x x x x 1 1 0 x x x x No Action (Allow Toggling of D15:WDIN)
TEST WDIN x x x x 1 1 1 x x x x Motorola Internal Use (Test)
x=Don’t care.
s=Output selection with the bits A1A0 as defined in Table 3.
Table 3. Output Selection
A1 (D12) A0 (D11) HS_s
0 0 HS0
0 1 HS1
1 0 HS2
1 1 HS3
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33580
19
Address A1A0011—Current Detection Time and Open
Load Register (CDTOLR)
The CDTOLR register is used by the MCU to determine the
amount of time the device will allow an overcurrent low
condition before an output latches OFF. Each output is
independently selected for configuration based on A1A0, which
are the state of the D12:D11 bits (refer to Table 3, page 18).
Bits D1:D0 (OCLT1_s:OCLT0_s) allow the MCU to select
one of three overcurrent fault blanking times defined in Table 6.
Note that these timeouts apply only to the overcurrent low
detection levels. If the selected overcurrent high level is
reached, the device will latch off within 20 µs.
A logic [1] on bit D2 (OCL_DIS_s) disables the overcurrent
low detection feature. When disabled, there is no timeout for
the selected output and the overcurrent low detection feature is
disabled.
A logic [1] on bit D3 (OL_DIS_s) disables the open load (OL)
detection feature for the output corresponding to the state of
bits D12:D11.
Address A1A0100—Direct Input Control Register (DICR)
The DICR register is used by the MCU to enable, disable, or
configure the direct IN terminal control of each output. Each
output is independently selected for configuration based on the
state bits D12:D11 (refer to Table 3, page 18).
For the selected output, a logic [0] on bit D1 (DIR_DIS_s)
will enable the output for direct control. A logic [1] on bit D1 will
disable the output from direct control.
While addressing this register, if the Input was enabled for
direct control, a logic [1] for the D0 (A/O_s) bit will result in a
Boolean AND of the IN terminal with its corresponding IN_SPI
D[4:0] message bit when addressing OCR0. Similarly, a logic
[0] on the D0 terminal results in a Boolean OR of the IN terminal
to the corresponding message bits when addressing the
OCR0. This register is especially useful if several loads are
required to be independently PWM controlled. For example,
the IN terminals of several devices can be configured to
operate all of the outputs with one PWM output from the MCU.
If each output is then configured to be Boolean ANDed to its
respective IN terminal, each output can be individually turned
OFF by SPI while controlling all of the outputs, commanded on
with the single PWM output.
A logic [1] on bit D2 (CSNS_high_s) is used to select the
high ratio on the CSNS terminal for the selected output. The
default value [0] is used to select the low ratio (Table 7).
A logic [1] on bit D3 (FAST_SR_s) is used to select the high
speed slew rate for the selected output, the default value [0]
corresponds to the low speed slew rate.
Address x0101—Undervoltage/Overvoltage Register
(UOVR)
The UOVR register disables the undervoltage (D1) and/or
overvoltage (D0) protection. When these two bits are [0], the
under- and overvoltage are active (default value).
Table 4. Overcurrent Low Detection Levels
SOCL2_s*
(D2)
SOCL1_s*
(D1)
SOCL0_s*
(D0)
Overcurrent Low
Detection (Amperes)
HS0 to HS3
0 0 0 18.2
0 0 1 16.3
0 1 0 14.4
0 1 1 12.5
1 0 0 10.5
1 0 1 8.6
1 1 0 6.7
1 1 1 4.8
* “_s” refers to the output, which is selected through bits D12 :D11;
refer to Table 3, page 18.
Table 5. Overcurrent High
Detection Levels
SOCH_s*
(D3)
Overcurrent High
Detection (Amperes)
HS0 to HS3
0100
170
* “_s” refers to the output, which is
selected through bits D12:D11; refer to
Table 3, page 18.
Table 6. Overcurrent Low Detection
Blanking Time
OCLT[1:0]_s*Timing
00 155 ms
01 Do not use
10 75 ms
11 150 µs
*“_s” refers to the output, which is selected through bits
D12:D11; refer to Table 3, page 18.
Table 7. Current Sense Ratio
CSNS_high_s* (D2)
Current Sense Ratio
HS0 to HS3
01/13000
11/40000
*“_s” refers to the output, which is selected
through bits D12:D11; refer to Table 3, page 18.
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Address x1101— Watchdog Register (WDR)
The WDR register is used by the MCU to configure the
Watchdog timeout. The Watchdog timeout is configured using
bits D1 and D0. When D1 and D0 bits are programmed for the
desired watchdog timeout period (Table 8), the WDSPI bit
should be toggled as well, ensuring the new timeout period is
programmed at the beginning of a new count sequence.
Address xx110—No Action Register (NAR)
The NAR register can be used to no-operation fill SPI data
packets in a daisy-chain SPI configuration. This would allow
devices to be unaffected by commands being clocked over a
daisy-chained SPI configuration. By toggling the WD bit (D15)
the watchdog circuitry would continue to be reset while no
programming or data read back functions are being requested
from the device.
Address xx111—TEST
The TEST register is reserved for test and is not accessible
with SPI during normal operation.
Serial Output Communication (Device Status Return
Data)
When the CS terminal is pulled low, the output register is
loaded. Meanwhile, the data is clocked out MSB- (OD15-) first
as the new message data is clocked into the SI terminal. The
first sixteen bits of data clocking out of the SO, and following a
CS transition, is dependent upon the previously written SPI
word.
Any bits clocked out of the Serial Output (SO) terminal after
the first 16 bits will be representative of the initial message bits
clocked into the SI terminal since the CS terminal first
transitioned to a logic [0]. This feature is useful for daisy-
chaining devices as well as message verification.
A valid message length is determined following a CS
transition of [0] to [1]. If there is a valid message length, the data
is latched into the appropriate registers. A valid message length
is a multiple of 16 bits. At this time, the SO terminal is tri-stated
and the fault status register is now able to accept new fault
status information.
SO data will represent information ranging from fault status
to register contents, user selected by writing to the STATR bits
OD4, OD3, OD2, OD1, and OD0. The value of the previous bits
SOA4 and SOA3 will determine which output the SO
information applies to for the registers which are output specific;
viz., Fault, SOCHLR, CDTOLR, and DICR registers.
Note that the SO data will continue to reflect the information
for each output (depending on the previous OD4, OD3 state)
that was selected during the most recent STATR write until
changed with an updated STATR write.
The output status register correctly reflects the status of the
STATR-selected register data at the time that the CS is pulled
to a logic [0] during SPI communication, and/or for the period of
time since the last valid SPI communication, with the following
exceptions:
• The previous SPI communication was determined to be
invalid. In this case, the status will be reported as though
the invalid SPI communication never occurred.
• Battery transients below 6.0 V resulting in an under-
voltage shutdown of the outputs may result in incorrect
data loaded into the status register. The SO data
transmitted to the MCU during the first SPI communication
following an undervoltage VPWR condition should be
ignored.
•The
RST terminal transition from a logic [0] to [1] while the
WAKE terminal is at logic [0] may result in incorrect data
loaded into the Status register. The SO data transmitted
to the MCU during the first SPI communication following
this condition should be ignored.
Serial Output Bit Assignment
The 16 bits of serial output data depend on the previous
serial input message, as explained in the following paragraphs.
Table 9, page 21, summarizes SO returned data for bits
OD15:OD0.
• Bit OD15 is the MSB; it reflects the state of the Watchdog
bit from the previously clocked-in message.
• Bit OD14 remains logic [0] except when an undervoltage
condition occurred.
• Bit OD13 remains logic [0] except when an overvoltage
condition occurred.
• Bits OD12:OD8 reflect the state of the bits SOA4:SOA0
from the previously clocked in message.
• Bits OD7:OD4 give the fault status flag of the outputs
HS3:HS0, respectively.
• The contents of bits OD3:OD0 depend on bits D4:D0
from the most recent STATR command SOA4:SOA0 as
explained in the paragraphs following Table 9.
Table 8. Watchdog Timeout
WD[1:0] (D1, D0) Timing (ms)
00 620
01 310
10 2500
11 1250
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33580
21
Previous Address SOA4:SOA0=A1A0000
Bits OD3:OD0 reflect the current state of the Fault register
(FLTR) corresponding to the output previously selected with the
bits A1A0 (Table 10).
Note The FS terminal reports all faults. For latched faults,
this terminal is reset by a new Switch ON command (via SPI or
direct input IN).
Previous Address SOA4:SOA0=x0001
Data in bits OD3:OD0 contains IN3_SPI:IN0_SPI
programmed bits for outputs HS3:HS0, respectively.
Previous Address SOA4:SOA0=x1001
Data in bits OD3:OD0 contains the programmed
CSNS3 EN:CSNS0 EN bits for outputs HS3:HS0, respectively.
Previous Address SOA4:SOA0=A1A0010
Data returned in bits OD3:OD0 are programmed current
values for the overcurrent high detection level (refer to Table 5,
page 19) and the overcurrent low detection level (refer to
Table 4, page 19), corresponding to the output previously
selected with A1A0.
Previous Address SOA4:SOA0=A1A0011
The returned data contains the programmed values in the
CDTOLR register for the output selected with A1A0.
Previous Address SOA4:SOA0=A1A0100
The returned data contains the programmed values in the
DICR register for the output selected with A1A0.
Previous Address SOA4:SOA0=x0101
The returned data contains the programmed values in the
UOVR register.
Previous Address SOA4:SOA0=x1101
The returned data contains the programmed values in the
WDR register. Bit OD2 (WDTO) reflects the status of the
watchdog circuitry. If WDTO bit is logic [1], the watchdog has
timed out and the device is in Fail-Safe mode. IF WDTO is
logic [0], the device is in Normal mode (assuming the device is
powered and not in the Sleep mode), with the watchdog either
enabled or disabled.
Previous Address SOA4:SOA0=x0110
The returned data OD3 and OD2 contain the state of the
outputs HS2 and HS0, respectively, in case of Fail-Safe state.
This information is stated with the external resistance placed at
the FSI terminal. OD1 indicates if the watchdog is enabled or
not. OD0 returns the state of the WAKE terminal.
Previous Address SOA4:SOA0=x1110
The returned data OD3:OD0 reflects the state of the direct
terminals IN3:IN0, respectively.
Table 9. Serial Output Bit Map Description
Previous STATR SO Returned Data
SO
A4
SO
A3
SO
A2
SO
A1
SO
A0
OD
15
OD
14
OD
13
OD
12
OD
11
OD
10 OD9 OD8 OD7 OD6 OD5 OD4 OD3 OD2 OD1 OD0
A1A00 0 0 WDIN UVF OVF SOA4 SOA3 SOA2 SOA1 SOA0 ST3 ST2 ST1 ST0 OTF_s OCHF_s OCLF_s OLF_s
x 0 0 0 1 WDIN UVF OVF SOA4 SOA3 SOA2 SOA1 SOA0 ST3 ST2 ST1 ST0 IN3_SPI IN2_SPI IN1_SPI IN0_SPI
x 1 0 0 1 WDIN UVF OVF SOA4 SOA3 SOA2 SOA1 SOA0 ST3 ST2 ST1 ST0 CSNS3 EN CSNS2 EN CSNS1 EN CSNS0 EN
A1A00 1 0 WDIN UVF OVF SOA4 SOA3 SOA2 SOA1 SOA0 ST3 ST2 ST1 ST0 SOCH_s SOCL2_s SOCL1_s SOCL0_s
A1A00 1 1 WDIN UVF OVF SOA4 SOA3 SOA2 SOA1 SOA0 ST3 ST2 ST1 ST0 OL_DIS_s OCL_DIS_s OCLT1_s OCLT0_s
A1A01 0 0 WDIN UVF OVF SOA4 SOA3 SOA2 SOA1 SOA0 ST3 ST2 ST1 ST0 Fast_SR_s CSNS_high_s DIR_DIS_s A/O_s
x 0 1 0 1 WDIN UVF OVF SOA4 SOA3 SOA2 SOA1 SOA0 ST3 ST2 ST1 ST0 – – UV_DIS OV_DIS
x 1 1 0 1 WDIN UVF OVF SOA4 SOA3 SOA2 SOA1 SOA0 ST3 ST2 ST1 ST0 –WDTO WD1 WD0
x 0 1 1 0 WDIN UVF OVF SOA4 SOA3 SOA2 SOA1 SOA0 ST3 ST2 ST1 ST0 HS2_failsaf HS0_failsaf WD_en WAKE
x 1 1 1 0 WDIN UVF OVF SOA4 SOA3 SOA2 SOA1 SOA0 ST3 ST2 ST1 ST0 IN3 IN2 IN1 IN0
x=Don’t care.
s=Output selection with the bits A1A0 as defined in Table 3, page 18.
Table 10. Output-Specific Fault Register
OD3 OD2 OD1 OD0
OTF_s OCHF_s OCLF_s OLF_s
s=Selection of the output.
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33580 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
22
MODES OF OPERATION
The 33580 has four operating modes: Sleep, Normal, Fault,
and Fail-Safe. Table 11 summarizes details contained in
succeeding paragraphs.
Sleep Mode
The Default mode of the 33580 is the Sleep mode. This is the
state of the device after first applying battery voltage (VPWR)
prior to any I/O transitions. This is also the state of the device
when the WAKE and RST are both logic [0]. In the Sleep mode,
the output and all unused internal circuitry, such as the internal
5.0 V regulator, are off to minimize current draw. In addition, all
SPI-configurable features of the device are as if set to logic [0].
The 33580 will transition to the Normal or Fail-Safe operating
modes based on the WAKE and RST inputs as defined in
Table 11.
Normal Mode
The 33580 is in Normal mode when:
•V
PWR is within the normal voltage range.
•RST terminal is logic [1].
• No fault has occurred.
Fail-Safe Mode
Fail-Safe Mode and Watchdog
If the FSI input is not grounded, the watchdog timeout
detection is active when either the WAKE or RST input terminal
transitions from logic [0] to logic [1]. The WAKE input is capable
of being pulled up to VPWR with a series of limiting resistance
limiting the internal clamp current according to the specification.
The Watchdog timeout is a multiple of an internal oscillator
and is specified in the Table 8, page 20. As long as the WD bit
(D15) of an incoming SPI message is toggled within the
minimum watchdog timeout period (WDTO), based on the
programmed value of the WDR, the device will operate
normally. If an internal watchdog timeout occurs before the WD
bit, the device will revert to a Fail-Safe mode until the device is
reinitialized.
During the Fail-Safe mode, the outputs will be ON or OFF
depending upon the resistor RFS connected to the FSI terminal,
regardless of the state of the various direct inputs and modes
(Table 12).
In the Fail-Safe mode, the SPI register content is retained
except for overcurrent high and low detection levels and timing,
which are reset to their default value (SOCL, SOCH, and
OCTL). Then the watchdog, overvoltage, overtemperature, and
overcurrent circuitry (with default value) are fully operational.
The Fail-Safe mode can be detected by monitoring the
WDTO bit D2 of the WD register. This bit is logic [1] when the
device is in Fail-Safe mode. The device can be brought out of
the Fail-Safe mode by transitioning the WAKE and RST
terminals from logic [1] to logic [0] or forcing the FSI terminal to
logic [0]. Table 11 summarizes the various methods for
resetting the device from the latched Fail-Safe mode.
If the FSI terminal is tied to GND, the Watchdog fail-safe
operation is disabled.
Table 11. Fail-Safe Operation and Transitions
to Other 33580 Modes
Mode FS Wake RST WDTO Comments
Sleep x 0 0 x Device is in Sleep mode. All
outputs are OFF
Normal 1 x 1 No Normal mode. Watchdog is
active if enabled.
Fault
0 1 1
No
Device is currently in fault
mode. The faulted output(s) is
(are) OFF.
0 1 0
0 x 1
Fail-
Safe
1 0 1
Yes
Watchdog has timed out and
the device is in Fail-Safe
Mode. The outputs are as
configured with the RFS
resistor connected to FSI.
RST and WAKE must be
transitioned to logic [0]
simultaneously to bring the
device out of the Fail-safe
mode or momentarily tied the
FSI terminal to ground.
1 1 1
1 1 0
x = Don’t care.
Table 12. Output State During
Fail-Safe Mode
RFS (kΩ)High-Side State
0Fail-Safe Mode Disabled
6.0 All HS OFF
15 HS0 ON
HS1:HS3 OFF
30 HS0 and HS2 ON
HS1 and HS3 OFF
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33580
23
Loss of VDD
If the external 5.0 V supply is not within specification, or
even disconnected, all register content is reset. The outputs
can still be driven by the direct inputs IN0:IN3. The 33580 uses
the battery input to power the output MOSFET-related current
sense circuitry and any other internal logic providing fail-safe
device operation with no VDD supplied. In this state, the
watchdog, overvoltage, overtemperature, and overcurrent
circuitry are fully operational with default values.
Fault Mode
This 33580 indicates the faults below as they occur by
driving the FS terminal to logic [0]:
• Overtemperature fault
• Overvoltage and undervoltage fault
• Open load fault
• Overcurrent fault (high and low)
The FS terminal will automatically return to logic [1] when
the fault condition is removed, except for overcurrent and in
some cases undervoltage.
Fault information is retained in the fault register and is
available (and reset) via the SO terminal during the first valid
SPI communication (refer to Table 10, page 21).
Overtemperature Fault (Non-Latching)
The 33580 incorporates overtemperature detection and
shutdown circuitry in the output structure. Overtemperature
detection is enabled when the output is in the ON state.
For the output, an overtemperature fault (OTF) condition
results in the faulted output turning OFF until the temperature
falls below the TSD(HYS). This cycle will continue indefinitely
until action is taken by the MCU to shut OFF the output, or until
the offending load is removed.
When experiencing this fault, the OTF fault bit will be set in
the status register and cleared after either a valid SPI read or
a power reset of the device.
Overvoltage Fault (Non-Latching)
The 33580 shuts down the output during an overvoltage
fault (OVF) condition on the VPWR terminal. The output
remains in the OFF state until the overvoltage condition is
removed. When experiencing this fault, the OVF fault bit is set
in the bit D1 and cleared after either a valid SPI read or a power
reset of the device.
The overvoltage protection can be disabled through SPI (bit
OV_DIS). When disabled, the returned SO bit OD13 still
reflects any overvoltage condition (overvoltage warning).
Undervoltage Shutdown (Latching or Non-Latching)
The output latches OFF at some battery voltage between
4.75 V and 5.75 V. As long as the VDD level stays within the
normal specified range, the internal logic states within the
device will be sustained. This ensures that when the battery
level then returns above 5.75 V, the 33580 can be returned to
the state that it was in prior to the low VPWR excursion. Once
the output latches OFF, the outputs must be turned OFF and
ON again to re-enable them. In the case IN1:IN0=0, this fault
is non-latched.
The undervoltage protection can be disabled through SPI
(bit UV_DIS). When disabled, the returned SO bit OD14 still
reflects any undervoltage condition (undervoltage warning).
Open Load Fault (Non-Latching)
The 33580 incorporates open load detection circuitry on the
output. Output open load fault (OLF) is detected and reported
as a fault condition when the output is disabled (OFF). The
open load fault is detected and latched into the status register
after the internal gate voltage is pulled low enough to turn OFF
the output. The OLF fault bit is set in the status register. If the
open load fault is removed, the status register will be cleared
after reading the register.
The open load protection can be disabled through SPI (bit
OL_DIS).
Overcurrent Fault (Latching)
The 33580 has eight programmable overcurrent low
detection levels (IOCL) and two programmable overcurrent high
detection levels (IOCH) for maximum device protection. The
two selectable, simultaneously active overcurrent detection
levels, defined by IOCH and IOCL, are illustrated in Figure 4,
page 14. The eight different overcurrent low detect levels
(IOCL0 :IOCL7) are illustrated in Figure 4.
If the load current level ever reaches the selected
overcurrent low detection level and the overcurrent condition
exceeds the programmed overcurrent time period (tOCx), the
device will latch the output OFF.
If at any time the current reaches the selected IOCH level,
then the device will immediately latch the fault and turn OFF
the output, regardless of the selected tOCLx driver.
For both cases, the device output will stay off indefinitely
until the device is commanded OFF and then ON again.
Reverse Battery
The output survives the application of reverse voltage as
low as -16 V. Under these conditions, the output’s gate is
enhanced to keep the junction temperature less than 150°C.
The ON resistance of the output is fairly similar to that in the
Normal mode. No additional passive components are required.
Ground Disconnect Protection
In the event the 33580 ground is disconnected from load
ground, the device protects itself and safely turns OFF the
output regardless of the state of the output at the time of
disconnection.
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33580 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
24
Soldering Information
The 33580 is packaged in a surface mount power package
intended to be soldered directly on the printed circuit board.
The 33580 was qualified in accordance with JEDEC
standards JESD22-A113-B and J-STD-020A. The
recommended reflow conditions are as follows:
• Convection: 235°C +5.0/-0°C
• Vapor Phase Reflow (VPR): 235°C +5.0/-0°C
• Infrared (IR)/Convection: 235°C +5.0/-0°C
The maximum peak temperature during the soldering
process should not exceed 240°C. The time at maximum
temperature should range from 10 s to 40 s maximum.
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33580
25
PACKAGE DIMENSIONS
12 A
B
12
0.1 C
2X
17X
13
19 20 21
1
24
14
15
22
21 20 19
18
17
16
13
24
1
22
16
18
M
M
DETAIL G
C
2.20
2.00
2.20
1.95
0.05
0.00
0.05 C
0.1 C
0.75
0.35
7X 1.3
0.8
0.1 MACB
0.05 MC
A
0.1 B
C
5.3
4.9
A
0.1 B
C
2.9
2.5
A
0.1 B
C
4.7
4.3
0.35
0.15
2 PLACES
3.35
2.95
(0.25)
A
0.1 B
C
0.2
0.0
3X 3.7
3.3
A
0.1 B
C
3X 2.05
1.55
A
0.1 B
C
6X 1.7
1.2
A
0.1 B
C
11.7
11.3
A
0.1 B
C
2.25
2.85
1.25
12X 0.9
0.35
0.15 (0.5)
(0.3)
2.4
2.0
3.075
2.45
0.9
1.15
0.75
1.3
0.9
0.2
0.0
2.5
2.1
1.75
1.35 0.55
0.15
0.6
0.2
1.2
0.8
3.35
2.95
2.15
1.65
A
0.1 B
C
1.8
1.3
0.7
0.3
(0.3)
A
0.1 B
C
17X
2X
0.2
0.0
DETAIL H
4
PIN 1
INDEX AREA
PIN NUMBER
REF. ONLY
SEATING
PLANE
14
15
13
0.1 C
2X
NOTES:
1.
2.
3.
4.
5.
ALL DIMENSIONS ARE IN MILLIMETERS.
DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
THE COMPLETE JEDEC DESIGNATOR FOR THIS
PACKAGE IS: HF-PQFP-N.
COPLANARITY APPLIES TO LEADS AND CORNER
LEADS.
MINIMUM METAL GAP SHOULD BE 0.25MM.
DETAIL H
DETAIL G
VIEW M-M
PNA SUFFIX
24-TERMINAL PQFN
NONLEADED PACKAGE
CASE 1593-02
ISSUE A
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33580 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
26
NOTES
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33580
27
NOTES
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P.O. Box 5405, Denver, Colorado 80217 81-3-3440-3569
1-800-521-6274 or 480-768-2130
ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre
2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong
852-26668334
HOME PAGE: http://motorola.com/semiconductors
MC33580
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