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DAdvanced Multibus Architecture With Three
Separate 16-Bit Data Memory Buses and
One Program Memory Bus
D40-Bit Arithmetic Logic Unit (ALU),
Including a 40-Bit Barrel Shifter and Two
Independent 40-Bit Accumulators
D17- ×17-Bit Parallel Multiplier Coupled to a
40-Bit Dedicated Adder for Non-Pipelined
Single-Cycle Multiply/Accumulate (MAC)
Operation
DCompare, Select, and Store Unit (CSSU) for
the Add/Compare Selection of the Viterbi
Operator
DExponent Encoder to Compute an
Exponent Value of a 40-Bit Accumulator
Value in a Single Cycle
DTwo Address Generators With Eight
Auxiliary Registers and Two Auxiliary
Register Arithmetic Units (ARAUs)
DData Bus With a Bus-Holder Feature
DExtended Addressing Mode for 1M × 16-Bit
Maximum Addressable External Program
Space
D4K x 16-Bit On-Chip ROM
D16K x 16-Bit Dual-Access On-Chip RAM
DSingle-Instruction-Repeat and
Block-Repeat Operations for Program Code
DBlock-Memory-Move Instructions for
Efficient Program and Data Management
DInstructions With a 32-Bit Long Word
Operand
DInstructions With Two- or Three-Operand
Reads
DArithmetic Instructions With Parallel Store
and Parallel Load
DConditional Store Instructions
DFast Return From Interrupt
DOn-Chip Peripherals
− Software-Programmable Wait-State
Generator and Programmable Bank
Switching
− On-Chip Phase-Locked Loop (PLL) Clock
Generator With Internal Oscillator or
External Clock Source
− Two Multichannel Buffered Serial Ports
(McBSPs)
− Enhanced 8-Bit Parallel Host-Port
Interface (HPI8)
− Two 16-Bit Timers
− Six-Channel Direct Memory Access
(DMA) Controller
DPower Consumption Control With IDLE1,
IDLE2, and IDLE3 Instructions With
Power-Down Modes
DCLKOUT Off Control to Disable CLKOUT
DOn-Chip Scan-Based Emulation Logic,
IEEE Std 1149.1† (JTAG) Boundary Scan
Logic
D10-ns Single-Cycle Fixed-Point Instruction
Execution Time (100 MIPS) for 3.3-V Power
Supply (1.8-V Core)
DAvailable in a 144-Pin Plastic Low-Profile
Quad Flatpack (LQFP) (PGE Suffix) and a
144-Pin Ball Grid Array (BGA) (GGU Suffix)
NOTE:This data sheet is designed to be used in conjunction with the TMS320C5000 DSP Family Functional Overview
(literature number SPRU307).
Copyright 2008, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications o
f
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
†IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
! " #$%! " &$'(#! )!%*
)$#!" # ! "&%##!" &% !+% !%" %," "!$%!"
"!)) -!.* )$#! &#%""/ )%" ! %#%""(. #($)%
!%"!/ (( &%!%"*
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TABLE OF CONTENTS
Description 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Assignments 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Terminal Functions 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
On-Chip Peripherals 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Software-Programmable Wait-State Generator 16. . . . . . . . .
Programmable Bank-Switching Wait States 18. . . . . . . . . . . .
Parallel I/O Ports 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Enhanced 8-Bit Host-Port Interface 19. . . . . . . . . . . . . . . . . . .
Multichannel Buffered Serial Ports 20. . . . . . . . . . . . . . . . . . . .
Hardware Timer 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Generator 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Controller 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory-Mapped Registers 27. . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP Control Registers And Subaddresses 29. . . . . . . . . .
DMA Subbank Addressed Registers 29. . . . . . . . . . . . . . . . . .
Interrupts 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Support 33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings 35. . . . . . . . . . . . . . . . . . . . . . . . . .
Recommended Operating Conditions 35. . . . . . . . . . . . . . . . .
Electrical Characteristics 36. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parameter Measurement Information 37. . . . . . . . . . . . . . . . . .
Internal Oscillator With External Crystal 37. . . . . . . . . . . . . . . .
Divide-By-Two Clock Option (PLL Disabled) 38. . . . . . . . . . . .
Multiply-By-N Clock Option 39. . . . . . . . . . . . . . . . . . . . . . . . . .
Memory and Parallel I/O Interface Timing 40. . . . . . . . . . . . . .
Ready Timing For Externally Generated Wait States 46. . . . .
HOLD and HOLDA Timings 50. . . . . . . . . . . . . . . . . . . . . . . . . .
Reset, BIO, Interrupt, and MP/MC Timings 51. . . . . . . . . . . . .
Instruction Acquisition (IAQ), Interrupt Acknowledge
(IACK), External Flag (XF), and TOUT Timings 53. . . . .
Multichannel Buffered Serial Port Timing 55. . . . . . . . . . . . . . .
HPI8 Timing 62. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mechanical Data 66. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
REVISION HISTORY
REVISION DATE PRODUCT STATUS HIGHLIGHTS
*October 1998 Advanced Information Original
AApril 1999 Advanced Information Revised to update characteristic data
BJuly 1999 Advanced Information Revised to update characteristic data
CSeptember 1999 Advanced Information Revised to update characteristic data
DJanuary 2000 Production Data Revised to release production data.
EAugust 2000 Production Data Added Table of Contents, Revision History, and corrected IDLE3
current on page 35.
FFebruary 2005 Production Data
Updated table of contents and revision history. Added notices con-
cerning JTAG (IEEE 1149.1) boundary scan test capability and re-
placed document support section on page 33. Added device and
development-support tool nomenclature section on page 34. Re-
placed Figure 9 on page 37. Replaced Figure 36 on page 65. Re-
placed mechanical section on page 66.
GOctober 2008 Production Data
Terminal Functions table:
− Updated DESCRIPTION of TRST
− Added footnote about TRST
Mechanical Data section:
− Revised paragraph
− Mechanical drawings will be appended to this document via an
automated process
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description
The TMS320VC5402 fixed-point, digital signal processor (DSP) (hereafter referred to as the 5402 unless
otherwise specified) is based on an advanced modified Harvard architecture that has one program memory bus
and three data memory buses. This processor provides an arithmetic logic unit (ALU) with a high degree of
parallelism, application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The basis
of the operational flexibility and speed of this DSP is a highly specialized instruction set.
Separate program and data spaces allow simultaneous access to program instructions and data, providing the
high degree of parallelism. Two read operations and one write operation can be performed in a single cycle.
Instructions with parallel store and application-specific instructions can fully utilize this architecture. In addition,
data can be transferred between data and program spaces. Such parallelism supports a powerful set of
arithmetic, logic, and bit-manipulation operations that can be performed in a single machine cycle. In addition,
the 5402 includes the control mechanisms to manage interrupts, repeated operations, and function calls.
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description (continued)
CV
HDS1
A18
A17
VSS
A16
D5
D4
D3
D2
D1
D0
RS
X2/CLKIN
X1
HD3
CLKOUT
VSS
HPIENA
CVDD
NC
TMS
TCK
TRST
TDI
TDO
EMU1/OFF
EMU0
TOUT0
HD2
NC
CLKMD3
CLKMD2
CLKMD1
VSS
DVDD
NC
NC
NC
NC
VSS
DVDD
A10
HD7
A11
A12
A13
A14
A15
NC
HAS
VSS
NC
CVDD
HCS
HR/W
READY
PS
DS
IS
R/W
MSTRB
IOSTRB
MSC
XF
HOLDA
IAQ
HOLD
BIO
MP/MC
DVDD
VSS
NC
NC
144 NC
CV
143
142
141 A8
140 A7
139 A6
138 A5
137 A4
136 HD6
135 A3
134 A2
133 A1
132 A0
131 DV
130
129
128
127
126
125 HD5
124 D15
123 D14
122 D13
121 HD4
120 D12
119 D11
118
117 D9
116 D8
115 D7
114 D6
113
112
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
NC
NC
HCNTL0
SS
BCLKR0
BCLKR1
BFSR0
BFSR1
BDR0
HCNTL1
BDR1
BCLKX0
BCLKX1
SS
DD
SS
HD0
BDX0
BDX1
IACK
HBIL
NMI
INT0
INT1
INT2
INT3
DD
HD1
SS
HRDY
HINT/TOUT1
111 V
110 A19
109
70
71
72
NC
NC
D10
NC
DV
DD
CV HDS2
SS
V
V
V
DV
V
CV
V
DD
DD
DD
DD
SS
TMS320VC5402 PGE PACKAGE†‡
(TOP VIEW)
BFSX0
A9
BFSX1
NC
NC
†NC = No internal connection
‡DVDD is the power supply for the I/O pins while CVDD is the power supply for the core CPU. VSS is the ground for both the I/O
pins and the core CPU.
The TMS320VC5402PGE (144-pin LQFP) package is footprint-compatible with the ’LC548, ’LC/VC549, and
’VC5410 devices.
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description (continued)
TMS320VC5402 GGU PACKAGE
(BOTTOM VIEW)
A
B
D
C
E
F
H
J
L
M
K
N
G
12
3456781012 1113 9
The pin assignments table to follow lists each signal quadrant and BGA ball number for the
TMS320VC5402GGU (144-pin BGA) package which is footprint-compatible with the ’LC548 and ’LC/VC549
devices.
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Pin Assignments for the TMS320VC5402GGU (144-Pin BGA) Package†
SIGNAL
NAME BGA BALL # SIGNAL
NAME BGA BALL # SIGNAL
NAME BGA BALL # SIGNAL
NAME BGA BALL #
NC A1 NC N13 NC N1 A19 A13
NC B1 NC M13 NC N2 NC A12
VSS C2 DVDD L12 HCNTL0 M3 VSS B11
DVDD C1 VSS L13 VSS N3 DVDD A11
A10 D4 CLKMD1 K10 BCLKR0 K4 D6 D10
HD7 D3 CLKMD2 K11 BCLKR1 L4 D7 C10
A11 D2 CLKMD3 K12 BFSR0 M4 D8 B10
A12 D1 NC K13 BFSR1 N4 D9 A10
A13 E4 HD2 J10 BDR0 K5 D10 D9
A14 E3 TOUT0 J11 HCNTL1 L5 D11 C9
A15 E2 EMU0 J12 BDR1 M5 D12 B9
NC E1 EMU1/OFF J13 BCLKX0 N5 HD4 A9
HAS F4 TDO H10 BCLKX1 K6 D13 D8
VSS F3 TDI H11 VSS L6 D14 C8
NC F2 TRST H12 HINT/TOUT1 M6 D15 B8
CVDD F1 TCK H13 CVDD N6 HD5 A8
HCS G2 TMS G12 BFSX0 M7 CVDD B7
HR/W G1 NC G13 BFSX1 N7 NC A7
READY G3 CVDD G11 HRDY L7 HDS1 C7
PS G4 HPIENA G10 DVDD K7 VSS D7
DS H1 VSS F13 VSS N8 HDS2 A6
IS H2 CLKOUT F12 HD0 M8 DVDD B6
R/W H3 HD3 F11 BDX0 L8 A0 C6
MSTRB H4 X1 F10 BDX1 K8 A1 D6
IOSTRB J1 X2/CLKIN E13 IACK N9 A2 A5
MSC J2 RS E12 HBIL M9 A3 B5
XF J3 D0 E11 NMI L9 HD6 C5
HOLDA J4 D1 E10 INT0 K9 A4 D5
IAQ K1 D2 D13 INT1 N10 A5 A4
HOLD K2 D3 D12 INT2 M10 A6 B4
BIO K3 D4 D11 INT3 L10 A7 C4
MP/MC L1 D5 C13 CVDD N11 A8 A3
DVDD L2 A16 C12 HD1 M11 A9 B3
VSS L3 VSS C11 VSS L11 CVDD C3
NC M1 A17 B13 NC N12 NC A2
NC M2 A18 B12 NC M12 NC B2
†DVDD is the power supply for the I/O pins while CVDD is the power supply for the core CPU. VSS is the ground for both the I/O pins and the core
CPU.
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terminal functions
The following table lists each signal, function, and operating mode(s) grouped by function.
Terminal Functions
TERMINAL
NAME
TYPE†
DESCRIPTION
TERMINAL
NAME
TYPE†
DESCRIPTION
DATA SIGNALS
A19 (MSB)
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0 (LSB)
O/Z Parallel address bus A19 [most significant bit (MSB)] through A0 [least significant bit (LSB)]. The lower sixteen
address pins (A0 to A15) are multiplexed to address all external memory (program, data) or I/O, while the upper
four address pins (A16 to A19) are only used to address external program space. These pins are placed in the
high-impedance state when the hold mode is enabled, or when OFF is low.
D15 (MSB)
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0 (LSB)
I/O/Z Parallel data bus D15 (MSB) through D0 (LSB). The sixteen data pins (D0 to D15) are multiplexed to transfer
data between the core CPU and external data/program memory or I/O devices. The data bus is placed in the
high-impedance state when not outputting or when RS or HOLD is asserted. The data bus also goes into the
high-impedance state when OFF is low.
The data bus has bus holders to reduce the static power dissipation caused by floating, unused pins. These bus
holders also eliminate the need for external bias resistors on unused pins. When the data bus is not being driven
by the 5402, the bus holders keep the pins at the previous logic level. The data bus holders on the 5402 are
disabled at reset and can be enabled/disabled via the BH bit of the bank-switching control register (BSCR).
INITIALIZATION, INTERRUPT, AND RESET OPERATIONS
IACK O/Z Interrupt acknowledge signal. IACK Indicates receipt of an interrupt and that the program counter is fetching the
interrupt vector location designated by A15−A0. IACK also goes into the high-impedance state when OFF is low .
INT0
INT1
INT2
INT3
IExternal user interrupts. INT0−INT3 are prioritized and are maskable by the interrupt mask register (IMR) and
the interrupt mode bit. INT0 −INT3 can be polled and reset by way of the interrupt flag register (IFR).
NMI INonmaskable interrupt. NMI is an external interrupt that cannot be masked by way of the INTM or the IMR. When
NMI is activated, the processor traps to the appropriate vector location.
†I = input, O = output, Z = high impedance, S = supply
‡All revisions of the 5402 can be operated with an external clock source, provided that the proper voltage levels be driven on the X2/CLKIN
pin. It should be noted that the X2/CLKIN pin is referenced to the device 1.8V power supply (CVDD), rather than the 3V I/O supply (DVDD).
Refer to the recommended operating conditions section of this document for the allowable voltage levels of the X2/CLKIN pin.
§Although this pin includes an internal pulldown resistor, a 470-Ω external pulldown is required. If the TRST pin is connected to multiple DSPs,
a buffer is recommended to ensure the VIL and VIH specifications are met.
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Terminal Functions (Continued)
TERMINAL
NAME DESCRIPTIONTYPE†
TERMINAL
NAME DESCRIPTIONTYPE†
INITIALIZATION, INTERRUPT, AND RESET OPERATIONS (CONTINUED)
RS IReset. RS causes the digital signal processor (DSP) to terminate execution and causes a reinitialization of the
CPU and peripherals. When RS is brought to a high level, execution begins at location 0FF80h of program
memory. RS affects various registers and status bits.
MP/MC I
Microprocessor/microcomputer mode select. If active low at reset, microcomputer mode is selected, and the
internal program ROM is mapped into the upper 4K words of program memory space. If the pin is driven high
during reset, microprocessor mode is selected, and the on-chip ROM is removed from program space. This pin
is only sampled at reset, and the MP/MC bit of the processor mode status (PMST) register can override the mode
that is selected at reset.
MULTIPROCESSING SIGNALS
BIO I Branch control. A branch can be conditionally executed when BIO is active. If low, the processor executes the
conditional instruction. For the XC instruction, the BIO condition is sampled during the decode phase of the
pipeline; all other instructions sample BIO during the read phase of the pipeline.
XF O/Z
External flag output (latched software-programmable signal). XF is set high by the SSBX XF instruction, set low
by the RSBX XF instruction or by loading ST1. XF is used for signaling other processors in multiprocessor
configurations or used as a general-purpose output pin. XF goes into the high-impedance state when OFF is
low, and is set high at reset.
MEMORY CONTROL SIGNALS
DS
PS
IS O/Z
Data, program, and I/O space select signals. DS, PS, and IS are always high unless driven low for accessing
a particular external memory space. Active period corresponds to valid address information. DS, PS, and IS are
placed into the high-impedance state in the hold mode; the signals also go into the high-impedance state when
OFF is low.
MSTRB O/Z Memory strobe signal. MSTRB is always high unless low-level asserted to indicate an external bus access to
data or program memory. MSTRB is placed in the high-impedance state in the hold mode; it also goes into the
high-impedance state when OFF is low.
READY I
Data ready. READY indicates that an external device is prepared for a bus transaction to be completed. If the
device is not ready (READY is low), the processor waits one cycle and checks READY again. Note that the
processor performs ready detection if at least two software wait states are programmed. The READY signal is
not sampled until the completion of the software wait states.
R/W O/Z Read/write signal. R/W indicates transfer direction during communication to an external device. R/W is normally
in the read mode (high), unless it is asserted low when the DSP performs a write operation. R/W is placed in
the high-impedance state in hold mode; it also goes into the high-impedance state when OFF is low.
IOSTRB O/Z I/O strobe signal. IOSTRB is always high unless low-level asserted to indicate an external bus access to an I/O
device. IOSTRB is placed in the high-impedance state in the hold mode; it also goes into the high-impedance
state when OFF is low.
HOLD I Hold. HOLD is asserted to request control of the address, data, and control lines. When acknowledged by the
’C54x, these lines go into the high-impedance state.
HOLDA O/Z Hold acknowledge. HOLDA indicates that the 5402 is in a hold state and that the address, data, and control lines
are in the high-impedance state, allowing the external memory interface to be accessed by other devices.
HOLDA also goes into the high-impedance state when OFF is low.
†I = input, O = output, Z = high impedance, S = supply
‡All revisions of the 5402 can be operated with an external clock source, provided that the proper voltage levels be driven on the X2/CLKIN
pin. It should be noted that the X2/CLKIN pin is referenced to the device 1.8V power supply (CVDD), rather than the 3V I/O supply (DVDD).
Refer to the recommended operating conditions section of this document for the allowable voltage levels of the X2/CLKIN pin.
§Although this pin includes an internal pulldown resistor, a 470-Ω external pulldown is required. If the TRST pin is connected to multiple DSPs,
a buffer is recommended to ensure the VIL and VIH specifications are met.
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Terminal Functions (Continued)
TERMINAL
NAME DESCRIPTIONTYPE†
TERMINAL
NAME DESCRIPTIONTYPE†
MEMORY CONTROL SIGNALS (CONTINUED)
MSC O/Z
Microstate complete. MSC indicates completion of all software wait states. When two or more software wait
states are enabled, the MSC pin goes active at the beginning of the first software wait state and goes inactive
high at the beginning of the last software wait state. If connected to the READY input, MSC forces one external
wait state after the last internal wait state is completed. MSC also goes into the high-impedance state when OFF
is low.
IAQ O/Z Instruction acquisition signal. IAQ is asserted (active low) when there is an instruction address on the address
bus. IAQ goes into the high-impedance state when OFF is low.
OSCILLATOR/TIMER SIGNALS
CLKOUT O/Z Master clock output signal. CLKOUT cycles at the machine-cycle rate of the CPU. The internal machine cycle
is bounded by rising edges of this signal. CLKOUT also goes into the high-impedance state when OFF is low.
CLKMD1
CLKMD2
CLKMD3 I
Clock mode select signals. These inputs select the mode that the clock generator is initialized to after reset. The
logic levels of CLKMD1–CLKMD3 are latched when the reset pin is low, and the clock mode register is initialized
to the selected mode. After reset, the clock mode can be changed through software, but the clock mode select
signals have no effect until the device is reset again.
X2/CLKIN I
Oscillator input. This is the input to the on-chip oscillator.
If the internal oscillator is not used, X2/CLKIN functions as the clock input, and can be driven by an external clock
source.‡
X1 O
Output pin from the internal oscillator for the crystal.
If the internal oscillator is not used, X1 should be left unconnected. X1 does not go into the high-impedance state
when OFF is low.‡
TOUT0 O/Z Timer0 output. TOUT0 signals a pulse when the on-chip timer 0 counts down past zero. The pulse is a CLKOUT
cycle wide. TOUT0 also goes into the high-impedance state when OFF is low.
TOUT1 O/Z Timer1 output. TOUT1 signals a pulse when the on-chip timer1 counts down past zero. The pulse is one
CLKOUT cycle wide. The TOUT1 output is multiplexed with the HINT pin of the HPI and is only available when
the HPI is disabled. TOUT1 also goes into the high-impedance state when OFF is low.
MULTICHANNEL BUFFERED SERIAL PORT SIGNALS
BCLKR0
BCLKR1 I/O/Z Receive clock input. BCLKR can be configured as an input or an output; it is configured as an input following
reset. BCLKR serves as the serial shift clock for the buffered serial port receiver.
BDR0
BDR1 ISerial data receive input
BFSR0
BFSR1 I/O/Z Frame synchronization pulse for receive input. BFSR can be configured as an input or an output; it is configured
as an input following reset. The BFSR pulse initiates the receive data process over BDR.
BCLKX0
BCLKX1 I/O/Z T ransmit clock. BCLKX serves as the serial shift clock for the McBSP transmitter. BCLKX can be configured as
an input or an output; it is configured as an input following reset. BCLKX enters the high-impedance state when
OFF goes low.
BDX0
BDX1 O/Z Serial data transmit output. BDX is placed in the high-impedance state when not transmitting, when RS is
asserted, or when OFF is low.
BFSX0
BFSX1 I/O/Z Frame synchronization pulse for transmit input/output. The BFSX pulse initiates the transmit data process. BFSX
can be configured as an input or an output; it is configured as an input following reset. BFSX goes into the
high-impedance state when OFF is low.
MISCELLANEOUS SIGNAL
NC No connection
†I = input, O = output, Z = high impedance, S = supply
‡All revisions of the 5402 can be operated with an external clock source, provided that the proper voltage levels be driven on the X2/CLKIN
pin. It should be noted that the X2/CLKIN pin is referenced to the device 1.8V power supply (CVDD), rather than the 3V I/O supply (DVDD).
Refer to the recommended operating conditions section of this document for the allowable voltage levels of the X2/CLKIN pin.
§Although this pin includes an internal pulldown resistor, a 470-Ω external pulldown is required. If the TRST pin is connected to multiple DSPs,
a buffer is recommended to ensure the VIL and VIH specifications are met.
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Terminal Functions (Continued)
TERMINAL
NAME DESCRIPTIONTYPE†
TERMINAL
NAME DESCRIPTIONTYPE†
HOST-PORT INTERFACE SIGNALS
HD0−HD7 I/O/Z
Parallel bidirectional data bus. The HPI data bus is used by a host device bus to exchange information with the
HPI registers. These pins can also be used as general-purpose I/O pins. HD0−HD7 is placed in the
high-impedance state when not outputting data or when OFF is low. The HPI data bus includes bus holders to
reduce the static power dissipation caused by floating, unused pins. When the HPI data bus is not being driven
by the 5402, the bus holders keep the pins at the previous logic level. The HPI data bus holders are disabled
at reset and can be enabled/disabled via the HBH bit of the BSCR.
HCNTL0
HCNTL1 IControl. HCNTL0 and HCNTL1 select a host access to one of the three HPI registers. The control inputs have
internal pullup resistors that are only enabled when HPIENA = 0.
HBIL I Byte identification. HBIL identifies the first or second byte of transfer. The HBIL input has an internal pullup
resistor that is only enabled when HPIENA = 0.
HCS I Chip select. HCS is the select input for the HPI and must be driven low during accesses. The chip-select input
has an internal pullup resistor that is only enabled when HPIENA = 0.
HDS1
HDS2 IData strobe. HDS1 and HDS2 are driven by the host read and write strobes to control transfers. The strobe inputs
have internal pullup resistors that are only enabled when HPIENA = 0.
HAS I Address strobe. Hosts with multiplexed address and data pins require HAS to latch the address in the HPIA
register. HAS has an internal pullup resistor that is only enabled when HPIENA = 0.
HR/W I Read/write. HR/W controls the direction of an HPI transfer. R/W has an internal pullup resistor that is only
enabled when HPIENA = 0.
HRDY O/Z Ready. The ready output informs the host when the HPI is ready for the next transfer. HRDY goes into the
high-impedance state when OFF is low.
HINT O/Z Host interrupt. This output is used to interrupt the host. When the DSP is in reset, HINT is driven high. HINT can
also be configured as the timer 1 output (TOUT1), when the HPI is disabled. The signal goes into the
high-impedance state when OFF is low.
HPIENA I
HPI module select. HPIENA must be driven high during reset to enable the HPI. An internal pulldown resistor
is always active and the HPIENA pin is sampled on the rising edge of RS. If HPIENA is left open or is driven low
during reset, the HPI module is disabled. Once the HPI is disabled, the HPIENA pin has no effect unt i l t h e 5 4 0 2
is reset.
SUPPLY PNS
CVDD S +VDD. Dedicated 1.8-V power supply for the core CPU
DVDD S +VDD. Dedicated 3.3-V power supply for the I/O pins
VSS S Ground
TEST PINS
TCK I
IEEE standard 1149.1 test clock. TCK is normally a free-running clock signal with a 50% duty cycle. The changes
on the test access port (TAP) of input signals TMS and TDI are clocked into the TAP controller, instruction
register, o r selected test data register on the rising edge of TCK. Changes at the TAP output signal (TDO) occur
on the falling edge of TCK.
TDI I IEEE standard 1149.1 test data input pin with internal pullup device. TDI is clocked into the selected register
(instruction or data) on a rising edge of TCK.
TDO O/Z IEEE standard 1149.1 test data output. The contents of the selected register (instruction or data) are shifted out
of TDO on the falling edge of TCK. TDO is in the high-impedance state except when the scanning of data is in
progress. TDO also goes into the high-impedance state when OFF is low.
TMS I IEEE standard 1149.1 test mode select. Pin with internal pullup device. This serial control input is clocked into
the TAP controller on the rising edge of TCK.
†I = input, O = output, Z = high impedance, S = supply
‡All revisions of the 5402 can be operated with an external clock source, provided that the proper voltage levels be driven on the X2/CLKIN
pin. It should be noted that the X2/CLKIN pin is referenced to the device 1.8V power supply (CVDD), rather than the 3V I/O supply (DVDD).
Refer to the recommended operating conditions section of this document for the allowable voltage levels of the X2/CLKIN pin.
§Although this pin includes an internal pulldown resistor, a 470-Ω external pulldown is required. If the TRST pin is connected to multiple DSPs,
a buffer is recommended to ensure the VIL and VIH specifications are met.
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Terminal Functions (Continued)
TERMINAL
NAME DESCRIPTIONTYPE†
TERMINAL
NAME DESCRIPTIONTYPE†
TEST PINS (CONTINUED)
TRST§IIEEE standard 1149.1 test reset. TRST, when high, gives the IEEE standard 1149.1 scan system control of the
operations o f the device. If TRST is driven low, the device operates in its functional mode, and the IEEE standard
1149.1 signals are ignored. Pin with internal pulldown device.
EMU0 I/O/Z Emulator 0 pin. When TRST is driven low, EMU0 must be high for activation of the OFF condition. When TRST
is driven high, EMU0 is used as an interrupt to or from the emulator system and is defined as input/output by
way of the IEEE standard 1149.1 scan system.
EMU1/OFF I/O/Z
Emulator 1 pin/disable all outputs. When TRST is driven high, EMU1/OFF is used as an interrupt to or from the
emulator system and is defined as input/output by way of the IEEE standard 1149.1 scan system. When TRST
is driven low, EMU1/OFF is configured as OFF. The EMU1/OFF signal, when active low, puts all output drivers
into the high-impedance state. Note that OFF is used exclusively for testing and emulation purposes (not for
multiprocessing applications). The OFF feature is selected by the following pin combinations:
TRST = low
EMU0 = high
EMU1/OFF = low
†I = input, O = output, Z = high impedance, S = supply
‡All revisions of the 5402 can be operated with an external clock source, provided that the proper voltage levels be driven on the X2/CLKIN
pin. It should be noted that the X2/CLKIN pin is referenced to the device 1.8V power supply (CVDD), rather than the 3V I/O supply (DVDD).
Refer to the recommended operating conditions section of this document for the allowable voltage levels of the X2/CLKIN pin.
§Although this pin includes an internal pulldown resistor, a 470-Ω external pulldown is required. If the TRST pin is connected to multiple DSPs,
a buffer is recommended to ensure the VIL and VIH specifications are met.
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memory
The 5402 device provides both on-chip ROM and RAM memories to aid in system performance and integration.
on-chip ROM with bootloader
The 5402 features a 4K-word ×16-bit on-chip maskable ROM. Customers can arrange to have the ROM of the
5402 programmed with contents unique to any particular application. A security option is available to protect
a custom ROM. This security option is described in the TMS320C54x DSP CPU and Peripherals Reference Set,
V olume 1 (literature number SPRU131). Note that only the ROM security option, and not the ROM/RAM option,
is available on the 5402 .
A bootloader is available in the standard 5402 on-chip ROM. This bootloader can be used to automatically
transfer user code from an external source to anywhere in the program memory at power up. If the MP/MC pin
is sampled low during a hardware reset, execution begins at location FF80h of the on-chip ROM. This location
contains a branch instruction to the start of the bootloader program. The standard 5402 bootloader provides
different ways to download the code to accomodate various system requirements:
DParallel from 8-bit or 16-bit-wide EPROM
DParallel from I/O space 8-bit or 16-bit mode
DSerial boot from serial ports 8-bit or 16-bit mode
DHost-port interface boot
The standard on-chip ROM layout is shown in Table 1.
Table 1. Standard On-Chip ROM Layout†
ADDRESS RANGE DESCRIPTION
F000h − F7FFh Reserved
F800h − FBFFh Bootloader
FC00h − FCFFh µ-law expansion table
FD00h − FDFFh A-law expansion table
FE00h − FEFFh Sine look-up table
FF00h − FF7Fh Reserved
FF80h − FFFFh Interrupt vector table
†In the ’VC5402 ROM, 128 words are reserved for factory device-testing purposes. Application
code to be implemented in on-chip ROM must reserve these 128 words at addresses
FF00h–FF7Fh in program space.
on-chip RAM
The 5402 device contains 16K ×16-bit of on-chip dual-access RAM (DARAM). The DARAM is composed of two
blocks of 8K words each. Each block in the DARAM can support two reads in one cycle, or a read and a write
in one cycle. The DARAM is located in the address range 0060h−3FFFh in data space, and can be mapped
into program/data space by setting the OVLY bit to one.
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memory map
Page 0 Program
Hex Data
On-Chip DARAM
(OVLY = 1)
External
(OVLY = 0)
MP/MC= 0
(Microcomputer Mode)
MP/MC= 1
(Microprocessor Mode)
0000
007F
0080
FFFF
Reserved
(OVLY = 1)
External
(OVLY = 0)
Interrupts
(External)
FF80
Memory
Mapped
Registers
On-Chip DARAM
(16K x 16-bit)
ROM (DROM=1)
or External
(DROM=0)
0080
FFFF
Hex
0000
FF7F FF00
FEFF
EFFF
F000
FFFF
3FFF
4000
0060
007F
0000
Hex
Page 0 Program
External
External
Scratch-Pad
RAM
Reserved
(DROM=1)
or External
(DROM=0)
005F
Reserved
(OVLY = 1)
External
(OVLY = 0)
007F
0080
3FFF
4000
On-Chip DARAM
(OVLY = 1)
External
(OVLY = 0)
FF00
FEFF
EFFF
F000
External
On-Chip ROM
(4K x 16-bit)
Interrupts
(On-Chip)
3FFF
4000
Reserved
FF7F
FF80
Figure 1. Memory Map
relocatable interrupt vector table
The reset, interrupt, and trap vectors are addressed in program space. These vectors are soft — meaning that
the processor, when taking the trap, loads the program counter (PC) with the trap address and executes the
code at the vector location. Four words are reserved at each vector location to accommodate a delayed branch
instruction, either two 1-word instructions or one 2-word instruction, which allows branching to the appropriate
interrupt service routine with minimal overhead.
At device reset, the reset, interrupt, and trap vectors are mapped to address FF80h in program space. However,
these vectors can be remapped to the beginning of any 128-word page in program space after device reset.
This is done by loading the interrupt vector pointer (IPTR) bits in the PMST register (see Figure 2) with the
appropriate 128-word page boundary address. After loading IPTR, any user interrupt or trap vector is mapped
to the new 128-word page.
NOTE: The hardware reset (RS) vector cannot be remapped because a hardware reset loads the IPTR
with 1s. Therefore, the reset vector is always fetched at location FF80h in program space.
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relocatable interrupt vector table (continued)
15 76543210
IPTR MP/MC OVLY AVIS DROM CLK
OFF SMUL SST
R/W R/W R/W R R R R/W R/W
LEGEND: R = Read, W = Write
Figure 2. Processor Mode Status (PMST) Registers
extended program memory
The 5402 uses a paged extended memory scheme in program space to allow access of up to 1024K program
memory locations. In order to implement this scheme, the 5402 includes several features that are also present
on the 548/549 devices:
DTwenty address lines, instead of sixteen
DAn extra memory-mapped register, the XPC register, defines the page selection. This register is
memory-mapped into data space to address 001Eh. At a hardware reset, the XPC is initialized to 0.
DSix extra instructions for addressing extended program space. These six instructions affect the XPC.
−FB[D] pmad (20 bits) − Far branch
−FBACC[D] Accu[19:0] − Far branch to the location specified by the value in accumulator A or
accumulator B
−FCALL[D] pmad (20 bits) − Far call
−FCALA[D] Accu[19:0] − Far call to the location specified by the value in accumulator A or accumulator B
−FRET[D] − Far return
−FRETE[D] − Far return with interrupts enabled
DIn addition to these new instructions, two 54x instructions are extended to use 20 bits in the 5402:
− READA data_memory (using 20-bit accumulator address)
− WRITA data_memory (using 20-bit accumulator address)
All other instructions, software interrupts and hardware interrupts do not modify the XPC register and access
only memory within the current page.
Program memory in the 5402 is organized into 16 pages that are each 64K in length, as shown in Figure 3.
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extended program memory (continued)
0 0000 1 0000
1 3FFF
Page 1
Lower
16K}
External
2 0000
2 3FFF
Page 2
Lower
16K}
External
. . .
. . .
F 0000
F 3FFF
Page 15
Lower
16K}
External
0 FFFF
Page 0
64K
Words{
1 4000
1 FFFF
Page 1
Upper
48K
External
2 4000
2 FFFF
Page 2
Upper
48K
External
. . .
. . .
F 4000
F FFFF
Page 15
Upper
48K
External
†See Figure 1
‡The lower 16K words of pages 1 through 15 are available only when the OVLY bit is cleared to 0. If the OVLY bit is set to 1, the on-chip RAM
is mapped to the lower 16K words of all program space pages.
Figure 3. Extended Program Memory
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on-chip peripherals
The 5402 device has the following peripherals:
DSoftware-programmable wait-state generator with programmable bank-switching wait states
DAn enhanced 8-bit host-port interface (HPI8)
DTwo multichannel buffered serial ports (McBSPs)
DTwo hardware timers
DA clock generator with a phase-locked loop (PLL)
DA direct memory access (DMA) controller
software-programmable wait-state generator
The software wait-state generator of the 5402 can extend external bus cycles by up to fourteen machine cycles.
Devices that require more than fourteen wait states can be interfaced using the hardware READY line. When
all external accesses are configured for zero wait states, the internal clocks to the wait-state generator are
automatically disabled. Disabling the wait-state generator clocks reduces the power comsumption of the 5402.
The software wait-state register (SWWSR) controls the operation of the wait-state generator. The 14 LSBs of
the SWWSR specify the number of wait states (0 to 7) to be inserted for external memory accesses to five
separate address ranges. This allows a different number of wait states for each of the five address ranges.
Additionally, the software wait-state multiplier (SWSM) bit of the software wait-state control register (SWCR)
defines a multiplication factor of 1 or 2 for the number of wait states. At reset, the wait-state generator is initialized
to provide seven wait states on all external memory accesses. The SWWSR bit fields are shown in Figure 4
and described in Table 2.
XPA I/O Data Data Program Program
14 12 11 9 8 6 5 3 2 015
R/W-111R/W-0 R/W-111 R/W-111 R/W-111 R/W-111
LEGEND: R=Read, W=Write, 0=Value after reset
Figure 4. Software Wait-State Register (SWWSR) [Memory-Mapped Register (MMR) Address 0028h]
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software-programmable wait-state generator (continued)
Table 2. Software Wait-State Register (SWWSR) Bit Fields
BIT
RESET
FUNCTION
NO. NAME
RESET
VALUE
FUNCTION
15 XPA 0 Extended program address control bit. XPA is used in conjunction with the program space fields
(bits 0 through 5) to select the address range for program space wait states.
14−12 I/O 1 I/O space. The field value (0−7) corresponds to the base number of wait states for I/O space accesses
within addresses 0000−FFFFh. The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for
the base number of wait states.
11−9 Data 1 Upper data space. The field value (0−7) corresponds to the base number of wait states for external
data space accesses within addresses 8000−FFFFh. The SWSM bit of the SWCR defines a
multiplication factor of 1 or 2 for the base number of wait states.
8−6 Data 1 Lower data space. The field value (0−7) corresponds to the base number of wait states for external
data space accesses within addresses 0000−7FFFh. The SWSM bit of the SWCR defines a
multiplication factor of 1 or 2 for the base number of wait states.
5−3 Program 1
Upper program space. The field value (0−7) corresponds to the base number of wait states for external
program space accesses within the following addresses:
-XPA = 0: x8000 − xFFFFh
-XPA = 1: The upper program space bit field has no effect on wait states.
The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait
states.
2−0 Program 1
Program space. The field value (0−7) corresponds to the base number of wait states for external
program space accesses within the following addresses:
-XPA = 0: x0000−x7FFFh
-XPA = 1: 00000−FFFFFh
The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait
states.
The software wait-state multiplier bit of the software wait-state control register (SWCR) is used to extend the
base number of wait states selected by the SWWSR. The SWCR bit fields are shown in Figure 5 and described
in Table 3.
Reserved
115
R/W-0
SWSM
0
R/W-0
LEGEND: R = Read, W = Write
Figure 5. Software Wait-State Control Register (SWCR) [MMR Address 002Bh]
Table 3. Software Wait-State Control Register (SWCR) Bit Fields
PIN
RESET
FUNCTION
NO. NAME
RESET
VALUE
FUNCTION
15−1 Reserved 0 These bits are reserved and are unaffected by writes.
0 SWSM 0
Software wait-state multiplier. Used to multiply the number of wait states defined in the SWWSR by a factor
of 1 or 2.
-SWSM = 0: wait-state base values are unchanged (multiplied by 1).
-SWSM = 1: wait-state base values are mulitplied by 2 for a maximum of 14 wait states.
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programmable bank-switching wait states
The programmable bank-switching logic of the 5402 is functionally equivalent to that of the 548/549 devices.
This feature automatically inserts one cycle when accesses cross memory-bank boundaries within program or
data memory space. A bank-switching wait state can also be automatically inserted when accesses cross the
data space boundary into program space.
The bank-switching control register (BSCR) defines the bank size for bank-switching wait states. Figure 6
shows the BSCR and its bits are described in Table 4.
BNKCMP PS-DS Reserved HBH
12 11 3 2 115
R/W-0R-0R/W-1R/W-1111
BH EXIO
010
R/W-0R/W-0
LEGEND: R = Read, W = Write
Figure 6. Bank-Switching Control Register (BSCR), MMR Address 0029h
Table 4. Bank-Switching Control Register (BSCR) Fields
BIT RESET
VALUE
FUNCTION
NO. NAME
RESET
VALUE
FUNCTION
15−12 BNKCMP 1111 Bank compare. Determines the external memory-bank size. BNKCMP is used to mask the four MSBs of
an address. For example, if BNKCMP = 1111b, the four MSBs (bits 12−15) are compared, resulting in a
bank size of 4K words. Bank sizes of 4K words to 64K words are allowed.
11 PS - DS 1
Program read − data read access. Inserts an extra cycle between consecutive accesses of program read
and data read or data read and program read.
PS-DS = 0 No extra cycles are inserted by this feature.
PS-DS = 1 One extra cycle is inserted between consecutive data and program reads.
10−3 Reserved 0 These bits are reserved and are unaffected by writes.
2 HBH 0
HPI Bus holder. Controls the HPI bus holder feature. HBH is cleared to 0 at reset.
HBH = 0 The bus holder is disabled.
HBH = 1 The bus holder is enabled. When not driven, the HPI data bus (HD[7:0]) is held in the
previous logic level.
1 BH 0
Bus holder. Controls the data bus holder feature. BH is cleared to 0 at reset.
BH = 0 The bus holder is disabled.
BH = 1 The bus holder is enabled. When not driven, the data bus (D[15:0]) is held in the
previous logic level.
External bus interface off. The EXIO bit controls the external bus-off function.
EXIO = 0 The external bus interface functions as usual.
0 EXIO 0
EXIO = 0 The external bus interface functions as usual.
EXIO = 1 The address bus, data bus, and control signals become inactive after completing the
current bus cycle. Note that the DROM, MP/MC, and OVLY bits in the PMST and the HM
current bus cycle. Note that the DROM, MP/MC, and OVLY bits in the PMST and the HM
bit of ST1 cannot be modified when the interface is disabled.
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parallel I/O ports
The 5402 has a total of 64K I/O ports. These ports can be addressed by the PORTR instruction or the PORTW
instruction. The IS signal indicates a read/write operation through an I/O port. The 5402 can interface easily with
external devices through the I/O ports while requiring minimal off-chip address-decoding circuits.
enhanced 8-bit host-port interface
The 5402 host-port interface, also referred to as the HPI8, is an enhanced version of the standard 8-bit HPI
found on earlier 54x DSPs (542, 545, 548, and 549). The HPI8 is an 8-bit parallel port for interprocessor
communication. The features of the HPI8 include:
Standard features:
DSequential transfers (with autoincrement) or random-access transfers
DHost interrupt and 54x interrupt capability
DMultiple data strobes and control pins for interface flexibility
Enhanced features of the 5402 HPI8:
DAccess to entire on-chip RAM through DMA bus
DCapability to continue transferring during emulation stop
The HPI8 functions as a slave and enables the host processor to access the on-chip memory of the 5402. A
major enhancement to the 5402 HPI over previous versions is that it allows host access to the entire on-chip
memory range of the DSP. The HPI8 memory map is identical to that of the DMA controller shown in Figure 7.
The host and the DSP both have access to the on-chip RAM at all times and host accesses are always
synchronized to the DSP clock. If the host and the DSP contend for access to the same location, the host has
priority, and the DSP waits for one HPI8 cycle. Note that since host accesses are always synchronized to the
5402 clock, an active input clock (CLKIN) is required for HPI8 accesses during IDLE states, and host accesses
are not allowed while the 5402 reset pin is asserted.
The HPI8 interface consists of an 8-bit bidirectional data bus and various control signals. Sixteen-bit transfers
are accomplished in two parts with the HBIL input designating high or low byte. The host communicates with
the HPI8 through three dedicated registers — HPI address register (HPIA), HPI data register (HPID), and an
HPI control register (HPIC). The HPIA and HPID registers are only accessible by the host, and the HPIC register
is accessible by both the host and the 5402.
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multichannel buffered serial ports
The 5402 device includes two high-speed, full-duplex multichannel buffered serial ports (McBSPs) that allow
direct interface to other ’C54x/’LC54x devices, codecs, and other devices in a system. The McBSPs are based
on the standard serial port interface found on other 54x devices. Like its predecessors, the McBSP provides:
DFull-duplex communication
DDouble-buffered data registers, which allow a continuous data stream
DIndependent framing and clocking for receive and transmit
In addition, the McBSP has the following capabilities:
DDirect interface to:
− T1/E1 framers
− MVIP switching compatible and ST-BUS compliant devices
− IOM-2 compliant devices
− Serial peripheral interface devices
DMultichannel transmit and receive of up to 128 channels
DA wide selection of data sizes including 8, 12, 16, 20, 24, or 32 bits
Dµ-law and A-law companding
DProgrammable polarity for both frame synchronization and data clocks
DProgrammable internal clock and frame generation
The McBSPs consist of separate transmit and receive channels that operate independently. The external
interface of each McBSP consists of the following pins:
DBCLKX Transmit reference clock
DBDX Transmit data
DBFSX Transmit frame synchronization
DBCLKR Receive reference clock
DBDR Receive data
DBFSR Receive frame synchronization
The six pins listed are functionally equivalent to previous serial port interface pins in the ’C5000 family of DSPs.
On the transmitter, transmit frame synchronization and clocking are indicated by the BFSX and BCLKX pins,
respectively. The CPU or DMA can initiate transmission of data by writing to the data transmit register (DXR).
Data written to DXR is shifted out on the BDX pin through a transmit shift register (XSR). This structure allows
DXR to be loaded with the next word to be sent while the transmission of the current word is in progress.
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multichannel buffered serial ports (continued)
On the receiver, receive frame synchronization and clocking are indicated by the BFSR and BCLKR pins,
respectively. The CPU or DMA can read received data from the data receive register (DRR). Data received on
the BDR pin is shifted into a receive shift register (RSR) and then buffered in the receive buffer register (RBR).
If the DRR is empty, the RBR contents are copied into the DRR. If not, the RBR holds the data until the DRR
is available. This structure allows storage of the two previous words while the reception of the current word is
in progress.
The CPU and DMA can move data to and from the McBSPs and can synchronize transfers based on McBSP
interrupts, event signals, and status flags. The DMA is capable of handling data movement between the
McBSPs and memory with no intervention from the CPU.
In addition to the standard serial port functions, the McBSP provides programmable clock and frame
synchronization signals. The programmable functions include:
DFrame synchronization pulse width
DFrame period
DFrame synchronization delay
DClock reference (internal vs. external)
DClock division
DClock and frame synchronization polarity
The on-chip companding hardware allows compression and expansion of data in either µ-law or A-law format.
When companding is used, transmit data is encoded according to specified companding law and received data
is decoded to 2s complement format.
The McBSP allows the multiple channels to be independently selected for the transmitter and receiver. When
multiple channels are selected, each frame represents a time-division multiplexed (TDM) data stream. In using
TDM data streams, the CPU may only need to process a few of them. Thus, to save memory and bus bandwidth,
multichannel selection allows independent enabling of particular channels for transmission and reception. Up
to 32 channels in a stream of up to 128 channels can be enabled.
The clock-stop mode (CLKSTP) in the McBSP provides compatibility with the serial peripheral interface (SPI)
protocol. The word sizes supported by the McBSP are programmable for 8-, 12-, 16-, 20-, 24-, or 32-bit
operation. When the McBSP is configured to operate in SPI mode, both the transmitter and the receiver operate
together as a master or as a slave.
The McBSP is fully static and operates at arbitrarily low clock frequencies. The maximum frequency is CPU
clock frequency divided by 2.
hardware timer
The 5402 device features two 16-bit timing circuits with 4-bit prescalers. The main counter of each timer is
decremented by one every CLKOUT cycle. Each time the counter decrements to 0, a timer interrupt is
generated. The timers can be stopped, restarted, reset, or disabled by specific control bits.
clock generator
The clock generator provides clocks to the 5402 device, and consists of an internal oscillator and a phase-locked
loop (PLL) circuit. The clock generator requires a reference clock input, which can be provided by using a crystal
resonator with the internal oscillator, or from an external clock source.
NOTE:All revisions of the 5402 can be operated with an external clock source, provided that the proper voltage
levels be driven on the X2/CLKIN pin. It should be noted that the X2/CLKIN pin is referenced to the device 1.8V
power supply (CVdd), rather than the 3V I/O supply (DVdd). Refer to the recommended operating conditions
section of this document for the allowable voltage levels of the X2/CLKIN pin.
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clock generator (continued)
The reference clock input is then divided by two (DIV mode) to generate clocks for the 5402 device, or the PLL
circuit can be used (PLL mode) to generate the device clock by multiplying the reference clock frequency by
a scale factor , allowing use of a clock source with a lower frequency than that of the CPU.The PLL is an adaptive
circuit that, once synchronized, locks onto and tracks an input clock signal.
When the PLL is initially started, it enters a transitional mode during which the PLL acquires lock with the input
signal. Once the PLL is locked, it continues to track and maintain synchronization with the input signal. Then,
other internal clock circuitry allows the synthesis of new clock frequencies for use as master clock for the 5402
device.
This clock generator allows system designers to select the clock source. The sources that drive the clock
generator are:
DA crystal resonator circuit. The crystal resonator circuit is connected across the X1 and X2/CLKIN pins of
the 5402 to enable the internal oscillator.
DAn external clock. The external clock source is directly connected to the X2/CLKIN pin, and X1 is left
unconnected.
NOTE: All revisions of the 5402 can be operated with an external clock source, provided that the proper voltage
levels be driven on the X2/CLKIN pin. It should be noted that the X2/CLKIN pin is referenced to the device 1.8V
power supply (CVdd), rather than the 3V I/O supply (DVdd). Refer to the recommended operating conditions
section of this document for the allowable voltage levels of the X2/CLKIN pin.
The software-programmable PLL features a high level of flexibility, and includes a clock scaler that provides
various clock multiplier ratios, capability to directly enable and disable the PLL, and a PLL lock timer that can
be used to delay switching to PLL clocking mode of the device until lock is achieved.Devices that have a built-in
software-programmable PLL can be configured in one of two clock modes:
DPLL mode. The input clock (X2/CLKIN) is multiplied by 1 of 31 possible ratios. These ratios are achieved
using the PLL circuitry.
DDIV (divider) mode. The input clock is divided by 2 or 4. Note that when DIV mode is used, the PLL can be
completely disabled in order to minimize power dissipation.
The software-programmable PLL is controlled using the 16-bit memory-mapped (address 0058h) clock mode
register (CLKMD). The CLKMD register is used to define the configuration of the PLL clock module. Upon reset,
the CLKMD register is initialized with a predetermined value dependent only upon the state of the CLKMD1 −
CLKMD3 pins as shown in Table 5.
Table 5. Clock Mode Settings at Reset
CLKMD1 CLKMD2 CLKMD3 CLKMD
RESET VALUE
CLOCK MODE
CLKMD1
CLKMD2
CLKMD3
RESET VALUE
CLOCK MODE
0 0 0 E007h PLL x 15
0 0 1 9007h PLL x 10
0 1 0 4007h PLL x 5
1 0 0 1007h PLL x 2
1 1 0 F007h PLL x 1
1 1 1 0000h 1/2 (PLL disabled)
1 0 1 F000h 1/4 (PLL disabled)
0 1 1 — Reserved (bypass mode)
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DMA controller
The 5402 direct memory access (DMA) controller transfers data between points in the memory map without
intervention by the CPU. The DMA controller allows movements of data to and from internal program/data
memory or internal peripherals (such as the McBSPs) to occur in the background of CPU operation. The DMA
has six independent programmable channels allowing six different contexts for DMA operation.
features
The DMA has the following features:
DThe DMA operates independently of the CPU.
DThe DMA has six channels. The DMA can keep track of the contexts of six independent block transfers.
DThe DMA has higher priority than the CPU for internal accesses.
DEach channel has independently programmable priorities.
DEach channel’s source and destination address registers can have configurable indexes through memory
on each read and write transfer, respectively. The address may remain constant, be post-incremented,
post-decremented, or be adjusted by a programmable value.
DEach read or write transfer may be initialized by selected events.
DUpon completion of a half-block or an entire-block transfer, each DMA channel may send an interrupt to the
CPU.
DThe DMA can perform double-word transfers (a 32-bit transfer of two 16-bit words).
DMA memory map
The DMA memory map is shown in Figure 7 to allow DMA transfers to be unaffected by the status of the MPMC,
DROM, and OVLY bits.
FFFF
Reserved
4000
3FFF
Hex
0000
005F
0060
On-Chip DARAM
Scratch-Pad
0080
007F
(16K x 16-bit)
RAM
Reserved
McBSP
Registers
001F
0020
0023
0024
Reserved
Figure 7. 5402 DMA Memory Map
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DMA priority level
Each DMA channel can be independently assigned high priority or low priority relative to each other. Multiple
DMA channels that are assigned to the same priority level are handled in a round-robin manner.
DMA source/destination address modification
The DMA provides flexible address-indexing modes for easy implementation of data management schemes
such as autobuffering and circular buffers. Source and destination addresses can be indexed separately and
can be post-incremented, post-decremented, or post-incremented with a specified index offset.
DMA in autoinitialization mode
The DMA can automatically reinitialize itself after completion of a block transfer. Some of the DMA registers can
be preloaded for the next block transfer through the DMA global reload registers (DMGSA, DMGDA, and
DMGCR). Autoinitialization allows:
DContinuous operation: Normally, the CPU would have to reinitialize the DMA immediately after the
completion of the current block transfer; but with the global reload registers, it can reinitialize these values
for the next block transfer any time after the current block transfer begins.
DRepetitive operation: The CPU does not preload the global reload register with new values for each block
transfer but only loads them on the first block transfer.
DMA transfer counting
The DMA channel element count register (DMCTRx) and the frame count register (DMSFCx) contain bit fields
that represent the number of frames and the number of elements per frame to be transferred.
DFrame count. This 8-bit value defines the total number of frames in the block transfer. The maximum number
of frames per block transfer is 128 (FRAME COUNT= 0ffh). The counter is decremented upon the last read
transfer in a frame transfer. Once the last frame is transferred, the selected 8-bit counter is reloaded with
the DMA global frame reload register (DMGFR) if the AUTOINIT bit is set to 1. A frame count of 0 (default
value) means the block transfer contains a single frame.
DElement count. This 16-bit value defines the number of elements per frame. This counter is decremented
after the read transfer of each element. The maximum number of elements per frame is 65536
(DMCTRn = 0FFFFh). In autoinitialization mode, once the last frame is transferred, the counter is reloaded
with the DMA global count reload register (DMGCR).
DMA transfers in double-word mode
Double-word mode allows the DMA to transfer 32-bit words in any index mode. In double-word mode, two
consecutive 16-bit transfers are initiated and the source and destination addresses are automatically updated
following each transfer. In this mode, each 32-bit word is considered to be one element.
DMA channel index registers
The particular DMA channel index register is selected by way of the SIND and DIND field in the DMA mode
control register (DMMCRx). Unlike basic address adjustment, in conjunction with the frame index DMFRI0 and
DMFRI1, the DMA allows different adjustment amounts depending on whether or not the element transfer is
the last in the current frame. The normal adjustment value (element index) is contained in the element index
registers DMIDX0 and DMIDX1. The adjustment value (frame index) for the end of the frame, is determined by
the selected DMA frame index register, either DMFRI0 or DMFRI1.
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DMA channel index registers (continued)
The element index and the frame index affect address adjustment as follows:
DElement index: For all except the last transfer in the frame, the element index determines the amount to be
added to the DMA channel for the source/destination address register (DMSRCx/DMDSTx) as selected by
the SIND/DIND bits.
DFrame index: If the transfer is the last in a frame, the frame index is used for address adjustment as selected
by the SIND/DIND bits. This occurs in both single-frame and multi-frame transfer.
DMA interrupts
The ability of the DMA to interrupt the CPU based on the status of the data transfer is configurable and is
determined by the IMOD and DINM bits in the DMA channel mode control register (DMMCRn). The available
modes are shown in Table 6.
Table 6. DMA Interrupts
MODE DINM IMOD INTERRUPT
ABU (non-decrement) 1 0 At full buffer only
ABU (non-decrement) 1 1 At half buffer and full buffer
Multi-Frame 1 0 At block transfer complete (DMCTRn = DMSEFCn[7:0] = 0)
Multi-Frame 1 1 At end of frame and end of block (DMCTRn = 0)
Either 0 X No interrupt generated
Either 0 X No interrupt generated
DMA controller synchronization events
The transfers associated with each DMA channel can be synchronized to one of several events. The DSYN bit
field of the DMA channel x sync select and frame count (DMSFCx) register selects the synchronization event
for a channel. The list of possible events and the DSYN values are shown in Table 7.
Table 7. DMA Synchronization Events
DSYN VALUE DMA SYNCHRONIZATION EVENT
0000b No synchronization used
0001b McBSP0 receive event
0010b McBSP0 transmit event
0011−0100b Reserved
0101b McBSP1 receive event
0110b McBSP1 transmit event
0111b−0110b Reserved
1101b Timer0 interrupt
1110b External interrupt 3
1111b Timer1 interrupt
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DMA channel interrupt selection
The DMA controller can generate a CPU interrupt for each of the six channels. However, the interrupt sources
for channels 0,1, 2, and 3 are multiplexed with other interrupt sources. DMA channels 2 and 3 share an interrupt
line with the receive and transmit portions of McBSP1 (IMR/IFR bits 10 and 11), and DMA channel 1 shares an
interrupt line with timer 1 (IMR/IFR bit 7). The interrupt source for DMA channel 0 is shared with a reserved
interrupt source. When the 5402 is reset, the interrupts from these four DMA channels are deselected. The
INTSEL bit field in the DMA channel priority and enable control (DMPREC) register can be used to select these
interrupts, as shown in Table 8.
Table 8. DMA Channel Interrupt Selection
INTSEL Value IMR/IFR[6] IMR/IFR[7] IMR/IFR[10] IMR/IFR[11]
00b (reset) Reserved TINT1 BRINT1 BXINT1
01b Reserved TINT1 DMAC2 DMAC3
10b DMAC0 DMAC1 DMAC2 DMAC3
11b Reserved
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memory-mapped registers
The 5402 has 27 memory-mapped CPU registers, which are mapped in data memory space addresses 0h to
1Fh. Table 9 gives a list of CPU memory-mapped registers (MMRs) available on 5402. The device also has a
set of memory-mapped registers associated with peripherals. Table 10, Table 11, and Table 12 show additional
peripheral MMRs associated with the 5402.
Table 9. CPU Memory-Mapped Registers
NAME
ADDRESS
DESCRIPTION
NAME
DEC HEX
DESCRIPTION
IMR 0 0 Interrupt mask register
IFR 1 1 Interrupt flag register
– 2−5 2−5 Reserved for testing
ST0 6 6 Status register 0
ST1 7 7 Status register 1
AL 8 8 Accumulator A low word (15−0)
AH 9 9 Accumulator A high word (31−16)
AG 10 A Accumulator A guard bits (39−32)
BL 11 BAccumulator B low word (15−0)
BH 12 C Accumulator B high word (31−16)
BG 13 D Accumulator B guard bits (39−32)
TREG 14 E Temporary register
TRN 15 F Transition register
AR0 16 10 Auxiliary register 0
AR1 17 11 Auxiliary register 1
AR2 18 12 Auxiliary register 2
AR3 19 13 Auxiliary register 3
AR4 20 14 Auxiliary register 4
AR5 21 15 Auxiliary register 5
AR6 22 16 Auxiliary register 6
AR7 23 17 Auxiliary register 7
SP 24 18 Stack pointer register
BK 25 19 Circular buffer size register
BRC 26 1A Block repeat counter
RSA 27 1B Block repeat start address
REA 28 1C Block repeat end address
PMST 29 1D Processor mode status (PMST) register
XPC 30 1E Extended program page register
– 31 1F Reserved
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memory-mapped registers (continued)
Table 10. Peripheral Memory-Mapped Registers
NAME ADDRESS DESCRIPTION TYPE
DRR20 20h
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
McBSP0 data receive register 2 McBSP #0
DRR10 21h
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
McBSP0 data receive register 1 McBSP #0
DXR20 22h
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
McBSP0 data transmit register 2 McBSP #0
DXR10 23h
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
McBSP0 data transmit register 1 McBSP #0
TIM 24h
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Timer0 register Timer0
PRD 25h
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Timer0 period counter Timer0
TCR 26h
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Timer0 control register Timer0
– 27h Reserved
SWWSR 28h
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Software wait-state register External Bus
BSCR 29h
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Bank-switching control register External Bus
– 2Ah Reserved
SWCR 2Bh
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Software wait-state control register External Bus
HPIC 2Ch
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
HPI control register HPI
– 2Dh−2Fh Reserved
TIM1 30h
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Timer1 register Timer1
PRD1 31h
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Timer1 period counter Timer1
TCR1 32h
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Timer1 control register Timer1
– 33h−37h Reserved
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
SPSA0
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
38h
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
McBSP0 subbank address register†
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
McBSP #0
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
SPSD0
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
39h
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
McBSP0 subbank data register†
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
McBSP #0
– 3Ah−3Bh Reserved
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
GPIOCR
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
3Ch
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
General-purpose I/O pins control register
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
GPIO
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
GPIOSR
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
3Dh
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
General-purpose I/O pins status register
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
GPIO
– 3Eh−3Fh Reserved
DRR21 40h
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
McBSP1 data receive register 2 McBSP #1
DRR11 41h
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
McBSP1 data receive register 1 McBSP #1
DXR21 42h
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
McBSP1 data transmit register 2 McBSP #1
DXR11 43h
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
McBSP1 data transmit register 1 McBSP #1
– 44h−47h Reserved
SPSA1 48h
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
McBSP1 subbank address register†McBSP #1
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
SPSD1
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
49h
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
McBSP1 subbank data register†
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
McBSP #1
– 4Ah−53h Reserved
DMPREC 54h
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
DMA channel priority and enable control register DMA
DMSA 55h
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
DMA subbank address register‡DMA
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
DMSDI
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
56h
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
DMA subbank data register with autoincrement‡
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
DMA
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
DMSDN
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
57h
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
DMA subbank data register‡
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
DMA
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
CLKMD
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
58h
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Clock mode register
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
PLL
– 59h−5Fh Reserved
†See Table 11 for a detailed description of the McBSP control registers and their sub-addresses.
‡See Table 12 for a detailed description of the DMA subbank addressed registers.
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McBSP control registers and subaddresses
The control registers for the multichannel buffered serial port (McBSP) are accessed using the subbank
addressing scheme. This allows a set or subbank of registers to be accessed through a single memory location.
The serial port subbank address (SPSA) register is used as a pointer to select a particular register within the
subbank. The serial port subbank data (SPSD) register is used to access (read or write) the selected register.
Table 11 shows the McBSP control registers and their corresponding sub-addresses.
Table 11. McBSP Control Registers and Subaddresses
McBSP0 McBSP1
NAME ADDRESS NAME ADDRESS SUB-
ADDRESS DESCRIPTION
ÁÁÁÁÁ
ÁÁÁÁÁ
SPCR10
ÁÁÁÁ
ÁÁÁÁ
39h
ÁÁÁÁÁ
ÁÁÁÁÁ
SPCR11
ÁÁÁÁ
ÁÁÁÁ
49h
ÁÁÁÁÁ
ÁÁÁÁÁ
00h
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Serial port control register 1
ÁÁÁÁÁ
SPCR20
ÁÁÁÁ
39h
ÁÁÁÁÁ
SPCR21
ÁÁÁÁ
49h
ÁÁÁÁÁ
01h
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Serial port control register 2
ÁÁÁÁÁ
ÁÁÁÁÁ
RCR10
ÁÁÁÁ
ÁÁÁÁ
39h
ÁÁÁÁÁ
ÁÁÁÁÁ
RCR11
ÁÁÁÁ
ÁÁÁÁ
49h
ÁÁÁÁÁ
ÁÁÁÁÁ
02h
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Receive control register 1
ÁÁÁÁÁ
ÁÁÁÁÁ
RCR20
ÁÁÁÁ
ÁÁÁÁ
39h
ÁÁÁÁÁ
ÁÁÁÁÁ
RCR21
ÁÁÁÁ
ÁÁÁÁ
49h
ÁÁÁÁÁ
ÁÁÁÁÁ
03h
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Receive control register 2
ÁÁÁÁÁ
ÁÁÁÁÁ
XCR10
ÁÁÁÁ
ÁÁÁÁ
39h
ÁÁÁÁÁ
ÁÁÁÁÁ
XCR11
ÁÁÁÁ
ÁÁÁÁ
49h
ÁÁÁÁÁ
ÁÁÁÁÁ
04h
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Transmit control register 1
ÁÁÁÁÁ
ÁÁÁÁÁ
XCR20
ÁÁÁÁ
ÁÁÁÁ
39h
ÁÁÁÁÁ
ÁÁÁÁÁ
XCR21
ÁÁÁÁ
ÁÁÁÁ
49h
ÁÁÁÁÁ
ÁÁÁÁÁ
05h
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Transmit control register 2
ÁÁÁÁÁ
ÁÁÁÁÁ
SRGR10
ÁÁÁÁ
ÁÁÁÁ
39h
ÁÁÁÁÁ
ÁÁÁÁÁ
SRGR11
ÁÁÁÁ
ÁÁÁÁ
49h
ÁÁÁÁÁ
ÁÁÁÁÁ
06h
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Sample rate generator register 1
ÁÁÁÁÁ
ÁÁÁÁÁ
SRGR20
ÁÁÁÁ
ÁÁÁÁ
39h
ÁÁÁÁÁ
ÁÁÁÁÁ
SRGR21
ÁÁÁÁ
ÁÁÁÁ
49h
ÁÁÁÁÁ
ÁÁÁÁÁ
07h
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Sample rate generator register 2
ÁÁÁÁÁ
ÁÁÁÁÁ
MCR10
ÁÁÁÁ
ÁÁÁÁ
39h
ÁÁÁÁÁ
ÁÁÁÁÁ
MCR11
ÁÁÁÁ
ÁÁÁÁ
49h
ÁÁÁÁÁ
ÁÁÁÁÁ
08h
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Multichannel register 1
ÁÁÁÁÁ
ÁÁÁÁÁ
MCR20
ÁÁÁÁ
ÁÁÁÁ
39h
ÁÁÁÁÁ
ÁÁÁÁÁ
MCR21
ÁÁÁÁ
ÁÁÁÁ
49h
ÁÁÁÁÁ
ÁÁÁÁÁ
09h
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Multichannel register 2
ÁÁÁÁÁ
RCERA0
ÁÁÁÁ
39h
ÁÁÁÁÁ
RCERA1
ÁÁÁÁ
49h
ÁÁÁÁÁ
0Ah
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Receive channel enable register partition A
ÁÁÁÁÁ
ÁÁÁÁÁ
RCERB0
ÁÁÁÁ
ÁÁÁÁ
39h
ÁÁÁÁÁ
ÁÁÁÁÁ
RCERB1
ÁÁÁÁ
ÁÁÁÁ
49h
ÁÁÁÁÁ
ÁÁÁÁÁ
0Bh
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Receive channel enable register partition B
ÁÁÁÁÁ
ÁÁÁÁÁ
XCERA0
ÁÁÁÁ
ÁÁÁÁ
39h
ÁÁÁÁÁ
ÁÁÁÁÁ
XCERA1
ÁÁÁÁ
ÁÁÁÁ
49h
ÁÁÁÁÁ
ÁÁÁÁÁ
0Ch
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Transmit channel enable register partition A
ÁÁÁÁÁ
ÁÁÁÁÁ
XCERB0
ÁÁÁÁ
ÁÁÁÁ
39h
ÁÁÁÁÁ
ÁÁÁÁÁ
XCERB1
ÁÁÁÁ
ÁÁÁÁ
49h
ÁÁÁÁÁ
ÁÁÁÁÁ
0Dh
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Transmit channel enable register partition B
ÁÁÁÁÁ
ÁÁÁÁÁ
PCR0
ÁÁÁÁ
ÁÁÁÁ
39h
ÁÁÁÁÁ
ÁÁÁÁÁ
PCR1
ÁÁÁÁ
ÁÁÁÁ
49h
ÁÁÁÁÁ
ÁÁÁÁÁ
0Eh
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Pin control register
DMA subbank addressed registers
The direct memory access (DMA) controller has several control registers associated with it. The main control
register (DMPREC) is a standard memory-mapped register. However, the other registers are accessed using
the subbank addressing scheme. This allows a set or subbank of registers to be accessed through a single
memory location. The DMA subbank address (DMSA) register is used as a pointer to select a particular register
within the subbank, while the DMA subbank data (DMSDN) register or the DMA subbank data register with
autoincrement (DMSDI) is used to access (read or write) the selected register.
When the DMSDI register is used to access the subbank, the subbank address is automatically
post-incremented so that a subsequent access af fects the next register within the subbank. This autoincrement
feature is intended for efficient, successive accesses to several control registers. If the autoincrement feature
is not required, the DMSDN register should be used to access the subbank. Table 12 shows the DMA controller
subbank addressed registers and their corresponding subaddresses.
SPRS079G − OC TOBER 1998 − REVISED OCTOBER 2008
30 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
DMA subbank addressed registers (continued)
Table 12. DMA Subbank Addressed Registers
DMA
NAME ADDRESS SUB-
ADDRESS DESCRIPTION
DMSRC0 56h/57h
ÁÁÁÁÁ
ÁÁÁÁÁ
00h DMA channel 0 source address register
DMDST0 56h/57h
ÁÁÁÁÁ
ÁÁÁÁÁ
01h DMA channel 0 destination address register
DMCTR0 56h/57h
ÁÁÁÁÁ
ÁÁÁÁÁ
02h DMA channel 0 element count register
ÁÁÁÁÁ
ÁÁÁÁÁ
DMSFC0
ÁÁÁÁ
ÁÁÁÁ
56h/57h
ÁÁÁÁÁ
ÁÁÁÁÁ
03h
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
DMA channel 0 sync select and frame count register
ÁÁÁÁÁ
ÁÁÁÁÁ
DMMCR0
ÁÁÁÁ
ÁÁÁÁ
56h/57h
ÁÁÁÁÁ
ÁÁÁÁÁ
04h
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
DMA channel 0 transfer mode control register
ÁÁÁÁÁ
ÁÁÁÁÁ
DMSRC1
ÁÁÁÁ
ÁÁÁÁ
56h/57h
ÁÁÁÁÁ
ÁÁÁÁÁ
05h
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
DMA channel 1 source address register
ÁÁÁÁÁ
ÁÁÁÁÁ
DMDST1
ÁÁÁÁ
ÁÁÁÁ
56h/57h
ÁÁÁÁÁ
ÁÁÁÁÁ
06h
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
DMA channel 1 destination address register
ÁÁÁÁÁ
ÁÁÁÁÁ
DMCTR1
ÁÁÁÁ
ÁÁÁÁ
56h/57h
ÁÁÁÁÁ
ÁÁÁÁÁ
07h
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
DMA channel 1 element count register
ÁÁÁÁÁ
DMSFC1
ÁÁÁÁ
56h/57h
ÁÁÁÁÁ
08h
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
DMA channel 1 sync select and frame count register
ÁÁÁÁÁ
ÁÁÁÁÁ
DMMCR1
ÁÁÁÁ
ÁÁÁÁ
56h/57h
ÁÁÁÁÁ
ÁÁÁÁÁ
09h
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
DMA channel 1 transfer mode control register
ÁÁÁÁÁ
ÁÁÁÁÁ
DMSRC2
ÁÁÁÁ
ÁÁÁÁ
56h/57h
ÁÁÁÁÁ
ÁÁÁÁÁ
0Ah
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
DMA channel 2 source address register
ÁÁÁÁÁ
ÁÁÁÁÁ
DMDST2
ÁÁÁÁ
ÁÁÁÁ
56h/57h
ÁÁÁÁÁ
ÁÁÁÁÁ
0Bh
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
DMA channel 2 destination address register
ÁÁÁÁÁ
ÁÁÁÁÁ
DMCTR2
ÁÁÁÁ
ÁÁÁÁ
56h/57h
ÁÁÁÁÁ
ÁÁÁÁÁ
0Ch
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
DMA channel 2 element count register
ÁÁÁÁÁ
ÁÁÁÁÁ
DMSFC2
ÁÁÁÁ
ÁÁÁÁ
56h/57h
ÁÁÁÁÁ
ÁÁÁÁÁ
0Dh
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
DMA channel 2 sync select and frame count register
ÁÁÁÁÁ
ÁÁÁÁÁ
DMMCR2
ÁÁÁÁ
ÁÁÁÁ
56h/57h
ÁÁÁÁÁ
ÁÁÁÁÁ
0Eh
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
DMA channel 2 transfer mode control register
ÁÁÁÁÁ
ÁÁÁÁÁ
DMSRC3
ÁÁÁÁ
ÁÁÁÁ
56h/57h
ÁÁÁÁÁ
ÁÁÁÁÁ
0Fh
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
DMA channel 3 source address register
ÁÁÁÁÁ
DMDST3
ÁÁÁÁ
56h/57h
ÁÁÁÁÁ
10h
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
DMA channel 3 destination address register
ÁÁÁÁÁ
ÁÁÁÁÁ
DMCTR3
ÁÁÁÁ
ÁÁÁÁ
56h/57h
ÁÁÁÁÁ
ÁÁÁÁÁ
11h
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
DMA channel 3 element count register
ÁÁÁÁÁ
ÁÁÁÁÁ
DMSFC3
ÁÁÁÁ
ÁÁÁÁ
56h/57h
ÁÁÁÁÁ
ÁÁÁÁÁ
12h
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
DMA channel 3 sync select and frame count register
ÁÁÁÁÁ
ÁÁÁÁÁ
DMMCR3
ÁÁÁÁ
ÁÁÁÁ
56h/57h
ÁÁÁÁÁ
ÁÁÁÁÁ
13h
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
DMA channel 3 transfer mode control register
ÁÁÁÁÁ
ÁÁÁÁÁ
DMSRC4
ÁÁÁÁ
ÁÁÁÁ
56h/57h
ÁÁÁÁÁ
ÁÁÁÁÁ
14h
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
DMA channel 4 source address register
ÁÁÁÁÁ
ÁÁÁÁÁ
DMDST4
ÁÁÁÁ
ÁÁÁÁ
56h/57h
ÁÁÁÁÁ
ÁÁÁÁÁ
15h
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
DMA channel 4 destination address register
ÁÁÁÁÁ
ÁÁÁÁÁ
DMCTR4
ÁÁÁÁ
ÁÁÁÁ
56h/57h
ÁÁÁÁÁ
ÁÁÁÁÁ
16h
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
DMA channel 4 element count register
ÁÁÁÁÁ
ÁÁÁÁÁ
DMSFC4
ÁÁÁÁ
ÁÁÁÁ
56h/57h
ÁÁÁÁÁ
ÁÁÁÁÁ
17h
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
DMA channel 4 sync select and frame count register
ÁÁÁÁÁ
ÁÁÁÁÁ
DMMCR4
ÁÁÁÁ
ÁÁÁÁ
56h/57h
ÁÁÁÁÁ
ÁÁÁÁÁ
18h
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
DMA channel 4 transfer mode control register
ÁÁÁÁÁ
DMSRC5
ÁÁÁÁ
56h/57h
ÁÁÁÁÁ
19h
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
DMA channel 5 source address register
ÁÁÁÁÁ
ÁÁÁÁÁ
DMDST5
ÁÁÁÁ
ÁÁÁÁ
56h/57h
ÁÁÁÁÁ
ÁÁÁÁÁ
1Ah
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
DMA channel 5 destination address register
ÁÁÁÁÁ
ÁÁÁÁÁ
DMCTR5
ÁÁÁÁ
ÁÁÁÁ
56h/57h
ÁÁÁÁÁ
ÁÁÁÁÁ
1Bh
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
DMA channel 5 element count register
ÁÁÁÁÁ
ÁÁÁÁÁ
DMSFC5
ÁÁÁÁ
ÁÁÁÁ
56h/57h
ÁÁÁÁÁ
ÁÁÁÁÁ
1Ch
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
DMA channel 5 sync select and frame count register
ÁÁÁÁÁ
ÁÁÁÁÁ
DMMCR5
ÁÁÁÁ
ÁÁÁÁ
56h/57h
ÁÁÁÁÁ
ÁÁÁÁÁ
1Dh
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
DMA channel 5 transfer mode control register
ÁÁÁÁÁ
ÁÁÁÁÁ
DMSRCP
ÁÁÁÁ
ÁÁÁÁ
56h/57h
ÁÁÁÁÁ
ÁÁÁÁÁ
1Eh
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
DMA source program page address (common channel)
ÁÁÁÁÁ
ÁÁÁÁÁ
DMDSTP
ÁÁÁÁ
ÁÁÁÁ
56h/57h
ÁÁÁÁÁ
ÁÁÁÁÁ
1Fh
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
DMA destination program page address (common channel)
ÁÁÁÁÁ
ÁÁÁÁÁ
DMIDX0
ÁÁÁÁ
ÁÁÁÁ
56h/57h
ÁÁÁÁÁ
ÁÁÁÁÁ
20h
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
DMA element index address register 0
ÁÁÁÁÁ
DMIDX1
ÁÁÁÁ
56h/57h
ÁÁÁÁÁ
21h
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
DMA element index address register 1
ÁÁÁÁÁ
ÁÁÁÁÁ
DMFRI0
ÁÁÁÁ
ÁÁÁÁ
56h/57h
ÁÁÁÁÁ
ÁÁÁÁÁ
22h
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
DMA frame index register 0
ÁÁÁÁÁ
ÁÁÁÁÁ
DMFRI1
ÁÁÁÁ
ÁÁÁÁ
56h/57h
ÁÁÁÁÁ
ÁÁÁÁÁ
23h
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
DMA frame index register 1
ÁÁÁÁÁ
ÁÁÁÁÁ
DMGSA
ÁÁÁÁ
ÁÁÁÁ
56h/57h
ÁÁÁÁÁ
ÁÁÁÁÁ
24h
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
DMA global source address reload register
ÁÁÁÁÁ
ÁÁÁÁÁ
DMGDA
ÁÁÁÁ
ÁÁÁÁ
56h/57h
ÁÁÁÁÁ
ÁÁÁÁÁ
25h
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
DMA global destination address reload register
ÁÁÁÁÁ
ÁÁÁÁÁ
DMGCR
ÁÁÁÁ
ÁÁÁÁ
56h/57h
ÁÁÁÁÁ
ÁÁÁÁÁ
26h
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
DMA global count reload register
ÁÁÁÁÁ
ÁÁÁÁÁ
DMGFR
ÁÁÁÁ
ÁÁÁÁ
56h/57h
ÁÁÁÁÁ
ÁÁÁÁÁ
27h
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
DMA global frame count reload register
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interrupts
Vector-relative locations and priorities for all internal and external interrupts are shown in Table 13.
Table 13. Interrupt Locations and Priorities
NAME LOCATION
DECIMAL HEX PRIORITY FUNCTION
RS, SINTR 0 00 1 Reset (hardware and software reset)
NMI, SINT16 4 04 2 Nonmaskable interrupt
SINT17 8 08 — Software interrupt #17
SINT18 12 0C — Software interrupt #18
SINT19 16 10 — Software interrupt #19
SINT20 20 14 — Software interrupt #20
SINT21 24 18 — Software interrupt #21
SINT22 28 1C — Software interrupt #22
SINT23 32 20 — Software interrupt #23
SINT24 36 24 — Software interrupt #24
SINT25 40 28 — Software interrupt #25
SINT26 44 2C — Software interrupt #26
SINT27 48 30 — Software interrupt #27
SINT28 52 34 — Software interrupt #28
SINT29 56 38 — Software interrupt #29
SINT30 60 3C — Software interrupt #30
INT0, SINT0 64 40 3 External user interrupt #0
INT1, SINT1 68 44 4 External user interrupt #1
INT2, SINT2 72 48 5 External user interrupt #2
TINT0, SINT3 76 4C 6 Timer0 interrupt
BRINT0, SINT4 80 50 7 McBSP #0 receive interrupt
BXINT0, SINT5 84 54 8 McBSP #0 transmit interrupt
Reserved(DMAC0), SINT6 88 58 9 Reserved (default) or DMA channel 0 inter-
rupt. The selection is made in the DMPREC
register.
TINT1(DMAC1), SINT7 92 5C 10 Timer1 interrupt (default) or DMA channel 1
interrupt. The selection is made in the
DMPREC register.
INT3, SINT8 96 60 11 External user interrupt #3
HPINT, SINT9 100 64 12 HPI interrupt
BRINT1(DMAC2), SINT10 104 68 13 McBSP #1 receive interrupt (default) or DMA
channel 2 interrupt. The selection is made in
the DMPREC register.
BXINT1(DMAC3), SINT11 108 6C 14 McBSP #1 transmit interrupt (default) or DMA
channel 3 interrupt. The selection is made in
the DMPREC register.
DMAC4,SINT12 112 70 15 DMA channel 4 interrupt
DMAC5,SINT13 116 74 16 DMA channel 5 interrupt
Reserved 120−127 78−7F — Reserved
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32 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
interrupts (continued)
The bits of the interrupt flag register (IFR) and interrupt mask register (IMR) are arranged as shown in Figure 8.
15−14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RES DMAC5 DMAC4 BXINT1
or
DMAC3
BRINT1
or
DMAC2
HPINT INT3 TINT1
or
DMAC1
RES
or
DMAC0
BXINT0 BRINT0 TINT0 INT2 INT1 INT0
Figure 8. IFR and IMR Registers
Table 14. IFR and IMR Register Bit Fields
BIT
FUNCTION
NUMBER NAME
FUNCTION
15−14 − Reserved for future expansion
13 DMAC5 DMA channel 5 interrupt flag/mask bit
12 DMAC4 DMA channel 4 interrupt flag/mask bit
11 BXINT1/DMAC3 This bit can be configured as either the McBSP1 transmit interrupt flag/mask bit, or the DMA
channel 3 interrupt flag/mask bit. The selection is made in the DMPREC register.
10 BRINT1/DMAC2 This bit can be configured as either the McBSP1 receive interrupt flag/mask bit, or the DMA
channel 2 interrupt flag/mask bit. The selection is made in the DMPREC register.
9 HPINT Host to 54x interrupt flag/mask
8 INT3 External interrupt 3 flag/mask
7 TINT1/DMAC1 This bit can be configured as either the timer1 interrupt flag/mask bit, or the DMA channel 1
interrupt flag/mask bit. The selection is made in the DMPREC register.
6 DMAC0 This bit can be configured as either reserved, or the DMA channel 0 interrupt flag/mask bit. The
selection is made in the DMPREC register.
5 BXINT0 McBSP0 transmit interrupt flag/mask bit
4 BRINT0 McBSP0 receive interrupt flag/mask bit
3 TINT0 Timer 0 interrupt flag/mask bit
2 INT2 External interrupt 2 flag/mask bit
1 INT1 External interrupt 1 flag/mask bit
0 INT0 External interrupt 0 flag/mask bit
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support
notices concerning JTAG (IEEE 1149.1) boundary scan test capability
initialization requirements for boundary scan test
The 5402 uses the JTAG port for boundary scan tests, emulation capability and factory test purposes. To use
boundary scan test, the EMU0 and EMU1/OFF pins must be held HIGH through a rising edge of the TRST
signal prior to the first scan. This operation selects the appropriate TAP control for boundary scan. If at any
time during a boundary scan test a rising edge of TRST occurs when EMU0 or EMU1/OFF are not high, a
factory test mode may be selected preventing boundary scan test from being completed. For this reason, it
is recommended that EMU0 and EMU1/OFF be pulled or driven high at all times during boundary scan test.
boundary scan description language (BSDL) model
BSDL models are available on the web in the 5402 product folder under the “simulation models” section.
documentation support
Extensive documentation supports all TMS320t DSP family of devices from product announcement through
applications development. The following types of documentation are available to support the design and use
of the C5000 family of DSPs:
DTMS320C54xt DSP Functional Overview (literature number SPRU307)
DDevice-specific data sheets (such as this document)
DComplete User Guides
DDevelopment-support tools
DHardware and software application reports
The five-volume TMS320C54x DSP Reference Set consists of:
DVolume 1: CPU and Peripherals (literature number SPRU131)
DVolume 2: Mnemonic Instruction Set (literature number SPRU172)
DVolume 3: Algebraic Instruction Set (literature number SPRU179)
DVolume 4: Applications Guide (literature number SPRU173)
DVolume 5: Enhanced Peripherals (literature number SPRU302)
The reference set describes in detail the TMS320C54x products currently available, and the hardware and
software applications, including algorithms, for fixed-point TMS320 devices.
A series of DSP textbooks is published by Prentice-Hall and John Wiley & Sons to support digital signal
processing research and education. The TMS320 newsletter, Details on Signal Processing, is published
quarterly and distributed to update TMS320 customers on product information.
Information regarding TIt DSP products is also available on the W orldwide W eb at http://www.ti.com uniform
resource locator (URL).
TMS320, TMS320C5000, and TI are trademarks of Texas Instruments.
SPRS079G − OC TOBER 1998 − REVISED OCTOBER 2008
34 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
support (continued)
device and development-support tool nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
TMS320 DSP devices and support tools. Each TMS320 DSP commercial family member has one of three
prefixes: TMX, TMP, or TMS (e.g., TMS320C6412GDK600). Texas Instruments recommends two of three
possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary
stages of product development from engineering prototypes (TMX/TMDX) through fully qualified production
devices/tools (TMS/TMDS).
Device development evolutionary flow:
TMX Experimental device that is not necessarily representative of the final device’s electrical
specifications
TMP Final silicon die that conforms to the device’s electrical specifications but has not completed
quality and reliability verification
TMS Fully qualified production device
Support tool development evolutionary flow:
TMDX Development-support product that has not yet completed Texas Instruments internal qualification
testing.
TMDS Fully qualified development-support product
TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer:
“Developmental product is intended for internal evaluation purposes.”
TMS devices and TMDS development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI’s standard warranty applies.
Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard
production devices. Texas Instruments recommends that these devices not be used in any production system
because their expected end-use failure rate still is undefined. Only qualified production devices are to be used.
TMS320 is a trademark of Texas Instruments.
SPRS079G − OC TOBER 1998 − REVISED OCTOBER 2008
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absolute maximum ratings over specified temperature range (unless otherwise noted)†
Supply voltage I/O range, DVDD‡ −0.3 V to 4.0 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply voltage core range, CVDD‡−0.3 V to 2.4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI−0.3 V to 4.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO−0.3 V to 4.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating case temperature range, TC−40°C to 100°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −55°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
‡All voltage values are with respect to VSS.
recommended operating conditions
MIN NOM MAX UNIT
DVDD Device supply voltage, I/O§3 3.3 3.6 V
CVDD Device supply voltage, core§1.71 1.8 1.98 V
VSS Supply voltage, GND 0 V
High-level input voltage
RS, INTn, NMI, BIO, BCLKR0, BCLKR1,
BCLKX0, BCLKX1, HCS, HDS1, HDS2, TDI,
TMS, CLKMDn 2.2 DVDD + 0.3
VIH High-level input voltage
DVDD = 3.3
"
0.3 V
X2/CLKIN¶1.35 CVDD+0.3 V
IH
DVDD = 3.3"0.3 V
TCK, TRST 2.5 DVDD + 0.3
All other inputs 2 DVDD + 0.3
VIL Low-level input voltage
DVDD = 3.3
"
0.3 V
RS, INTn, NMI, X2/CLKIN¶, BIO, BCLKR0,
BCLKR1, BCLKX0, BCLKX1, HCS, HDS1,
HDS2, TCK, CLKMDn −0.3 0.6 V
IL
DVDD = 3.3"0.3 V
All other inputs −0.3 0.8
IOH High-level output current −300 µA
IOL Low-level output current 1.5 mA
TCOperating case temperature −40 100 °C
§Texas Instrument DSPs do not require specific power sequencing between the core supply and the I/O supply. However, systems should be
designed to ensure that neither supply is powered up for extended periods of time if the other supply is below the proper operating voltage.
Excessive exposure to these conditions can adversely af fect the long term reliability of the devices. System-level concerns such as bus contention
may require supply sequencing to be implemented. In this case, the core supply should be powered up at the same time as or prior to the I/O
buffers and then powered down after the I/O buffers.
¶All revisions of the 5402 can be operated with an external clock source, provided that the proper voltage levels be driven on the X2/CLKIN pin.
It should be noted that the X2/CLKIN pin is referenced to the device 1.8V power supply (CVdd), rather than the 3V I/O supply (DVdd). Refer to
the recommended operating conditions section of this document for the allowable voltage levels of the X2/CLKIN pin.
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36 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
electrical characteristics over recommended operating case temperature range (unless otherwise
noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
VOH High-level output voltage IOH = MAX 2.4 V
VOL Low-level output voltage IOL = MAX 0.4 V
I
IZ
Input current fo
r
outputs in high D[15:0], HD[7:0] Bus holders enabled, DVDD = MAX,
VI = VSS to DVDD −175 175 µA
IIZ
outputs in high
impedance All other inputs DVDD = MAX, VO = VSS to DVDD −5 5
µA
X2/CLKIN}−40 40
TRST With internal pulldown −5 300
II
Input current HPIENA With internal pulldown (V
I
= V
SS
to DV )
−5 300
µA
II
Input current
TMS, TCK, TDI, HPIwWith internal pullups,
HPIENA = 0
(VI = VSS
to DVDD)−300 5
µ
A
All other input-only pins
−5
5
All other input-only pins −
5
5
IDDC Supply current, core CPU CVDD = 1.8 V, fclock = 100 MHz¶, TC = 25°C#45 mA
IDDP Supply current, pins DVDD = 3.3 V, fclock = 100 MHz¶, TC = 25°C|| 30 mA
IDD
Supply current,
standby
IDLE2 PLL × 1 mode, 100 MHz input 2 mA
I
DD
Supply current,
standby IDLE3 Divide-by-two mode, CLKIN stopped 20 µA
CiInput capacitance 5 pF
CoOutput capacitance 5 pF
†All values are typical unless otherwise specified.
‡All revisions of the 5402 can be operated with an external clock source, provided that the proper voltage levels be driven on the X2/CLKIN pin.
It should be noted that the X2/CLKIN pin is referenced to the device 1.8V power supply (CVdd), rather than the 3V I/O supply (DVdd). Refer to
the recommended operating conditions section of this document for the allowable voltage levels of the X2/CLKIN pin.
§HPI input signals except for HPIENA.
¶Clock mode: PLL × 1 with external source
#This value represents the current consumption of the CPU, on-chip memory, and on-chip peripherals. Conditions include: program execution
from on-chip RAM, with 50% usage of MAC and 50% usage of NOP instructions. Actual operating current varies with program being executed.
|| This value was obtained using the following conditions: external memory writes at a rate of 20 million writes per second, CLKOFF=0, full-duplex
operation of McBSP0 and McBSP1 at a rate of 10 million bits per second each, and 15-pF loads on all outputs. For more details on how this
calculation is performed, refer to the Calculation of TMS320C54x Power Dissipation Application Report (literature number SPRA164).
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PARAMETER MEASUREMENT INFORMATION
Transmission Line
4.0 pF 1.85 pF
Z0 = 50 W
(see note)
Tester Pin Electronics Data Sheet Timing Reference Point
Output
Under
Test
NOTE: The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects
must taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line effect.
The transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or longer) from
the data sheet timings.
42 W3.5 nH
Device Pin
(see note)
Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin.
Figure 9. Tester Pin Electronics
internal oscillator with external crystal
The internal oscillator is enabled by connecting a crystal across X1 and X2/CLKIN. The frequency of CLKOUT
is a multiple of the oscillator frequency. The multiply ratio is determined by the bit settings in the CLKMD register .
The crystal should be in fundamental-mode operation, and parallel resonant, with an effective series resistance
of 30 Ω and power dissipation of 1 mW.
The connection of the required circuit, consisting of the crystal and two load capacitors, is shown in Figure 10.
The load capacitors, C1 and C2, should be chosen such that the equation below is satisfied. CL in the equation
is the load specified for the crystal.
CL+C1C2
(C1)C2)
recommended operating conditions of internal oscillator with external crystal (see Figure 10)
MIN MAX UNIT
fclock Input clock frequency 10 20 MHz
X1 X2/CLKIN
C1C2
Crystal
Figure 10. Internal Oscillator With External Crystal
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38 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
divide-by-two clock option (PLL disabled)
The frequency of the reference clock provided at the X2/CLKIN pin can be divided by a factor of two to generate
the internal machine cycle. The selection of the clock mode is described in the clock generator section.
When an external clock source is used, the frequency injected must conform to specifications listed i n th e ti mi ng
requirements table.
NOTE:All revisions of the 5402 can be operated with an external clock source, provided that the proper
voltage levels be driven on the X2/CLKIN pin. It should be noted that the X2/CLKIN pin is referenced to
the device 1.8V power supply (CVdd), rather than the 3V I/O supply (DVdd). Refer to the recommended
operating conditions section of this document for the allowable voltage levels of the X2/CLKIN pin.
timing requirements (see Figure 11)
MIN MAX UNIT
tc(CI) Cycle time, X2/CLKIN 20 †ns
tf(CI) Fall time, X2/CLKIN 8 ns
tr(CI) Rise time, X2/CLKIN 8 ns
†This device utilizes a fully static design and therefore can operate with tc(CI) approaching ∞. The device is characterized at frequencies
approaching 0 Hz.
switching characteristics over recommended operating conditions [H = 0.5tc(CO)]† (see Figure 10,
Figure 11, and the recommended operating conditions table)
PARAMETER MIN TYP MAX UNIT
tc(CO) Cycle time, CLKOUT 10‡2tc(CI) †ns
td(CIH-CO) Delay time, X2/CLKIN high to CLKOUT high/low 4 10 17 ns
tf(CO) Fall time, CLKOUT 2 ns
tr(CO) Rise time, CLKOUT 2 ns
tw(COL) Pulse duration, CLKOUT low H−2 H ns
tw(COH) Pulse duration, CLKOUT high H−2 H ns
†This device utilizes a fully static design and therefore can operate with tc(CI) approaching ∞. The device is characterized at frequencies
approaching 0 Hz.
‡It is recommended that the PLL clocking option be used for maximum frequency operation.
tr(CO)
tf(CO)
CLKOUT
X2/CLKIN
tw(COL)
td(CIH-CO)
tf(CI)
tr(CI)
tc(CO)
tc(CI)
tw(COH)
Figure 11. External Divide-by-Two Clock Timing
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multiply-by-N clock option
The frequency of the reference clock provided at the X2/CLKIN pin can be multiplied by a factor of N to generate
the internal machine cycle. The selection of the clock mode and the value of N is described in the clock generator
section.
When an external clock source is used, the external frequency injected must conform to specifications listed
in the timing requirements table.
NOTE:All revisions of the 5402 can be operated with an external clock source, provided that the proper
voltage levels be driven on the X2/CLKIN pin. It should be noted that the X2/CLKIN pin is referenced to
the device 1.8V power supply (CVdd), rather than the 3V I/O supply (DVdd). Refer to the recommended
operating conditions section of this document for the allowable voltage levels of the X2/CLKIN pin.
timing requirements (see Figure 12)†
MIN MAX UNIT
Integer PLL multiplier N (N = 1−15) 20‡200
t
c(CI)
Cycle time, X2/CLKIN PLL multiplier N = x.5 20‡100 ns
tc(CI)
Cycle time, X2/CLKIN
PLL multiplier N = x.25, x.75 20‡50
ns
tf(CI) Fall time, X2/CLKIN 8 ns
tr(CI) Rise time, X2/CLKIN 8 ns
†N = Multiplication factor
‡The multiplication factor and minimum X2/CLKIN cycle time should be chosen such that the resulting CLKOUT cycle time is within the specified
range (tc(CO))
switching characteristics over recommended operating conditions [H = 0.5tc(CO)]
(see Figure 10 and Figure 12)
PARAMETER MIN TYP MAX UNIT
tc(CO) Cycle time, CLKOUT 10 tc(CI)/N†ns
td(CI-CO) Delay time, X2/CLKIN high/low to CLKOUT high/low 4 10 17 ns
tf(CO) Fall time, CLKOUT 2 ns
tr(CO) Rise time, CLKOUT 2 ns
tw(COL) Pulse duration, CLKOUT low H−2 H ns
tw(COH) Pulse duration, CLKOUT high H−2 H ns
tpTransitory phase, PLL lock up time 30 ms
†N = Multiplication factor
tc(CO)
tc(CI)
tw(COH) tf(CO)
tr(CO)
tf(CI)
X2/CLKIN
CLKOUT
td(CI-CO)
tw(COL)
tr(CI)
tp
Unstable
Figure 12. External Multiply-by-One Clock Timing
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40 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
memory and parallel I/O interface timing
timing requirements for a memory read (MSTRB = 0) [H = 0.5 tc(CO)]† (see Figure 13)
MIN MAX UNIT
ta(A)M Access time, read data access from address valid 2H−7 ns
ta(MSTRBL) Access time, read data access from MSTRB low 2H−8 ns
tsu(D)R Setup time, read data before CLKOUT low 6 ns
th(D)R Hold time, read data after CLKOUT low −2 ns
th(A-D)R Hold time, read data after address invalid 0 ns
th(D)MSTRBH Hold time, read data after MSTRB high 0 ns
†Address, PS, and DS timings are all included in timings referenced as address.
switching characteristics over recommended operating conditions for a memory read
(MSTRB = 0)† (see Figure 13)
PARAMETER MIN MAX UNIT
td(CLKL-A) Delay time, CL KOUT low to address valid‡−2 3 ns
td(CLKH-A) Delay time, CL KOUT high (transition) to address valid§−2 3 ns
td(CLKL-MSL) Delay time, CLKOUT low to MSTRB low −1 3 ns
td(CLKL-MSH) Delay time, CLKOUT low to MST RB high −1 3 ns
th(CLKL-A)R Hold time, address valid after CLKOUT low‡−2 3 ns
th(CLKH-A)R Hold time, address valid after CLKOUT high§−2 3 ns
†Address, PS, and DS timings are all included in timings referenced as address.
‡In the case of a memory read preceded by a memory read
§In the case of a memory read preceded by a memory write
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memory and parallel I/O interface timing (continued)
PS, DS
R/W
MSTRB
D[15:0]
A[19:0]
CLKOUT
th(D)R
th(CLKL-A)R
td(CLKL-MSH)
td(CLKL-A)
td(CLKL-MSL)
tsu(D)R
ta(A)M
ta(MSTRBL)
th(A-D)R
th(D)MSTRBH
NOTE A: A[19:16] are always driven low during accesses to external data space.
Figure 13. Memory Read (MSTRB = 0)
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42 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
memory and parallel I/O interface timing (continued)
switching characteristics over recommended operating conditions for a memory write
(MSTRB = 0) [H = 0.5 tc(CO)]† (see Figure 14)
PARAMETER MIN MAX UNIT
td(CLKH-A) Delay time, CL KOUT high to address v alid‡−2 3 ns
td(CLKL-A) Delay time, CL KOUT low to address valid§−2 3 ns
td(CLKL-MSL) Delay time, CLKOUT low to MSTRB low −1 3 ns
td(CLKL-D)W Delay time, CL KOUT low to data valid 0 6 ns
td(CLKL-MSH) Delay time, CLKOUT low to MSTRB high −1 3 ns
td(CLKH-RWL) Delay time, CLKOUT high to R/W low −1 3 ns
td(CLKH-RWH) Delay time, CLKOUT high to R/W high −1 3 ns
td(RWL-MSTRBL) Delay time, R/W low to MSTRB low H − 2 H + 1 ns
th(A)W Hold time, address valid after CL KOUT high‡1 3 ns
th(D)MSH Hold time, write data valid after MSTRB high H−3 H+6§ns
tw(SL)MS Pulse duration, MSTRB low 2H−2 ns
tsu(A)W Setup time, address valid before MSTRB low 2H−2 ns
tsu(D)MSH Setup time, write data valid before MSTRB high 2H−6 2H+5§ns
ten(D−RWL) Enable time, data bus driven after R/W low H−5 ns
tdis(RWH−D) Disable time, R/W high to data bus high impedance 0 ns
†Address, PS, and DS timings are all included in timings referenced as address.
‡In the case of a memory write preceded by a memory write
§In the case of a memory write preceded by an I/O cycle
SPRS079G − OC TOBER 1998 − REVISED OCTOBER 2008
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memory and parallel I/O interface timing (continued)
PS, DS
R/W
MSTRB
D[15:0]
A[19:0]
CLKOUT
td(CLKH-RWH)
th(A)W
td(CLKL-MSH)
tsu(D)MSH
td(CLKL-D)W
tw(SL)MS
tsu(A)W
td(CLKL-MSL)
th(D)MSH
td(CLKL-A)
td(CLKH-RWL)
td(RWL-MSTRBL)
td(CLKH-A)
ten(D-RWL)
tdis(RWH-D)
NOTE A: A[19:16] are always driven low during accesses to external data space.
Figure 14. Memory Write (MSTRB = 0)
SPRS079G − OC TOBER 1998 − REVISED OCTOBER 2008
44 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
memory and parallel I/O interface timing (continued)
timing requirements for a parallel I/O port read (IOSTRB = 0) [H = 0.5 tc(CO)]† (see Figure 15)
MIN MAX UNIT
ta(A)IO Access time, read data access from address valid 3H−7 ns
ta(ISTRBL)IO Access time, read data access from IOSTRB low 2H−7 ns
tsu(D)IOR Setup time, read data before CLKOUT high 6 ns
th(D)IOR Hold time, read data after CLKOUT high 0 ns
th(ISTRBH-D)R Hold time, read data after IOSTRB high 0 ns
†Address and IS timings are included in timings referenced as address.
switching characteristics over recommended operating conditions for a parallel I/O port read
(IOSTRB = 0)† (see Figure 15)
PARAMETER MIN MAX UNIT
td(CLKL-A) Delay time, CL KOUT low to address valid −2 3 ns
td(CLKH-ISTRBL) Delay time, CLKOUT high to IOSTRB low −2 3 ns
td(CLKH-ISTRBH) Delay time, CLKOUT high to IOSTRB high −2 3 ns
th(A)IOR Hold time, address after CLKOUT low 0 3 ns
†Address and IS timings are included in timings referenced as address.
IS
R/W
IOSTRB
D[15:0]
A[19:0]
CLKOUT
th(A)IOR
td(CLKH-ISTRBH)
th(D)IOR
tsu(D)IOR
ta(A)IO
td(CLKH-ISTRBL)
td(CLKL-A)
ta(ISTRBL)IO th(ISTRBH-D)R
NOTE A: A[19:16] are always driven low during accesses to I/O space.
Figure 15. Parallel I/O Port Read (IOSTRB = 0)
SPRS079G − OC TOBER 1998 − REVISED OCTOBER 2008
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
memory and parallel I/O interface timing (continued)
switching characteristics over recommended operating conditions for a parallel I/O port write
(IOSTRB = 0) [H = 0.5 tc(CO)]† (see Figure 16)
PARAMETER MIN MAX UNIT
td(CLKL-A) Delay time, CL KOUT low to address valid −2 3 ns
td(CLKH-ISTRBL) Delay time, CLKOUT high to IOSTRB low −2 3 ns
td(CLKH-D)IOW Delay time, CLK OUT high to write data valid H−5 H+8 ns
td(CLKH-ISTRBH) Delay time, CLKOUT high to IOSTRB high −2 3 ns
td(CLKL-RWL) Delay time, CLKOUT low to R/W low −1 3 ns
td(CLKL-RWH) Delay time, CLKOUT low to R/W high −1 3 ns
th(A)IOW Hold time, address valid after CL KOUT low 0 3 ns
th(D)IOW Hold time, write data after IOSTRB high H−3 H+7 ns
tsu(D)IOSTRBH Setup time, write data before IOSTRB high H−7 H+1 ns
tsu(A)IOSTRBL Setup time, address valid before IOSTRB low H−2 H+2 ns
†Address and IS timings are included in timings referenced as address.
IS
R/W
IOSTRB
D[15:0]
A[19:0]
CLKOUT
td(CLKH-ISTRBH)
th(A)IOW
th(D)IOW
td(CLKH-D)IOW
td(CLKH-ISTRBL)
td(CLKL-A)
td(CLKL-RWL) td(CLKL-RWH)
tsu(A)IOSTRBL
tsu(D)IOSTRBH
NOTE A: A[19:16] are always driven low during accesses to I/O space.
Figure 16. Parallel I/O Port Write (IOSTRB = 0)
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46 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ready timing for externally generated wait states
timing requirements for externally generated wait states [H = 0.5 tc(CO)]† (see Figure 17, Figure 18,
Figure 19, and Figure 20)
MIN MAX UNIT
tsu(RDY) Setup time, READY before CLKOUT low 6 ns
th(RDY) Hold time, READY after CLKOUT low 0 ns
tv(RDY)MSTRB Valid time, READY after MSTRB low‡4H−8 ns
th(RDY)MSTRB Hold time, READY after MSTRB low‡4H ns
tv(RDY)IOSTRB Valid time, READY after IOSTRB low‡5H−8 ns
th(RDY)IOSTRB Hold time, READY after IOSTRB low‡5H ns
tv(MSCL) Valid time, MSC low after CLKOUT low −1 3 ns
tv(MSCH) Valid time, MSC high after CLKOUT low −1 3 ns
†The hardware wait states can be used only in conjunction with the software wait states to extend the bus cycles. To generate wait states using
READY, at least two software wait states must be programmed.
‡These timings are included for reference only. The critical timings for READY are those referenced to CLKOUT.
MSC
MSTRB
READY
A[19:0]
CLKOUT
tv(MSCH)
tv(MSCL)
th(RDY)
th(RDY)MSTRB
tv(RDY)MSTRB
Wait State
Generated
by READY
Wait States
Generated Internally
tsu(RDY)
NOTE A: A[19:16] are always driven low during accesses to external data space.
Figure 17. Memory Read With Externally Generated Wait States
SPRS079G − OC TOBER 1998 − REVISED OCTOBER 2008
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ready timing for externally generated wait states (continued)
MSC
MSTRB
READY
D[15:0]
A[19:0]
CLKOUT
tv(MSCH)
th(RDY)
Wait State Generated
by READY
Wait States
Generated Internally
th(RDY)MSTRB
tv(RDY)MSTRB
tv(MSCL)
tsu(RDY)
NOTE A: A[19:16] are always driven low during accesses to external data space.
Figure 18. Memory Write With Externally Generated Wait States
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48 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ready timing for externally generated wait states (continued)
tsu(RDY)
MSC
IOSTRB
READY
A[19:0]
CLKOUT
tv(MSCH)
th(RDY)
Wait State Generated
by READY
Wait
States
Generated
Internally
tv(RDY)IOSTRB
tv(MSCL)
th(RDY)IOSTRB
NOTE A: A[19:16] are always driven low during accesses to I/O space.
Figure 19. I/O Read With Externally Generated Wait States
SPRS079G − OC TOBER 1998 − REVISED OCTOBER 2008
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ready timing for externally generated wait states (continued)
IOSTRB
MSC
READY
D[15:0]
A[19:0]
CLKOUT
th(RDY)
Wait State Generated
by READY
Wait States
Generated
Internally
tv(RDY)IOSTRB
tsu(RDY)
tv(MSCH)
tv(MSCL)
th(RDY)IOSTRB
NOTE A: A[19:16] are always driven low during accesses to I/O space.
Figure 20. I/O Write With Externally Generated Wait States
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50 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
HOLD and HOLDA timings
timing requirements for memory control signals and HOLDA, [H = 0.5 tc(CO)] (see Figure 21)
MIN MAX UNIT
tw(HOLD) Pulse duration, HOLD low 4H+7 ns
tsu(HOLD) Setup time, HOLD low/high before CLKOUT low 7 ns
switching characteristics over recommended operating conditions for memory control signals
and HOLDA, [H = 0.5 tc(CO)] (see Figure 21)
PARAMETER MIN MAX UNIT
tdis(CLKL-A) Disable time, address, PS, DS, IS high impedance from CLKOUT low 5 ns
tdis(CLKL-RW) Disable time, R/W high impedance from CLKOUT low 5 ns
tdis(CLKL-S) Disable time, MSTRB, IOSTRB high impedance from CLKOUT low 5 ns
ten(CLKL-A) Enable time, address, PS, DS, IS from CLKOUT low 2H+5 ns
ten(CLKL-RW) Enable time, R/W enabled from CLKOUT low 2H+5 ns
ten(CLKL-S) Enable time, MSTRB, IOSTRB enabled from CLKOUT low 2 2H+5 ns
tv(HOLDA)
Valid time, HOLDA low after CLKOUT low −1 2 ns
tv(HOLDA) Valid time, HOLDA high after CLKOUT low −1 2 ns
tw(HOLDA) Pulse duration, HOLDA low duration 2H−1 ns
IOSTRB
MSTRB
R/W
D[15:0]
PS, DS, IS
A[19:0]
HOLDA
HOLD
CLKOUT
ten(CLKL-S)
ten(CLKL-S)
ten(CLKL-RW)
tdis(CLKL-S)
tdis(CLKL-S)
tdis(CLKL-RW)
tdis(CLKL-A)
tv(HOLDA) tv(HOLDA)
tw(HOLDA)
tw(HOLD)
tsu(HOLD) tsu(HOLD)
ten(CLKL-A)
Figure 21. HOLD and HOLDA Timings (HM = 1)
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
reset, BIO, interrupt, and MP/MC timings
timing requirements for reset, BIO, interrupt, and MP/MC [H = 0.5 tc(CO)] (see Figure 22, Figure 23,
and Figure 24)
MIN
MAX
UNIT
MIN
MAX
UNIT
th(RS) Hold time, RS after CLKOUT low 0 ns
th(BIO) Hold time, BIO after CLKOUT low 0 ns
th(INT) Hold time, INTn, NMI, after CLKOUT low†0 ns
th(MPMC) Hold time, MP/MC after CLKOUT low 0 ns
tw(RSL) Pulse duration, RS lowठ4H+5 ns
tw(BIO)S Pulse duration, BIO low, synchronous 2H+2 ns
tw(BIO)A Pulse duration, BIO low, asynchronous 4H ns
tw(INTH)S Pulse duration, INTn, NMI high (synchronous) 2H ns
tw(INTH)A Pulse duration, INTn, NMI high (asynchronous) 4H ns
tw(INTL)S Pulse duration, INTn, NMI low (synchronous) 2H+2 ns
tw(INTL)A Pulse duration, INTn, NMI low (asynchronous) 4H ns
tw(INTL)WKP Pulse duration, INTn, NMI low for IDLE2/IDLE3 wakeup 10 ns
tsu(RS) Setup time, RS before X2/CLKIN low¶5 ns
tsu(BIO) Setup time, BIO before CLKOUT low 7 10 ns
tsu(INT) Setup time, INTn, NMI, RS before CLKOUT low 7 10 ns
tsu(MPMC) Setup time, MP/MC before CLKOUT low 5 ns
†The external interrupts (INT0−INT3, NMI) are synchronized to the core CPU by way of a two-flip-flop synchronizer which samples these inputs
with consecutive falling edges of CLKOUT. The input to the interrupt pins is required to represent a 1-0-0 sequence at the timing that is
corresponding to three CLKOUT sampling sequences.
‡If the PLL mode is selected, then at power-on sequence, or at wakeup from IDLE3, RS must be held low for at least 50 µs to ensure
synchronization and lock-in of the PLL.
§Note that RS may cause a change in clock frequency, therefore changing the value of H.
¶Divide-by-two mode
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52 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
reset, BIO, interrupt, and MP/MC timings (continued)
BIO
CLKOUT
RS, INTn, NMI
X2/CLKIN
th(BIO)
th(RS)
tsu(INT)
tw(BIO)S
tsu(BIO)
tw(RSL)
tsu(RS)
Figure 22. Reset and BIO Timings
INTn, NMI
CLKOUT
th(INT)
tsu(INT)
tsu(INT)
tw(INTL)A
tw(INTH)A
Figure 23. Interrupt Timing
MP/MC
RS
CLKOUT
tsu(MPMC)
th(MPMC)
Figure 24. MP/MC Timing
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
instruction acquisition (IAQ), interrupt acknowledge (IACK), external flag (XF), and TOUT timings
switching characteristics over recommended operating conditions for IAQ and IACK
[H = 0.5 tc(CO)] (see Figure 25)
PARAMETER MIN MAX UNIT
td(CLKL-IAQL) Delay time, CLKOUT low to IAQ low −1 3 ns
td(CLKL-IAQH) Delay time, CLKOUT low to IAQ high −1 3 ns
td(A)IAQ Delay time, address valid to IAQ low 1 ns
td(CLKL-IACKL) Delay time, CLKOUT low to IACK low −1 3 ns
td(CLKL-IACKH) Delay time , CLKOUT low to IACK high −1 3 ns
td(A)IACK Delay time, address valid to IACK low 3 ns
th(A)IAQ Hold time, IAQ high after address invalid −2 ns
th(A)IACK Hold time, IACK high after address invalid −2 ns
tw(IAQL) Pulse duration, IAQ low 2H−2 ns
tw(IACKL) Pulse duration, IACK low 2H−2 ns
MSTRB
IACK
IAQ
A[19:0]
CLKOUT
td(A)IACK
td(A)IAQ
tw(IACKL)
th(A)IACK
td(CLKL-IACKL)
tw(IAQL)
th(A)IAQ
td(CLKL-IAQL)
td(CLKL-IACKH)
td(CLKL-IAQH)
Figure 25. IAQ and IACK Timings
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54 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
instruction acquisition (IAQ), interrupt acknowledge (IACK), external flag (XF), and TOUT timings
(continued)
switching characteristics over recommended operating conditions for XF and TOUT
[H = 0.5 tc(CO)] (see Figure 26 and Figure 27)
PARAMETER MIN MAX UNIT
td(XF)
Delay time, CLKOUT low to XF high −1 3
ns
td(XF) Delay time, CLKOUT low to XF low −1 3 ns
td(TOUTH) Delay time, CLKOUT low to TOUT high 0 4 ns
td(TOUTL) Delay time, CLKOUT low to TOUT low 0 4 ns
tw(TOUT) Pulse duration, TOUT 2H ns
XF
CLKOUT
td(XF)
Figure 26. XF Timing
TOUT
CLKOUT
tw(TOUT)
td(TOUTL)
td(TOUTH)
Figure 27. TOUT Timing
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multichannel buffered serial port timing
timing requirements for McBSP [H=0.5tc(CO)]†(see Figure 28 and Figure 29)
MIN MAX UNIT
tc(BCKRX) Cycle time, BCLKR/X BCLKR/X ext 4H ns
tw(BCKRX) Pulse duration, BCLKR/X high or BCLKR/X low BCLKR/X ext 2H−2 ns
tsu(BFRH-BCKRL)
Setup time, external BFSR high before BCLKR low
BCLKR int 8
ns
tsu(BFRH-BCKRL) Setup time, external BFSR high before BCLKR low BCLKR ext 1ns
th(BCKRL-BFRH)
Hold time, external BFSR high after BCLKR low
BCLKR int 0
ns
th(BCKRL-BFRH) Hold time, external BFSR high after BCLKR low BCLKR ext 3ns
tsu(BDRV-BCKRL)
Setup time, BDR valid before BCLKR low
BCLKR int 5
ns
tsu(BDRV-BCKRL) Setup time, BDR valid before BCLKR low BCLKR ext 0ns
th(BCKRL-BDRV)
Hold time, BDR valid after BCLKR low
BCLKR int 0
ns
th(BCKRL-BDRV) Hold time, BDR valid after BCLKR low BCLKR ext 4ns
tsu(BFXH-BCKXL)
Setup time, external BFSX high before BCLKX low
BCLKX int 7
ns
tsu(BFXH-BCKXL) Setup time, external BFSX high before BCLKX low BCLKX ext 0ns
th(BCKXL-BFXH)
Hold time, external BFSX high after BCLKX low
BCLKX int 0
ns
th(BCKXL-BFXH) Hold time, external BFSX high after BCLKX low BCLKX ext 3ns
tr(BCKRX) Rise time, BCKR/X BCLKR/X ext 8 ns
tf(BCKRX) Fall time, BCKR/X BCLKR/X ext 8 ns
†CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
switching characteristics for McBSP [H=0.5tc(CO)]† (see Figure 28 and Figure 29)
PARAMETER MIN MAX UNIT
tc(BCKRX) Cycle time, BCLKR/X BCLKR/X int 4H ns
tw(BCKRXH) Pulse duration, BCLKR/X high BCLKR/X int D − 2‡D + 2‡ns
tw(BCKRXL) Pulse duration, BCLKR/X low BCLKR/X int C − 2‡C + 2‡ns
td(BCKRH-BFRV)
Delay time, BCLKR high to internal BFSR valid
BCLKR int −2 2 ns
td(BCKRH-BFRV) Delay time, BCLKR high to internal BFSR valid BCLKR ext 3 9 ns
td(BCKXH-BFXV)
Delay time, BCLKX high to internal BFSX valid
BCLKX int 0 4
ns
td(BCKXH-BFXV) Delay time, BCLKX high to internal BFSX valid BCLKX ext 811 ns
tdis(BCKXH-BDXHZ)
Disable time, BCLKX high to BDX high impedance following last data
BCLKX int −1 4
ns
tdis(BCKXH-BDXHZ
)
Disable time, BCLKX high to BDX high impedance following last data
bit of transfer BCLKX ext 3 9 ns
td(BCKXH-BDXV)
Delay time, BCLKX high to BDX valid
DXENA = 0§
BCLKX int 0¶7
ns
td(BCKXH-BDXV) Delay time, BCLKX high to BDX valid DXENA = 0
§
BCLKX ext 311 ns
td(BFXH-BDXV)
Delay time, BFSX high to BDX valid BFSX int −1¶3
ns
td(BFXH-BDXV) ONLY applies when in data delay 0 (XDATDLY = 00b) mode BFSX ext 3 13 ns
†CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
‡T = BCLKRX period = (1 + CLKGDV) * 2H
C = BCLKRX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2H when CLKGDV is even
D = BCLKRX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2H when CLKGDV is even
§The transmit delay enable (DXENA) and A−bis mode (ABIS) features of the McBSP are not implemented on the TMS320VC5402.
¶Minimum delay times also represent minimum output hold times.
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56 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
multichannel buffered serial port timing (continued)
(n−2)Bit (n−1)
(n−3)(n−2)Bit (n−1)
(n−4)(n−3)(n−2)Bit (n−1)
th(BCKRL−BDRV)
tsu(BDRV−BCKRL)
th(BCKRL−BDRV)
tsu(BDRV−BCKRL)
tsu(BDRV−BCKRL) th(BCKRL−BDRV)
th(BCKRL−BFRH)
tsu(BFRH−BCKRL)
td(BCKRH−BFRV)
td(BCKRH−BFRV) tr(BCKRX)
tr(BCKRX)
tw(BCKRXL)
tc(BCKRX)
tw(BCKRXH)
(RDATDLY=10b)
BDR
(RDATDLY=01b)
BDR
(RDATDLY=00b)
BDR
BFSR (ext)
BFSR (int)
BCLKR
Figure 28. McBSP Receive Timings
td(BCKXH−BDXV)
td(BCKXH−BDXV)
tdis(BCKXH−BDXHZ)
td(BCKXH−BDXV)
td(BDFXH−BDXV)
(XDATDLY=10b)
BDX
(XDATDLY=01b)
BDX
(XDATDLY=00b)
BDX
(n−2)Bit (n−1)Bit 0
(n−4)Bit (n−1) (n−3)(n−2)
Bit 0
(n−3)(n−2)Bit (n−1)
Bit 0
th(BCKXL−BFXH)
tf(BCKRX)
tr(BCKRX)
tw(BCKRXL)
tc(BCKRX)
tw(BCKRXH)
BFSX (ext)
BFSX (int)
BCLKX
td(BCKXH−BFXV)
td(BCKXH−BFXV)
tsu(BFXH−BCKXL)
Figure 29. McBSP Transmit Timings
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multichannel buffered serial port timing (continued)
timing requirements for McBSP general-purpose I/O (see Figure 30)
MIN MAX UNIT
tsu(BGPIO-COH) Setup time, BGPIOx input mode before CLKOUT high†9 ns
th(COH-BGPIO) Hold time, BGPIOx input mode after CLKOUT high†0 ns
†BGPIOx refers to BCLKRx, BFSRx, BDRx, BCLKXx, or BFSXx when configured as a general-purpose input.
switching characteristics for McBSP general-purpose I/O (see Figure 30)
PARAMETER MIN MAX UNIT
td(COH-BGPIO) Delay time, CLKOUT high to BGPIOx output mode‡0 5 ns
‡BGPIOx refers to BCLKRx, BFSRx, BCLKXx, BFSXx, or BDXx when configured as a general-purpose output.
tsu(BGPIO-COH)
th(COH-BGPIO)
td(COH-BGPIO)
CLKOUT
BGPIOx Input
Mode†
BGPIOx Output
Mode‡
†BGPIOx refers to BCLKRx, BFSRx, BDRx, BCLKXx, or BFSXx when configured as a general-purpose input.
‡BGPIOx refers to BCLKRx, BFSRx, BCLKXx, BFSXx, or BDXx when configured as a general-purpose output.
Figure 30. McBSP General-Purpose I/O Timings
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58 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
multichannel buffered serial port timing (continued)
timing requirements for McBSP as SPI master or slave: [H=0.5tc(CO)] CLKSTP = 10b, CLKXP = 0†
(see Figure 31)
MASTER SLAVE
UNIT
MIN MAX MIN MAX
UNIT
tsu(BDRV-BCKXL) Setup time, BDR valid before BCLKX low 9− 12H ns
th(BCKXL-BDRV) Hold time, BDR valid after BCLKX low 05 + 12H ns
tsu(BFXL-BCKXH) Setup time, BFSX low before BCLKX high 10 ns
tc(BCKX) Cycle time, BCLKX 12H 32H ns
†For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
switching characteristics for McBSP as SPI master or slave: [H=0.5tc(CO)] CLKSTP = 10b,
CLKXP = 0† (see Figure 31)
PARAMETER
MASTER‡SLAVE
UNIT
PARAMETER
MIN MAX MIN MAX
UNIT
th(BCKXL-BFXL) Hold time, BFSX low after BCLKX low§T − 3 T + 4 ns
td(BFXL-BCKXH) Delay time, BFSX low to BCLKX high¶C − 5 C + 3 ns
td(BCKXH-BDXV) Delay time, BCLKX high to BDX valid −2 6 6H + 5 10H + 15 ns
tdis(BCKXL-BDXHZ) Disable time, BDX high impedance following last data bit from
BCLKX low C − 2 C + 3 ns
tdis(BFXH-BDXHZ) Disable time, BDX high impedance following last data bit from
BFSX high 2H+ 4 6H + 17 ns
td(BFXL-BDXV) Delay time, BFSX low to BDX valid 4H − 2 8H + 17 ns
†For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
‡T = BCLKX period = (1 + CLKGDV) * 2H
C = BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2H when CLKGDV is even
§FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX
and BFSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
¶BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(BCLKX).
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
BCLKX
BFSX
BDX
BDR
tsu(BDRV-BCLXL)
td(BCKXH-BDXV)
th(BCKXL-BDRV)
tdis(BFXH-BDXHZ)
tdis(BCKXL-BDXHZ)
th(BCKXL-BFXL)
td(BFXL-BDXV)
td(BFXL-BCKXH)
LSB MSB
tsu(BFXL-BCKXH) tc(BCKX)
Figure 31. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
SPRS079G − OC TOBER 1998 − REVISED OCTOBER 2008
59
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
multichannel buffered serial port timing (continued)
timing requirements for McBSP as SPI master or slave: [H=0.5tc(CO)] CLKSTP = 11b, CLKXP = 0†
(see Figure 32)
MASTER SLAVE
UNIT
MIN MAX MIN MAX
UNIT
tsu(BDRV-BCKXH) Setup time, BDR valid before BCLKX high 12 2 − 12H ns
th(BCKXH-BDRV) Hold time, BDR valid after BCLKX high 45 + 12H ns
tsu(BFXL-BCKXH) Setup time, BFSX low before BCLKX high 10 ns
tc(BCKX) Cycle time, BCLKX 12H 32H ns
†For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
switching characteristics for McBSP as SPI master or slave: [H=0.5tc(CO)] CLKSTP = 11b,
CLKXP = 0† (see Figure 32)
PARAMETER
MASTER‡SLAVE
UNIT
PARAMETER
MIN MAX MIN MAX
UNIT
th(BCKXL-BFXL) Hold time, BFSX low after BCLKX low§C − 3 C + 4 ns
td(BFXL-BCKXH) Delay time, BFSX low to BCLKX high¶T − 5 T + 3 ns
td(BCKXL-BDXV) Delay time, BCLKX low to BDX valid −2 6 6H + 5 10H + 15 ns
tdis(BCKXL-BDXHZ) Disable time, BDX high impedance following last data bit from
BCLKX low −2 4 6H + 3 10H + 17 ns
td(BFXL-BDXV) Delay time, BFSX low to BDX valid D − 2 D + 4 4H − 2 8H + 17 ns
†For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
‡T = BCLKX period = (1 + CLKGDV) * 2H
C = BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2H when CLKGDV is even
D = BCLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2H when CLKGDV is even
§FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX
and BFSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
¶BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(BCLKX).
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
BCLKX
BFSX
BDX
BDR
td(BFXL-BCKXH)
tdis(BCKXL-BDXHZ) td(BCKXL-BDXV)
th(BCKXH-BDRV)
tsu(BDRV-BCKXH)
td(BFXL-BDXV)
th(BCKXL-BFXL)
LSB MSB
tsu(BFXL-BCKXH) tc(BCKX)
Figure 32. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
SPRS079G − OC TOBER 1998 − REVISED OCTOBER 2008
60 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
multichannel buffered serial port timing (continued)
timing requirements for McBSP as SPI master or slave: [H=0.5tc(CO)] CLKSTP = 10b, CLKXP = 1†
(see Figure 33)
MASTER SLAVE
UNIT
MIN MAX MIN MAX
UNIT
tsu(BDRV-BCKXH) Setup time, BDR valid before BCLKX high 12 2 − 12H ns
th(BCKXH-BDRV) Hold time, BDR valid after BCLKX high 45 + 12H ns
tsu(BFXL-BCKXL) Setup time, BFSX low before BCLKX low 10 ns
tc(BCKX) Cycle time, BCLKX 12H 32H ns
†For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
switching characteristics for McBSP as SPI master or slave: [H=0.5tc(CO)] CLKSTP = 10b,
CLKXP = 1†‡ (see Figure 33)
PARAMETER
MASTER SLAVE
UNIT
PARAMETER
MIN MAX MIN MAX
UNIT
th(BCKXH-BFXL) Hold time, BFSX low after BCLKX high§T − 3 T + 4 ns
td(BFXL-BCKXL) Delay time, BFSX low to BCLKX low¶D − 5 D + 3 ns
td(BCKXL-BDXV) Delay time, BCLKX low to BDX valid −2 6 6H + 5 10H + 15 ns
tdis(BCKXH-BDXHZ) Disable time, BDX high impedance following last data bit from
BCLKX high D − 2 D + 3 ns
tdis(BFXH-BDXHZ) Disable time, BDX high impedance following last data bit from
BFSX high 2H + 3 6H + 17 ns
td(BFXL-BDXV) Delay time, BFSX low to BDX valid 4H − 2 8H + 17 ns
†For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
‡T = BCLKX period = (1 + CLKGDV) * 2H
D = BCLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2H when CLKGDV is even
§FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX
and BFSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
¶BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(BCLKX).
tsu(BFXL-BCKXL)
th(BCKXH-BDRV)
tdis(BFXH-BDXHZ)
tdis(BCKXH-BDXHZ)
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
BCLKX
BFSX
BDX
BDR
td(BFXL-BCKXL)
td(BFXL-BDXV) td(BCKXL-BDXV)
tsu(BDRV-BCKXH)
th(BCKXH-BFXL)
LSB MSB tc(BCKX)
Figure 33. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
SPRS079G − OC TOBER 1998 − REVISED OCTOBER 2008
61
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
multichannel buffered serial port timing (continued)
timing requirements for McBSP as SPI master or slave: [H=0.5tc(CO)] CLKSTP = 11b, CLKXP = 1†
(see Figure 34)
MASTER SLAVE
UNIT
MIN MAX MIN MAX
UNIT
tsu(BDRV-BCKXL) Setup time, BDR valid before BCLKX low 9− 12H ns
th(BCKXL-BDRV) Hold time, BDR valid after BCLKX low 05 + 12H ns
tsu(BFXL-BCKXL) Setup time, BFSX low before BCLKX low 10 ns
tc(BCKX) Cycle time, BCLKX 12H 32H ns
†For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
switching characteristics for McBSP as SPI master or slave: [H=0.5tc(CO)] CLKSTP = 11b,
CLKXP = 1†‡ (see Figure 34)
PARAMETER
MASTER‡SLAVE
UNIT
PARAMETER
MIN MAX MIN MAX
UNIT
th(BCKXH-BFXL) Hold time, BFSX low after BCLKX high§D − 3 D + 4 ns
td(BFXL-BCKXL) Delay time, BFSX low to BCLKX low¶T − 5 T + 3 ns
td(BCKXH-BDXV) Delay time, BCLKX high to BDX valid −2 6 6H + 5 10H + 15 ns
tdis(BCKXH-BDXHZ) Disable time, BDX high impedance following last data bit from
BCLKX high −2 4 6H + 3 10H + 17 ns
td(BFXL-BDXV) Delay time, BFSX low to BDX valid C − 2 C + 4 4H − 2 8H + 17 ns
†For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
‡T = BCLKX period = (1 + CLKGDV) * 2H
C = BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2H when CLKGDV is even
D = BCLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2H when CLKGDV is even
§FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX
and BFSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
¶BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(BCLKX).
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
BCLKX
BFSX
BDX
BDR
td(BFXL-BCKXL)
tsu(BDRV-BCKXL)
tdis(BCKXH-BDXHZ)
th(BCKXH-BFXL)
td(BCKXH-BDXV)
th(BCKXL-BDRV)
td(BFXL-BDXV)
LSB MSB
tsu(BFXL-BCKXL) tc(BCKX)
Figure 34. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
SPRS079G − OC TOBER 1998 − REVISED OCTOBER 2008
62 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
HPI8 timing
switching characteristics over recommended operating conditions†‡§¶ [H = 0.5tc(CO)]
(see Figure 35, Figure 36, Figure 37, and Figure 38)
PARAMETER MIN MAX UNIT
ten(DSL-HD) Enable time, HD driven from DS low 2 16 ns
Case 1a: Memory accesses when
DMAC is active in 16-bit mode and
tw(DSH) < 18H 18H+16 – tw(DSH)
Case 1b: Memory accesses when
DMAC is active in 16-bit mode and
tw(DSH) ≥ 18H 16
td(DSL-HDV1)
Delay time, DS low to HDx valid for
first byte of an HPI read
Case 1c: Memory access when
DMAC is active in 32-bit mode and
tw(DSH) < 26H 26H+16 – tw(DSH)
ns
t
d(DSL-HDV1)
Delay time, DS low to HDx valid for
first byte of an HPI read Case 1d: Memory access when
DMAC is active in 32-bit mode and
tw(DSH) ≥ 26H 16
ns
Case 2a: Memory accesses when
DMAC is inactive and tw(DSH) < 10H 10H+16 – tw(DSH)
Case 2b: Memory accesses when
DMAC is inactive and tw(DSH) ≥ 10H 16
Case 3: Register accesses 16
td(DSL-HDV2) Delay time, DS low to HDx valid for second byte of an HPI read 16 ns
th(DSH-HDV)R Hold time, HDx valid after DS high, for a HPI read 3 5 ns
tv(HYH-HDV) Valid time, HDx valid after HRDY high 9
td(DSH-HYL) Delay time, DS high to HRDY low (see Note 1) 16 ns
Case 1a: Memory accesses when
DMAC is active in 16-bit mode 18H+16 ns
td(DSH-HYH)
Delay time, DS high to HRDY high
Case 1b: Memory accesses when
DMAC is active in 32-bit mode 26H+16 ns
td(DSH-HYH) Delay time, DS high to HRDY high Case 2: Memory accesses when
DMAC is inactive 10H+16
ns
Case 3: Write accesses to HPIC
register (see Note 2) 6H+16
ns
td(HCS-HRDY) Delay time, HCS low/high to HRDY low/high 16 ns
td(COH-HYH)Delay time, CLKOUT high to HRDY high 3 ns
td(COH-HTX) Delay time, CLKOUT high to HINT change 5 ns
td(COH-GPIO) Delay time, CLKOUT high to HDx output change. HDx is configured as a
general-purpose output. 6 ns
NOTES: 1. The HRDY output is always high when the HCS input is high, regardless of DS timings.
2. This timing applies when writing a one to the DSPINT bit or HINT bit of the HPIC register. All other writes to the HPIC occur
asynchronoulsy, and do not cause HRDY to be deasserted.
†DS refers to the logical OR of HCS, HDS1, and HDS2.
‡HDx refers to any of the HPI data bus pins (HD0, HD1, HD2, etc.).
§DMAC stands for direct memory access (DMA) controller. The HPI8 shares the internal DMA bus with the DMAC, thus HPI8 access times are
affected by DMAC activity.
¶GPIO refers to the HD pins when they are configured as general-purpose input/outputs.
SPRS079G − OC TOBER 1998 − REVISED OCTOBER 2008
63
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
HPI8 timing (continued)
timing requirements†‡§ (see Figure 35, Figure 36, Figure 37, and Figure 38)
MIN MAX UNIT
tsu(HBV-DSL) Setup time, HBIL and HAD valid before DS low or before HAS low¶# 5 ns
th(DSL-HBV) Hold time, HBIL and HAD valid after DS low or after HAS low¶# 5 ns
tsu(HSL-DSL) Setup time, HAS low before DS low 10 ns
tw(DSL) Pulse duration, DS low 20 ns
tw(DSH) Pulse duration, DS high 10 ns
tsu(HDV-DSH) Setup time, HDx valid before DS high, HPI write 2 ns
th(DSH-HDV)W Hold time, HDx valid after DS high, HPI write 3 ns
tsu(GPIO-COH) Setup time, HDx input valid before CLKOUT high, HDx configured as general-purpose input 6 ns
th(GPIO-COH) Hold time, HDx input valid after CLKOUT high, HDx configured as general-purpose input 0 ns
†DS refers to the logical OR of HCS, HDS1, and HDS2.
‡HDx refers to any of the HPI data bus pins (HD0, HD1, HD2, etc.).
§GPIO refers to the HD pins when they are configured as general-purpose input/outputs.
¶HAD refers to HCNTL0, HCNTL1, and H/RW.
#When the HAS signal is used to latch the control signals, this timing refers to the falling edge of the HAS signal. Otherwise, when HAS is not used
(always high), this timing refers to the falling edge of DS.
SPRS079G − OC TOBER 1998 − REVISED OCTOBER 2008
64 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
HPI8 timing (continued)
Valid
tsu(HSL-DSL)
Valid
tsu(HBV-DSL)
tsu(HBV-DSL)‡
HAS
HBIL
th(DSL-HBV)
th(DSL-HBV)‡
td(DSH-HYH)
tw(DSL)
td(DSL-HDV1)
tv(HYH-HDV)
Valid Valid
Valid
td(COH-HYH)
Valid
tw(DSH)
td(DSH-HYL)
th(DSH-HDV)R
th(DSH-HDV)W
Valid
tsu(HDV-DSH)
td(DSL-HDV2)
ten(DSL-HD)
HCS
HDS
HRDY
HD READ
Valid
H
D WRITE
CLKOUT
Second Byte First Byte Second Byte
HAD†
†HAD refers to HCNTL0, HCNTL1, and HR/W.
‡When HAS is not used (HAS always high)
Figure 35. Using HDS to Control Accesses (HCS Always Low)
SPRS079G − OC TOBER 1998 − REVISED OCTOBER 2008
65
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
HPI8 timing (continued)
td(HCS-HRDY)
HCS
HDS
HRDY
Figure 36. Using HCS to Control Accesses
HINT
CLKOUT
td(COH-HTX)
Figure 37. HINT Timing
GPIOx Input Mode†
CLKOUT
th(GPIO-COH)
GPIOx Output Mode†
tsu(GPIO-COH)
td(COH-GPIO)
†GPIOx refers to HD0, HD1, HD2, ...HD7, when the HD bus is configured for general-purpose input/output (I/O).
Figure 38. GPIOx† Timings
SPRS079G − OC TOBER 1998 − REVISED OCTOBER 2008
66 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
mechanical data
The following packaging information reflects the most current released data available for the designated
device(s). This data is subject to change without notice and without revision of this document.
package thermal resistance characteristics
Table 1 provides the estimated thermal resistance characteristics for the recommended package types used
on the device.
Table 1. Thermal Resistance Characteristics
PARAMETER PGE PACKAGE GGU PACKAGE UNIT
RΘJA 56 38 °C/W
RΘJC 5 5 °C/W
PACKAGE OPTION ADDENDUM
www.ti.com 11-Oct-2010
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TMS320VC5402GGU100 ACTIVE BGA
MICROSTAR GGU 144 160 TBD SNPB Level-3-220C-168 HR Purchase Samples
TMS320VC5402GGUR10 ACTIVE BGA
MICROSTAR GGU 144 1000 TBD SNPB Level-3-220C-168 HR Purchase Samples
TMS320VC5402PGE100 ACTIVE LQFP PGE 144 60 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Request Free Samples
TMS320VC5402PGER10 ACTIVE LQFP PGE 144 500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples
TMS320VC5402ZGU100 ACTIVE BGA
MICROSTAR ZGU 144 160 Green (RoHS
& no Sb/Br) SNAGCU Level-3-260C-168 HR Purchase Samples
TMS320VC5402ZGUR10 ACTIVE BGA
MICROSTAR ZGU 144 1000 Green (RoHS
& no Sb/Br) SNAGCU Level-3-260C-168 HR Purchase Samples
TMX320VC5402GGU100 OBSOLETE BGA
MICROSTAR GGU 144 TBD Call TI Call TI Samples Not Available
TMX320VC5402PGE100 OBSOLETE LQFP PGE 144 TBD Call TI Call TI Samples Not Available
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
PACKAGE OPTION ADDENDUM
www.ti.com 11-Oct-2010
Addendum-Page 2
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
MECHANICAL DATA
MPBG021C – DECEMBER 1996 – REVISED MAY 2002
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
GGU (S–PBGA–N144) PLASTIC BALL GRID ARRAY
1,40 MAX
0,85
0,55
0,45 0,45
0,35
0,95
12,10
11,90 SQ
4073221-2/C 12/01
Seating Plane
5
G
1
A
D
B
C
E
F
3
2 4
H
J
L
K
M
N
76 98 1110 1312
9,60 TYP
0,80
0,80
Bottom View
A1 Corner
0,08 0,10
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice
C. MicroStar BGAt configuration
MicroStar BGA is a trademark of Texas Instruments Incorporated.
MECHANICAL DATA
MTQF017A – OCTOBER 1994 – REVISED DECEMBER 1996
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PGE (S-PQFP-G144) PLASTIC QUAD FLATPACK
4040147/C 10/96
0,27
72
0,17
37
73
0,13 NOM
0,25
0,75
0,45
0,05 MIN
36
Seating Plane
Gage Plane
108
109
144
SQ
SQ
22,20
21,80
1
19,80
17,50 TYP
20,20
1,35
1,45
1,60 MAX
M
0,08
0°–7°
0,08
0,50
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
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Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products Applications
Amplifiers amplifier.ti.com Audio www.ti.com/audio
Data Converters dataconverter.ti.com Automotive www.ti.com/automotive
DLP® Products www.dlp.com Communications and www.ti.com/communications
Telecom
DSP dsp.ti.com Computers and www.ti.com/computers
Peripherals
Clocks and Timers www.ti.com/clocks Consumer Electronics www.ti.com/consumer-apps
Interface interface.ti.com Energy www.ti.com/energy
Logic logic.ti.com Industrial www.ti.com/industrial
Power Mgmt power.ti.com Medical www.ti.com/medical
Microcontrollers microcontroller.ti.com Security www.ti.com/security
RFID www.ti-rfid.com Space, Avionics & www.ti.com/space-avionics-defense
Defense
RF/IF and ZigBee® Solutions www.ti.com/lprf Video and Imaging www.ti.com/video
Wireless www.ti.com/wireless-apps
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