ESURGENT Data Sheet S E M I C O N D U C T O R Comlinear CLC2000, CLC4000 (R) FEATURES n 9.4V pp output drive into RL= 25 n Using both amplifiers, 18.8V pp differential output drive into RL= 25 n 200mA @ V = 9.4V o pp n 0.009%/0.06 differential gain/ phase error n 250MHz -3dB bandwidth at G = 2 n 510MHz -3dB bandwidth at G = 1 n 210V/s slew rate n 4.5nV/Hz input voltage noise n 2.7pA/Hz input current noise n 7mA supply current n Fully specified at 5V and 12V supplies General Description APPLICATIONS n ADSL PCI modem cards n ADSL external modems n Cable drivers n Video line driver n Twisted pair driver/receiver n Power line communications Typical Application - ADSL Application The Comlinear CLC2000 and CLC400 are dual and quad voltage feedback amplifiers that offer 200mA of output current at 9.4Vpp. The CLC2000 and CLC4000 are capable of driving signals to within 1V of the power rails. When connected as a differential line driver, the amplifier drives signals up to 18.8Vpp into a 25 load, which supports the peak upstream power levels for upstream full-rate ADSL CPE applications. The Comlinear CLC2000 and CLC4000 can operate from single or dual supplies from 5V to 12V. It consumes only 7mA of supply current per channel. The combination of wide bandwidth, low noise, low distortion, and high output current capability makes the CLC2000 and CLC4000 ideally suited for Customer Premise ADSL or video line driving applications. +Vs + 1/2 CLC2000 Rf+ Ro+=12.5 Vo+ 1:2 VIN Rg RL=100 Rf- VOUT Vo- Ro-=12.5 1/2 CLC2000 - -Vs Rev 1D.R Ordering Information Part Number Package Pb-Free Operating Temperature Range Packaging Method CLC2000ISO8X SOIC-8 Yes -40C to +85C Reel CLC2000ISO8* SOIC-8 Yes -40C to +85C Rail CLC4000ISO14X* SOIC-14 Yes -40C to +85C Reel CLC4000ISO14* SOIC-14 Yes -40C to +85C Rail Moisture sensitivity level for all parts is MSL-1. *Contact Resurgent Semiconductor for availability. (c) 2018 Resurgent Semiconductor, LLC 1 / 19 Comlinear CLC2000, CLC4000 High Output Current Dual and Quad Amplifiers High Output Current Dual and Quad Amplifiers Rev 1D.R Data Sheet CLC2000 Pin Assignments CLC2000 Pin Configuration 1 8 +VS -IN1 2 7 OUT2 +IN1 3 6 -IN2 -V S 4 5 +IN2 -IN1 Pin Name Description 1 OUT1 Output, channel 1 2 -IN1 Negative input, channel 1 3 +IN1 Positive input, channel 1 4 -VS 5 +IN2 Negative supply Positive input, channel 2 6 -IN2 Negative input, channel 2 7 OUT2 Output, channel 2 8 +VS Positive supply CLC4000 Pin Configuration CLC4000 Pin Configuration OUT1 Pin No. Pin No. Pin Name 1 OUT1 Description Output, channel 1 1 14 OUT4 2 -IN1 Negative input, channel 1 2 13 -IN4 3 +IN1 Positive input, channel 1 4 +VS Positive supply 5 +IN2 Positive input, channel 2 +IN1 3 12 +IN4 +VS 4 11 -VS 6 -IN2 Negative input, channel 2 +IN2 5 10 +IN3 7 OUT2 Output, channel 2 -IN2 6 9 -IN3 8 OUT3 Output, channel 3 7 8 OUT3 9 -IN3 Negative input, channel 3 10 +IN3 Positive input, channel 3 11 -VS 12 +IN4 Positive input, channel 4 13 -IN4 Negative input, channel 4 14 OUT4 Output, channel 4 OUT2 Comlinear CLC2000, CLC4000 High Output Current Dual and Quad Amplifiers OUT1 Negative supply Rev 1D.R (c) 2018 Resurgent Semiconductor, LLC 2 / 19 Rev 1D.R Data Sheet Absolute Maximum Ratings The safety of the device is not guaranteed when it is operated above the "Absolute Maximum Ratings". The device should not be operated at these "absolute" limits. Adhere to the "Recommended Operating Conditions" for proper device function. The information contained in the Electrical Characteristics tables and Typical Performance plots reflect the operating conditions noted on the tables and plots. Supply Voltage Input Voltage Range Min Max Unit 0 -Vs -0.5V 7 or 14 +Vs +0.5V V V Comlinear CLC2000, CLC4000 High Output Current Dual and Quad Amplifiers Parameter Reliability Information Parameter Junction Temperature Storage Temperature Range Lead Temperature (Soldering, 10s) Package Thermal Resistance 8-Lead SOIC 14-Lead SOIC Min Typ -65 Max Unit 150 150 260 C C C 100 88 C/W C/W Notes: Package thermal resistance (qJA), JDEC standard, multi-layer test boards, still air. ESD Protection Product Human Body Model (HBM) Charged Device Model (CDM) 2.5kV 2kV Recommended Operating Conditions Parameter Min Operating Temperature Range Supply Voltage Range -40 2.5 Typ Max Unit +85 6.5 C V Rev 1D.R (c) 2018 Resurgent Semiconductor, LLC 3 / 19 Rev 1D.R Data Sheet Electrical Characteristics TA = 25C, Vs = 5V, Rf = Rg = 510, RL = 100 to VS/2, G = 2; unless otherwise noted. Symbol Parameter Conditions Min Typ Max Units Frequency Domain Response -3dB Bandwidth G = +1, VOUT = 0.2Vpp, Rf = 0 422 MHz BWSS BWLS -3dB Bandwidth G = +2, VOUT = 0.2Vpp 236 MHz Large Signal Bandwidth G = +2, VOUT = 2Vpp 68 BW0.1dB MHz 0.1dB Gain Flatness G = +2, VOUT = 0.2Vpp 77 MHz Time Domain Response tR, tF Rise and Fall Time VOUT = 1V step; (10% to 90%) 3.7 ns tS Settling Time to 0.1% VOUT = 2V step 20 ns OS Overshoot VOUT = 0.2V step 6 % SR Slew Rate VOUT = 2V step 200 V/s 2Vpp, 100KHz, RL = 25 -83 dBc 2Vpp, 1MHz, RL = 100 -85 dBc 2Vpp, 100KHz, RL = 25 -86 dBc 2Vpp, 1MHz, RL = 100 -82 dBc % Distortion/Noise Response HD2 2nd Harmonic Distortion HD3 3rd Harmonic Distortion DG Differential Gain NTSC (3.58MHz), DC-coupled, RL = 150 0.01 DP Differential Phase NTSC (3.58MHz), DC-coupled, RL = 150 0.05 en Input Voltage Noise > 1MHz 4.2 nV/Hz in Input Current Noise > 1MHz 2.7 pA/Hz XTALK Crosstalk Channel-to-channel 5MHz -63 dB DC Performance VIO Input Offset Voltage 0.3 mV dVIO Average Drift 0.383 V/C IIO Input Offset Current 0.2 A Ib Input Bias Current 10 A Average Drift 2.5 nA/C 81 dB dIbni PSRR Power Supply Rejection Ratio DC AOL Open-Loop Gain RL = 25 76 dB IS Supply Current per channel 6.75 mA Non-inverting 2.5 M 1 pF 0.4 to 4.6 V 80 dB Input Characteristics RIN Input Resistance CIN Input Capacitance CMIR Common Mode Input Range CMRR Common Mode Rejection Ratio DC Output Characteristics RO ISC Closed Loop, DC 0.01 RL = 25 0.95 to 4.05 V RL = 1k 0.75 to 4.25 V 1000 mA Output Voltage Swing Short-Circuit Output Current VOUT = VS / 2 (c) 2018 Resurgent Semiconductor, LLC 4 / 19 Rev 1D.R Rev 1D.R VOUT Output Resistance Comlinear CLC2000, CLC4000 High Output Current Dual and Quad Amplifiers UGBW Data Sheet Electrical Characteristics TA = 25C, Vs = 12V, Rf = Rg = 510, RL = 100 to VS/2, G = 2; unless otherwise noted. Symbol Parameter Conditions Min Typ Max Units Frequency Domain Response -3dB Bandwidth G = +1, VOUT = 0.2Vpp, Rf = 0 510 MHz BWSS BWLS -3dB Bandwidth G = +2, VOUT = 0.2Vpp 250 MHz Large Signal Bandwidth G = +2, VOUT = 4Vpp 35 BW0.1dB MHz 0.1dB Gain Flatness G = +2, VOUT = 0.2Vpp 32 MHz 13.3 ns 20 ns Time Domain Response tR, tF Rise and Fall Time VOUT = 4V step; (10% to 90%) tS Settling Time to 0.1% VOUT = 2V step OS Overshoot VOUT = 0.2V step 2 % SR Slew Rate VOUT = 4V step 210 V/s 2Vpp, 100KHz, RL = 25 -84 dBc 2Vpp, 1MHz, RL = 100 -86 dBc 8.4Vpp, 100KHz, RL = 25 -63 dBc 8.4Vpp, 1MHz, RL = 100 -82 dBc 2Vpp, 100KHz, RL = 25 -88 dBc 2Vpp, 1MHz, RL = 100 -80 dBc 8.4Vpp, 100KHz, RL = 25 -63 dBc Distortion/Noise Response HD2 2nd Harmonic Distortion HD3 3rd Harmonic Distortion DG Differential Gain DP 8.4Vpp, 1MHz, RL = 100 -83 dBc NTSC (3.58MHz), DC-coupled, RL = 150 0.009 % Differential Phase NTSC (3.58MHz), DC-coupled, RL = 150 0.06 en Input Voltage Noise > 1MHz 4.5 nV/Hz in Input Current Noise > 1MHz 2.7 pA/Hz Crosstalk Channel-to-channel 5MHz -62 dB XTALK DC Performance VIO dVIO Input Offset Voltage(1) -6 Average Drift 0.3 6 0.383 IIO Input Offset Current(1) 0.2 2 Ib Input Bias Current(1) 10 20 Average Drift 2.5 nA/C 81 dB dIbni -2 mV V/C PSRR Power Supply Rejection Ratio(1) DC AOL Open-Loop Gain RL = 25 73 76 IS Supply Current(1) per channel 7 A A dB 12 mA Input Characteristics RIN Input Resistance CIN Input Capacitance CMIR Common Mode Input Range CMRR Common Mode Rejection Ratio(1) Non-inverting M 1 pF 0.6 to 11.4 V 70 79 dB Closed Loop, DC 0.01 RL = 25 (1) 1.5 1.2 to 10.8 DC Rev 1D.R 2.5 Output Characteristics RO VOUT ISC Output Resistance Output Voltage Swing Short-Circuit Output Current 10.5 V RL = 1k 0.8 to 11.2 V VOUT = VS / 2 1000 mA Notes: 1. 100% tested at 25C (c) 2018 Resurgent Semiconductor, LLC 5 / 19 Comlinear CLC2000, CLC4000 High Output Current Dual and Quad Amplifiers UGBW Rev 1D.R Data Sheet Typical Performance Characteristics TA = 25C, Vs = 12V, Rf = 510, RL = 100 to VS/2, G = 2; unless otherwise noted. Non-Inverting Frequency Response (VS=5V) 1 2 0 1 Normalized Gain (dB) -1 G = 10 -2 G=2 G=5 -3 -4 G=1 Rf = 0 -5 -6 G=1 Rf = 0 0 -1 G = 10 G=5 -3 -4 -5 VOUT = 0.2Vpp -7 VOUT = 0.2Vpp -6 0.1 1 10 100 1000 0.1 1 Frequency (MHz) 10 1000 Inverting Frequency Response (VS=5V) 1 1 G = -1 0 G = -1 0 -1 -1 Normalized Gain (dB) G = -2 -2 G = -10 -3 -4 G = -5 -5 G = -2 -2 G = -10 -3 -4 G = -5 -5 -6 -6 VOUT = 0.2Vpp -7 VOUT = 0.2Vpp -7 0.1 1 10 100 1000 0.1 1 Frequency (MHz) 10 100 1000 100 1000 Frequency (MHz) Frequency Response vs. RL Frequency vs. RL (VS = 5V) 2 2 RL = 5k 1 RL = 5k 1 RL = 1k Normalized Gain (dB) 0 -1 -2 RL = 150 -3 RL = 50 -4 -5 RL = 1k 0 -1 -2 RL = 150 -3 RL = 50 -4 -5 VOUT = 0.2Vpp VOUT = 0.2Vpp RL = 25 -6 Rev 1D.R Normalized Gain (dB) 100 Frequency (MHz) Inverting Frequency Response Normalized Gain (dB) G=2 -2 RL = 25 -6 0.1 1 10 100 1000 0.1 Frequency (MHz) (c) 2018 Resurgent Semiconductor, LLC 1 10 Frequency (MHz) 6 / 19 Comlinear CLC2000, CLC4000 High Output Current Dual and Quad Amplifiers Normalized Gain (dB) Non-Inverting Frequency Response Rev 1D.R Data Sheet Typical Performance Characteristics TA = 25C, Vs = 12V, Rf = 510, RL = 100 to VS/2, G = 2; unless otherwise noted. Frequency vs. CL Frequency vs. CL (VS = 5V) 1 0 0 CL = 1000pF Rs = 5 CL = 500pF Rs = 6 -2 -3 CL = 100pF Rs = 13 -4 CL = 50pF Rs = 20 -5 -6 CL = 1000pF Rs = 5 -1 Normalized Gain (dB) Normalized Gain (dB) -1 -3 CL = 100pF Rs = 13 -4 CL = 50pF Rs = 25 -5 -6 CL = 10pF Rs = 30 VOUT = 0.2Vpp CL = 500pF Rs = 6 -2 -7 VOUT = 0.2Vpp -7 0.1 1 10 100 1000 0.1 1 Frequency (MHz) 100 1000 Recommended RS vs. CL (VS = 5V) 45 40 35 30 RS () RS () 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 0 10 Frequency (MHz) Recommended RS vs. CL 25 20 15 10 VOUT = 0.2Vpp RS optimized for <1dB peaking 10 VOUT = 0.2Vpp RS optimized for <1dB peaking 5 0 100 1000 10 100 CL (pf) 1000 CL (pF) Frequency Response vs. VOUT Frequency Response vs. VOUT (VS = 5V) 1 1 VOUT = 1Vpp 0 Normalized Gain (dB) -1 VOUT = 5Vpp VOUT = 2Vpp -2 -3 VOUT = 4Vpp -4 VOUT = 1Vpp 0 -5 -6 -1 VOUT = 2Vpp -2 -3 VOUT = 3Vpp -4 Rev 1D.R Normalized Gain (dB) CL = 10pF Rs = 45 -5 -6 -7 -7 0.1 1 10 100 1000 0.1 Frequency (MHz) (c) 2018 Resurgent Semiconductor, LLC 1 10 100 1000 Frequency (MHz) 7 / 19 Comlinear CLC2000, CLC4000 High Output Current Dual and Quad Amplifiers 1 Rev 1D.R Data Sheet Typical Performance Characteristics - Continued TA = 25C, Vs = 12V, Rf = 510, RL = 100 to VS/2, G = 2; unless otherwise noted. Frequency Response vs. Temperature Frequency vs. Temperature (VS = 5V) 1 - 40degC 0 + 25degC -1 Normalized Gain (dB) Normalized Gain (dB) 0 + 85degC -2 -3 -4 -5 -6 -1 -2 -3 + 25degC -4 - 40degC -5 + 85degC -6 VOUT = 2V 0.2V pp pp -7 VOUT = .2V 0.2V pppp -7 0.1 1 10 100 1000 0.1 1 Frequency (MHz) -3dB Bandwidth vs. Output Voltage 275 250 250 225 225 200 200 175 1000 150 125 100 75 175 150 125 100 75 50 50 25 25 0 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0.0 0.5 1.0 VOUT (VPP) -60 -80 Phase -100 -120 10 -140 0 -160 -10 -180 -20 1k 10k 100k 1M 10M 3.0 100M 1G -200 30 20 10 0 0.0001 0.001 Frequency (Hz) (c) 2018 Resurgent Semiconductor, LLC 40 Rev 1D.R 20 Input Voltage Noise (nV/Hz) -40 50 30 2.5 50 Open Loop Phase (deg) -20 Gain 60 40 2.0 Input Voltage Noise 0 80 70 1.5 VOUT (VPP) Open Loop Transimpendance Gain/Phase vs. Frequency Open Loop Gain (dB) 100 -3dB Bandwidth vs. Output Voltage (VS=5V) -3dB Bandwidth (MHz) -3dB Bandwidth (MHz) 10 Frequency (MHz) 0.01 0.1 1 10 100 Frequency (MHz) 8 / 19 Comlinear CLC2000, CLC4000 High Output Current Dual and Quad Amplifiers 1 Rev 1D.R Data Sheet Typical Performance Characteristics - Continued TA = 25C, Vs = 12V, Rf = 510, RL = 100 to VS/2, G = 2; unless otherwise noted. 2nd Harmonic Distortion vs. RL 3rd Harmonic Distortion vs. RL -20 -30 -30 RL = 25 RL = 25 -40 RL = 100 Distortion (dBc) Distortion (dBc) -40 -50 -60 -70 RL = 1k -80 RL = 100 -50 -60 -70 RL = 1k -80 -90 -90 VOUT = 2Vpp -100 VOUT = 2Vpp -100 0 5 10 15 20 0 5 10 Frequency (MHz) -20 -20 -30 -30 -40 -40 10MHz -60 -70 5MHz -80 -90 -50 10MHz -60 -70 5MHz -80 -90 1MHz 1MHz -100 -100 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 0.5 0.75 1 1.25 Output Amplitude (Vpp) 1.5 1.75 2 2.25 2.5 2.75 3 Output Amplitude (Vpp) Differential Gain & Phase AC Coupled Differential Gain & Phase DC Coupled 0.01 0.06 RL = 150 AC coupled into 220F 0.005 0.05 Diff Gain (%) and Diff Phase () 0.0075 DG 0.0025 0 -0.0025 -0.005 DP -0.0075 -0.01 DP 0.04 0.03 0.02 0.01 0 -0.01 DG -0.02 RL = 150 DC coupled Rev 1D.R Diff Gain (%) and Diff Phase () 20 3rd Harmonic Distortion vs. VOUT Distortion (dBc) Distortion (dBc) 2nd Harmonic Distortion vs. VOUT -50 15 Frequency (MHz) VOUT = 2Vpp -0.03 -0.7 -0.5 -0.3 -0.1 Comlinear CLC2000, CLC4000 High Output Current Dual and Quad Amplifiers -20 0.1 0.3 0.5 0.7 -0.7 Input Voltage (V) (c) 2018 Resurgent Semiconductor, LLC -0.5 -0.3 -0.1 0.1 0.3 0.5 0.7 Input Voltage (V) 9 / 19 Rev 1D.R Data Sheet Typical Performance Characteristics - Continued TA = 25C, Vs = 12V, Rf = 510, RL = 100 to VS/2, G = 2; unless otherwise noted. 2nd Harmonic Distortion vs. RL (VS=5V) -20 -30 -30 Distortion (dBc) -50 RL = 25 -40 RL = 25 RL = 100 -60 -70 RL = 1k -80 RL = 100 -50 -60 -70 RL = 1k -80 -90 -90 VOUT = 2Vpp -100 VOUT = 2Vpp -100 0 5 10 15 20 0 5 10 Frequency (MHz) 2nd Harmonic Distortion vs. VOUT (VS=5V) -45 -50 -50 10MHz -55 -60 5MHz Distortion (dBc) Distortion (dBc) -55 -65 -70 -75 -80 10MHz -60 -65 -70 5MHz -75 1MHz -80 1MHz -85 -85 -90 -90 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 0.5 0.75 1 1.25 Output Amplitude (Vpp) 1.5 1.75 2 2.25 2.5 2.75 3 Output Amplitude (Vpp) Differential Gain & Phase AC Coupled (VS=5V) Differential Gain & Phase DC Coupled (VS=5V) 0.01 0.04 RL = 150 AC coupled into 220F DG Diff Gain (%) and Diff Phase () 0.0075 0.005 0.0025 0 -0.0025 -0.005 DP -0.0075 RL = 150 DC coupled 0.03 0.02 DG 0.01 0 Rev 1D.R Diff Gain (%) and Diff Phase () 20 3rd Harmonic Distortion vs. VOUT (VS=5V) -45 15 Frequency (MHz) -0.01 DP -0.01 -0.02 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 -0.4 Input Voltage (V) (c) 2018 Resurgent Semiconductor, LLC -0.2 0 0.2 0.4 Input Voltage (V) 10 / 19 Comlinear CLC2000, CLC4000 High Output Current Dual and Quad Amplifiers -20 -40 Distortion (dBc) 3rd Harmonic Distortion vs. RL (VS=5V) Rev 1D.R Data Sheet Typical Performance Characteristics - Continued TA = 25C, Vs = 12V, Rf = 510, RL = 100 to VS/2, G = 2; unless otherwise noted. Large Signal Pulse Response 9.0 6.1 8.0 6.05 7.0 Voltage (V) 6.15 6 VOUT = 2Vpp 6.0 5.95 5.0 5.9 4.0 5.85 VOUT = 4Vpp 3.0 0 20 40 60 80 100 120 140 160 180 200 0 20 40 60 80 Time (ns) 100 120 140 160 180 200 Time (ns) Small Signal Pulse Response (VS=5V) Large Signal Pulse Response (VS=5V) 2.65 4.5 VOUT = 3Vpp 4.0 2.60 3.5 VOUT = 2Vpp Voltage (V) Voltage (V) 2.55 2.50 2.45 3.0 2.5 2.0 1.5 2.40 1.0 2.35 0.5 0 20 40 60 80 100 120 140 160 180 200 0 20 40 60 80 Time (ns) Crosstalk vs. Frequency 120 140 160 180 200 Crosstalk vs. Frequency (VS=5V) -30 -35 -35 -40 -40 -45 -45 -50 -50 Crosstalk (dB) -30 -55 -60 -65 -70 -75 -55 -60 -65 -70 Rev 1D.R Crosstalk (dB) 100 Time (ns) -75 -80 -80 VOUT = 2Vpp -85 VOUT = 2Vpp -85 -90 -90 0.1 1 10 100 0.1 Frequency (MHz) (c) 2018 Resurgent Semiconductor, LLC 1 10 100 Frequency (MHz) 11 / 19 Comlinear CLC2000, CLC4000 High Output Current Dual and Quad Amplifiers Voltage (V) Small Signal Pulse Response Rev 1D.R Data Sheet Typical Performance Characteristics - Continued TA = 25C, Vs = 12V, Rf = 510, RL = 100 to VS/2, G = 2; unless otherwise noted. Closed Loop Output Impedance vs. Frequency CMRR vs. Frequency 1 -30 CMRR (dB) Output Impedance () -20 0.1 0.01 -40 -50 -60 -70 -80 0.001 1k 10k 100k 1M 10M -90 100M 10 100 1k PSRR vs. Frequency 1M 10M 100M 1.25 1.00 -40 0.75 -50 0.50 -60 0.25 IOUT (A) PSRR (dB) 100k Input Voltage vs. Output Current -30 -70 -80 IOUT+ 0.00 -0.25 -0.50 -0.75 -90 -100 10k Frequency (Hz) Frequency (Hz) -1.00 IOUTRL = 2.668 G = -1 VS = 6V -1.25 10 100 1k 10k 100k 1M 10M 100M 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VIN (V) Frequency (Hz) Comlinear CLC2000, CLC4000 High Output Current Dual and Quad Amplifiers -10 10 Rev 1D.R (c) 2018 Resurgent Semiconductor, LLC 12 / 19 Rev 1D.R Data Sheet Application Information Basic Operation +Vs 6.8F Power Dissipation Input 0.1F + Output - RL 0.1F Rg Rf 6.8F G = 1 + (Rf/Rg) -Vs Figure 1. Typical Non-Inverting Gain Circuit +Vs R1 Input Rg 6.8F Output 0.1F Maximum power levels are set by the absolute maximum junction rating of 150C. To calculate the junction temperature, the package thermal resistance value ThetaJA (JA) is used along with the total die power dissipation. TJunction = TAmbient + (JA x PD) 0.1F + Power dissipation is an important consideration in applications with low impedance DC, coupled loads. Guidelines listed below can be used to verify that the particular application will not cause the device to operate beyond its intended operating range. Calculations below relate to a single amplifier. For the CLC2000/CLC4000, all amplifiers power contribution needs to be added for the total power dissipation. RL Rf 6.8F -Vs G = - (Rf/Rg) For optimum input offset voltage set R1 = Rf || Rg Figure 2. Typical Inverting Gain Circuit Where TAmbient is the temperature of the working environment. In order to determine PD, the power dissipated in the load needs to be subtracted from the total power delivered by the supplies. PD = Psupply - Pload Supply power is calculated by the standard power equation. Psupply = Vsupply x I(RMS supply) The CLC2000 and CLC4000 can be powered with a low noise supply anywhere in the range from +5V to +13V. Ensure adequate metal connections to power pins in the PC board layout with careful attention paid to decoupling the power supply. Vsupply = V(S+) - V(S-) High quality capacitors with low equivalent series resistance (ESR) such as multilayer ceramic capacitors (MLCC) should be used to minimize supply voltage ripple and power dissipation. (c) 2018 Resurgent Semiconductor, LLC Power delivered to a purely resistive load is: Pload = ((VLOAD)RMS2) / Rloadeff The effective load resistor will need to include the effect of the feedback network. For instance, Rloadeff in figure 1 would be calculated as: RL || (Rf + Rg) 13 / 19 Rev 1D.R Rev 1D.R Power Supply and Decoupling Comlinear CLC2000, CLC4000 High Output Current Dual and Quad Amplifiers Figures 1 and 2 illustrate typical circuit configurations for non-inverting, inverting, and unity gain topologies for dual supply applications. They show the recommended bypass capacitor values and overall closed loop gain equations. Two decoupling capacitors should be placed on each power pin with connection to a local PC board ground plane. A large, usually tantalum, 10F to 47F capacitor is required to provide good decoupling for lower frequency signals and to provide current for fast, large signal changes at the CLC2000/CLC4000 outputs. It should be within 0.25" of the pin. A secondary smaller 0.1F MLCC capacitor should located within 0.125" to reject higher frequency noise on the power line. Data Sheet These measurements are basic and are relatively easy to perform with standard lab equipment. For design purposes however, prior knowledge of actual signal levels and load impedance is needed to determine the dissipated power. Here, PD can be found from Quiescent power can be derived from the specified IS values along with known supply voltage, VSupply. Load power can be calculated as above with the desired signal amplitudes using: (VLOAD)RMS = VPEAK / 2 ( ILOAD)RMS = (VLOAD)RMS / Rloadeff The dynamic power is focused primarily within the output stage driving the load. This value can be calculated as: Driving Capacitive Loads Increased phase delay at the output due to capacitive loading can cause ringing, peaking in the frequency response, and possible unstable behavior. Use a series resistance, RS, between the amplifier and the load to help improve stability and settling performance. Refer to Figure 4. Input + PDYNAMIC = (VS+ - VLOAD)RMS x (ILOAD)RMS - Maximum Power Dissipation (W) Figure 4. Addition of RS for Driving Capacitive Loads Table 1 provides the recommended RS for various capacitive loads. The recommended RS values result in <=1dB peaking in the frequency response. The Frequency Response vs. CL plots, on page 7, illustrates the response of the CLC2000. 2.5 SOIC-14 1.5 SOIC-8 0.5 0 -40 -20 0 20 RL Rg Figure 3 shows the maximum safe power dissipation in the package vs. the ambient temperature for the 8 Lead SOIC packages. 1 Output CL Rf Assuming the load is referenced in the middle of the power rails or Vsupply/2. 2 Rs 40 60 80 Ambient Temperature (C) CL (pF) RS () -3dB BW (MHz) 10 40 275 20 24.5 250 50 20 175 100 13.5 135 500 6 75 1000 5 45 Figure 3. Maximum Power Derating Better thermal ratings can be achieved by maximizing PC board metallization at the package pins. However, be careful of stray capacitance on the input pins. In addition, increased airflow across the package can also help to reduce the effective JA of the package. (c) 2018 Resurgent Semiconductor, LLC For a given load capacitance, adjust RS to optimize the tradeoff between settling time and bandwidth. In general, reducing RS will increase bandwidth at the expense of additional overshoot and ringing. 14 / 19 Rev 1D.R Rev 1D.R Table 1: Recommended RS vs. CL Comlinear CLC2000, CLC4000 High Output Current Dual and Quad Amplifiers PD = PQuiescent + PDynamic - PLoad In the event of a short circuit condition, the CLC2000/ CLC4000 has circuitry to limit output drive capability to 1000mA. This will only protect against a momentary event. Extended duration under these conditions will cause junction temperatures to exceed 150C. Due to internal metallization constraints, continuous output current should be limited to 100mA. Data Sheet Overdrive Recovery +Vs 3 Rf+ VIN - 4 Input 1 2 0 0 -1 -2 Output -2 Ro+=12.5 Vo+ 1:2 Rg RL=100 Rf- Output Voltage (V) Input Voltage (V) 1/2 CLC2000 6 VIN = 2.5Vpp G=5 2 + Ro-=12.5 VOUT Vo- 1/2 CLC2000 -Vs Figure 6: Typical Differential Transmission Line Driver -4 -3 -6 0 20 40 60 80 100 120 140 160 180 200 Time (ns) Figure 5. Overdrive Recovery Using the CLC2000/CLC4000 as a Differential Line Driver The combination of good large signal bandwidth and high output drive capability makes the CLC2000/CLC4000 well suited for low impedance line driver applications, such as the upstream data path for a ADSL CPE modem. The dual channel configuration of the CLC2000 provides better channel matching than a typical single channel device, resulting in better overall performance in differential applications. When configured as a differential amplifier as in figure 6, it can easily deliver the 13dBm to a standard 100 twisted-pair CAT3 or CAT5 cable telephone network, as required in a ADSL CPE application. (c) 2018 Resurgent Semiconductor, LLC Data transmission techniques, such as ADSL, utilize amplitude modulation techniques which are sensitive to output clipping. A signal's PEAK to RMS ratio, or Crest Factor (CF), can be used to determine the adequate peak signal levels to insure fidelity for a given signal. For an ADSL system, the signal consists of 256 independent frequencies with varying amplitudes. This results in a noise-like signal with a crest factor of about 5.3. If the driver does not have enough swing to handle the signal peaks, clipping will occur and amplitude modulated information can be corrupted, causing degradation in the signals Bit Error Rate. To determine the required swing, first use the specified load impedance to convert the RMS power to an RMS voltage. Then, multiply the RMS voltage by the crest factor to get the peak values. For example 13dBm, as referenced to 1mW, is ~20mW. 20mW into the 100 CAT5 impedance yields a RMS voltage of 1.413 VRMS . Using the ADSL crest factor of 5.3 yields ~ 7.5V peak signals. 15 / 19 Rev 1D.R Rev 1D.R Differential circuits have several advantages over singleended configurations. These include better rejection of common mode signals and improvement of power-supply rejection. The use of differential signaling also improves overall dynamic performance. Total harmonic distortion (THD) is reduced by the suppression of even signal harmonics and the larger signal swings allow for an improved signal to noise ratio (SNR). For any transmission requirement, the fundamental design parameters needed are the effective impedance of the transmission line, the power required at the load, and knowledge concerning the content of the transmitted signal. The basic design of such a circuit is briefly outlined below, using the ADSL parameters as a guideline. Comlinear CLC2000, CLC4000 High Output Current Dual and Quad Amplifiers An overdrive condition is defined as the point when either one of the inputs or the output exceed their specified voltage range. Overdrive recovery is the time needed for the amplifier to return to its normal or linear operating point. The recovery time varies, based on whether the input or output is overdriven and by how much the range is exceeded. The CLC2000/CLC4000 will typically recover in less than 40ns from an overdrive condition. Figure 5 shows the CLC2000 in an overdriven condition. Data Sheet Evalutaion Board Schematics Evaluation board schematics and layouts are shown in Figures 7-9. These evaluation boards are built for dual- supply operation. Follow these steps to use the board in a single-supply application: 1. Short -Vs to ground. 2. Use C3 and C4, if the -VS pin of the amplifier is not directly connected to the ground plane. In general, the CLC2000/CLC4000 can be used in any application where an economical and local hardwired connection is needed. For example, routing analog or digital video information for a in-cabin entertainment system. Networking of a local surveillance system also could be considered. Layout Considerations General layout and supply bypassing play major roles in high frequency performance. Resurgent Semiconductor has evaluation boards to use as a guide for high frequency layout and as aid in device testing and characterization. Follow the steps below as a basis for high frequency layout: * Include 6.8F and 0.1F ceramic capacitors for power supply decoupling * Place the 6.8F capacitor within 0.75 inches of the power pin * Place the 0.1F capacitor within 0.1 inches of the power pin Figure 7. CEB006 Schematic * Remove the ground plane under and around the part, especially near the input and output pins to reduce parasitic capacitance * Minimize all trace lengths to reduce series inductances Refer to the evaluation board layouts below for more information. Evaluation Board Information Evaluation Board # CEB006 CEB018 Rev 1D.R The following evaluation board is available to aid in the testing and layout of this device: Products CLC2000 CLC4000 Figure 8. CEB006 Top View (c) 2018 Resurgent Semiconductor, LLC Comlinear CLC2000, CLC4000 High Output Current Dual and Quad Amplifiers Line coupling through a 1:2 transformer is used to realize these levels. Standard back termination is used to match the characteristic 100 impedance of the CAT5 cable. For proper power transfer, this requires an effective 1:4 impedance match of 25 at the inputs of the transformer. To account for the voltage drop of the impedance matching resistors, the signal levels at the output of the amplifier need to be doubled. Thus each amplifier will swing 3.75V about a centered common mode output voltage. 16 / 19 Rev 1D.R Data Sheet Comlinear CLC2000, CLC4000 High Output Current Dual and Quad Amplifiers Figure 9. CEB006 Bottom View Figure 11 CEB018 Top View Figure 12. CEB018 Bottom View Rev 1D.R Figure 10. CEB018 Schematic (c) 2018 Resurgent Semiconductor, LLC 17 / 19 Rev 1D.R Data Sheet Mechanical Dimensions SOIC-8 Package Comlinear CLC2000, CLC4000 High Output Current Dual and Quad Amplifiers SOIC-14 Package Rev 1D.R (c) 2018 Resurgent Semiconductor, LLC 18 / 19 Rev 1D.R Data Sheet Revision History Revision July 2018 Description Updated to Resurgent Semiconductor. For Further Assistance: ESURGENT S E M I C O N D U C T O R www.resurgentsemi.net Rev 1D.R NOTICE Resurgent Semiconductor reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. Resurgent Semiconductor assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. Resurgent Semiconductor does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Resurgent Semiconductor receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of Resurgent Semiconductor is adequately protected under the circumstances. Reproduction, in part or whole, without the prior written consent of Resurgent Semiconductor is prohibited. (c) 2018 Resurgent Semiconductor, LLC Comlinear CLC2000, CLC4000 High Output Current Dual and Quad Amplifiers 1D.R Date 19 / 19 Rev 1D.R