a Video Encoders with Six 10-Bit DACs and 54 MHz Oversampling ADV7190/ADV7191* FEATURES Six High Quality 10-Bit Video DACs Multistandard Video Input Multistandard Video Output 4 Oversampling with Internal 54 MHz PLL Programmable Video Control Includes: Digital Noise Reduction Gamma Correction LUMA Delay CHROMA Delay Multiple Luma and Chroma Filters Luma SSAFTM (Super Subalias Filter) Average Brightness Detection Field Counter Macrovision Rev 7.1 (ADV7190 Only) CGMS (Copy Generation Management System) WSS (Wide Screen Signaling) Closed Captioning Support Teletext Insertion Port (PAL-WST) 2-Wire Serial MPU Interface Supply Voltage 5 V and 3.3 V Operation 64-Lead LQFP Package APPLICATIONS DVD Playback Systems, PC Video/Multimedia Playback Systems GENERAL DESCRIPTION The ADV7190/ADV7191 is part of the new generation of video encoders from Analog Devices. The device builds on the performance of previous video encoders and provides new features such as Digital Noise Reduction, Gamma Correction, 4 Oversampling and 54 MHz operation, Average Brightness Detection, Chroma Delay, an additional Chroma Filter, and so on. The ADV7190/ADV7191 supports NTSC-M, NTSC-N (Japan), PAL N, PAL M, PAL-B/D/G/H/I, and PAL-60 standards. Input standards supported include ITU-R.BT656/601 4:2:2 YCrCb in 8- or 16-bit format. The ADV7190/ADV7191 can output Composite Video (CVBS), S-Video (Y/C), Component YUV1, or RGB. The analog component output is also compatible with Betacam, MII and SMPTE/EBU N10 levels, SMPTE 170M NTSC, and ITUR.BT 470 PAL. For more information about the ADV7190/ADV7191's features, refer to Detailed Description. Continued on page 11 SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM DIGITAL INPUT 27MHz CLOCK VIDEO INPUT PROCESSING 8-BIT YCrCb IN 4:2:2 FORMAT ANALOG OUTPUT PLL AND 54MHz CHROMA LPF DEMUX ITU-R.BT 656/601 VIDEO OUTPUT PROCESSING VIDEO SIGNAL PROCESSING AND YCrCb- TO- YUV MATRIX COLOR CONTROL DNR GAMMA CORRECTION VBI TELETEXT CLOSED CAPTION CGMS/WSS MACROVISION 10-BIT DAC 2 OVERSAMPLING SSAF LPF LUMA LPF OR 4 OVERSAMPLING 10-BIT DAC 10-BIT DAC 10-BIT DAC COMPOSITE VIDEO Y [S-VIDEO] C [S-VIDEO] RGB YUV TVSCREEN 10-BIT DAC 10-BIT DAC I2C INTERFACE ADV7190/ADV7191 *This device is protected by U.S. Patent Numbers 4631603, 4577216, and 4819098, and other intellectual property rights. 1 Throughout the document, YUV refers to digital or analog component video. The Macrovision anticopy process is licensed for noncommercial home use only, which is its sole intended use in the device. Please contact sales office for latest available Macrovision version. ITU-R and CCIR are used interchangeably in this document (ITU-R has replaced CCIR recommendations). SSAF is a trademark of Analog Devices Inc. I2C is a registered trademark of Philips Corporation. REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2002 ADV7190/ADV7191 CONTENTS REGISTER PROGRAMMING . . . . . . . . . . . . . . . . . . . . . MODE REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TIMING REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . SUBCARRIER FREQUENCY AND PHASE REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . CLOSED CAPTIONING REGISTERS . . . . . . . . . . . . . . . NTSC PEDESTAL REGISTERS . . . . . . . . . . . . . . . . . . . . TELETEXT REQUEST CONTROL REGISTER . . . . . . CGMS_WSS REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . CONTRAST CONTROL REGISTER . . . . . . . . . . . . . . . . COLOR CONTROL REGISTERS . . . . . . . . . . . . . . . . . . HUE ADJUST CONTROL REGISTER . . . . . . . . . . . . . . BRIGHTNESS CONTROL REGISTERS . . . . . . . . . . . . . SHARPNESS CONTROL REGISTER . . . . . . . . . . . . . . . DNR REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GAMMA CORRECTION REGISTERS . . . . . . . . . . . . . . BRIGHTNESS DETECT REGISTER . . . . . . . . . . . . . . . . OUTPUT CLOCK REGISTER . . . . . . . . . . . . . . . . . . . . . FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1 SPECIFICATIONS 5V ........................................... 3 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 V DYNAMIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.3 V DYNAMIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5 V TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . 6 3.3 V TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . 7 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . 9 PACKAGE THERMAL PERFORMANCE . . . . . . . . . . . . . 9 PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . 10 DETAILED DESCRIPTION OF FEATURES . . . . . . . . . 11 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . 11 DATA PATH DESCRIPTION . . . . . . . . . . . . . . . . . . . . . 12 INTERNAL FILTER RESPONSE.. . . . . . . . . . . . . . . . . . . 13 FEATURES: FUNCTIONAL DESCRIPTION . . . . . . . . . 17 Brightness Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Chroma/Luma Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Clamp Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 CSO, HSO, and VSO Outputs . . . . . . . . . . . . . . . . . . . . . 17 Color Bar Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Color Burst Signal Control . . . . . . . . . . . . . . . . . . . . . . . 17 Color Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Chrominance Control . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Undershoot Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Digital Noise Reduction . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Double Buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Gamma Correction Control . . . . . . . . . . . . . . . . . . . . . . . 18 NTSC Pedestal Control . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Power-On RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Real-Time Control, Subcarrier Reset, and Timing Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 SCH Phase Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Square Pixel Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Vertical Blanking Data Insertion And BLANK Input . . . . 19 YUV Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 16-Bit Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4 Oversampling and Internal PLL . . . . . . . . . . . . . . . . . 19 VIDEO TIMING DESCRIPTION . . . . . . . . . . . . . . . . . . . 19 RESET SEQUENCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 MPU PORT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . 27 REGISTER ACCESSES . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 APPENDIX 1 BOARD DESIGN AND LAYOUT CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . APPENDIX 2 CLOSED CAPTIONING . . . . . . . . . . . . . . . . . . . . . . . . APPENDIX 3 COPY GENERATION MANAGEMENT SYSTEM (CGMS) . . . . . . . . . . . . . . . . . . . . . . . . . . . APPENDIX 4 WISE SCREEN SIGNALING (WSS) . . . . . . . . . . . . . . . APPENDIX 5 TELETEXT INSERTION . . . . . . . . . . . . . . . . . . . . . . . APPENDIX 6 OPTIONAL OUTPUT FILTER . . . . . . . . . . . . . . . . . . APPENDIX 7 DAC BUFFERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . APPENDIX 8 RECOMMENDED REGISTER VALUES . . . . . . . . . . . APPENDIX 9 NTSC WAVEFORMS (WITH PEDESTAL) . . . . . . . . . NTSC WAVEFORMS (WITHOUT PEDESTAL) . . . . . PAL WAVEFORMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . UV WAVEFORMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OUTPUT WAVEFORMS . . . . . . . . . . . . . . . . . . . . . . . . VIDEO MEASUREMENT PLOTS . . . . . . . . . . . . . . . . APPENDIX 10 VECTOR PLOTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2- 28 29 35 36 36 37 37 37 38 38 39 39 40 40 42 43 43 44 46 47 48 49 50 51 52 56 57 58 59 60 64 68 69 70 REV. B SPECIFICATIONS (V 5 V SPECIFICATIONS1 ADV7190/ADV7191 = 5 V, VREF = 1.235 V, RSET1,2 = 1200 , unless otherwise noted. All specifications TMIN to TMAX2, unless otherwise noted.) AA Parameter Min Typ STATIC PERFORMANCE Resolution (Each DAC) Accuracy (Each DAC) Integral Nonlinearity3 Differential Nonlinearity3 DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN Input Leakage Current DIGITAL OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Three-State Leakage Current Three-State Output Capacitance ANALOG OUTPUTS Output Current (Max) Output Current (Min) DAC-to-DAC Matching3 Output Compliance, VOC Output Impedance, ROUT Output Capacitance, COUT VOLTAGE REFERENCE Reference Range, VREF Max Unit 10 Bits 1.0 1.0 LSB LSB 0.8 1 10 V V mA pF mA 2 0 6 1 2.4 4.125 0.8 10 6 0.4 4.33 2.16 0.4 4.625 10 2.5 1.4 0 100 6 RL = 300 W, RSET1,2 = 1200 W RL = 600 W, RSET1,2 = 2400 W 1.359 V 4.75 5.0 5.25 V 29 80 120 6 35 120 170 10 mA mA mA mA mA mA Specifications subject to change without notice. REV. B mA mA % V kW pF 1.235 NOTES 1 All measurements are made in 4 Oversampling Mode unless otherwise specified. 2 Temperature range T MIN to TMAX: 0C to 70C. 3 Guaranteed by characterization. 4 Measurement made in 2 oversampling mode. 5 IDAC is the total current required to supply all DACs including the V REF circuitry. 6 All six DACs ON. 7 ICCT, or the circuit current, is the continuous current required to drive the digital core without I PLL. -3- VIN = 0.4 V or 2.4 V ISOURCE = 400 mA ISINK = 3.2 mA 1.112 0.01 85 Guaranteed Monotonic V V mA pF 4 POWER REQUIREMENTS VAA Normal Power Mode IDAC5 ICCT (2 Oversampling)6, 7 ICCT (4 Oversampling)6, 7 IPLL Sleep Mode IDAC ICCT Test Conditions IOUT = 0 mA ADV7190/ADV7191-SPECIFICATIONS 2 1 (VAA = 3.3 V, VREF = 1.235 V, RSET1,2 = 1200 , unless otherwise noted. All specifications TMIN to TMAX , 3.3 V SPECIFICATIONS unless otherwise noted.) Parameter Min Typ STATIC PERFORMANCE Resolution (Each DAC) Accuracy (Each DAC) Integral Nonlinearity Differential Nonlinearity DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN Input Leakage Current 2 0.8 6 1 DIGITAL OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Three-State Leakage Current Three-State Output Capacitance ANALOG OUTPUTS Output Current (Max) Output Current (Min) DAC-to-DAC Matching Output Compliance, VOC Output Impedance, ROUT Output Capacitance, COUT VOLTAGE REFERENCE Reference Range, VREF 2.4 0.4 10 6 4.25 Max Unit 10 Bits 1.0 1.0 LSB LSB 1 10 V V mA pF mA 10 4.33 2.16 0.4 4.625 1.4 100 6 30 Test Conditions Guaranteed Monotonic VIN = 0.4 V or 2.4 V V V mA pF ISOURCE = 400 mA ISINK = 3.2 mA mA mA % V kW pF RSET1,2 = 1200 W, RL = 300 W RL = 600 W, RSET1,2 = 2400 W V IVREFOUT = 20 mA IOUT = 0 mA 3 POWER REQUIREMENTS VAA Normal Power Mode IDAC4 ICCT (2 Oversampling)5, 6 ICCT (4 Oversampling)5, 6 IPLL Sleep Mode IDAC ICCT 1.235 3.15 3.3 3.45 V 29 42 68 6 54 86 mA mA mA mA mA mA 0.01 85 NOTES 1 All measurements are made in 4 Oversampling Mode unless otherwise specified and are guaranteed by characterization. In 2 Oversampling Mode, the power requirement for the ADV7190/ADV7191 are typically 3.0 V. 2 Temperature range T MIN to TMAX: 0C to 70C. 3 Measurement made in 2 oversampling mode. 4 IDAC is the total current required to supply all DACs including the V REF circuitry. 5 All six DACs ON. 6 ICCT, or the circuit current, is the continuous current required to drive the digital core without I PLL. Specifications subject to change without notice. -4- REV. B ADV7190/ADV7191 5 V DYNAMIC-SPECIFICATIONS1 Parameter (VAA = 5 V 250 mV, VREF = 1.235 V, RSET1,2 = 1200 , unless otherwise noted. All specifications TMIN to TMAX2, unless otherwise noted.) Min 3 Differential Gain Differential Phase3 SNR (Pedestal)3 SNR (Ramp)3 Typ Max Unit 0.1 (0.4) 0.4 (0.15) 78.5 (78) 78 (78) 0.3 (0.5) 0.5 (0.3) % Degrees dB rms dB p-p dB rms dB p-p Degrees % % Degrees % % ns % dB dB 61.7 (61.7) 62 (63) Hue Accuracy Color Saturation Accuracy Chroma Nonlinear Gain Chroma Nonlinear Phase Chroma/Luma Intermod Chroma/Luma Gain Ineq Chroma/Luma Delay Ineq Luminance Nonlinearity Chroma AM Noise Chroma PM Noise 0.5 0.7 0.7 0.5 0.1 1.7 2.2 0.6 82 72 0.9 0.7 Test Conditions RMS Peak Periodic RMS Peak Periodic Referenced to 40 IRE NOTES 1 All measurements are made in 4 Oversampling Mode unless otherwise specified. 2 Temperature range T MIN to TMAX: 0C to 70C. 3 Values in parentheses apply to 2 Oversampling Mode. Specifications subject to change without notice. (VAA = 3.3 V 150 mV, VREF = 1.235 V, RSET1,2 = 1200 , unless otherwise noted. All 2 MIN to TMAX , unless otherwise noted.) 3.3 V DYNAMIC-SPECIFICATIONS1 specifications T Parameter Min Differential Gain3 Differential Phase3 SNR (Pedestal)3 SNR (Ramp)3 Hue Accuracy Color Saturation Accuracy Chroma Nonlinear Gain Chroma Nonlinear Phase Chroma/Luma Intermod Luminance Nonlinearity Chroma AM Noise Chroma PM Noise Typ Max 0.2 (0.5) 0.5 (0.2) 78.5 (78) 78 (78) 62.3 (62) 61 (62.5) 0.5 0.8 0.6 0.5 0.1 0.6 83 71 NOTES 1 All measurements are made in 4 Oversampling Mode unless otherwise specified. 2 Temperature range T MIN to TMAX: 0C to 70C. 3 Values in parentheses apply to 2 Oversample Mode. Specifications subject to change without notice. REV. B -5- Unit % Degrees dB rms dB p-p dB rms dB p-p Degrees % % Degrees % % dB dB Test Conditions RMS Peak Periodic RMS Peak Periodic Referenced to 40 IRE ADV7190/ADV7191 (VAA = 5 V 250 mV, VREF = 1.235 V, RSET1,2 = 1200 , unless otherwise noted. All specifications 1 MIN to TMAX , unless otherwise noted.) 5 V TIMING CHARACTERISTICS T Parameter Min Typ Max Unit 400 kHz ms ms ms ms ns ns ns ms Test Conditions 2 MPU PORT SCLOCK Frequency SCLOCK High Pulsewidth, t1 SCLOCK Low Pulsewidth, t2 Hold Time (Start Condition), t3 Setup Time (Start Condition), t4 Data Setup Time, t5 SDATA, SCLOCK Rise Time, t6 SDATA, SCLOCK Fall Time, t7 Setup Time (Stop Condition), t8 0 0.6 1.3 0.6 0.6 100 300 300 0.6 After This Period, the First Clock is Generated Relevant for Repeated Start Condition 2 ANALOG OUTPUTS Analog Output Delay DAC Analog Output Skew 8 0.1 ns ns 27 13 12 57 67 MHz ns ns ns ns ns ns ns ns Clock Cycles Clock Cycles TELETEXT PORT4 Digital Output Access Time, t16 Data Setup Time, t17 Data Hold Time, t18 11 3 6 ns ns ns RESET CONTROL RESET Low Time 3 CLOCK CONTROL AND PIXEL PORT3 fCLOCK Clock High Time, t9 Clock Low Time, t10 Data Setup Time, t11 Data Hold Time, t12 Control Setup Time, t11 Control Hold Time, t12 Digital Output Access Time, t13 Digital Output Hold Time, t14 Pipeline Delay, t15 (2 Oversampling) Pipeline Delay, t15 (4 Oversampling) 8 8 6 5 6 4 20 ns 2 PLL PLL Output Frequency 54 MHz NOTES 1 Temperature range T MIN to TMAX: 0C to 70C. 2 Guaranteed by characterization. 3 Pixel Port consists of: Data: P15-P0 Pixel Inputs, Control: HSYNC, VSYNC, BLANK, Clock: CLKIN Input. 4 Teletext Port consists of: Digital Output: TTXREQ, Data: TTX. Specifications subject to change without notice. -6- REV. B ADV7190/ADV7191 3.3 V TIMING CHARACTERISTICS Parameter Max Unit 400 2 kHz ms ms ms ms ns ns ns ms 8 0.1 ns ns 27 13 12 57 67 MHz ns ns ns ns ns ns ns ns Clock Cycles Clock Cycles TELETEXT PORT4 Digital Output Access Time, t16 Data Setup Time, t17 Data Hold Time, t18 11 3 6 ns ns ns RESET CONTROL RESET Low Time 3 PLL PLL Output Frequency 54 MPU PORT SCLOCK Frequency SCLOCK High Pulsewidth, t1 SCLOCK Low Pulsewidth, t2 Hold Time (Start Condition), t3 Setup Time (Start Condition), t4 Data Setup Time, t5 SDATA, SCLOCK Rise Time, t6 SDATA, SCLOCK Fall Time, t7 Setup Time (Stop Condition), t8 Min (VAA = 3.3 V 150 mV, VREF = 1.235 V, RSET1,2 = 1200 , unless otherwise noted. All specifications TMIN to TMAX1, unless otherwise noted2.) 0 0.6 1.3 0.6 0.6 100 300 300 0.6 ANALOG OUTPUTS Analog Output Delay DAC Analog Output Skew CLOCK CONTROL AND PIXEL PORT3 fCLOCK Clock High Time, t9 Clock Low Time, t10 Data Setup Time, t11 Data Hold Time, t12 Control Setup Time, t11 Control Hold Time, t12 Digital Output Access Time, t13 Digital Output Hold Time, t14 Pipeline Delay, t15 (2 Oversampling) Pipeline Delay, t15 (4 Oversampling) Typ 8 8 6 4 2.5 3 20 ns MHz NOTES 1 Temperature range T MIN to TMAX: 0C to 70C. 2 Guaranteed by characterization. 3 Pixel Port consists of: Data: P15-P0 Pixel Inputs, Control: HSYNC, VSYNC, BLANK, Clock: CLKIN Input. 4 Teletext Port consists of: Digital Output: TTXREQ, Data: TTX. Specifications subject to change without notice. REV. B -7- Test Conditions After This Period, the First Clock is Generated Relevant for Repeated Start Condition ADV7190/ADV7191 t5 t3 t3 SDA t6 t1 SCL t2 t7 t4 t8 Figure 1. MPU Port Timing Diagram CLOCK t9 CONTROL I/PS PIXEL INPUT DATA CONTROL O/PS t12 t10 HSYNC, VSYNC, BLANK Cb Y Cr Y t11 HSYNC, VSYNC, BLANK, CSO_HSO, VSO, CLAMP Cb Y t13 t14 Figure 2. Pixel and Control Data Timing Diagram TTXREQ t16 CLOCK t17 t18 TTX 4 CLOCK CYCLES 4 CLOCK CYCLES 4 CLOCK CYCLES 3 CLOCK CYCLES 4 CLOCK CYCLES Figure 3. Teletext Timing Diagram -8- REV. B ADV7190/ADV7191 ABSOLUTE MAXIMUM RATINGS 1 PACKAGE THERMAL PERFORMANCE VAA to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Voltage on Any Digital Input Pin . . . . GND - 0.5 V to VAA + 0.5 V Storage Temperature (TS) . . . . . . . . . . . . . . -65C to +150C Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . 150C Body Temperature (Soldering, 10 secs) . . . . . . . . . . . . 220C Analog Outputs to GND2 . . . . . . . . . . . . GND - 0.5 to VAA The 64-lead package is used for this device. The junction-toambient (qJA) thermal resistance in still air on a four-layer PCB is 38C/W. NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Analog output short circuit to any power supply or common can be of an indefinite duration. To reduce power consumption when using this part, the user can run the part on a 3.3 V supply, and turn off any unused DACs. The user must at all times stay below the maximum junction temperature of 110C. The following equation shows how to calculate this junction temperature: Junction Temperature = (VAA (IDAC + ICCT)) qJA + 70C TAMB IDAC = 10 mA + (sum of the average currents consumed by each powered-on DAC) Average current consumed by each powered-on DAC = (VREF K )/RSET VREF = 1.235 V K = 4.2146 RESET VSO/CLAMP CSO_HSO NC PAL NTSC AGND VAA NC TTX NC NC NC NC NC AGND VAA PIN CONFIGURATION 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 1 48 RSET1 47 VREF P2 3 46 COMP 1 P3 4 P4 5 45 P0 P1 2 PIN 1 IDENTIFIER DAC A DAC B 43 VAA 44 P5 6 ADV7190/ADV7191 LQFP P6 7 P7 8 42 41 TOP VIEW (Not to Scale) P8 9 P9 10 AGND DAC C 40 DAC D AGND 38 VAA 39 P10 11 P11 12 P12 13 37 P13 14 35 DAC E 36 DAC F COMP 2 34 RSET2 P14 15 P15 16 33 AGND SCRESET/RTC/TR NC = NO CONNECT SCL SDA AGND CLKIN CLKOUT VAA AGND VAA BLANK ALSB TTXREQ VSYNC HSYNC VAA AGND 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 ORDERING GUIDE Model Temperature Range Package Description Package Option ADV7190KST ADV7191KST 0C to 70C 0C to 70C 64-Lead Quad Flatpack 64-Lead Quad Flatpack ST-64 ST-64 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADV7190/ADV7191 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. B -9- WARNING! ESD SENSITIVE DEVICE ADV7190/ADV7191 PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Input/ Output 1-16 P0-P15 I 17, 25, 29, 38, 43, 54, 63 18, 24, 26, 33, 39, 42, 55, 64 19 VAA P 8-Bit or 16-Bit 4:2:2 Multiplexed YCrCb Pixel Port. The LSB of the input data is set up on Pin P0. Analog Power Supply (3.3 V to 5 V). AGND G Analog Ground. HSYNC I/O 20 VSYNC I/O 21 BLANK I/O 22 23 27 ALSB TTXREQ CLKIN I O I 28 30 31 32 O I I/O I 34 CLKOUT SCL SDA SCRESET/ RTC/TR RSET2 35 36 37 40 41 44 45 46 47 COMP 2 DAC F DAC E DAC D DAC C DAC B DAC A COMP 1 VREF O O O O O O O O I/O 48 RSET1 I 49 RESET I 50 51 CSO_HSO VSO/CLAMP O I/O 52 53, 57-62 56 PAL_NTSC NC TTX I HSYNC (Modes 1, 2, and 3) Control Signal. This pin may be configured to be an output (Master Mode) or an input (Slave Mode) and accept Sync Signals. VSYNC Control Signal. This pin may be configured as an output (Master Mode) or as an input (Slave Mode) and accept VSYNC as a Control Signal. Video Blanking Control Signal. This signal is optional. For further information see Vertical Blanking Data Insertion and BLANK Input section. TTL Address Input. This signal sets up the LSB of the MPU address. Teletext Data Request Output Signal, used to control teletext data transfer. TTL Clock Input. Requires a stable 27 MHz reference clock for standard operation. Alternatively, a 24.5454 MHz (NTSC) or 29.5 MHz (PAL) can be used for square pixel operation. Clock Output Pin. MPU Port Serial Interface Clock Input. MPU Port Serial Data Input/Output. Multifunctional Input: Real-Time Control (RTC) Input, Timing Reset Input, Subcarrier Reset Input. A 1200 W resistor connected from this pin to ground is used to control full-scale amplitudes of the Video Signals from DACs D, E, and F. Compensation Pin for DACs D, E, and F. Connect a 0.1 mF Capacitor from COMP2 to VAA. S-Video C/V/RED Analog Output. This DAC is capable of providing 4.33 mA output. S-Video Y/U/BLUE Analog Output. This DAC is capable of providing 4.33 mA output. Composite/Y/GREEN Analog Output. This DAC is capable of providing 4.33 mA output. S-Video C/V/RED Analog Output. This DAC is capable of providing 4.33 mA output. S-Video Y/U/BLUE Analog Output. This DAC is capable of providing 4.33 mA output. Composite/Y/GREEN Analog Output. This DAC is capable of providing 4.33 mA output. Compensation Pin for DACs A, B, and C. Connect a 0.1 mF Capacitor from COMP1 to VAA. Voltage Reference Input for DACs or Voltage Reference Output (1.235 V). An external VREF cannot be used in 4 oversampling mode. A 1200 W resistor connected from this pin to ground is used to control full-scale amplitudes of the Video Signals from DACs A, B, and C. The input resets the on-chip timing generator and sets the ADV7190/ADV7191 into default mode. See Appendix 8 for Default Register settings. Dual Function CSO or HSO Output Sync Signal at TTL Level. Multifunction Pin. VSO Output Sync Signal at TTL level. CLAMP TTL Output Signals can be used to drive external circuitry to enable clamping of all Video Signals. Input signal to select PAL or NTSC mode of operation, pin set to Logic 1 selects PAL. No Connect. Teletext Data Input Pin. I I Function -10- REV. B ADV7190/ADV7191 DETAILED DESCRIPTION OF FEATURES Clocking: Single 27 MHz Clock Required to Run the Device 4 Oversampling with Internal 54 MHz PLL Square Pixel Operation Advanced Power Management Programmable Video Control Features: Digital Noise Reduction Pedestal level Hue, Brightness, Contrast and Saturation Clamping Output Signal VBI (Vertical Blanking Interval) Subcarrier Frequency and Phase LUMA Delay CHROMA Delay Gamma Correction Luma and Chroma Filters Luma SSAF (Super Subalias Filter) Average Brightness Detection Field Counter Interlaced/Noninterlaced Operation Complete On-Chip Video Timing Generator Programmable Multimode Master/Slave Operation CGMS (Copy Generation Management System) WSS (Wide Screen Signaling) Macrovision 7.1 Rev (ADV7190 Only) Closed Captioning Support Teletext Insertion Port (PAL-WST) 2-Wire Serial MPU Interface I2C Registers Synchronized to VSYNC Six DACs are available on the ADV7190/ADV7191, each of which is capable of providing 4.33 mA of current. In addition to the composite output signal there is the facility to output S-Video (Y/C Video), RGB Video and YUV Video. All YUV formats (Betacam, MII and (SMPTE/EBU N10) are supported. Digital Noise Reduction allows improved picture quality in removing low amplitude, high frequency noise. The block diagram below shows the DNR functionality in the two modes available. DNR MODE DNR CONTROL NOISE SIGNAL PATH SUBTRACT SIGNAL IN THRESHOLD RANGE FROM ORIGINAL SIGNAL INPUT FILTER BLOCK FILTER OUTPUT <THRESHOLD? Y DATA INPUT FILTER OUTPUT> THRESHOLD MAIN SIGNAL PATH DNR CONTROL ADD SIGNAL ABOVE THRESHOLD RANGE TO ORIGINAL SIGNAL NOISE SIGNAL PATH INPUT FILTER BLOCK FILTER OUTPUT >THRESHOLD? Y DATA INPUT FILTER OUTPUT< THRESHOLD MAIN SIGNAL PATH The ADV7190/ADV7191 is an integrated Digital Video Encoder that converts digital CCIR-601/656 4:2:2 8-bit or 16-bit component video data into a standard analog baseband television signal compatible with worldwide standards. HSYNC VSYNC BLANK CSO_HSO SDA ALSB I2C MPU PORT RESET TELETEXT INSERTION BLOCK TTX 10 10 YCrCb Y TO 10 YUV U MATRIX 10 DNR Y AND 10 GAMMA U CORRECTION 10 V V 10 10 10 P0 BRIGHTNESS CONTROL AND ADD SYNC AND INTERPOLATOR SATURATION CONTROL AND ADD BURST AND INTERPOLATOR PROGRAMMABLE LUMA FILTER AND SHARPNESS FILTER PROGRAMMABLE CHROMA FILTER YUV-TO-RGB MATRIX AND YUV LEVEL CONTROL BLOCK MODULATOR AND HUE CONTROL DEMUX P15 CLKIN PLL ADV7190/ADV7191 REAL-TIME CONTROL CIRCUIT SIN/COS DDS BLOCK CLKOUT SCRESET/RTC/TR Figure 4. Detailed Functional Block Diagram REV. B DNR OUT Figure 5. Block Diagram for DNR Mode and DNR Sharpness Mode SCL CGMS/WSS AND CLOSED CAPTIONING CONTROL VIDEO TIMING GENERATOR TTXREQ GAIN BLOCK SIZE CONTROL CORING GAIN DATA BORDER AREA CORING GAIN BORDER BLOCK OFFSET GENERAL DESCRIPTION VSO/CLAMP DNR OUT DNR SHARPNESS MODE (continued from page 1) PAL_NTSC GAIN BLOCK SIZE CONTROL CORING GAIN DATA BORDER AREA CORING GAIN BORDER BLOCK OFFSET -11- M U L T I P L E X E R I N T E R P O L A T O R I N T E R P O L A T O R 10-BIT DAC DAC A 10-BIT DAC DAC B 10-BIT DAC DAC C DAC CONTROL BLOCK VREF RSET2 COMP2 10-BIT DAC DAC D 10-BIT DAC DAC F 10-BIT DAC DAC E DAC CONTROL BLOCK RSET1 COMP1 ADV7190/ADV7191 The ADV7190/ADV7191 also supports both PAL and NTSC square pixel operation. In this case the encoder requires a 24.5454 MHz Clock for NTSC or 29.5 MHz Clock for PAL square pixel mode operation. All internal timing is generated on-chip. Programmable gamma correction is also available. Figure 6 shows the response of different gamma values to a ramp signal. 300 GAMMA-CORRECTED AMPLITUDE GAMMA CORRECTION BLOCK OUTPUT TO A RAMP INPUT FOR VARIOUS GAMMA VALUES An advanced power management circuit enables optimal control of power consumption in normal operating modes or sleep modes. 250 SIGNAL OUTPUTS The Output Video Frames are synchronized with the incoming data Timing Reference Codes. Optionally, the Encoder accepts (and can generate) HSYNC, VSYNC, and FIELD timing signals. These timing signals can be adjusted to change pulsewidth and position while the part is in master mode. 200 0.3 0.5 150 UT NP LI A 1.5 GN SI 100 HSO/CSO and VSO TTL outputs are also available and are timed to the analog output video. 1.8 50 0 0 50 100 150 LOCATION 200 A separate teletext port enables the user to directly input teletext data during the vertical blanking interval. 250 The ADV7190/ADV7191 also incorporates WSS and CGMS-A data control generation. The ADV7190 incorporates Macrovision Rev 7.1. Figure 6. Signal Input (Ramp) and Selectable Gamma Output Curves The on-board SSAF (Super Subalias Filter) with extended luminance frequency response and sharp stopband attenuation enables studio quality video playback on modern TVs, giving optimal horizontal line resolution. An additional sharpness control feature allows high-frequency enhancement on the luminance signal. The device is driven by a 27 MHz clock. Data can be output at 27 MHz or 54 MHz (on-board PLL) when 4 oversampling is enabled. Also, the output filter requirements in 4 oversampling and 2 oversampling differ, as can be seen in Figure 7. 4 FILTER REQUIREMENTS -30dB 6.75MHz 13.5MHz 27.0MHz 40.5MHz 54.0MHz Figure 7. Output Filter Requirements in 4 Oversampling Mode ADV7190/ADV7191 MPEG2 PIXEL BUS 27MHz ENCODER CORE 54MHz PLL 2 I N T E R P O L A T I O N 6 D A C O U T P U T S 54MHz OUTPUT RATE Figure 8. PLL and 4 Oversampling Block Diagram The ADV7190ADV7191 is packaged in a 64-lead LQFP package. DATA PATH DESCRIPTION 2 FILTER REQUIREMENTS 0dB The ADV7190/ADV7191 modes are set up over a 2-wire serial bidirectional port (I2C-compatible) with two slave addresses, and the device is register-compatible with the ADV7172/ADV7173. For PAL B, D, G, H, I, M, N, and NTSC M, N modes, YCrCb 4:2:2 Data is input via the CCIR-656/601-compatible Pixel Port at a 27 MHz data rate. The pixel data is demultiplexed to form three data paths. Y typically has a range of 16 to 235, Cr and Cb typically have a range of 128+/-112; however, it is possible to input data from 1 to 254 on both Y, Cb, and Cr. The ADV7190/ADV7191 supports PAL (B, D, G, H, I, N) and NTSC M, N (with and without Pedestal) PAL.M (ADV7190 only) and PAL60 standards. Digital Noise Reduction can be applied to the Y signal. Programmable gamma correction can also be applied to the Y signal if required. The Y data can be manipulated for contrast control and a set-up level can be added for brightness control. The Cr, Cb data can be scaled to achieve color saturation control. All settings become effective at the start of the next field when double buffering is enabled. The appropriate sync, blank, and burst levels are added to the YCrCb data. Macrovision antitaping, (ADV7190 only) ClosedCaptioning, and Teletext levels are also added to Y and the resultant data is interpolated to 54 MHz when 4 Oversampling is enabled. The interpolated data is filtered and scaled by three digital FIR filters. The U and V signals are modulated by the appropriate Subcarrier Sine/Cosine waveforms and a phase offset may be added onto the color subcarrier during active video to allow hue adjustment. The resulting U and V signals are added together to make up the Chrominance Signal. The Luma (Y) signal can be delayed by up to six clock cycles (at 27 MHz) and the Chroma signal can be delayed by up to eight clock cycles (at 27 MHz). The -12- REV. B ADV7190/ADV7191 Luma and Chroma Signals are added together to make up the Composite Video Signal. All timing signals are controlled. INTERNAL FILTER RESPONSE The Y Filter supports several different frequency responses including two low-pass responses, two notch responses, an Extended (SSAF) response with or without gain boost/attenuation, a CIF response and a QCIF response. The UV Filter supports several different frequency responses including five low-pass responses, a CIF response and a QCIF response, as can be seen on the following pages. The YCrCb data is also used to generate RGB data with appropriate sync and blank levels. The YUV levels are scaled to output the suitable SMPTE/EBU N10, MII, or Betacam levels. Each DAC can be individually powered off if not required. A complete description of DAC output configurations is given in the MR2 Bit Description section. In Extended Mode there is the option of twelve responses in the range from -4 dB to +4 dB. The desired response can be chosen by the user by programming the correct value via the I2C. The variation of frequency responses can be seen on the following pages. For more detailed plots refer to AN-562 Analog Devices' Application note. Video output levels are illustrated in Appendix 9. Table I. Luminance Internal Filter Specifications (4 Oversampling) Filter Type Low-Pass (NTSC) Low-Pass (PAL) Notch (NTSC) Notch (PAL) Extended (SSAF) CIF QCIF Filter Selection MR04 0 0 0 0 1 1 1 MR03 0 0 1 1 0 0 1 MR02 0 1 0 1 0 1 0 Passband Ripple1 (dB) 3 dB Bandwidth2 (MHz) 0.16 0.1 0.09 0.1 0.04 0.127 Monotonic 4.24 4.81 2.3/4.9/6.6 3.1/5.6/6.4 6.45 3.02 1.5 NOTES 1 Passband ripple is defined to be fluctuations from the 0 dB response in the passband, measured in (dB). The passband is defined to have 0-fc frequency limits for a low-pass filter, 0-f1 and f2-infinity for a notch filter, where fc, f1, f2 are the -3 dB points. 2 3 dB bandwidth refers to the -3 dB cutoff frequency. Table II. Chrominance Internal Filter Specifications (4 Oversampling) Filter Type 1.3 MHz Low-Pass 0.65 MHz Low-Pass 1.0 MHz Low-Pass 2.0 MHz Low-Pass 3.0 MHz Low-Pass CIF QCIF Filter Selection MR07 0 0 0 0 1 1 1 MR06 0 0 1 1 1 0 1 MR05 0 1 0 1 1 1 0 Passband Ripple1 (dB) 3 dB Bandwidth2 (MHz) 0.09 Monotonic Monotonic 0.048 Monotonic Monotonic Monotonic 1.395 0.65 1.0 2.2 3.2 0.65 0.5 NOTES 1 Passband ripple is defined to be fluctuations from the 0 dB response in the passband, measured in (dB). The passband is defined to have 0-fc frequency limits for a low-pass filter, 0-f1 and f2-infinity for a notch filter, where fc, f1, f2 are the -3 dB points. 2 3 dB bandwidth refers to the -3 dB cutoff frequency. REV. B -13- 0 0 -10 -10 -20 -20 MAGNITUDE - dB MAGNITUDE - dB ADV7190/ADV7191 -30 -40 -30 -40 -50 -50 -60 -60 -70 2 0 4 6 8 FREQUENCY - MHz 10 -70 12 0 0 -10 -10 -20 -20 -30 -40 -60 -60 4 6 8 FREQUENCY - MHz 10 10 12 -40 -50 2 6 8 FREQUENCY - MHz -30 -50 0 4 Figure 12. NTSC Notch Luma Filter MAGNITUDE - dB MAGNITUDE - dB Figure 9. NTSC Low-Pass Luma Filter -70 2 0 -70 12 2 0 Figure 10. PAL Low-Pass Luma Filter 4 6 8 FREQUENCY - MHz 10 12 Figure 13. PAL Notch Luma Filter 5 0 4 -20 MAGNITUDE - dB MAGNITUDE - dB -10 -30 -40 3 2 1 -50 0 -60 -70 0 2 4 6 8 FREQUENCY - MHz 10 -1 12 Figure 11. Extended Mode (SSAF) Luma Filter 0 1 2 4 3 FREQUENCY - MHz 5 6 7 Figure 14. Extended SSAF and Programmable Gain, Showing Range 0 dB/+4 dB Range -14- REV. B ADV7190/ADV7191 1 0 -10 -1 -20 MAGNITUDE - dB MAGNITUDE - dB 0 -2 -3 -30 -40 -50 -4 -5 -60 0 1 4 3 FREQUENCY - MHz 2 5 6 -70 7 0 2 Figure 15. Extended SSAF and Programmable Attenuation, Showing Range 0 dB/-4 dB 0 2 -10 MAGNITUDE - dB MAGNITUDE - dB 0 -2 -4 -6 0 1 4 3 FREQUENCY - MHz 2 5 6 10 12 -20 -30 -40 -70 7 Figure 16. Extended SSAF and Programmable Attenuation, Showing Range +4 dB/-12 dB 0 0 0 -10 -10 -20 -20 -30 -40 -60 -60 4 6 8 FREQUENCY - MHz 10 6 8 FREQUENCY - MHz -40 -50 2 4 -30 -50 0 2 Figure 19. Chroma 0.65 MHz Low-Pass Filter MAGNITUDE - dB MAGNITUDE - dB 12 -60 -10 -70 12 Figure 17. Luma CIF Filter REV. B 10 -50 -8 -70 6 8 FREQUENCY - MHz Figure 18. QCIF Filter 4 -12 4 0 2 4 6 8 FREQUENCY - MHz 10 Figure 20. Chroma 1.0 MHz Low-Pass Filter -15- 12 0 0 -10 -10 -20 -20 MAGNITUDE - dB MAGNITUDE - dB ADV7190/ADV7191 -30 -40 -30 -40 -50 -50 -60 -60 -70 0 2 4 6 8 FREQUENCY - MHz 10 -70 12 0 0 0 -10 -10 -20 -20 -30 -40 -60 -60 2 4 6 8 FREQUENCY - MHz 10 10 12 10 12 -40 -50 0 6 8 FREQUENCY - MHz -30 -50 -70 4 Figure 24. Chroma CIF Filter MAGNITUDE - dB MAGNITUDE - dB Figure 21. Chroma 1.3 MHz Low-Pass Filter 2 -70 12 Figure 22. Chroma 2 MHz Low-Pass Filter 0 2 4 6 8 FREQUENCY - MHz Figure 25. Chroma QCIF Filter 0 MAGNITUDE - dB -10 -20 -30 -40 -50 -60 -70 0 2 4 6 8 FREQUENCY - MHz 10 12 Figure 23. Chroma 3 MHz Low-Pass Filter -16- REV. B ADV7190/ADV7191 Color Bar Generation FEATURES: FUNCTIONAL DESCRIPTION Brightness Detect This feature is used to monitor the average brightness of the incoming Y signal on a field-by-field basis. The information is read from the I2C and based on this information, the color saturation, contrast and brightness controls can be adjusted (for example to compensate for very dark pictures). (Brightness Detect Register.) Chroma/Luma Delay The luminance data can be delayed by maximum of six clock cycles. Additionally the Chroma can be delayed by a maximum of eight clock cycles (one clock cycle at 27 MHz). (Timing Register 0 and Mode Register 9.) The ADV7190/ADV7191 can be configured to generate 100/ 7.5/75/7.5 color bars for NTSC or 100/0/75/0 color bars for PAL. (Mode Register 4.) Color Burst Signal Control The burst information can be switched on and off the composite and chroma video output. (Mode Register 4.) Color Controls The ADV7190/ADV7191 allows the user to control the brightness, contrast, hue, and saturation of the color. The control registers may be double-buffered, meaning that any modification to the registers will be done outside the active video region and, therefore, changes made will not be visible during active video. Contrast Control Contrast adjustment is achieved by scaling the Y input data by a factor programmed by the user. This factor allows the data to be scaled between 0% and 150%. (Contrast Control Register.) Brightness Control LUMA DELAY CHROMA DELAY The brightness is controlled by adding a programmable setup level onto the scaled Y data. For NTSC with pedestal, the setup can vary from 0 IRE to 22.5 IRE. For NTSC without pedestal and PAL, the setup can vary from -7.5 IRE to +15 IRE. (Brightness Control Register.) Figure 26. Chroma Delay Figure 27. Luma Delay Clamp Output The ADV7190/ADV7191 has a programmable clamp TTL output signal. This clamp signal is programmable to the front and back porch. The clamp signal can be varied by one to three clock cycles in a positive and negative direction from the default position. (Mode Register 5, Mode Register 7.) CLAMP OUTPUT PIN Chrominance Control The color information can be switched on and off the composite, chroma and color component video outputs. (Mode Register 4.) Figure 28. Clamp Output Timing CSO, HSO, and VSO Outputs The ADV7190/ADV7191 supports three output timing signals, CSO (Composite Sync Signal), HSO (Horizontal Sync Signal) and VSO (Vertical Sync Signal). These output TTL signals are aligned with the analog video outputs. See Figure 29 for an example of these waveforms. (Mode Register 7.) EXAMPLE:- NTSC 1 2 3 4 5 6 7 8 9 10 OUTPUT VIDEO 11-19 Undershoot Limiter A limiter is placed after the digital filters. This prevents any synchronization problems for TVs. The level of undershoot is programmable between -1.5 IRE, -6 IRE, -11 IRE when operating in 4 Oversampling. In 2 Oversampling mode the limits are -7.5 IRE and 0 IRE. (Mode Register 9 and Timing Register 0.) Digital Noise Reduction DNR is applied to the Y data only. A filter block selects the high frequency, low amplitude components of the incoming signal (DNR Input Select). The absolute value of the filter output is compared to a programmable threshold value (DNR Threshold Control). CSO HSO VSO Figure 29. CSO, HSO, VSO Timing Diagram REV. B Hue Adjust Control CVBS OUTPUT PIN MR57 = 1 525 Color adjustment is achieved by scaling the Cr and Cb input data by a factor programmed by the user. This factor allows the data to be scaled between 0% and 200%. (U Scale Register and V Scale Register.) The hue adjustment is achieved on the composite and chroma outputs by adding a phase offset onto the color subcarrier in the active video but leaving the color burst unmodified, i.e., only the phase between the video and the colorburst is modified and thus the hue is shifted. The ADV7190/ADV7191 provides a range of 22 in increments of 0.17578125. (Hue Adjust Register.) CLAMP O/P SIGNALS MR57 = 0 Color Saturation Two DNR modes are available: DNR Mode and DNR Sharpness Mode. -17- ADV7190/ADV7191 commence counting again. The minimum time the pin has to be held high is 37 ns (1 clock cycle at 27 MHz), otherwise the reset signal might not be recognized. In DNR Mode, if the absolute value of the filter output is smaller than the threshold, it is assumed to be noise. A programmable amount (Coring Gain Control) of this noise signal will be subtracted from the original signal. In DNR Sharpness Mode, if the absolute value of the filter output is less than the programmed threshold, it is assumed to be noise, as before. Otherwise, if the level exceeds the threshold, now being identified as a valid signal, a fraction of the signal (Coring Gain Control) will be added to the original signal in order to boost high frequency components and to sharpen the video image. (b) The SUBCARRIER PHASE will reset to that of Field 0 at the start of the following field when a low-to-high transition occurs on this input pin. (c) In RTC MODE, the ADV7190/ADV7191 can be used to lock to an external video source. The real-time control mode allows the ADV7190/ADV7191 to automatically alter the subcarrier frequency to compensate for line length variations. When the part is connected to a device that outputs a digital datastream in the RTC format such as an ADV7185 video decoder (see Figure 32), the part will automatically change to the compensated subcarrier frequency on a line-by-line basis. This digital datastream is 67 bits wide and the subcarrier is contained in Bits 0 to 21. Each bit is two clock cycles long. 00Hex should be written into all four Subcarrier Frequency registers when using this mode. It is recommended to use the ADV7185 in this mode. (Mode Register 4.) In MPEG systems it is common to process the video information in blocks of 8 8 pixels for MPEG2 systems, or 16 16 pixels for MPEG1 systems (Block Size Control). DNR can be applied to the resulting block transition areas that are known to contain noise. Generally the block transition area contains two pixels. It is possible to define this area to contain four pixels (Border Area Control). It is also possible to compensate for variable block positioning or differences in YCrCb pixel timing with the use of the (Block Offset Control). See Figure 82 for further information. (Mode Register 8, DNR Registers 0-2.) Double Buffering Double buffering can be enabled or disabled on the following registers: Closed Captioning Registers, Brightness Control, V Scale, U Scale, Contrast Control, Hue Adjust, the Gamma Curve Select bit, and Macrovision Registers (ADV7190 only). These registers are updated once per field on the falling edge of the VSYNC signal. Double buffering improves the overall performance of the ADV7190/ADV7191, since modifications to register settings will not be made during active video, but take effect on the start of the active video. (Mode Register 8.) Gamma Correction Control Gamma correction may be performed on the luma data. The user has the choice to use either of two different gamma curves, A or B. At any one time one of these curves is operational if gamma correction is enabled. Gamma correction allows the mapping of the luma data to a user-defined function. (See Gamma Correction Registers 0-13 section.) (Mode Register 8, Gamma Correction Registers 0-13.) NTSC Pedestal Control In NTSC mode it is possible to have the pedestal signal generated on the output video signal. (Mode Register 2.) After power-up, it is necessary to execute a RESET operation. A reset occurs on the falling edge of a high-to-low transition on the RESET pin. This initializes the pixel port such that the data on the pixel input pins is ignored. See Appendix 8 for the register settings after RESET is applied. Together with the SCRESET/RTC/TR pin of Mode Register 4 (Genlock Control), the ADV7190/ADV7191 can be used in (a) Timing Reset Mode, (b) Subcarrier Phase Reset Mode or (c) RTC Mode. (a) A TIMING RESET is achieved in holding this pin high. In this state the horizontal and vertical counters will remain reset. On releasing this pin (set to low), the internal counters will The SCH phase is configured in default mode to reset every four (NTSC) or eight (PAL) fields to avoid an accumulation of SCH phase error over time. In an ideal system, zero SCH phase error would be maintained forever, but in reality, this is impossible to achieve due to clock frequency variations. This effect is reduced by the use of a 32-bit DDS, which generates this SCH. Resetting the SCH phase every four or eight fields avoids the accumulation of SCH phase error, and results in very minor SCH phase jumps at the start of the four or eight field sequence. Automatically resetting the SCH phase should not be done if the video source does not have stable timing or the ADV7190/ ADV7191 is configured in RTC mode. Under these conditions (unstable video) the Subcarrier Phase Reset should be enabled but no reset applied. In this configuration the SCH Phase will never be reset; this means that the output video will now track the unstable input video. The Subcarrier Phase Reset, when applied, will reset the SCH phase to Field 0 at the start of the next field (e.g., Subcarrier Phase Reset applied in Field 5 (PAL) on the start of the next field SCH phase will be reset to Field 0). (Mode Register 4.) Sleep Mode Power-On Reset Real-Time Control, Subcarrier Reset, and Timing Reset SCH Phase Mode If, after RESET, the SCRESET/RTC/TR and NTSC_PAL pins are both set high, the ADV7190/ADV7191 will power up in Sleep Mode to facilitate low power consumption before all registers have been initialized. If Power-Up in Sleep Mode is disabled, Sleep Mode control passes to the Sleep Mode control in Mode Register 2 (i.e., control via I2C). (Mode Register 2 and Mode Register 6.) Square Pixel Mode The ADV7190/ADV7191 can be used to operate in square pixel mode. For NTSC operation an input clock of 24.5454 MHz is required. Alternatively, for PAL operation, an input clock of 29.5 MHz is required. The internal timing logic adjusts accordingly for square pixel mode operation. Square pixel mode is not available in 4 Oversampling mode. (Mode Register 2.) -18- REV. B ADV7190/ADV7191 Vertical Blanking Data Insertion and BLANK Input ENCODER ADV7190/ADV7191 It is possible to allow encoding of incoming YCbCr data on those lines of VBI that do not have line sync or pre-/postequalization pulses (see Figures 34 to 45). This mode of operation is called Partial Blanking. It allows the insertion of any VBI data (Opened VBI) into the encoded output waveform. This data is present in digitized incoming YCbCr data stream (e.g., WSS data, CGMS, VPS etc.). Alternatively, the entire VBI may be blanked (no VBI data inserted) on these lines. VBI is available in all timing modes. PIXEL BUS MPEG2 ENCODER CORE 27MHz 54MHz PLL It is possible to allow control over the BLANK signal using Timing Register 0. When the BLANK input is enabled (TR03 = 0 and input pin tied low), the BLANK input can be used to input externally generated blank signals in Slave Mode 1, 2, or 3. When the BLANK input is disabled (TR03 = 1 and input pin tied low or tied high), the BLANK input is not used and the ADV7190/ ADV7191 automatically blanks all normally blank lines as per CCIR-624. (Timing Register 0.) As the data path is branched at the output of the filters the luma signal relating to the CVBS or S-Video Y/C output is unaltered. It is only the Y output of the YCrCb outputs that is scaled. This control allows color component levels to have a peak-peak amplitude of 700 mV, 1000 mV or the default values of 934 mV in NTSC and 700 mV in PAL. (Mode Register 5.) 16-Bit Interface It is possible to input data in 16-bit format. In this case, the interface only operates if the data is accompanied by separate HSYNC/VSYNC/BLANK signals. Sixteen-bit mode is not available in Slave Mode 0 since EAV/SAV timing codes are used. (Mode Register 8.) 4 Oversampling and Internal PLL It is possible to operate all six DACs at 27 MHz (2 Oversampling) or 54 MHz (4 Oversampling). The ADV7190/ADV7191 is supplied with a 27 MHz clock synced with the incoming data. Two options are available: to run the device throughout at 27 MHz or to enable the PLL. In the latter case, even if the incoming data runs at 27 MHz, 4 Oversampling and the internal PLL will output the data at 54 MHz. NOTE In 4 Oversampling Mode the requirements for the optional output filters are different from those in 2 Oversampling. (Mode Register 1, Mode Register 6.) See Appendix 6 for further details. REV. B O 6 U T D P A U C T S 54MHz OUTPUT 2 FILTER REQUIREMENTS 4 FILTER REQUIREMENTS 6.75 13.5 YUV Levels This functionality allows the ADV7190/ADV7191 to output SMPTE levels or Betacam levels on the Y output when configured in PAL or NTSC mode. Sync Video Betacam 286 mV 714 mV SMPTE 300 mV 700 mV MII 300 mV 700 mV I N T E R P 2 O L A T I O N 27.0 FREQUENCY - MHz 40.5 54.0 Figure 30. PLL and 4 Oversampling Block Diagram VIDEO TIMING DESCRIPTION The ADV7190/ADV7191 is intended to interface to off-theshelf MPEG1 and MPEG2 Decoders. As a consequence, the ADV7190/ADV7191 accepts 4:2:2 YCrCb Pixel Data via a CCIR-656 Pixel Port and has several Video Timing Modes of operation that allow it to be configured as either System Master Video Timing Generator or a Slave to the System Video Timing Generator. The ADV7190/ADV7191 generates all of the required horizontal and vertical timing periods and levels for the analog video outputs. The ADV7190/ADV7191 calculates the width and placement of analog sync pulses, blanking levels, and color burst envelopes. Color bursts are disabled on appropriate lines and serration and equalization pulses are inserted where required. In addition, the ADV7190/ADV7191 supports a PAL or NTSC square pixel operation. The part requires an input pixel clock of 24.5454 MHz for NTSC square pixel operation and an input pixel clock of 29.5 MHz for PAL square pixel operation. The internal horizontal line counters place the various video waveform sections in the correct location for the new clock frequencies. The ADV7190/ADV7191 has four distinct Master and four distinct Slave timing configurations. Timing Control is established with the bidirectional HSYNC, BLANK, and VSYNC pins. Timing Register 1 can also be used to vary the timing pulsewidths and where they occur in relation to each other. (Mode Register 2, Timing Register 0, 1.) RESET SEQUENCE When RESET becomes active the ADV7190/ADV7191 reverts to the default output configuration (see Appendix 8 for register settings). The ADV7190/ADV7191 internal timing is under the control of the logic level on the NTSC_PAL pin. -19- ADV7190/ADV7191 When RESET is released Y, Cr, Cb values corresponding to a black screen are input to the ADV7190/ADV7191. Output timing signals are still suppressed at this stage. DACs A, B, C are switched off and DACs D, E, F are switched on. to that on the NTSC_PAL pin, Standard I2C Control should be enabled (MR25 = 1) and the video standard required is selected by programming Mode Register 0 (Output Video Standard Selection). Figure 31 illustrates the RESET sequence timing. When the user requires valid data, Pixel Data Valid Control is enabled (MR26 = 1) to allow the valid pixel data to pass through the encoder. Digital output timing signals become active and the encoder timing is now under the control of the Timing Registers. If at this stage, the user wishes to select a different video standard RESET DAC D, DAC E XXXXXXX XXXXXXX BLACK VALUE WITH SYNC VALID VIDEO DAC F XXXXXXX XXXXXXX BLACK VALUE VALID VIDEO DAC A, DAC B, DAC C XXXXXXX MR26 PIXEL_DATA_VALID XXXXXXX DIGITAL TIMING XXXXXXX VALID VIDEO OFF 0 1 DIGITAL TIMING SIGNALS SUPPRESSED TIMING ACTIVE Figure 31. RESET Sequence Timing Diagram -20- REV. B ADV7190/ADV7191 CLOCK COMPOSITE VIDEO e.g., VCR OR CABLE VIDEO DECODER LCC1 ADV7190/ADV7191 SCRESET/RTC/TR GLL GREEN/COMPOSITE/Y BLUE/LUMA/U ADV7185 P19-P12 P7-P0 RED/CHROMA/V GREEN/COMPOSITE/Y BLUE/LUMA/U RED/CHROMA/V H/L TRANSITION COUNT START LOW 128 13 14 BITS RESERVED SEQUENCE BIT2 RESET 5 BITS BIT3 RESERVED RESERVED 4 BITS RESERVED 0 FSCPLL INCREMENT1 21 0 RTC TIME SLOT: 01 14 NOT USED IN ADV7190/ ADV7191 67 68 19 VALID SAMPLE 8/LINE LOCKED CLOCK INVALID SAMPLE NOTES: 1F SC PLL INCREMENT IS 22 BITS LONG, VALUE LOADED INTO ADV7190/ADV7191. FSC DDS REGISTER IS FSC PLL INCREMENTS BITS 21:0 PLUS BITS 0:9 OF SUBCARRIER FREQUENCY REGISTERS. ALL ZEROS SHOULD BE WRITTEN TO THE SUBCARRIER FREQUENCY REGISTERS OF THE ADV7190/ADV7191. 2SEQUENCE BIT PAL: 0 = LINE NORMAL, 1 = LINE INVERTED NTSC: 0 = NO CHANGE 3RESET BIT RESET ADV7190/ADV7191's DDS Figure 32. RTC Timing and Connections Mode 0 (CCIR-656): Slave Option (Timing Register 0 TR0 = X X X X X 0 0 0) The ADV7190/ADV7191 is controlled by the SAV (Start Active Video) and EAV (End Active Video) Time Codes in the Pixel Data. All timing information is transmitted using a 4-byte synchronization pattern. A synchronization pattern is sent immediately before and after each line during active picture and retrace. Mode 0 is illustrated in Figure 33. The HSYNC, VSYNC and BLANK pins (if not used) should be tied high during this mode. ANALOG VIDEO EAV CODE INPUT PIXELS NTSC/PAL M SYSTEM (525 LlNES/60Hz) PAL SYSTEM (625 LINES/50Hz) C F 0 0 X 8 1 8 1 Y r Y F 0 0 Y 0 0 0 0 4 CLOCK SAV CODE 0 F F A A A 0 F F B B B 8 1 8 1 F 0 0 X C C C C C 0 0 0 0 F 0 0 Y b Y r Y b Y r Y b ANCILLARY DATA (HANC) 1440 CLOCK 4 CLOCK 4 CLOCK 280 CLOCK END OF ACTIVE VIDEO LINE 1440 CLOCK START OF ACTIVE VIDEO LINE Figure 33. Timing Mode 0, Slave Mode REV. B 4 CLOCK 268 CLOCK -21- ADV7190/ADV7191 Mode 0 (CCIR-656): Master Option (Timing Register 0 TR0 = X X X X X 0 0 1) The ADV7190/ADV7191 generates H, V, and F signals required for the SAV and EAV Time Codes in the CCIR656 standard. The H bit is output on the HSYNC pin, the V bit is output on the BLANK pin and the F bit is output on the VSYNC pin. Mode 0 is illustrated in Figure 34 (NTSC) and Figure 35 (PAL). The H, V, and F transitions relative to the video waveform are illustrated in Figure 36. DISPLAY DISPLAY VERTICAL BLANK 522 523 524 525 1 2 3 4 6 5 7 8 9 10 11 20 21 22 H V F EVEN FIELD ODD FIELD DISPLAY DISPLAY VERTICAL BLANK 260 261 262 263 264 265 266 267 268 269 270 271 272 273 283 274 284 285 H V ODD FIELD F EVEN FIELD Figure 34. Timing Mode 0, NTSC Master Mode DISPLAY DISPLAY 622 623 VERTICAL BLANK 624 625 1 2 3 4 5 6 7 21 22 23 H V F EVEN FIELD ODD FIELD DISPLAY DISPLAY 309 310 VERTICAL BLANK 311 312 313 314 315 316 317 318 319 320 334 335 336 H V F ODD FIELD EVEN FIELD Figure 35. Timing Mode 0, PAL Master Mode -22- REV. B ADV7190/ADV7191 ANALOG VIDEO H F V Figure 36. Timing Mode 0 Data Transitions, Master Mode Mode 1: Slave Option HSYNC, BLANK, FIELD (Timing Register 0 TR0 = X X X X X 0 1 0) In this mode the ADV7190/ADV7191 accepts Horizontal SYNC and Odd/ Even FIELD signals. A transition of the FIELD input when HSYNC is low indicates a new frame, i.e., Vertical Retrace. The BLANK signal is optional. When the BLANK input is disabled the ADV7190/ADV7191 automatically blanks all normally blank lines as per CCIR-624. Mode 1 is illustrated in Figure 37 (NTSC) and Figure 38 (PAL). DISPLAY 522 523 524 DISPLAY VERTICAL BLANK 525 1 2 3 4 6 5 7 8 9 10 20 11 21 22 HSYNC BLANK EVEN FIELD FIELD ODD FIELD DISPLAY DISPLAY 260 261 262 VERTICAL BLANK 263 264 265 266 267 268 269 270 271 272 273 283 274 284 285 HSYNC BLANK ODD FIELD FIELD EVEN FIELD Figure 37. Timing Mode 1, NTSC DISPLAY 622 623 DISPLAY VERTICAL BLANK 624 625 1 2 3 4 5 6 7 21 22 23 HSYNC BLANK FIELD EVEN FIELD ODD FIELD DISPLAY DISPLAY 309 310 VERTICAL BLANK 311 312 313 314 315 316 317 318 HSYNC BLANK FIELD ODD FIELD EVEN FIELD Figure 38. Timing Mode 1, PAL REV. B -23- 319 320 334 335 336 ADV7190/ADV7191 Mode 1: Master Option HSYNC, BLANK, FIELD (Timing Register 0 TR0 = X X X X X 0 1 1) In this mode the ADV7190/ADV7191 can generate Horizontal SYNC and Odd/Even FIELD signals. A transition of the FIELD input when HSYNC is low indicates a new frame, i.e., Vertical Retrace. The BLANK signal is optional. When the BLANK input is disabled the ADV7190/ADV7191 automatically blanks all normally blank lines as per CCIR-624. Pixel data is latched on the rising clock edge following the timing signal transitions. Mode 1 is illustrated in Figure 37 (NTSC) and Figure 38 (PAL). Figure 39 illustrates the HSYNC, BLANK and FIELD for an odd or even field transition relative to the pixel data. HSYNC FIELD PAL = 12 CLOCK/2 NTSC = 16 CLOCK/2 BLANK PIXEL DATA Cb Y Cr Y PAL = 132 CLOCK/2 NTSC = 122 CLOCK/2 Figure 39. Timing Mode 1, Odd/Even Field Transitions Master/Slave Mode 2: Slave Option HSYNC, VSYNC, BLANK (Timing Register 0 TR0 = X X X X X 1 0 0) In this mode the ADV7190/ADV7191 accepts Horizontal and Vertical SYNC signals. A coincident low transition of both HSYNC and VSYNC inputs indicates the start of an Odd Field. A VSYNC low transition when HSYNC is high indicates the start of an Even Field. The BLANK signal is optional. When the BLANK input is disabled, the ADV7190/ADV7191 automatically blanks all normally blank lines as per CCIR-624. Mode 2 is illustrated in Figure 40 (NTSC) and Figure 41 (PAL). DISPLAY 522 523 524 DISPLAY VERTICAL BLANK 525 1 2 3 4 6 5 7 8 10 9 11 20 21 22 HSYNC BLANK EVEN FIELD VSYNC ODD FIELD DISPLAY 260 261 262 263 DISPLAY VERTICAL BLANK 264 265 266 267 268 269 270 271 272 273 274 283 284 285 HSYNC BLANK VSYNC ODD FIELD EVEN FIELD Figure 40. Timing Mode 2, NTSC -24- REV. B ADV7190/ADV7191 DISPLAY 622 623 DISPLAY VERTICAL BLANK 624 625 1 2 3 4 6 5 7 21 22 23 HSYNC BLANK VSYNC EVEN FIELD ODD FIELD DISPLAY DISPLAY 309 310 VERTICAL BLANK 311 312 313 314 315 316 318 317 319 320 334 335 336 HSYNC BLANK VSYNC ODD FIELD EVEN FIELD Figure 41. Timing Mode 2, PAL Mode 2: Master Option HSYNC, VSYNC, BLANK (Timing Register 0 TR0 = X X X X X 1 0 1) In this mode the ADV7190/ADV7191 can generate Horizontal and Vertical SYNC signals. A coincident low transition of both HSYNC and VSYNC inputs indicates the start of an Odd Field. A VSYNC low transition when HSYNC is high indicates the start of an Even Field. The BLANK signal is optional. When the BLANK input is disabled the ADV7190/ADV7191 automatically blanks all normally blank lines as per CCIR-624. Mode 2 is illustrated in Figure 40 (NTSC) and Figure 41 (PAL). Figure 42 illustrates the HSYNC, BLANK and VSYNC for an even-to-odd field transition relative to the pixel data. Figure 43 illustrates the HSYNC, BLANK and VSYNC for an odd-to-even field transition relative to the pixel data. HSYNC VSYNC PAL = 12 CLOCK/2 NTSC = 16 CLOCK/2 BLANK PIXEL DATA Cb Y PAL = 132 CLOCK/2 NTSC = 122 CLOCK/2 Figure 42. Timing Mode 2, Even-to-Odd Field Transition Master/Slave HSYNC VSYNC PAL = 12 CLOCK/2 NTSC = 16 CLOCK/2 PAL = 864 CLOCK/2 NTSC = 858 CLOCK/2 BLANK Cb PIXEL DATA Y Cr Y Cb PAL = 132 CLOCK/2 NTSC = 122 CLOCK/2 Figure 43. Timing Mode 2, Odd-to-Even Field Transition Master/Slave REV. B -25- Cr Y ADV7190/ADV7191 Mode 3: Master/Slave Option HSYNC, BLANK, FIELD (Timing Register 0 TR0 = X X X X X 1 1 0 or X X X X X 1 1 1) In this mode the ADV7190/ADV7191 accepts or generates Horizontal SYNC and Odd/Even FIELD signals. A transition of the FIELD input when HSYNC is high indicates a new frame, i.e., Vertical Retrace. The BLANK signal is optional. When the BLANK input is disabled the ADV7190/ADV7191 automatically blanks all normally blank lines as per CCIR-624. Mode 3 is illustrated in Figure 44 (NTSC) and Figure 45 (PAL). DISPLAY 522 523 524 DISPLAY VERTICAL BLANK 525 1 2 3 4 6 5 7 8 9 10 20 11 21 22 HSYNC BLANK FIELD EVEN FIELD ODD FIELD DISPLAY 260 261 262 263 DISPLAY VERTICAL BLANK 264 265 266 267 268 269 270 271 272 273 283 274 284 285 HSYNC BLANK FIELD ODD FIELD EVEN FIELD Figure 44. Timing Mode 3, NTSC DISPLAY 622 623 DISPLAY VERTICAL BLANK 624 625 1 2 3 4 5 6 7 21 22 23 HSYNC BLANK FIELD EVEN FIELD ODD FIELD DISPLAY DISPLAY 309 310 VERTICAL BLANK 311 312 313 314 315 316 317 318 319 320 334 335 336 HSYNC BLANK FIELD EVEN FIELD ODD FIELD Figure 45. Timing Mode 3, PAL -26- REV. B ADV7190/ADV7191 A Logic 0 on the LSB of the first byte means that the master will write information to the peripheral. A Logic 1 on the LSB of the first byte means that the master will read information from the peripheral. MPU PORT DESCRIPTION The ADV7190/ADV7191 supports a two-wire serial (I2 Ccompatible) microprocessor bus driving multiple peripherals. Two inputs, Serial Data (SDA) and Serial Clock (SCL), carry information between any device connected to the bus. Each slave device is recognized by a unique address. The ADV7190/ ADV7191 has four possible slave addresses for both read and write operations. These are unique addresses for each device and are illustrated in Figure 46 and Figure 47. The LSB sets either a read or write operation. Logic Level 1 corresponds to a read operation while Logic Level 0 corresponds to a write operation. A1 is set by setting the ALSB pin of the ADV7190/ADV7191 to Logic Level 0 or Logic Level 1. 1 1 0 1 0 1 A1 The ADV7190/ADV7191 acts as a standard slave device on the bus. The data on the SDA pin is eight bits long supporting the 7-bit addresses plus the R/W bit. It interprets the first byte as the device address and the second byte as the starting subaddress. The subaddresses autoincrement allowing data to be written to or read from the starting subaddress. A data transfer is always terminated by a stop condition. The user can also access any unique subaddress register on a one-by-one basis without having to update all the registers. There is one exception. The Subcarrier Frequency Registers should be updated in sequence, starting with Subcarrier Frequency Register 0. The autoincrement function should be then used to increment and access Subcarrier Frequency Registers 1, 2, and 3. The Subcarrier Frequency Registers should not be accessed independently. X ADDRESS CONTROL SETUP BY ALSB Stop and start conditions can be detected at any stage during the data transfer. If these conditions are asserted out of sequence with normal read and write operations, they cause an immediate jump to the idle condition. During a given SCL high period the user should issue only one start condition, one stop condition, or a single stop condition followed by a single start condition. If, an invalid subaddress is issued by the user, the ADV7190/ ADV7191 will not issue an acknowledge and will return to the idle condition. If in autoincrement mode, the user exceeds the highest subaddress, the following action will be taken: READ/WRITE CONTROL 0 WRITE 1 READ Figure 46a. Slave Address for ADV7190 0 1 0 1 0 1 A1 X ADDRESS CONTROL SETUP BY ALSB 1. In Read Mode, the highest subaddress register contents will continue to be output until the master device issues a no-acknowledge. This indicates the end of a read. A noacknowledge condition is where the SDA line is not pulled low on the ninth pulse. READ/WRITE CONTROL 0 WRITE 1 READ Figure 46b. Slave Address for ADV7191 To control the various devices on the bus the following protocol must be followed. First, the master initiates a data transfer by establishing a start condition, defined by a high-to-low transition on SDA while SCL remains high. This indicates that an address/ data stream will follow. All peripherals respond to the start condition and shift the next eight bits (7-bit address + R/W bit). The bits are transferred from MSB down to LSB. The peripheral that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse. This is known as an acknowledge bit. All other devices withdraw from the bus at this point and maintain an idle condition. The idle condition is where the device monitors the SDA and SCL lines waiting for the start condition and the correct transmitted address. The R/W bit determines the direction of the data. 2. In Write Mode, the data for the invalid byte will be not be loaded into any subaddress register, a no-acknowledge will be issued by the ADV7190/ADV7191 and the part will return to the idle condition. SDATA SCLOCK S 1-7 8 9 1-7 8 9 1-7 START ADDR R/W ACK SUBADDRESS ACK DATA S SLAVE ADDR A(S) SUB ADDR S SLAVE ADDR A(S) S = START BIT P = STOP BIT SUB ADDR DATA A(S) DATA A(S) S SLAVE ADDR A(S) = ACKNOWLEDGE BY SLAVE A(M) = ACKNOWLEDGE BY MASTER A(S) P A(S) DATA -27- A(M) A(S) = NO ACKNOWLEDGE BY SLAVE A(M) = NO ACKNOWLEDGE BY MASTER Figure 48. Write and Read Sequences REV. B P STOP Figure 47 illustrates an example of data transfer for a read sequence and the start and stop conditions. LSB = 1 LSB = 0 READ SEQUENCE A(S) 9 ACK Figure 47. Bus Data Transfer Figure 48 shows bus write and read sequences. WRITE SEQUENCE 8 DATA A(M) P ADV7190/ADV7191 REGISTER ACCESSES Subaddress Register (SR7-SR0) The MPU can write to or read from all of the registers of the ADV7190/ADV7191 with the exception of the Subaddress Registers, which are write-only registers. The Subaddress Register determines which register the next read or write operation accesses. All communications with the part through the bus start with an access to the Subaddress Register. Then a read/write operation is performed from/to the target address which then increments to the next address until a stop command on the bus is performed. The Communications Register is an eight bit write-only register. After the part has been accessed over the bus and a read/write operation is selected, the subaddress is set up. The Subaddress Register determines to/from which register the operation takes place. Figure 49 shows the various operations under the control of the Subaddress Register 0 should always be written to SR7. Register Select (SR6-SR0) These bits are set up to point to the required starting address. REGISTER PROGRAMMING The following section describes each register. All registers can be read from as well as written to. SR7 SR7 ZERO SHOULD BE WRITTEN HERE SR6 SR5 SR4 SR3 SR2 SR1 SR0 ADV7190/ADV7191 SUBADDRESS REGISTER ADDRESS 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 40H 41H 42H 43H 44H 45H 46H 47H 48H 49H 4AH 4BH SR6 SR5 SR4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 1 1 1 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 SR3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 SR2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 SR1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 0 1 SR0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 MODE REGISTER 0 MODE REGISTER 1 MODE REGISTER 2 MODE REGISTER 3 MODE REGISTER 4 MODE REGISTER 5 MODE REGISTER 6 MODE REGISTER 7 MODE REGISTER 8 MODE REGISTER 9 TIMING REGISTER 0 TIMING REGISTER 1 SUBCARRIER FREQUENCY REGISTER 0 SUBCARRIER FREQUENCY REGISTER 1 SUBCARRIER FREQUENCY REGISTER 2 SUBCARRIER FREQUENCY REGISTER 3 SUBCARRIER PHASE REGISTER CLOSED CAPTIONING EXTENDED DATA BYTE 0 CLOSED CAPTIONING EXTENDED DATA BYTE 1 CLOSED CAPTIONING DATA BYTE 0 CLOSED CAPTIONING DATA BYTE 1 NTSC PEDESTAL/TELETEXT CONTROL REGISTER 0 NTSC PEDESTAL/TELETEXT CONTROL REGISTER 1 NTSC PEDESTAL/TELETEXT CONTROL REGISTER 2 NTSC PEDESTAL/TELETEXT CONTROL REGISTER 3 CGMS/WSS 0 CGMS/WSS 1 CGMS/WSS 2 TELETEXT REQUEST CONTROL REGISTER CONTRAST CONTROL REGISTER U SCALE V SCALE HUE ADJUST CONTROL REGISTER BRIGHTNESS CONTROL REGISTER SHARPNESS CONTROL REGISTER DNR 0 DNR 1 DNR 2 GAMMA CORRECTION REGISTER 0 GAMMA CORRECTION REGISTER 1 GAMMA CORRECTION REGISTER 2 GAMMA CORRECTION REGISTER 3 GAMMA CORRECTION REGISTER 4 GAMMA CORRECTION REGISTER 5 GAMMA CORRECTION REGISTER 6 GAMMA CORRECTION REGISTER 7 GAMMA CORRECTION REGISTER 8 GAMMA CORRECTION REGISTER 9 GAMMA CORRECTION REGISTER 10 GAMMA CORRECTION REGISTER 11 GAMMA CORRECTION REGISTER 12 GAMMA CORRECTION REGISTER 13 BRIGHTNESS DETECT REGISTER OUTPUT CLOCK REGISTER RESERVED RESERVED RESERVED RESERVED MACROVISION REGISTER (ADV7190 ONLY) MACROVISION REGISTER (ADV7190 ONLY) MACROVISION REGISTER (ADV7190 ONLY) MACROVISION REGISTER (ADV7190 ONLY) MACROVISION REGISTER (ADV7190 ONLY) MACROVISION REGISTER (ADV7190 ONLY) MACROVISION REGISTER (ADV7190 ONLY) MACROVISION REGISTER (ADV7190 ONLY) MACROVISION REGISTER (ADV7190 ONLY) MACROVISION REGISTER (ADV7190 ONLY) MACROVISION REGISTER (ADV7190 ONLY) MACROVISION REGISTER (ADV7190 ONLY) MACROVISION REGISTER (ADV7190 ONLY) MACROVISION REGISTER (ADV7190 ONLY) MACROVISION REGISTER (ADV7190 ONLY) MACROVISION REGISTER (ADV7190 ONLY) MACROVISION REGISTER (ADV7190 ONLY) MACROVISION REGISTER (ADV7190 ONLY) Figure 49. Subaddress Register -28- REV. B ADV7190/ADV7191 MODE REGISTER 0 MR0 (MR07-MR00) (Address (SR4-SR0) = 00H) MODE REGISTER 1 MR1 (MR17-MR10) (Address (SR4-SR0) = 01H) Figure 50 shows the various operations under the control of Mode Register 0. Figure 51 shows the various operations under the control of Mode Register 1. MR0 BIT DESCRIPTION Output Video Standard Selection (MR00-MR01) MR1 BIT DESCRIPTION DAC Control (MR10-MR15) These bits are used to set up the encoder mode. The ADV7190/ ADV7191 can be set up to output NTSC, PAL (B, D, G, H, I), PAL M or PAL N standard video. Bits MR15-MR10 can be used to power down the DACs. This is used to reduce the power consumption of the ADV7190/ADV7191 or if any of the DACs are not required in the application. Luminance Filter Select (MR02-MR04) 4 Oversampling Control (MR16) These bits specify which luma filter is to be selected. The filter selection is made independent of whether PAL or NTSC is selected. To enable 4 Oversampling this bit has to be set to 1. When enabled, the data is output at a frequency of 54 MHz. Note that PLL Enable Control has to be enabled (MR61 = 0) in 4 Oversampling mode. Chrominance Filter Select (MR05-MR07) These bits select the chrominance filter. A low-pass filter can be selected with a choice of cut-off frequencies (0.65 MHz, 1.0 MHz, 1.3 MHz, 2 MHz, or 3 MHz) along with a choice of CIF or QCIF filters. MR07 MR06 MR05 Reserved (MR17) A Logical 0 must be written to this bit. MR04 MR03 MR02 MR01 OUTPUT VIDEO STANDARD SELECTION CHROMA FILTER SELECT MR07 MR06 MR05 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 MR00 MR01 MR00 1.3 MHz LOW-PASS FILTER 0.65 MHz LOW-PASS FILTER 1.0 MHz LOW-PASS FILTER 2.0 MHz LOW-PASS FILTER RESERVED CIF QCIF 3.0 MHz LOW-PASS FILTER 0 0 1 1 0 1 0 1 NTSC PAL (B, D, G, H, I) PAL (M) (ADV7190 ONLY) PAL (N) LUMA FILTER SELECT MR04 MR03 MR02 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 LOW-PASS FILTER (NTSC) LOW-PASS FILTER (PAL) NOTCH FILTER (NTSC) NOTCH FILTER (PAL) EXTENDED MODE CIF QCIF RESERVED Figure 50. Mode Register 0 (MR0) MR17 MR17 ZERO MUST BE WRITTEN TO THIS BIT MR16 MR15 MR13 DAC A DAC CONTROL 0 1 MR12 0 1 MR11 POWER-DOWN NORMAL DAC B DAC CONTROL MR14 0 1 0 1 POWER-DOWN NORMAL DAC D DAC CONTROL MR12 POWER-DOWN NORMAL 0 1 -29- DAC F DAC CONTROL MR10 POWER-DOWN NORMAL Figure 51. Mode Register 1 (MR1) REV. B MR10 DAC E DAC CONTROL MR13 POWER-DOWN NORMAL 2 OVERSAMPLING 4 OVERSAMPLING MR11 DAC C DAC CONTROL MR15 4 OVERSAMPLING CONTROL MR16 0 1 MR14 0 1 POWER-DOWN NORMAL ADV7190/ADV7191 Standard I2C Control (MR25) MODE REGISTER 2 MR2 (MR27-MR20) (Address (SR4-SR0) = 02H) This bit controls the video standard used by the ADV7190/ ADV7191. When this bit is set to 1 the video standard as programmed in Output Video Standard Selection (MR00, MR01). When MR25 is set to 0, the ADV7190/ADV7191 is forced into the standard selected by the NTSC_PAL pin. When NTSC_PAL is low the standard is NTSC, when the NTSC_PAL pin is high, the standard is PAL. Mode Register 2 is an 8-bit-wide register. Figure 52 shows the various operations under the control of Mode Register. MR2 BIT DESCRIPTION-- RGB/YUV Control (MR20) This bit enables the output from the small or large DACs to be set to YUV or RGB output video standard. Pixel Data Valid Control (MR26) This bit controls the output from DACs A, B, and C. When this bit is set to 1, Composite, Luma, and Chroma Signals are output from DACs A, B, and C (respectively). When this bit is set to 0, RGB or YUV may be output from these DACs. After resetting the device, this bit has the value 0 and the pixel data input to the encoder is blanked such that a black screen is output from the DACs. The ADV7190/ADV7191 will be set to Master Mode timing. When this bit is set to 1 by the user (via the I2C), pixel data passes to the pins and the encoder reverts to the Timing Mode defined by Timing Register 0. SCART Enable Control (MR22) Sleep Mode Control (MR27) DAC Output Control (MR21) This bit is used to switch the DAC outputs from SCART to a EUROSCART configuration. A complete table of all DAC output configurations is shown in Table III. When this bit is set (1), Sleep Mode is enabled. With this mode enabled, the ADV7190/ADV7191 current consumption is reduced to less than 1 mA. The I2C registers can be written to and read from when the ADV7190/ADV7191 is in Sleep Mode. Pedestal Control (MR23) This bit specifies whether a pedestal is to be generated on the NTSC composite video signal. This bit is invalid when the device is configured in PAL mode. When the device is in Sleep Mode and 0 is written to MR27, the ADV7190/ADV7191 will come out of Sleep Mode and resume normal operation. Also, if a RESET is applied during Sleep Mode, the ADV7190/ADV7191 will come out of Sleep Mode and resume normal operation. Square Pixel Control (MR24) This bit is used to set up square pixel mode. This is available in Slave Mode only. For NTSC, a 24.5454 MHz clock must be supplied. For PAL, a 29.5 MHz clock must be supplied. Square pixel operation is not available in 4 Oversampling mode. For this to operate, Power Up in Sleep Mode Control has to be enabled (MR60 = 0), otherwise Sleep Mode is controlled by the PAL_NTSC and SCRESET/RTC/TR pins. Table III. DAC Output Configuration Matrix SCART MR22 DAC O/P MR21 RGB/YUV MR20 DAC A DAC B DAC C DAC D DAC E DAC F 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 G Y CVBS CVBS CVBS CVBS CVBS CVBS B U LUMA LUMA B U LUMA LUMA R V CHROMA CHROMA R V CHROMA CHROMA CVBS CVBS G Y G Y G Y LUMA LUMA B U LUMA LUMA B U CHROMA CHROMA R V CHROMA CHROMA R V MR27 MR26 MR25 PIXEL DATA VALID CONTROL MR26 0 DISABLE 1 ENABLE SLEEP MODE CONTROL MR27 0 DISABLE 1 ENABLE MR24 MR23 SQUARE PIXEL CONTROL MR25 0 DISABLE 1 ENABLE MR21 SCART ENABLE CONTROL MR24 0 DISABLE 1 ENABLE STANDARD I2C CONTROL MR22 MR22 0 DISABLE 1 ENABLE MR20 RGB/YUV CONTROL MR20 0 RGB OUTPUT 1 YUV OUTPUT PEDESTAL CONTROL DAC OUTPUT CONTROL MR23 0 PEDESTAL OFF 1 PEDESTAL ON MR21 0 RGB/YUV/COMP 1 COMP/LUMA/CHROMA Figure 52. Mode Register 2 (MR2) -30- REV. B ADV7190/ADV7191 MODE REGISTER 3 MR3 (MR37-MR30) (Address (SR4-SR0) = 03H) Genlock Control (MR41-MR42) Mode Register 3 is an 8-bit-wide register. Figure 53 shows the various operations under the control of Mode Register 3. These bits control the Genlock feature and timing reset of the ADV7190/ADV7191. Setting MR41 and MR42 to Logic 0 disables the SCRESET/RTC/TR pin and allows the ADV7190/ ADV7191 to operate in normal mode. MR3 BIT DESCRIPTION Revision Code (MR30-MR31) 1. By setting MR41 to zero and MR42 to one a timing reset is applied, resetting the horizontal and vertical counters. This has the effect of resetting the Field Count to Field 0. This bit is read only and indicates the revision of the device. If the SCRESET/RTC/TR pin is held high, the counters will remain reset. Once the pin is released the counters will commence counting again. For correct counter reset, the SCRESET/RTC/TR pin has to remain high for at least 37 ns (one clock cycle at 27 MHz). VBI_Open (MR32) This bit determines whether or not data in the Vertical Blanking Interval (VBI) is output to the analog outputs or blanked. Note that this condition is also valid in Timing Slave Mode 0. For further information see Vertical Blanking Data Insertion and BLANK Input section. 2. If MR41 is set to one and MR42 is set to zero, the SCRESET/ RTC/TR pin is configured as a subcarrier reset input and the subcarrier phase will reset to Field 0 whenever a low-tohigh transition is detected on the SCRESET/RTC/TR pin (SCH phase resets at the start of the next field). Teletext Enable (MR33) This bit must be set to 1 to enable teletext data insertion on the TTX pin. Teletext Bit Request Mode Control (MR34) 3. If MR41 is set to one and MR42 is set to one, the SCRESET/ RTC/TR pin is configured as a real-time control input and the ADV7190/ADV7191 can be used to lock to an external video source working in RTC mode. For more information see Real-Time Control, Subcarrier Reset and Timing Reset section. This bit enables switching of the teletext request signal from a continuous high signal (MR34 = 0) to a bitwise request signal (MR34 = 1). Closed Captioning Field Control (MR35-MR36) These bits control the fields that closed captioning data is displayed on, closed captioning information can be displayed on an odd field, even field or both fields. Active Video Line Duration (MR43) This bit switches between two active video line durations. A zero selects CCIR Rec. 601 (720 pixels PAL/NTSC) and a one selects ITU-R BT. 470 standard for active video duration (710 pixels NTSC, 702 pixels PAL). Reserved (MR37) A Logic 0 must be written to this bit. Chrominance Control (MR44) MODE REGISTER 4 MR4 (MR47-MR40) (Address (SR4-SR0) = 04H) This bit enables the color information to be switched on and off the chroma composite, color component outputs. Mode Register 4 is an 8-bit-wide register. Figure 54 shows the various operations under the control of Mode Register 4. Burst Control (MR45) MR4 BIT DESCRIPTION VSYNC_3H Control (MR40) Color Bar Control (MR46) This bit enables the color burst to be switched on and off the chroma and composite outputs. This bit can be used to generate and output an internal color bar test pattern. The color bar configuration is 100/7.5/75/7.5 for NTSC and 100/0/75/0 for PAL. It is important to note that when color bars are enabled the ADV7190/ADV7191 is configured in a Master Timing mode. When this bit is enabled (1) in Slave Mode, it is possible to drive the VSYNC input low for 2.5 lines in PAL mode and three lines in NTSC mode. When this bit is enabled in Master Mode the ADV7190/ADV7191 outputs an active low VSYNC signal for three lines in NTSC mode and 2.5 lines in PAL mode. MR37 MR36 MR35 MR34 MR33 MR32 TTX BIT REQUEST MODE CONTROL MR37 MR34 0 DISABLE 1 ENABLE ZERO MUST BE WRITTEN TO THIS BIT CLOSED CAPTIONING FIELD CONTROL MR36 MR35 0 0 0 1 1 0 1 1 NO DATA OUT ODD FIELD ONLY EVEN FIELD ONLY DATA OUT (BOTH FIELDS) VBI OPEN MR32 0 DISABLE 1 ENABLE TELETEXT ENABLE MR33 0 DISABLE 1 ENABLE Figure 53. Mode Register 3 (MR3) REV. B -31- MR31 MR30 MR31 MR30 RESERVED FOR REVISION CODE ADV7190/ADV7191 MR47 MR46 MR45 COLOR BAR CONTROL MR46 0 DISABLE 1 ENABLE INTERLACED MODE CONTROL MR44 CHROMINANCE CONTROL MR44 0 ENABLE COLOR 1 DISABLE COLOR BURST CONTROL MR47 0 INTERLACED 1 NONINTERLACED MR43 MR42 MR41 GENLOCK CONTROL MR42 MR41 0 0 0 1 1 1 0 1 DISABLE GENLOCK ENABLE SUBCARRIER RESET PIN TIMING RESET ENABLE RTC PIN ACTIVE VIDEO LINE DURATION MR43 0 720 PIXELS 1 710 PIXELS/702 PIXELS MR45 0 ENABLE BURST 1 DISABLE BURST MR40 VSYNC 3H CONTROL MR40 0 1 DISABLE ENABLE Figure 54. Mode Register 4 (MR4) It is also possible to have default values of 934 mV for NTSC and 700 mV for PAL (MR52 + MR51 = 00). Interlaced Mode Control (MR47) This bit is used to setup the output to interlaced or noninterlaced mode. RGB Sync (MR53) This bit is used to set up the RGB outputs with the sync information encoded on all RGB outputs. MODE REGISTER 5 MR5 (MR57-MR50) (Address (SR4-SR0) = 05H) Clamp Delay Value (MR54-MR55) These bits control the delay or advance of the CLAMP signal in the front or back porch of the ADV7190/ADV7191. It is possible to delay or advance the pulse by zero, one, two, or three clock cycles. Mode Register 5 is an 8-bit-wide register. Figure 55 shows the various operations under the control of Mode Register 5. MR5 BIT DESCRIPTION Y-Level Control (MR50) Note: Pin 51 is a multifunctional pin (VSO/CLAMP). CLAMP/ VSO Select Control (MR77) has to be set accordingly. This bit controls the component Y output level on the ADV7190/ ADV7191. If this bit is set (0), the encoder outputs Betacam levels when configured in PAL or NTSC mode. If this bit is set (1), the encoder outputs SMPTE levels when configured in PAL or NTSC mode. Clamp Delay Direction (MR56) This bit controls a positive or negative delay in the CLAMP signal. If this bit is set (1), the delay is negative. If it is set (0), the delay is positive. UV-Levels Control (MR51-MR52) Clamp Position (MR57) These bits control the component U and V output levels on the ADV7190/ADV7191. It is possible to have UV levels with a peak-to-peak amplitude of either 700 mV (MR52 + MR51 = 01 ) or 1000 mV (MR52 + MR51 = 10) in NTSC and PAL. MR57 MR56 MR55 This bit controls the position of the CLAMP signal. If this bit is set (1), the CLAMP signal is located in the back porch position. If this bit is set (0), the CLAMP signal is located in the front porch position. MR54 MR53 CLAMP DELAY DIRECTION MR57 0 FRONT PORCH 1 BACK PORCH 0 1 0 1 0 1 MR50 0 DISABLE 1 ENABLE DISABLE ENABLE CLAMP DELAY MR50 Y LEVEL CONTROL MR53 UV LEVEL CONTROL MR52 MR51 MR55 MR54 0 0 1 1 MR51 RGB SYNC MR56 0 POSITIVE 1 NEGATIVE CLAMP POSITION MR52 NO DELAY 1 PCLK 2 PCLK 3 PCLK 0 0 1 1 0 1 0 1 DEFAULT LEVELS 700mV 1000mV RESERVED Figure 55. Mode Register 5 (MR5) -32- REV. B ADV7190/ADV7191 MODE REGISTER 6 MR6 (MR67-MR60) (ADDRESS (SR4-SR0) = 06H) Luma Saturation Control (MR71) When this bit is set (1), the luma signal will be clipped if it reaches a limit that corresponds to an input luma value of 255 (after scaling by the Contrast Control Register). This prevents the chrominance component of the composite video signal being clipped if the amplitude of the luma is too high. When this bit is set (0), this control is disabled. Mode Register 6 is an 8-bit-wide register. Figure 56 shows the various operations under the control of Mode Register 6. MR6 BIT DESCRIPTION Power-Up Sleep Mode Control (MR60) Hue Adjust Control (MR72) After RESET is applied this control is enabled (MR60 = 0) if both SCRESET/RTC/TR and NTSC_PAL pins are tied high. The ADV7190/ADV7191 will then power up in Sleep Mode to facilitate low power consumption while the I2C is initialized. When this control is disabled (MR60 = 1, via the I2C) Sleep Mode control passes to Sleep Mode Control, MR27. This bit is used to enable hue adjustment on the composite and chroma output signals of the ADV7190/ADV7191. When this bit is set (1), the hue of the color is adjusted by the phase offset described in the Hue Adjust Control Register. When this bit is set (0), hue adjustment is disabled. Brightness Enable Control (MR73) PPL Enable Control (MR61) Reserved (MR62, MR63, MR64) This bit is used to enable the brightness control of the ADV7190/ ADV7191. The actual brightness level is programmed in the Brightness Control Register. This value or "setup" level is added to the scaled Y data. When this bit is set (1), brightness control is enabled. When this bit is set (0), brightness control is disabled. A Logic 0 must be written to these bits. Sharpness Filter Enable (MR74) Field Counter (MR65, MR66, MR67) This bit is used to enable the sharpness control of the luminance signal on the ADV7190/ADV7191 (Luma Filter Select has to be set to Extended, i.e., MR04-MR02 = 100). The various responses of the filter are determined by the Sharpness Control Register. When this bit is set (1), the luma response is altered by the amount described in the Sharpness Control Register. When this bit is set (0), the sharpness control is disabled. See Internal Filter Response section for luma signal responses. The PLL control should be enabled (MR61 = 0 ) when 4 Oversampling is enabled (MR16 = 1). It is also used to reset the PLL when this bit is toggled. These three bits are read-only bits. The field count can be read back over the I2C interface. In NTSC mode the field count goes from 0-3, in PAL Mode from 0-7. MODE REGISTER 7 MR7 (MR77-MR70) (Address (SR4-SR0) = 07H) Mode Register 7 is an 8-bit-wide register. Figure 57 shows the various operations under the control of Mode Register 7. CSO_HSO Output Control (MR75) This bit is used to determine whether HSO or CSO TTL output signal is output at the CSO_HSO pin. If this bit is set (1), the CSO TTL signal is output. If this bit is set 0, the HSO TTL signal is output. MR7 BIT DESCRIPTION Color Control Enable (MR70) This bit is used to enable control of contrast and saturation of color. If this bit is set (1), color controls are enabled (Contrast Control Register, U-Scale Register, V-Scale Register). If this bit is set (0), the color control features are disabled. MR67 MR66 MR65 MR64 MR63 MR62 MR67 MR66 MR65 MR64 MR63 MR62 FIELD COUNTER ZERO MUST BE WRITTEN TO THESE BITS MR61 MR60 PLL ENABLE CONTROL MR61 0 1 POWER-UP SLEEP MODE CONTROL ENABLED DISABLED MR60 0 ENABLED 1 DISABLED Figure 56. Mode Register 6 (MR6) MR77 MR76 MR75 MR76 ZERO MUST BE WRITTEN TO THIS BIT CLAMP/ VSO SELECT MR77 0 VSO OUTPUT 1 CLAMP OUTPUT MR74 SHARPNESS FILTER ENABLE MR74 0 DISABLE 1 ENABLE CSO_HSO OUTPUT CONTROL MR75 0 1 MR73 HSO OUT CSO OUT MR72 MR71 HUE ADJUST CONTROL MR72 0 DISABLE 1 ENABLE BRIGHTNESS ENABLE CONTROL MR73 0 DISABLE 1 ENABLE -33- COLOR CONTROL ENABLE MR70 0 DISABLE 1 ENABLE LUMA SATURATION CONTROL MR71 0 DISABLE 1 ENABLE Figure 57. Mode Register 7 (MR7) REV. B MR70 ADV7190/ADV7191 A Logic 0 must be written to this bit. on Gamma Correction controls see Gamma Correction Registers 0-13 (Gamma 0-13) (Address (SR5-SR0) = 26H-32H) section. CLAMP/VSO Select (MR77) Gamma Curve Select Control (MR87) This bit is used to select the functionality of Pin 51. A 1 selects CLAMP as the output signal. A 0 selects VSO output. This bit selects which of the two programmable gamma curves is used. When setting MR87 to 0, the gamma correction curve to be processed is Curve A. Otherwise, Curve B is selected. For further information on Gamma Correction controls see Gamma Correction Registers 0-13 (Gamma 0-13) (Address (SR5-SR0) = 26H-32H) section. Reserved (MR76) MODE REGISTER 8 MR8 (MR87-MR80) (Address (SR4-SR0) = 08H) Mode Register 8 is an 8-bit-wide register. Figure 58 shows the various operations under the control of Mode Register 8. MODE REGISTER 9 MR9 (MR97-MR90) (Address (SR4-SR0) = 09H) MR8 BIT DESCRIPTION Reserved (MR80, MR81) Mode Register 9 is an 8-bit-wide register. Figure 59 shows the various operations under the control of Mode Register 9. A Logic 0 must be written to these bits. Double Buffer Control (MR82) Double buffering can be enabled or disabled on the Contrast Control Register, U Scale Register, V Scale Register, Hue Adjust Control Register, Closed Captioning Register, Brightness Control Register, Gamma Curve Select Bit and the Macrovision Registers (ADV7190 only). Double Buffering is not available in Master Timing mode. MR9 BIT DESCRIPTION Undershoot Limiter (MR90-MR91) 16-Bit Pixel Port (MR83) Note that this facility is only available in 4 Oversampling mode (MR16 = 1). When the device is operated in 2 Oversampling mode (MR16 = 0) or RGB outputs without RGB sync are selected, the minimum luma level is set in Timing Register 0, TR06 (Min Luma Control). This control ensures that no luma video data will go below a programmable level. This prevents any synchronization problems due to luma signals going below the blanking level. Available limit levels are -1.5 IRE, -6 IRE, -11 IRE. This bit controls if the ADV7190/ADV7191 accepts 8-bit or 16-bit input data. In 8-bit mode the data will be input on Pins P0-P7. Unused pixel inputs should be grounded. Reserved (MR84) Reserved (MR92-MR93) A Logic 0 must be written to this bit. A Logic 0 must be written to these bits. DNR Enable Control (MR85) To enable the DNR process this bit has to be set to 1. If this bit is set to 0, the DNR processing is bypassed. For further information on DNR controls see DNR Registers 2-0, DNR1 Bit Description, and DNR2 Bit Description sections. Chroma Delay Control (MR94-MR95) Gamma Enable Control (MR86) Reserved (MR96-MR97) The Chroma Signal can be delayed by up to 296 ns (eight clock cycles at 27 MHz) using MR94-MR95. For further information see also Chroma/Luma Delay section. A Logic 0 must be written to these bits. To enable the programmable gamma correction this bit has to be set to enabled (MR86 is set to 1). For further information MR87 MR86 MR85 GAMMA ENABLE CONTROL MR86 0 DISABLE 1 ENABLE GAMMA CURVE SELECT CONTROL MR87 0 CURVE A 1 CURVE B MR84 MR83 MR84 MR81 DOUBLE BUFFER CONTROL MR82 0 DISABLE 1 ENABLE ZERO MUST BE WRITTEN TO THIS BIT DNR ENABLE CONTROL MR85 0 DISABLE 1 ENABLE MR82 MR80 MR81 MR80 ZERO MUST BE WRITTEN TO THESE BITS 16-PIXEL PORT MR83 0 8-BIT PIXEL PORT 1 16-BIT PIXEL PORT Figure 58. Mode Register 8 (MR8) MR97 MR96 MR95 MR97 MR96 ZERO MUST BE WRITTEN TO THESE BITS MR94 MR93 MR95 MR94 0 1 0 1 MR91 MR93 MR92 CHROMA DELAY CONTROL 0 0 1 1 MR92 0ns DELAY 148ns DELAY 296ns DELAY RESERVED ZERO MUST BE WRITTEN TO THESE BITS MR90 UNDERSHOOT LIMITER MR91 MR90 0 0 1 1 0 1 0 1 DISABLED -11 IRE -6 IRE -1.5 IRE Figure 59. Mode Register 9 (MR9) -34- REV. B ADV7190/ADV7191 TIMING REGISTER 0 (TR07-TR00) (Address (SR4-SR0) = 0AH) TIMING REGISTER 1 (TR17-TR10) (Address (SR4-SR0) = 0BH) Figure 60 shows the various operations under the control of Timing Register 0. This register can be read from as well as written to. Timing Register 1 is an 8-bit-wide register. Figure 61 shows the various operations under the control of Timing Register 1. This register can be read from as well written to. This register can be used to adjust the width and position of the master mode timing signals. TR0 BIT DESCRIPTION Master/Slave Control (TR00) This bit controls whether the ADV7190/ADV7191 is in master or slave mode. TR1 BIT DESCRIPTION HSYNC Width (TR10-TR11) Timing Mode Selection (TR01-TR02) These bits control the timing mode of the ADV7190/ADV7191. These modes are described in more detail in the Video Timing Description and RESET Sequence sections of the data sheet. These bits adjust the HSYNC pulsewidth. BLANK Input Control (TR03) These bits adjust the position of the HSYNC output relative to the VSYNC output. TPCLK = one clock cycle at 27 MHz. HSYNC to VSYNC Delay Control (TR12-TR13) This bit controls whether the BLANK input is used to accept blank signals or whether blank signals are internally generated. TPCLK = one clock cycle at 27 MHz. Note: When this input pin is tied high (to 5 V), the input is disabled regardless of the register setting. It, therefore, should be tied low (to Ground) to allow control over the I2C register. HSYNC to VSYNC Rising Edge Control (TR14-TR15) When the ADV7190/ADV7191 is in Timing Mode 1, these bits adjust the position of the HSYNC output relative to the VSYNC output rising edge. Luma Delay (TR04-TR05) The luma signal can be delayed by up to 222 ns (or six clock cycles at 27 MHz) using TR04-TR05. For further information see Chroma/Luma Delay section. TPCLK = one clock cycle at 27 MHz. VSYNC Width (TR14-TR15) When the ADV7190/ADV7191 is configured in Timing Mode 2, these bits adjust the VSYNC pulsewidth. Min Luminance Value (TR06) This bit is used to control the minimum luma output value by the ADV7190/ADV7191 in 2 Oversampling Mode (MR 16 = 0). When this bit is set to a Logic 1, the luma is limited to 7.5IRE below the blank level. When this bit is set to (0), the luma value can be as low as the sync bottom level (40IRE below blanking). TPCLK = one clock cycle at 27 MHz. HSYNC to Pixel Data Adjust (TR16-TR17) This enables the HSYNC to be adjusted with respect to the pixel data. This allows the Cr and Cb components to be swapped. This adjustment is available in both master and slave timing modes. Timing Register Reset (TR07) Toggling TR07 from low to high and low again resets the internal timing counters. This bit should be toggled after power-up, reset, or changing to a new timing mode. TR07 TR06 TR05 TR04 TR03 TR02 TR07 LUMA DELAY MIN LUMINANCE VALUE TR05 TR04 0 0 1 1 0 1 0 1 0ns DELAY 74ns DELAY 148ns DELAY 222ns DELAY -35- TR00 MASTER / SLAVE CONTROL TR00 0 SLAVE TIMING 1 MASTER TIMING TIMING MODE CONTROL TR02 TR01 0 0 0 1 1 0 1 1 Figure 60. Timing Register 0 REV. B TR01 BLANK INPUT CONTROL TR03 0 ENABLE 1 DISABLE TIMING REGISTER RESET TR06 0 LUMA MIN = SYNC BOTTOM 1 LUMA MIN = BLANK -7.5 IRE TPCLK = one clock cycle at 27 MHz. MODE 0 MODE 1 MODE 2 MODE 3 ADV7190/ADV7191 TR17 TR16 TR15 TR17 TR16 TR15 TR14 0 TPCLK 1 T PCLK 2 TPCLK 3 TPCLK 0 1 0 1 TR13 TR13 TR12 TC 0 1 TR12 TR11 HSYNC TO VSYNC DELAY HSYNC TO VSYNC RISING EDGE DELAY (MODE 1 ONLY) HSYNC TO PIXEL DATA ADJUST 0 0 1 1 TR14 0 0 1 1 TB TB + 32s HSYNC WIDTH TB TR11 TR10 0 TPCLK 4 T PCLK 8 TPCLK 18 TPCLK 0 1 0 1 TR10 0 0 1 1 TA 1 TPCLK 4 T PCLK 16 TPCLK 128 TPCLK 0 1 0 1 VSYNC WIDTH (MODE 2 ONLY) TR15 TR14 0 0 1 1 0 1 0 1 1 TPCLK 4 T PCLK 16 TPCLK 128 TPCLK TIMING MODE 1 (MASTER/PAL) LINE 1 HSYNC LINE 313 LINE 314 TA TC TB VSYNC Figure 61. Timing Register 1 SUBCARRIER FREQUENCY REGISTERS 3-0 (FSC31-FSC0) (Address (SR4-SR0) = 0CH-0FH) SUBCARRIER PHASE REGISTER (FPH7-FPH0) (Address (SR4-SR0) = 10H) These 8-bit-wide registers are used to set up the Subcarrier Frequency. The value of these registers are calculated by using the following equation: This 8-bit-wide register is used to set up the Subcarrier Phase. Each bit represents 1.41. For normal operation this register is set to 00Hex. (2 32 Subcarrier Frequency Register = ) - 1 f SCF SUBCARRIER PHASE REGISTER fCLK FPH7 FPH6 FPH5 FPH4 FPH3 FPH2 FPH1 FPH0 Figure 63. Subcarrier Phase Register Example: NTSC Mode, fCLK = 27 MHz, fSCF = 3.5795454 MHz (2 Subcarrier Frequency Value = 32 ) - 1 3.5795454 106 27 106 Subcarrier Register Value = 21F07C16 Hex Figure 62 shows how the frequency is set up by the four registers. SUBCARRIER FREQUENCY REG 3 SUBCARRIER FREQUENCY REG 2 SUBCARRIER FREQUENCY REG 1 SUBCARRIER FREQUENCY REG 0 FSC31 FSC30 FSC29 FSC28 FSC27 FSC26 FSC25 FSC24 FSC23 FSC22 FSC21 FSC20 FSC19 FSC18 FSC17 FSC16 FSC15 FSC14 FSC13 FSC12 FSC11 FSC10 FSC9 FSC8 FSC7 FSC6 FSC5 FSC4 FSC3 FSC2 FSC1 FSC0 Figure 62. Subcarrier Frequency Registers CLOSED CAPTIONING EVEN FIELD DATA REGISTER 1-0 (CCD15-CCD0) (Address (SR4-SR0) = 11-12H) These 8-bit-wide registers are used to set up the closed captioning extended data bytes on Even Fields. Figure 64 shows how the high and low bytes are set up in the registers. BYTE 1 BYTE 0 CCD15 CCD14 CCD7 CCD6 CCD13 CCD12 CCD11 CCD10 CCD5 CCD4 CCD3 CCD2 CCD9 CCD1 CCD8 CCD0 Figure 64. Closed Captioning Extended Data Register CLOSED CAPTIONING ODD FIELD DATA REGISTER 1-0 (CED15-CED0) (Subaddress (SR4-SR0) = 13-14H) These 8-bit-wide registers are used to set up the closed captioning data bytes on Odd Fields. Figure 65 shows how the high and low bytes are set up in the registers. BYTE 1 BYTE 0 CED15 CED7 CED14 CED6 CED13 CED5 CED12 CED4 CED11 CED3 CED10 CED2 CED9 CED1 CED8 CED0 Figure 65. Closed Captioning Data Register -36- REV. B ADV7190/ADV7191 Bits TC07-TC04 are changed then the falling edge of TTREQ will track that of the rising edge (i.e., the time between the falling and rising edge remains constant). NTSC PEDESTAL/PAL TELETEXT CONTROL REGISTERS 3-0 (PCE15-0, PCO15-0)/(TXE15-0, TXO15-0) (Subaddress (SR4-SR0) = 15-18H) PCLK = clock cycle at 27 MHz. These 8-bit-wide registers are used to enable the NTSC pedestal/ PAL Teletext on a line-by-line basis in the vertical blanking interval for both odd and even fields. Figures 66 and 67 show the four control registers. A Logic 1 in any of the bits of these registers has the effect of turning the Pedestal OFF on the equivalent line when used in NTSC. A Logic 1 in any of the bits of these registers has the effect of turning Teletext ON on the equivalent line when used in PAL. LINE 17 LINE 16 FIELD 1/3 FIELD 1/3 FIELD 2/4 FIELD 2/4 PCO7 PCO6 PCO5 PCO4 PCO3 PCO2 PCO1 LINE 25 LINE 24 LINE 23 LINE 22 LINE 21 LINE 20 PCO12 PCO11 PCO10 PCLK = clock cycle at 27 MHz. TC07 LINE 19 LINE 18 PCO9 PCO8 LINE 15 LINE 14 LINE 13 LINE 12 LINE 11 LINE 10 PCE7 PCE5 PCE4 PCE3 PCE2 PCE1 LINE 25 LINE 24 LINE 23 LINE 22 LINE 21 LINE 20 PCE15 PCE12 PCE13 PCE11 PCE10 LINE 14 LINE 13 FIELD 1/3 TXO7 TXO6 FIELD 2/4 TXO5 TXO4 TXO3 PCE0 PCE9 LINE 8 LINE 7 TXO2 TXO1 TXO0 LINE 19 LINE 18 LINE 17 TXO15 TXO12 TXO14 TXE7 TXE6 TXO13 TXO10 TXO9 TXO8 LINE 12 LINE 11 LINE 10 LINE 9 LINE 8 LINE 7 TXE1 TXE0 TXE5 TXE4 TXE3 TXE2 LINE 19 LINE 18 LINE 17 TXE15 TXE12 TXE14 TXE13 TXE11 TXE10 TC03 TC02 TC01 TC00 TTXREQ FALLING EDGE CONTROL TC03 TC02 TC01 TC00 0 0 0 0 0 PCLK 0 0 0 1 1 PCLK '' '' '' '' '' PCLK 1 1 1 0 14 PCLK 1 1 1 1 15 PCLK CGMS_WSS REGISTER 0 C/W0 (C/W07-C/W00) (Address (SR4-SR0) = 19H) CGMS_WSS register 0 is an 8-bit-wide register. Figure 69 shows the operations under control of this register. C/W0 BIT DESCRIPTION CGMS Data (C/W00-C/W03) LINE 16 LINE 15 TXO11 LINE 22 LINE 21 LINE 20 TC04 Figure 68. Teletext Control Register PCE8 LINE 9 LINE 22 LINE 21 LINE 20 LINE 14 LINE 13 FIELD 2/4 LINE 12 LINE 11 LINE 10 TC05 LINE 19 LINE 18 Figure 66. Pedestal Control Registers FIELD 1/3 TC06 TTXREQ RISING EDGE CONTROL TC07 TC06 TC05 TC04 0 0 0 0 0 PCLK 0 0 0 1 1 PCLK '' '' '' '' '' PCLK 1 1 1 0 14 PCLK 1 1 1 1 15 PCLK PCO0 LINE 17 LINE 16 PCE14 These bits control the position of the rising edge of TTXREQ. It can be programmed from zero clock cycles to a maximum of 15 clock cycles. LINE 15 LINE 14 LINE 13 LINE 12 LINE 11 LINE 10 PCO15 PCO14 PCO13 PCE6 TTXREQ Rising Edge Control (TC04-TC07) These four data bits are the final four bits of CGMS data output stream. Note it is CGMS data ONLY in these bit positions, i.e., WSS data does not share this location. CGMS CRC Check Control (C/W04) LINE 16 LINE 15 TXE9 When this bit is enabled (1), the last six bits of the CGMS data, i.e., the CRC check sequence, is internally calculated by the ADV7190/ADV7191. If this bit is disabled (0), the CRC values in the register are output to the CGMS data stream. TXE8 Figure 67. Teletext Control Registers TELETEXT REQUEST CONTROL REGISTER (TC07-TC00) (Address (SR4-SR0) = 1CH) CGMS Odd Field Control (C/W05) Teletext Control Register is an 8-bit-wide register. See Figure 68. When this bit is set (1), CGMS is enabled for odd fields. Note this is only valid in NTSC mode. TTXREQ Falling Edge Control (TC00-TC03) CGMS Even Field Control (C/W06) These bits control the position of the falling edge of TTXREQ. It can be programmed from zero clock cycles to a maximum of 15 clock cycles. This controls the active window for Teletext data. Increasing this value reduces the amount of Teletext bits below the default of 360. If Bits TC00-TC03 are 00Hex when C/W07 C/W06 WSS CONTROL C/W07 0 1 DISABLE ENABLE C/W05 WSS Control (C/W07) When this bit is set (1), wide screen signalling is enabled. Note this is only valid in PAL mode. C/W04 CGMS ODD FIELD CONTROL C/W05 0 1 CGMS EVEN FIELD CONTROL C/W06 0 1 When this bit is set (1), CGMS is enabled for even fields. Note this is only valid in NTSC mode. DISABLE ENABLE C/W03 C/W02 C/W03 - C/W00 CGMS DATA DISABLE ENABLE CGMS CRC CHECK CONTROL C/W04 0 1 DISABLE ENABLE Figure 69. CGMS_WSS Register 0 REV. B C/W01 -37- C/W00 ADV7190/ADV7191 CGMS_WSS REGISTER 1 C/W1 (C/W17-C/W10) (Address (SR4-SR0) = 1AH) CC07 CC06 CC05 CGMS_WSS Register 1 is an 8-bit-wide register. Figure 70 shows the operations under control of this register. These bits are CGMS data bits only. C/W14 C/W13 CC01 CC00 Figure 72. Contrast Control Register CGMS Data (C/W16-C/W17) C/W15 CC02 CC07 - CC00 These bit locations are shared by CGMS data and WSS data. In NTSC mode these bits are CGMS data. In PAL mode these bits are WSS data. C/W16 CC03 Y SCALE VALUE C/W1 BIT DESCRIPTION CGMS/WSS Data (C/W10-C/W15) C/W17 CC04 C/W12 C/W17 - C/W16 C/W15 - C/W10 CGMS DATA CGMS/WSS DATA C/W11 COLOR CONTROL REGISTERS 2-1 (CC2-CC1) (Address (SR4-SR0) = 1EH-1FH) The color control registers are 8-bit-wide registers used to scale the U and V output levels. Figure 73 shows the operations under control of these registers. C/W10 CC17 CC16 CC15 CC14 CC13 CC12 CC11 CC10 CC22 CC21 CC20 CC17 - CC10 U SCALE VALUE Figure 70. CGMS_WSS Register 1 CC27 CC26 CC25 CGMS_WSS REGISTER 2 C/W1 (C/W27-C/W20) (Address (SR4-SR0) = 1BH) CC27 - CC20 Figure 73. Color Control Registers CC1 BIT DESCRIPTION U Scale Value (CC10-CC17) C/W2 BIT DESCRIPTION CGMS/WSS Data (C/W20-C/W27) These bit locations are shared by CGMS data and WSS data. In NTSC mode these bits are CGMS data. In PAL mode these bits are WSS data. C/W26 C/W25 C/W24 CC23 V SCALE VALUE CGMS_WSS Register 2 is an 8-bit-wide register. Figure 71 shows the operations under control of this register. C/W27 CC24 C/W23 C/W22 C/W21 C/W20 These eight bits represent the value required to scale the U level from 0.0 to 2.0 of its initial level. The value of these eight bits is calculated using the following equation: U Scale Value = Scale Factor 128 Example: Scale Factor = 1.18 C/W27 - C/W20 U Scale Value = 1.18 128 = 151.04 U Scale Value = 151 (rounded to the nearest integer) U Scale Value = 10010111b U Scale Value = 97h CGMS/WSS DATA Figure 71. CGMS_WSS Register 2 CONTRAST CONTROL REGISTER (CC00-CC07) (Address (SR4-SR0) = 1DH) CC2 BIT DESCRIPTION V Scale Value (CC20-CC27) The contrast control register is an 8-bit-wide register used to scale the Y output levels. Figure 72 shows the operation under control of this register. Y Scale Value (CC00-CC07) These eight bits represent the value required to scale the V pixel data from 0.0 to 2.0 of its initial level. The value of these eight bits is calculated using the following equation: These eight bits represent the value required to scale the Y pixel data from 0.0 to 1.5 of its initial level. The value of these eight bits is calculated using the following equation: Example: Y Scale Value = Scale Factor 128 Example: Scale Factor = 1.18 Y Scale Value = 1.18 128 = 151.04 Y Scale Value = 151 (rounded to the nearest integer) Y Scale Value = 10010111b Y Scale Value = 97h V Scale Value = Scale Factor 128 Scale Factor = 1.18 V Scale Value = 1.18 128 = 151.04 V Scale Value = 151 (rounded to the nearest integer) V Scale Value = 10010111b V Scale Value = 97h -38- REV. B ADV7190/ADV7191 HUE ADJUST CONTROL REGISTER (HCR) (Address (SR5-SR0) = 20H) The hue control register is an 8-bit-wide register used to adjust the hue on the composite and chroma outputs. Figure 74 shows the operation under control of this register. HCR7 HCR6 HCR5 HCR4 HCR3 HCR2 HCR1 BRIGHTNESS CONTROL REGISTERS (BCR) (Address (SR5-SR0) = 21H) The brightness register is an 8-bit-wide register which allows brightness control. Figure 75 shows the operation under control of this register. BCR BIT DESCRIPTION Brightness Value (BCR0-BCR6) HCR0 Seven bits of this 8-bit-wide register are used to control the brightness level. The brightness is controlled by adding a programmable setup level onto the scaled Y data. This brightness level can be a positive or negative value. HCR7 - HCR0 HUE ADJUST VALUE Figure 74. Hue Adjust Control Register HCR Bit Description Hue Adjust Value (HCR0-HCR7) These eight bits represent the value required to vary the hue of the video data, i.e., the variance in phase of the subcarrier during active video with respect to the phase of the subcarrier during the colorburst. The ADV7190/ADV7191 provides a range of 22.5 increments of 0.17578125. For normal operation (zero adjustment) this register is set to 80Hex. FFHex and 00Hex represent the upper and lower limit (respectively) of adjustment attainable. Hue Adjust [] = 0.17578125 (HCRd - 128); for positive Hue Adjust Value Example: To adjust the hue by 4 write 97h to the Hue Adjust Control Register: (4/0.17578125) + 128 = 151d* = 97h The programmable brightness level in NTSC without pedestal and PAL are max 15 IRE and min -7.5 IRE, in NTSC with pedestal max 22.5 IRE and min 0 IRE. Table IV. Brightness Control Register Value Setup Level in NTSC with Pedestal Setup Level in NTSC No Pedestal Setup Level in PAL Brightness Control Register Value 22.5 IRE 15 IRE 7.5 IRE 0 IRE 15 IRE 7.5 IRE 0 IRE -7.5 IRE 15 IRE 7.5 IRE 0 IRE -7.5 IRE 1Eh 0Fh 00h 71h NOTE Values in the range from 3F h to 44h might result in an invalid output signal. To adjust the hue by (-4) write 69h to the Hue Adjust Control Register: (-4/0.17578125) + 128 = 10dd* = 69h *Rounded to the nearest integer. EXAMPLE 1. Standard: NTSC with Pedestal. To add +20 IRE brightness level, write 28h into the Brightness Control Register: [Brightness Control Register Value]h = [IRE Value 2.015631]h = [20 2.015631]h = [40.31262]h = 28h 2. Standard: PAL. To add -7 IRE brightness level write 72h into the Brightness Control Register: [|IRE Value| 2.015631] = [7 2.015631] = [14.109417] = 0001110b [0001110] into two's complement = 1110010b = 72h NTSC WITHOUT PEDESTAL +7.5 IRE 100 IRE 0 IRE -7.5 IRE NO SETUP VALUE ADDED BCR7 BCR6 POSITIVE SETUP VALUE ADDED WRITE TO BRIGHTNESS CONTROL REGISTER: 12h BCR5 BCR4 BCR3 NEGATIVE SETUP VALUE ADDED WRITE TO BRIGHTNESS CONTROL REGISTER: 6Eh BCR2 BCR7 BCR6 - BCR0 ZERO MUST BE WRITTEN TO THIS BIT BRIGHTNESS VALUE BCR1 Figure 75. Brightness Control Register REV. B -39- BCR0 ADV7190/ADV7191 Figures 77 and 78 show the various operations under the control of DNR Register 0. SHARPNESS CONTROL REGISTER (PR) (Address (SR5-SR0) = 22H) The sharpness response register is an 8-bit-wide register. The four MSBs are set to 0. The four LSBs are written to in order to select a desired filter response. Figure 76 shows the operation under control of this register. DNR07 DNR06 DNR05 DNR04 DNR03 CORING GAIN DATA 0 0 0 0 0 0 0 0 1 These four bits are used to select the desired luma filter response. The option of twelve responses is given supporting a gain boost/ attenuation in the range -4 dB to +4 dB. The value 12 (1100) written to these four bits corresponds to a boost of +4 dB while the value 0 (0000) corresponds to -4 dB. For normal operation these four bits are set to 6 (0110). 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 DNR01 DNR00 CORING GAIN BORDER DNR DNR DNR DNR 07 06 05 04 PR BIT DESCRIPTION Sharpness Response Value (PR3-PR0) DNR02 DNR DNR DNR DNR 03 02 01 00 0 1/16 2/16 3/16 4/16 5/16 6/16 7/16 8/16 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 0 1/16 2/16 3/16 4/16 5/16 6/16 7/16 8/16 Figure 77. DNR Register 0 in Sharpness Mode Note: Luma Filter Select has to be set to Extended Mode and Sharpness Filter Enable Control has to be enabled for settings in the Sharpness Control Register to take effect (MR02-04 = 100; MR74 = 1). See Internal Filter Response section. DNR07 DNR06 DNR05 DNR04 DNR03 DNR02 DNR01 DNR00 Reserved (PR4-PR7) CORING GAIN DATA A Logic 0 must be written to these bits. CORING GAIN BORDER DNR DNR DNR DNR 07 06 05 04 PR7 PR6 PR5 PR4 PR3 PR2 PR1 PR7 - PR4 PR3 - PR0 ZERO MUST BE WRITTEN TO THESE BITS SHARPNESS RESPONSE VALUE 0 0 0 0 0 0 0 0 1 PR0 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 DNR DNR DNR DNR 03 02 01 00 0 1/8 2/8 3/8 4/8 5/8 6/8 7/8 1 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 0 1/8 2/8 3/8 4/8 5/8 6/8 7/8 1 Figure 76. Sharpness Control Register Figure 78. DNR Register 0 in DNR Mode DNR REGISTERS 2-0 (DNR 2-DNR 0) (Address (SR5-SR0) = 23H-25H) DNR1 BIT DESCRIPTION DNR Threshold (DNR10-DNR15) The Digital Noise Reduction Registers are three 8-bit-wide registers. They are used to control the DNR processing. See Digital Noise Reduction section. These six bits are used to define the threshold value in the range of 0 to 63. The range is an absolute value. Coring Gain Border (DNR00-DNR03) In setting DNR16 to a Logic 1 the block transition area can be defined to consist of four pixels. If this bit is set to a Logic 0 the border transition area consists of two pixels, where one pixel refers to two clock cycles at 27 MHz. Border Area (DNR16) These four bits are assigned to the gain factor applied to border areas. In DNR Mode the range of gain values is 0-1, in increments of 1/8. This factor is applied to the DNR filter output which lies below the set threshold range. The result is then subtracted from the original signal. In DNR Sharpness Mode the range of gain values is 0-0.5 in increments of 1/16. This factor is applied to the DNR filter output which lies above the threshold range. Block Size Control (DNR17) This bit is used to select the size of the data blocks to be processed (see Figure 79). Setting the block size control function to a Logic 1 defines a 16 16 pixel data block, a Logic 0 defines an 8 8 pixel data block, where one pixel refers to two clock cycles at 27 MHz. The result is added to the original signal. 720 485 PIXELS (NTSC) 2 PIXEL BORDER DATA Coring Gain Data (DNR04-DNR07) These four bits are assigned to the gain factor applied to the luma data inside the MPEG pixel block. In DNR Mode the range of gain values is 0-1, in increments of 1/8. This factor is applied to the DNR filter output which lies below the set threshold range. The result is then subtracted from the original signal. In DNR Sharpness Mode the range of gain values is 0-0.5, in increments of 1/16. This factor is applied to the DNR filter output which lies above the threshold range. The result is added to the original signal. -40- 88 88 PIXEL BLOCK PIXEL BLOCK Figure 79. MPEG Block Diagram REV. B ADV7190/ADV7191 DNR17 BLOCK SIZE CONTROL DNR17 0 1 8 PIXELS 16 PIXELS DNR16 DNR15 DNR14 DNR13 DNR11 DNR10 DNR THRESHOLD BORDER AREA DNR DNR DNR DNR DNR DNR 15 14 13 12 11 10 DNR16 0 1 DNR12 2 PIXELS 4 PIXELS 0 0 * * * 1 1 0 0 * * * 1 1 0 0 * * * 1 1 0 0 * * * 1 1 0 0 * * * 1 1 0 1 * * * 0 1 0 1 * * * 62 63 Figure 80. DNR Register 1 DNR2 BIT DESCRIPTION DNR Input Select (DNR20-DNR22) GAIN CONTROL BLOCK SIZE CONTROL BORDER AREA BLOCK OFFSET GAIN CORING GAIN DATA CORING GAIN BORDER DNR MODE Three bits are assigned to select the filter that is applied to the incoming Y data. The signal that lies in the passband of the selected filter is the signal that will be DNR processed. Figure 81 shows the filter responses selectable with this control. NOISE SIGNAL PATH 1 FILTER BLOCK MAGNITUDE - dB 0.8 FILTER OUTPUT < THRESHOLD ? Y DATA INPUT FILTER D FILTER OUTPUT > THRESHOLD FILTER C 0.6 MAIN SIGNAL PATH 0.4 FILTER B DNR SHARPNESS MODE 0.2 FILTER A 0 1 2 3 4 FREQUENCY - MHz 5 6 FILTER BLOCK Figure 81. Filter Response of Filters Selectable FILTER OUTPUT > THRESHOLD ? Y DATA INPUT DNR Mode Control (DNR23) FILTER OUTPUT < THRESHOLD This bit controls the DNR mode selected. A Logic 0 selects DNR mode, a Logic 1 selects DNR Sharpness mode. MAIN SIGNAL PATH DNR works on the principle of defining low amplitude, highfrequency signals as probable noise and subtracting this noise from the original signal. DNR OUT GAIN CONTROL BLOCK SIZE CONTROL BORDER AREA BLOCK OFFSET GAIN CORING GAIN DATA CORING GAIN BORDER NOISE SIGNAL PATH 0 SUBTRACT SIGNAL IN THRESHOLD RANGE FROM ORIGINAL SIGNAL ADD SIGNAL ABOVE THRESHOLD RANGE TO ORIGINAL SIGNAL DNR OUT Figure 82. Block Diagram for DNR Mode and DNR Sharpness Mode In DNR mode, it is possible to subtract a fraction of the signal that lies below the set threshold, assumed to be noise, from the original signal. The threshold is set in DNR Register 1. Block Offset (DNR24-DNR27) When DNR Sharpness mode is enabled it is possible to add a fraction of the signal that lies above the set threshold to the original signal, since this data is assumed to be valid data and not noise. The overall effect being that the signal will be boosted (similar to using Extended SSAF Filter). Four bits are assigned to this control which allows a shift of the data block of 15 pixels maximum. Consider the coring gain positions fixed. The block offset shifts the data in steps of one pixel such that the border coring gain factors can be applied at the same position regardless of variations in input timing of the data. APPLY DATA CORING GAIN DNR27 - DNR24 = 01 HEX APPLY BORDER CORING GAIN O X X X X X X O O X X X X X X O O X X X X X X O O X X X X X X O O X X X X X X O O X X X X X X O OFFSET CAUSED BY VARIATIONS IN INPUT TIMING Figure 83. DNR27-DNR24, Block Offset Control REV. B -41- ADV7190/ADV7191 DNR27 DNR26 DNR25 DNR24 DNR23 DNR MODE CONTROL BLOCK OFFSET DNR DNR DNR DNR 27 26 25 24 0 0 0 * * * 1 1 1 0 0 0 * * * 1 1 1 0 0 1 * * * 0 1 1 0 1 0 * * * 1 0 1 DNR22 0 PIXEL OFFSET 1 PIXEL OFFSET 2 PIXEL OFFSET * * * 13 PIXEL OFFSET 14 PIXEL OFFSET 15 PIXEL OFFSET DNR21 DNR20 DNR INPUT SELECT DNR DNR DNR 22 21 20 DNR23 0 DNR MODE 1 DNR SHARPNESS MODE 0 0 0 1 0 1 1 0 1 0 1 0 FILTER A FILTER B FILTER C FILTER D Figure 84. DNR Register 2 y96 = [(80/224)0.5 224] + 16 = 150* y128 = [(112/224)0.5 224] + 16 = 174* GAMMA CORRECTION REGISTERS 0-13 (GAMMA CORRECTION 0-13) (Address (SR5-SR0) = 26H-32H) *Rounded to the nearest integer. The Gamma Correction Registers are fourteen 8-bit-wide registers. They are used to program the gamma correction Curves A and B. The above will result in a gamma curve shown below, assuming a ramp signal as an input. Gamma correction is applied to compensate for the nonlinear relationship between signal input and brightness level output (as perceived on the CRT). It can also be applied wherever nonlinear processing is used. 300 GAMMA-CORRECTED AMPLITUDE GAMMA CORRECTION BLOCK OUTPUT TO A RAMP INPUT Gamma correction uses the function: SignalOUT = where (SignalIN )g g = gamma power factor Gamma correction is performed on the luma data only. The user has the choice to use two different curves, Curve A, or Curve B. At any one time only one of these curves can be used. SIGNAL OUTPUT 200 250 0.5 150 200 150 100 100 SIGNAL INPUT 50 0 0 50 100 150 LOCATION 200 250 Figure 85. Signal Input (Ramp) and Signal Output for Gamma 0.5 Values at Location 0, 16, 240, and 255 are fixed and cannot be changed. 300 GAMMA CORRECTION BLOCK OUTPUT TO A RAMP INPUT FOR VARIOUS GAMMA VALUES GAMMA-CORRECTED AMPLITUDE For the length of 16 to 240 the gamma correction curve has to be calculated as below: y = xg where y = gamma corrected output x = linear input signal g = gamma power factor To program the gamma correction registers, the seven values for y have to be calculated using the following formula: g yn = [x(n-16) /(240-16) ] (240-16) + 16 where Example: 300 50 The response of the curve is programmed at seven predefined locations. In changing the values at these locations the gamma curve can be modified. Between these points linear interpolation is used to generate intermediate values. Considering the curve to have a total length of 256 points, the seven locations are at: 32, 64, 96, 128, 160, 192, and 224. x(n-16) = Value for x along x-axis yn = Value for y along the y-axis, which has to be written into the gamma correction register n = 32, 64, 96, 128, 160, 192, or 224 250 250 SIGNAL OUTPUTS 200 0.3 0.5 150 T PU IN L A 1.5 GN SI 100 1.8 50 0 0 50 100 150 LOCATION 200 250 Figure 86. Signal Input (Ramp) and Selectable Gamma Output Curves The gamma curves shown above are examples only, any userdefined curve is acceptable in the range of 16-240. y32 = [(16/224)0.5 224] + 16 = 76* y64 = [(48/224)0.5 224] + 16 =120* -42- REV. B ADV7190/ADV7191 BRIGHTNESS DETECT REGISTER (Address (SR5-SR0) = 34H) The Brightness Detect Register is an 8-bit-wide register used only to read back data in order to monitor the brightness/darkness of the incoming video data on a field-by-field basis. The brightness information is read from the I2C and based on this information, the color controls or the gamma correction controls may be adjusted. The luma data is monitored in the active video area only. The average brightness I2C register is updated on the falling edge of every VSYNC signal. OCR BIT DESCRIPTION Reserved (OCR00) A Logic 0 must be written to this bit. CLKOUT Pin Control (OCR01) This bit enables the CLKOUT pin when set to 1 and, therefore, outputs a 54 MHz clock generated by the internal PLL. The PLL and 4 Oversampling have to be enabled for this control to take effect (MR61 = 0; MR16 = 1). Reserved (OCR02-03) A Logic 0 must be written to these bits. Reserved (OCR04-06) OUTPUT CLOCK REGISTER (OCR 9-0) A Logic 1 must be written to these bits. (Address (SR4-SR0) = 35H) The Output Clock Register is an 8-bit-wide register. Figure Reserved (OCR07) A Logic 0 must be written to this bit. 87 shows the various operations under the control of this register. OCR07 OCR06 OCR05 OCR04 OCR03 OCR02 OCR01 OCR00 OCR07 OCR06 - OCR04 OCR03 - OCR02 OCR00 ZERO MUST BE WRITTEN TO THIS BIT ONE MUST BE WRITTEN TO THESE BITS ZERO MUST BE WRITTEN TO THESE BITS ZERO MUST BE WRITTEN TO THIS BIT CLKOUT PIN CONTROL OCR01 0 ENSABLED 1 DISABLED Figure 87. Output Clock Register (OCR) REV. B -43- ADV7190/ADV7191 APPENDIX 1 BOARD DESIGN AND LAYOUT CONSIDERATIONS The ADV7190/ADV7191 is a highly integrated circuit containing both precision analog and high-speed digital circuitry. It has been designed to minimize interference effects on the integrity of the analog circuitry by the high-speed digital circuitry. It is imperative that these same design and layout techniques be applied to the system-level design such that high-speed, accurate performance is achieved. The Recommended Analog Circuit Layout shows the analog interface between the device and monitor. The layout should be optimized for lowest noise on the ADV7190/ ADV7191 power and ground lines by shielding the digital inputs and providing good decoupling. The lead length between groups of VAA and AGND pins should by minimized in order to minimize inductive ringing. Ground Planes The ground plane should encompass all ADV7190/ADV7191 ground pins, voltage reference circuitry, power supply bypass circuitry for the ADV7190/ADV7191, the analog output traces, and all the digital signal traces leading up to the ADV7190/ADV7191. to reduce the lead inductance. Best performance is obtained with 0.1 mF ceramic capacitor decoupling. Each group of VAA pins on the ADV7190/ADV7191 must have at least one 0.1 mF decoupling capacitor to AGND. These capacitors should be placed as close as possible to the device. It is important to note that while the ADV7190/ADV7191 contains circuitry to reject power supply noise, this rejection decreases with frequency. If a high-frequency switching power supply is used, the designer should pay close attention to reducing power supply noise and consider using a three-terminal voltage regulator for supplying power to the analog power plane. Digital Signal Interconnect The digital inputs to the ADV7190/ADV7191 should be isolated as much as possible from the analog outputs and other analog circuitry. Also, these input signals should not overlay the analog power plane. Due to the high clock rates involved, long clock lines to the ADV7190/ADV7191 should be avoided to reduce noise pickup. Power Planes The ADV7190/ADV7191 and any associated analog circuitry should have its own power plane, referred to as the analog power plane (VAA). This power plane should be connected to the regular PCB power plane (VCC) at a single point through a ferrite bead. This bead should be located within three inches of the ADV7190/ADV7191. The metallization gap separating device power plane and board power plane should be as narrow as possible to minimize the obstruction to the flow of heat from the device into the general board. Any active termination resistors for the digital inputs should be connected to the regular PCB power plane (VCC), and not the analog power plane. Analog Signal Interconnect The ADV7190/ADV7191 should be located as close as possible to the output connectors to minimize noise pickup and reflections due to impedance mismatch. The video output signals should overlay the ground plane, and not the analog power plane, to maximize the high frequency power supply rejection. The PCB power plane should provide power to all digital logic on the PC board, and the analog power plane should provide power to all ADV7190/ADV7191 power pins and voltage reference circuitry. Plane-to-plane noise coupling can be reduced by ensuring that portions of the regular PCB power and ground planes do not overlay portions of the analog power plane, unless they can be arranged so the plane-to-plane noise is common-mode. Digital inputs, especially pixel data inputs and clocking signals should never overlay any of the analog signal circuitry and should be kept as far away as possible. For best performance, the outputs should each have a 300 W load resistor connected to AGND. These resistors should be placed as close as possible to the ADV7190/ADV7191 so as to minimize reflections. The ADV7190/ADV7191 should have no inputs left floating. Any inputs that are not required should be tied to ground. Supply Decoupling For optimum performance, bypass capacitors should be installed using the shortest leads possible, consistent with reliable operation, -44- REV. B ADV7190/ADV7191 APPENDIX 1 BOARD LAYOUT POWER SUPPLY DECOUPLING FOR EACH POWER SUPPLY GROUP 5V (VAA) 10nF 5V (VAA) 0.1F 17, 25, 29, 38, 43, 54, 63 5V (VAA) VAA 0.1F COMP1 DAC A COMP2 300 VREF DAC B P0 ADV7190/ ADV7191 P15 300 DAC C VSO/CLAMP DAC D 300 PAL_NTSC SCRESET/RTC/TR DAC E 300 HSYNC VSYNC 5V (VAA) DAC F 5V (VAA) 300 BLANK 4.7k CONNECT DAC OUTPUTS TO OPTIONAL OUTPUT FILTER AND BUFFER CIRCUIT 300 CSO_HSO UNUSED INPUTS SHOULD BE GROUNDED 100 4.7F 6.3V 5V (VAA) 27MHz CLOCK (SAME CLOCK AS USED BY MPEG2 DECODER) 0.1F 4.7k RESET SCL TTX SDA 100 TTXREQ RSET2 CLKIN RSET1 ALSB 5k CLKOUT AGND 1.2k 1.2k 18, 24, 26, 33, 39, 42, 55, 64 Figure 88. Recommended Analog Circuit Layout REV. B -45- 5V (VAA) 5k MPU BUS ADV7190/ADV7191 APPENDIX 2 CLOSED CAPTIONING FCC Code of Federal Regulations (CFR) 47 Section 15.119 and EIA608 describe the closed captioning information for Lines 21 and 284. The ADV7190/ADV7191 supports closed captioning conforming to the standard television synchronizing waveform for color transmission. Closed captioning is transmitted during the blanked active line time of Line 21 of the odd fields and Line 284 of even fields. Closed captioning consists of a seven-cycle sinusoidal burst that is frequency and phase locked to the caption data. After the clock run-in signal, the blanking level is held for two data bits and is followed by a Logic Level 1 start bit. Sixteen bits of data follow the start bit. These consist of two eight-bit bytes, seven data bits, and one odd parity bit. The data for these bytes is stored in Closed Captioning Data Registers 0 and 1. The ADV7190/ADV7191 also supports the extended closed captioning operation that is active during even fields and is encoded on Scan Line 284. The data for this operation is stored in Closed Captioning Extended Data Registers 0 and 1. All clock run-in signals and timing to support closed captioning on Lines 21 and 284 are generated automatically by the ADV7190/ ADV7191 All pixel inputs are ignored during Lines 21 and 284 if closed captioning is enabled. 10.5 0.25s The ADV7190/ADV7191 uses a single buffering method. This means that the closed captioning buffer is only one byte deep, therefore there will be no frame delay in outputting the closed captioning data, unlike other two byte deep buffering systems. The data must be loaded one line before (Line 20 or Line 283) it is outputted on Line 21 and Line 284. A typical implementation of this method is to use VSYNC to interrupt a microprocessor, which in turn, will load the new data (two bytes) every field. If no new data is required for transmission, 0s must be inserted in both data registers, this is called NULLING. It is also important to load control codes, all of which are double bytes on Line 21, or a TV will not recognize them. If there is a message like Hello World, which has an odd number of characters, it is important to pad it out to even in order to get end of caption 2-byte control code to land in the same field. 12.91s 7 CYCLES OF 0.5035 MHz (CLOCK RUN-IN) TWO 7-BIT + PARITY ASCII CHARACTERS (DATA) S T A R T 50 IRE P A R I T Y D0-D6 BYTE 0 D0-D6 P A R I T Y BYTE 1 40 IRE REFERENCE COLOR BURST (9 CYCLES) FREQUENCY = FSC = 3.579545MHz AMPLITUDE = 40 IRE 10.003s 33.764s 27.382s Figure 89. Closed Captioning Waveform (NTSC) -46- REV. B ADV7190/ADV7191 APPENDIX 3 COPY GENERATION MANAGEMENT SYSTEM (CGMS) Function of CGMS Bits The ADV7190/ADV7191 supports Copy Generation Management System (CGMS) conforming to the standard. CGMS data is transmitted on Line 20 of the odd fields and Line 283 of even fields. Bits C/W05 and C/W06 control whether or not CGMS data is outputed on ODD and EVEN fields. CGMS data can only be transmitted when the ADV7190/ADV7191 is configured in NTSC mode. The CGMS data is 20 bits long, the function of each of these bits is as shown below. The CGMS data is preceded by a reference pulse of the same amplitude and duration as a CGMS bit, see Figure 94. These bits are output from the configuration registers in the following order: C/W00 = C16, C/W01 = C17, C/W02 = C18, C/W03 = C19, C/W10 = C8, C/W11 = C9, C/W12 = C10, C/W13 = C11, C/W14 = C12, C/W15 = C13, C/W16 = C14, C/W17 = C15, C/W20 = C0, C/W21 = C1, C/W22 = C2, C/W23 = C3, C/W24 = C4, C/W25 = C5, C/W26 = C6, C/W27 = C7. If the bit C/W04 is set to a Logic 1, the last six bits C19-C14 which comprise the 6-bit CRC check sequence are calculated automatically on the ADV7190/ADV7191 based on the lower 14 bits (C0-C13) of the data in the data registers and output with the remaining 14-bits to form the complete 20-bits of the CGMS data. The calculation of the CRC sequence is based on the polynomial X6 + X + 1 with a preset value of 111111. If C/W04 is set to a Logic 0, all 20 bits (C0-C19) are output directly from the CGMS registers (no CRC calculated, must be calculated by the user). Word 0 - 6 Bits Word 1 - 4 Bits Word 2 - 6 Bits CRC - 6 Bits CRC Polynomial = X6 + X + 1 (Preset to 111111) WORD 0 B1 B2 B3 Aspect Ratio Display Format Undefined WORD 0 B4, B5, B6 1 16:9 Letterbox Identification Information About Video and Other Signals (e.g., Audio) WORD 1 B7, B8, B9, B10 Identification Signal Incidental to Word 0 WORD 2 B11, B12, B13, B14 Identification Signal and Information Incidental to Word 0 100 IRE CRC SEQUENCE REF 70 IRE C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 0 IRE 49.1s 0.5s -40 IRE 11.2s 2.235s 20ns Figure 90. CGMS Waveform Diagram REV. B -47- 0 4:3 Normal ADV7190/ADV7191 APPENDIX 4 WIDE SCREEN SIGNALING (WSS) The ADV7190/ADV7191 supports Wide Screen Signaling (WSS) conforming to the standard. WSS data is transmitted on Line 23. WSS data can only be transmitted when the ADV7190/ADV7191 is configured in PAL mode. The WSS data is 14-bits long, the function of each of these bits is as shown below. The WSS data is preceded by a run-in sequence and a Start Code, see Figure 91. The bits are output from the configuration registers in the following order: C/W20 = W0, C/W21 = W1, C/W22 = W2, C/W23 = W3, C/W24 = W4, C/W25 = W5, C/W26 = W6, C/W27 = W7, C/W10 = W8, C/W11 = W9, C/W12 = W10, C/W13 = W11, C/W14 = W12, C/W15 = W13. If the bit C/W07 is set to a Logic 1, it enables the WSS data to be transmitted on Line 23. The latter portion of Line 23 (42.5 ms from the falling edge of HSYNC) is available for the insertion of video. Function of CGMS Bits Bit 0-Bit 2 Bit 3 B0, 0 1 0 1 0 1 0 1 B1, 0 0 1 1 0 0 1 1 Aspect Ratio/Format/Position Is Odd Parity Check of Bit 0-Bit 2 B2, 0 0 0 0 1 1 1 1 B3 1 0 0 1 0 1 1 0 Aspect Ratio 4:3 14:9 14:9 16:9 16:9 >16:9 14:9 16:9 Format Full Format Letterbox Letterbox Letterbox Letterbox Letterbox Full Format Nonapplicable Position Nonapplicable Center Top Center Top Center Center Nonapplicable B4 0 1 Camera Mode Film Mode B5 0 1 Standard Coding Motion Adaptive Color Plus B6 0 1 No Helper Modulated Helper B7 RESERVED B9 0 1 0 1 B10 0 0 1 1 No Open Subtitles Subtitles in Active Image Area Subtitles Out of Active Image Area RESERVED B11 0 No Surround Sound Information 1 Surround Sound Mode B12 RESERVED B13 RESERVED 500mV W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 RUN-IN SEQUENCE START CODE ACTIVE VIDEO 11.0s 38.4s 42.5s Figure 91. WSS Waveform Diagram -48- REV. B ADV7190/ADV7191 APPENDIX 5 TELETEXT INSERTION Time, tPD, is the time needed by the ADV7190/ADV7191 to interpolate input data on TTX and insert it onto the CVBS or Y outputs, such that it appears tSYNTTXOUT = 10.2 ms after the leading edge of the horizontal signal. Time, TTXDEL, is the pipeline delay time by the source that is gated by the TTXREQ signal in order to deliver TTX data. Teletext Protocol With the programmability that is offered with TTXREQ signal on the Rising/Falling edges, the TTX data is always inserted at the correct position of 10.2 ms after the leading edge of Horizontal Sync pulse, which enables a source interface with variable pipeline delays. Thus 37 TTX bits correspond to 144 clocks (27 MHz), each bit has a width of almost four clock cycles. The ADV7190/ADV7191 uses an internal sequencer and variable phase interpolation filter to minimize the phase jitter and thus generate a bandlimited signal which can be output on the CVBS and Y outputs. The width of the TTXREQ signal must always be maintained so it allows the insertion of 360 (in order to comply with the Teletext Standard PAL-WST) teletext bits at a text data rate of 6.9375 Mbits/s. This is achieved by setting TC03-TC00 to 0. The insertion window is not open if the Teletext Enable bit (MR33) is set to 0. At the TTX input the bit duration scheme repeats after every 37 TTX bits or 144 clock cycles. The protocol requires that TTX Bits 10, 19, 28, 37 are carried by three clock cycles, all other bits by four clock cycles. After 37 TTX bits, the next bits with three clock cycles are Bits 47, 56, 65, and 74. This scheme holds for all following cycles of 37 TTX bits, until all 360 TTX bits are completed. All teletext lines are implemented in the same way. Individual control of teletext lines are controlled by Teletext Setup Registers. The relationship between the TTX bit clock (6.9375 MHz) and the system CLOCK (27 MHz) for 50 Hz is given as follows: (27 MHz/4) = 6.75 MHz (6.9375 106/6.75 106 = 1.027777 45 BYTES (360 BITS) - PAL TELETEXT VBI LINE ADDRESS & DATA RUN-IN CLOCK Figure 92. Teletext VBI Line tSYNTTXOUT CVBS/Y tPD tPD HSYNC 10.2s TTXDATA TTXDEL TTXREQ PROGRAMMABLE PULSE EDGES TTXST tSYNTTXOUT = 10.2s tPD = PIPELINE DELAY THROUGH ADV7190/ADV7191 TTXDEL = TTXREQ TO TTX (PROGRAMMABLE RANGE = 4 BITS [0-15 CLOCK CYCLES]) Figure 93. Teletext Functionality Diagram REV. B -49- ADV7190/ADV7191 APPENDIX 6 OPTIONAL OUTPUT FILTER If an output filter is required for the CVBS, YUV, Chroma, and RGB outputs of the ADV7190/ADV7191, the filter in Figure 94 can be used in 2 Oversampling Mode. Figure 96 shows a filter that can be used in 4 Oversampling Mode. The plot of the filter characteristics are shown in Figures 95 and 97. An output filter is not required if the outputs of the ADV7190/ADV7191 are connected to most analog monitors, or TVs; however, if the output signals are applied to a system where sampling is used (e.g., Digital TVs), a filter is required to prevent aliasing. 22H 10H FILTER I/P FILTER O/P 600 68pF 27pF 600 Figure 96. Output Filter for 4 Oversampling Mode 0 22H 22H 6.8H -7 FILTER O/P FILTER I/P 22pF 68pF 56pF 600 MAGNITUDE - dB 600 -14 Figure 94. Output Filter for 2 Oversampling Mode -21 -28 -35 -42 -49 0 -56 -63 -10 -70 100k MAGNITUDE - dB -20 1.0M 10M FREQUENCY - Hz 100M Figure 97. Output Filter Plot for 4 Oversampling Filter -30 -40 -50 -60 -70 100k 1.0M 100M 10M FREQUENCY - Hz Figure 95. Output Filter Plot for 2 Oversampling Filter 2 FILTER REQUIREMENTS 4 FILTER REQUIREMENTS 6.75 13.5 27.0 FREQUENCY - MHz 40.5 54.0 Figure 98. Output Filter Requirements in 4 Oversampling Mode -50- REV. B ADV7190/ADV7191 APPENDIX 7 DAC BUFFERING External buffering is needed on the ADV7190/ADV7191 DAC outputs. The configuration in Figure 99 is recommended. +VCC 4 When calculating absolute output full-scale current and voltage use the following equations: INPUT/ OPTIONAL FILTER O/P VOUT = IOUT RLOAD VAA ADV7190/ADV7191 1.2k PIXEL PORT DAC A OUTPUT BUFFER CVBS DAC B OUTPUT BUFFER LUMA DAC C OUTPUT BUFFER CHROMA DAC D OUTPUT BUFFER G DAC E OUTPUT BUFFER B DAC F OUTPUT BUFFER R DIGITAL CORE RSET2 1.2k Figure 99. Output DAC Buffering Configuration REV. B 1 OUTPUT TO TV MONITOR 2 Figure 100. Recommended DAC Output Buffer Using an Op Amp K = 4.2146 constant, VREF = 1.235 V RSET1 AD8051 -VCC IOUT = (VREF K)/RSET VREF 3 5 -51- ADV7190/ADV7191 APPENDIX 8 RECOMMENDED REGISTER VALUES The ADV7190/ADV7191 registers can be set depending on the user standard required. The following examples give the various register formats for several video standards. PAL B, D, G, H, I (FSC = 4.43361875 MHz) NTSC (FSC = 3.5795454 MHz) Address 00Hex 01Hex 02Hex 03Hex 04Hex 05Hex 06Hex 07Hex 08Hex 09Hex 0AHex 0BHex 0CHex 0DHex 0EHex 0FHex 10Hex 11Hex 12Hex 13Hex 14Hex 15Hex 16Hex 17Hex 18Hex 19Hex 1AHex 1BHex 1CHex 1DHex 1EHex 1FHex 20Hex 21Hex 22Hex 23Hex 24Hex 25Hex 35Hex Mode Register 0 Mode Register 1 Mode Register 2 Mode Register 3 Mode Register 4 Mode Register 5 Mode Register 6 Mode Register 7 Mode Register 8 Mode Register 9 Timing Register 0 Timing Register 1 Subcarrier Frequency Register 0 Subcarrier Frequency Register 1 Subcarrier Frequency Register 2 Subcarrier Frequency Register 3 Subcarrier Phase Register Closed Captioning Ext Register 0 Closed Captioning Ext Register 1 Closed Captioning Register 0 Closed Captioning Register 1 Pedestal Control Register 0 Pedestal Control Register 1 Pedestal Control Register 2 Pedestal Control Register 3 CGMS_WSS Reg 0 CGMS_WSS Reg 1 CGMS_WSS Reg 2 Teletext Control Register Contrast Control Register Color Control Register 1 Color Control Register 2 Hue Control Register Brightness Control Register Sharpness Response Register DNR 0 DNR 1 DNR 2 Output Clock Register Data Address 10Hex 3FHex 62Hex 00Hex 00Hex 00Hex 00Hex 00Hex 04Hex 00Hex 08Hex 00Hex 16Hex 7CHex F0Hex 21Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 44Hex 20Hex 00Hex 70Hex 00Hex 01Hex 02Hex 03Hex 04Hex 05Hex 06Hex 07Hex 08Hex 09Hex 0AHex 0BHex 0CHex 0DHex 0EHex 0FHex 10Hex 11Hex 12Hex 13Hex 14Hex 15Hex 16Hex 17Hex 18Hex 19Hex 1AHex 1BHex 1CHex 1DHex 1EHex 1FHex 20Hex 21Hex 22Hex 23Hex 24Hex 25Hex 35Hex -52- Data Mode Register 0 Mode Register 1 Mode Register 2 Mode Register 3 Mode Register 4 Mode Register 5 Mode Register 6 Mode Register 7 Mode Register 8 Mode Register 9 Timing Register 0 Timing Register 1 Subcarrier Frequency Register 0 Subcarrier Frequency Register 1 Subcarrier Frequency Register 2 Subcarrier Frequency Register 3 Subcarrier Phase Register Closed Captioning Ext Register 0 Closed Captioning Ext Register 1 Closed Captioning Register 0 Closed Captioning Register 1 Pedestal Control Register 0 Pedestal Control Register 1 Pedestal Control Register 2 Pedestal Control Register 3 CGMS_WSS Reg 0 CGMS_WSS Reg 1 CGMS_WSS Reg 2 Teletext Control Register Contrast Control Register Color Control Register 1 Color Control Register 2 Hue Control Register Brightness Control Register Sharpness Response Register DNR0 DNR1 DNR2 Output Clock Register 11Hex 3FHex 62Hex 00Hex 00Hex 00Hex 00Hex 00Hex 04Hex 00Hex 08Hex 00Hex CBHex 8AHex 09Hex 2AHex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 44Hex 20Hex 00Hex 70Hex REV. B ADV7190/ADV7191 PAL 60 (FSC = 4.43361875 MHz) PAL N (FSC = 4.43361875 MHz) Address 00Hex 01Hex 02Hex 03Hex 04Hex 05Hex 06Hex 07Hex 08Hex 09Hex 0AHex 0BHex 0CHex 0DHex 0EHex 0FHex 10Hex 11Hex 12Hex 13Hex 14Hex 15Hex 16Hex 17Hex 18Hex 19Hex 1AHex 1BHex 1CHex 1DHex 1EHex 1FHex 20Hex 21Hex 22Hex 23Hex 24Hex 25Hex 35Hex REV. B Mode Register 0 Mode Register 1 Mode Register 2 Mode Register 3 Mode Register 4 Mode Register 5 Mode Register 6 Mode Register 7 Mode Register 8 Mode Register 9 Timing Register 0 Timing Register 1 Subcarrier Frequency Register 0 Subcarrier Frequency Register 1 Subcarrier Frequency Register 2 Subcarrier Frequency Register 3 Subcarrier Phase Register Closed Captioning Ext Register 0 Closed Captioning Ext Register 1 Closed Captioning Register 0 Closed Captioning Register 1 Pedestal Control Register 0 Pedestal Control Register 1 Pedestal Control Register 2 Pedestal Control Register 3 CGMS_WSS Reg 0 CGMS_WSS Reg 1 CGMS_WSS Reg 2 Teletext Control Register Contrast Control Register Color Control Register 1 Color Control Register 2 Hue Control Register Brightness Control Register Sharpness Response Register DNR 0 DNR 1 DNR 2 Output Clock Register Data Address 13Hex 3FHex 62Hex 00Hex 00Hex 00Hex 00Hex 00Hex 04Hex 00Hex 08Hex 00Hex CBHex 8AHex 09Hex 2AHex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 44Hex 20Hex 00Hex 70Hex 00Hex 01Hex 02Hex 03Hex 04Hex 05Hex 06Hex 07Hex 08Hex 09Hex 0AHex 0BHex 0CHex 0DHex 0EHex 0FHex 10Hex 11Hex 12Hex 13Hex 14Hex 15Hex 16Hex 17Hex 18Hex 19Hex 1AHex 1BHex 1CHex 1DHex 1EHex 1FHex 20Hex 21Hex 22Hex 23Hex 24Hex 25Hex 35Hex -53- Data Mode Register 0 Mode Register 1 Mode Register 2 Mode Register 3 Mode Register 4 Mode Register 5 Mode Register 6 Mode Register 7 Mode Register 8 Mode Register 9 Timing Register 0 Timing Register 1 Subcarrier Frequency Register 0 Subcarrier Frequency Register 1 Subcarrier Frequency Register 2 Subcarrier Frequency Register 3 Subcarrier Phase Register Closed Captioning Ext Register 0 Closed Captioning Ext Register 1 Closed Captioning Register 0 Closed Captioning Register 1 Pedestal Control Register 0 Pedestal Control Register 1 Pedestal Control Register 2 Pedestal Control Register 3 CGMS_WSS Reg 0 CGMS_WSS Reg 1 CGMS_WSS Reg 2 Teletext Control Register Contrast Control Register Color Control Register 1 Color Control Register 2 Hue Control Register Brightness Control Register Sharpness Response Register DNR 0 DNR 1 DNR 2 Output Clock Register 12Hex 3FHex 62Hex 00Hex 00Hex 00Hex 00Hex 00Hex 04Hex 00Hex 08Hex 00Hex CBHex 8AHex 09Hex 2AHex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 44Hex 20Hex 00Hex 70Hex ADV7190/ADV7191 PAL M (FSC = 3.57561149 MHz) Address 00Hex 01Hex 02Hex 03Hex 04Hex 05Hex 06Hex 07Hex 08Hex 09Hex 0AHex 0BHex 0CHex 0DHex EHex 0FHex 10Hex 11Hex 12Hex 13Hex Mode Register 0 Mode Register 1 Mode Register 2 Mode Register 3 Mode Register 4 Mode Register 5 Mode Register 6 Mode Register 7 Mode Register 8 Mode Register 9 Timing Register 0 Timing Register 1 Subcarrier Frequency Register 0 Subcarrier Frequency Register 1 Subcarrier Frequency Register 2 Subcarrier Frequency Register 3 Subcarrier Phase Register Closed Captioning Ext Register 0 Closed Captioning Ext Register 1 Closed Captioning Register 0 Data Address 12Hex 3FHex 62Hex 00Hex 00Hex 00Hex 00Hex 00Hex 04Hex 00Hex 08Hex 00Hex A3Hex EFHex E6Hex 21Hex 00Hex 00Hex 00Hex 00Hex 14Hex 15Hex 16Hex 17Hex 18Hex 19Hex 1AHex 1BHex 1CHex 1DHex 1EHex 1FHex 20Hex 21Hex 22Hex 23Hex 24Hex 25Hex 35Hex -54- Data Closed Captioning Register 1 Pedestal Control Register 0 Pedestal Control Register 1 Pedestal Control Register 2 Pedestal Control Register 3 CGMS_WSS Reg 0 CGMS_WSS Reg 1 CGMS_WSS Reg 2 Teletext Control Register Contrast Control Register Color Control Register 1 Color Control Register 2 Hue Control Register Brightness Control Register Sharpness Response Register DNR 0 DNR 1 DNR 2 Output Clock Register 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 44Hex 20Hex 00Hex 70Hex REV. B ADV7190/ADV7191 POWER-ON RESET REGISTER VALUES POWER-ON RESET REG VALUES (PAL_NTSC = 0, NTSC Selected) Address 00Hex 01Hex 02Hex 03Hex 04Hex 05Hex 06Hex 07Hex 08Hex 09Hex 0AHex 0BHex 0CHex 0DHex 0EHex 0FHex 10Hex 11Hex 12Hex 13Hex 14Hex 15Hex 16Hex 17Hex 18Hex 19Hex 1AHex 1BHex 1CHex 1DHex 1EHex 1FHex 20Hex 21Hex 22Hex 23Hex 24Hex 25Hex 26Hex 27Hex 28Hex 29Hex 2AHex 2BHex 2CHex 2DHex 2EHex 2FHex 30Hex 31Hex 32Hex 33Hex 34Hex 35Hex REV. B Mode Register 0 Mode Register 1 Mode Register 2 Mode Register 3 Mode Register 4 Mode Register 5 Mode Register 6 Mode Register 7 Mode Register 8 Mode Register 9 Timing Register 0 Timing Register 1 Subcarrier Frequency Register 0 Subcarrier Frequency Register 1 Subcarrier Frequency Register 2 Subcarrier Frequency Register 3 Subcarrier Phase Register Closed Captioning Ext Register 0 Closed Captioning Ext Register 1 Closed Captioning Register 0 Closed Captioning Register 1 Pedestal Control Register 0 Pedestal Control Register 1 Pedestal Control Register 2 Pedestal Control Register 3 CGMS_WSS Reg 0 CGMS_WSS Reg 1 CGMS_WSS Reg 2 Teletext Control Register Contrast Control Register Color Control Register 1 Color Control Register 2 Hue Control Register Brightness Control Register Sharpness Response Register DNR 0 DNR 1 DNR 2 Gamma 0 Gamma 1 Gamma 2 Gamma 3 Gamma 4 Gamma 5 Gamma 6 Gamma 7 Gamma 8 Gamma 9 Gamma 10 Gamma 11 Gamma 12 Gamma 13 Brightness Detect Register Output Clock Register POWER-ON RESET REG VALUES (PAL_NTSC = 1, PAL Selected) Data Address 00Hex 07Hex 08Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 08Hex 00Hex 16Hex 7CHex F0Hex 21Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex xxHex xxHex xxHex xxHex xxHex xxHex xxHex xxHex xxHex xxHex xxHex xxHex xxHex xxHex xxHex 72Hex 00Hex 01Hex 02Hex 03Hex 04Hex 05Hex 06Hex 07Hex 08Hex 09Hex 0AHex 0BHex 0CHex 0DHex 0EHex 0FHex 10Hex 11Hex 12Hex 13Hex 14Hex 15Hex 16Hex 17Hex 18Hex 19Hex 1AHex 1BHex 1CHex 1DHex 1EHex 1FHex 20Hex 21Hex 22Hex 23Hex 24Hex 25Hex 26Hex 27Hex 28Hex 29Hex 2AHex 2BHex 2CHex 2DHex 2EHex 2FHex 30Hex 31Hex 32Hex 33Hex 34Hex 35Hex -55- Data Mode Register 0 Mode Register 1 Mode Register 2 Mode Register 3 Mode Register 4 Mode Register 5 Mode Register 6 Mode Register 7 Mode Register 8 Mode Register 9 Timing Register 0 Timing Register 1 Subcarrier Frequency Register 0 Subcarrier Frequency Register 1 Subcarrier Frequency Register 2 Subcarrier Frequency Register 3 Subcarrier Phase Register Closed Captioning Ext Register 0 Closed Captioning Ext Register 1 Closed Captioning Register 0 Closed Captioning Register 1 Pedestal Control Register 0 Pedestal Control Register 1 Pedestal Control Register 2 Pedestal Control Register 3 CGMS_WSS Reg 0 CGMS_WSS Reg 1 CGMS_WSS Reg 2 Teletext Control Register Contrast Control Register Color Control Register 1 Color Control Register 2 Hue Control Register Brightness Control Register Sharpness Response Register DNR 0 DNR 1 DNR 2 Gamma 0 Gamma 1 Gamma 2 Gamma 3 Gamma 4 Gamma 5 Gamma 6 Gamma 7 Gamma 8 Gamma 9 Gamma 10 Gamma 11 Gamma 12 Gamma 13 Brightness Detect Register Output Clock Register 01Hex 07Hex 08Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 08Hex 00Hex CBHex 8AHex 09Hex 2AHex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex xxHex xxHex xxHex xxHex xxHex xxHex xxHex xxHex xxHex xxHex xxHex xxHex xxHex xxHex xxHex 72Hex ADV7190/ADV7191 APPENDIX 9 NTSC WAVEFORMS (WITH PEDESTAL) 130.8 IRE PEAK COMPOSITE 1268.1mV 100 IRE REF WHITE 1048.4mV 714.2mV 387.6mV 334.2mV 7.5 IRE 0 IRE BLACK LEVEL BLANK LEVEL -40 IRE SYNC LEVEL 48.3mV REF WHITE 1048.4mV Figure 101. NTSC Composite Video Levels 100 IRE 714.2mV 7.5 IRE 0 IRE BLACK LEVEL BLANK LEVEL -40 IRE SYNC LEVEL 387.6mV 334.2mV 48.3mV Figure 102. NTSC Luma Video Levels PEAK CHROMA 963.8mV 629.7mV (p-p) 286mV (p-p) BLANK/BLACK LEVEL 650mV PEAK CHROMA 335.2mV 0mV Figure 103. NTSC Chroma Video Levels 100 IRE REF WHITE 1052.2mV 720.8mV 7.5 IRE 0 IRE BLACK LEVEL BLANK LEVEL 387.5mV 331.4mV -40 IRE SYNC LEVEL 45.9mV Figure 104. NTSC RGB Video Levels -56- REV. B ADV7190/ADV7191 NTSC WAVEFORMS (WITHOUT PEDESTAL) 130.8 IRE PEAK COMPOSITE 1289.8mV 100 IRE REF WHITE 1052.2mV 714.2mV 0 IRE BLANK/BLACK LEVEL 338mV -40 IRE SYNC LEVEL 52.1mV Figure 105. NTSC Composite Video Levels 100 IRE REF WHITE 1052.2mV 714.2mV 0 IRE BLANK/BLACK LEVEL SYNC LEVEL -40 IRE 338mV 52.1mV Figure 106. NTSC Luma Video Levels PEAK CHROMA 978mV 694.9mV (p-p) 307mV (p-p) 650mV BLANK/BLACK LEVEL 283mV PEAK CHROMA 0mV Figure 107. NTSC Chroma Video Levels 100 IRE REF WHITE 1052.2mV 715.7mV BLANK/BLACK LEVEL 0 IRE SYNC LEVEL -40 IRE Figure 108. NTSC RGB Video Levels REV. B -57- 336.5mV 51mV ADV7190/ADV7191 PAL WAVEFORMS PEAK COMPOSITE 1284.2mV 1047.1mV REF WHITE 696.4mV 350.7mV BLANK/BLACK LEVEL 50.8mV SYNC LEVEL Figure 109. PAL Composite Video Levels REF WHITE 1047mV 696.4mV BLANK/BLACK LEVEL 350.7mV SYNC LEVEL 50.8mV Figure 110. PAL Luma Video Levels PEAK CHROMA 990mV 672mV (p-p) 300mV (p-p) 650mV BLANK/BLACK LEVEL 318mV PEAK CHROMA 0mV Figure 111. PAL Chroma Video Levels REF WHITE 1050.2mV 698.4mV BLANK/BLACK LEVEL 351.8mV SYNC LEVEL 51mV Figure 112. PAL RGB Video Levels -58- REV. B ADV7190/ADV7191 BLACK BLUE RED MAGENTA GREEN CYAN YELLOW WHITE BLACK BLUE RED MAGENTA GREEN CYAN WHITE YELLOW UV WAVEFORMS 505mV 505mV 423mV 334mV 171mV BETACAM LEVEL BETACAM LEVEL 82mV 0mV 0mV 0mV 0mV -82mV 171mV 334mV -423mV -505mV 505mV BLACK BLUE RED MAGENTA GREEN CYAN YELLOW WHITE Figure 116. NTSC 100% Color Bars, No Pedestal V Levels BLACK BLUE RED MAGENTA GREEN CYAN WHITE YELLOW Figure 113. NTSC 100% Color Bars, No Pedestal U Levels 467mV 467mV 391mV 309mV 158mV BETACAM LEVEL BETACAM LEVEL 76mV 0mV 0mV 0mV 0mV -76mV -158mV -309mV -391mV -467mV -467mV 350mV BLACK BLUE 350mV 293mV 232mV SMPTE LEVEL RED MAGENTA GREEN CYAN WHITE BLACK BLUE RED MAGENTA GREEN CYAN YELLOW WHITE YELLOW Figure 117. NTSC 100% Color Bars with Pedestal V Levels Figure 114. NTSC 100% Color Bars with Pedestal U Levels SMPTE LEVEL 118mV 57mV 0mV 0mV 0mV 0mV -57mV -118mV -232mV -293mV -350mV -350mV Figure 118. PAL 100% Color Bars V Levels Figure 115. PAL 100% Color Bars U Levels REV. B -59- ADV7190/ADV7191 OUTPUT WAVEFORMS 0.6 VOLTS 0.4 0.2 0.0 0.2 L608 0.0 10.0 20.0 30.0 40.0 50.0 60.0 MICROSECONDS NOISE REDUCTION: 0.00 dB APL = 39.1% 625 LINE PAL NO FILTERING PRECISION MODE OFF SYNCHRONOUS SLOW CLAMP TO 0.00 V AT 6.72 s SOUND-IN-SYNC OFF SYNC = SOURCE FRAMES SELECTED: 1 2 3 4 Figure 119. 100/0/75/0 PAL Color Bars VOLTS 0.5 0.0 L575 0.0 10.0 APL NEEDS SYNC = SOURCE! 625 LINE PAL NO FILTERING 20.0 30.0 40.0 50.0 MICROSECONDS PRECISION MODE OFF SYNCHRONOUS SLOW CLAMP TO 0.00 V AT 6.72 s 60.0 70.0 SOUND-IN-SYNC OFF SYNC = A FRAMES SELECTED: 1 Figure 120. 100/0/75/0 PAL Color Bars Luminance -60- REV. B ADV7190/ADV7191 VOLTS 0.5 0.0 -0.5 L575 10.0 20.0 30.0 40.0 MICROSECONDS APL NEEDS SYNC = SOURCE! 625 LINE PAL NO FILTERING 50.0 60.0 NO BRUCH SIGNAL PRECISION MODE OFF SYNCHRONOUS SLOW CLAMP TO 0.00 V AT 6.72 s SOUND-IN-SYNC OFF SYNC = A FRAMES SELECTED: 1 Figure 121. 100/0/75/0 PAL Color Bars Chrominance 100.0 VOLTS IRE:FLT 0.5 50.0 0.0 0.0 -50.0 0.0 F1 L76 10.0 20.0 30.0 40.0 MICROSECONDS APL = 44.6% 525 LINE NTSC 50.0 PRECISION MODE OFF NO FILTERING SYNCHRONOUS SLOW CLAMP TO 0.00 V AT 6.72 s SYNC = A FRAMES SELECTED: 1 2 Figure 122. 100/7.5/75/7.5 NTSC Color Bars REV. B 60.0 -61- ADV7190/ADV7191 100.0 0.6 0.2 50.0 IRE:FLT VOLTS 0.4 0.0 0.0 -0.2 F2 L238 10.0 20.0 30.0 40.0 MICROSECONDS NOISE REDUCTION: 15.05dB APL = 44.7% 525 LINE NTSC NO FILTERING 50.0 PRECISION MODE OFF SYNCHRONOUS SLOW CLAMP TO 0.00 V AT 6.72 s 60.0 SYNC = SOURCE FRAMES SELECTED: 1 2 Figure 123. 100/7.5/75/7.5 NTSC Color Bars Luminance 0.4 50.0 0.0 IRE:FLT VOLTS 0.2 -0.2 -50.0 -0.4 F1 L76 0.0 10.0 20.0 30.0 40.0 MICROSECONDS NOISE REDUCTION: 15.05dB APL NEEDS SYNC = SOURCE! 525 LINE NTSC 50.0 60.0 PRECISION MODE OFF NO FILTERING SYNCHRONOUS SLOW CLAMP TO 0.00 V AT 6.72 s SYNC = B FRAMES SELECTED: 1 2 Figure 124. 100/7.5/75/7.5 NTSC Color Bars Chrominance -62- REV. B ADV7190/ADV7191 PARADE SMPTE/EBU PAL mV Y(A) mV Pb(B) mV Pr(C) 700 250 250 600 200 200 500 150 150 400 100 100 300 50 50 200 0 0 -50 -50 0 -100 -100 -100 -150 -150 -200 -200 -250 -250 100 -200 -300 Figure 125. PAL YUV Parade Plot mV GREEN (A) mV 700 700 600 600 500 500 400 400 300 300 200 200 100 100 0 BLUE (B) mV RED (C) 700 600 500 400 300 200 100 0 0 -100 -100 -100 -200 -200 -200 -300 -300 -300 Figure 126. PAL RGB Waveforms REV. B -63- ADV7190/ADV7191 VIDEO MEASUREMENT PLOTS COLOR BAR (NTSC) FIELD = 1 LINE = 21 WFM FCC COLOR BAR LUMINANCE LEVEL (IRE) 99.6 69.0 55.9 48.1 36.3 28.3 15.7 7.7 GRAY YELLOW CYAN GREEN MAGENTA RED BLUE BLACK 100 50 0 CHROMINANCE LEVEL (IRE) 0.0 62.1 87.6 81.8 81.8 87.8 62.1 0.0 GRAY YELLOW CYAN GREEN MAGENTA RED BLUE BLACK 167.3 283.8 240.9 60.80 103.6 347.1 YELLOW CYAN GREEN MAGENTA RED BLUE 100 50 0 CHROMINANCE PHASE (DEGREE) 400 200 0 GRAY AVERAGE 32 BLACK 32 Figure 127. NTSC Color Bar Measurement COLOR BAR (PAL) LINE = 570 WFM COLOR BAR LUMINANCE LEVEL (mV) 1000 695.7 464.8 366.6 305.7 217.3 156.4 61.2 -0.4 GRAY YELLOW CYAN GREEN MAGENTA RED BLUE BLACK 500 0 CHROMINANCE LEVEL (mV) 1000 0.0 474.4 669.1 623.5 624.7 669.6 475.2 0.0 GRAY YELLOW CYAN GREEN MAGENTA RED BLUE BLACK 166.7 283.3 240.4 60.4 103.2 346.7 YELLOW CYAN GREEN MAGENTA RED BLUE 500 0 CHROMINANCE PHASE (DEGREE) 400 300 200 100 0 GRAY AVERAGE 32 BLACK 32 Figure 128. PAL Color Bar Measurement -64- REV. B ADV7190/ADV7191 DG DP (NTSC) MOD 5 STEP WFM DG DP (PAL) FIELD = 1, LINE = 21 2.5 0.21 0.02 0.07 0.27 MIN = 0.00, MAX = 0.32, pk-pk = 0.32 DIIFFERENTIAL GAIN (PERCENT) MIN = 0.00, MAX = 0.27, p-p/MAX = 0.27 DIIFFERENTIAL GAIN (PERCENT) 0.00 MOD 5 STEP WFM LINE = 570 0.08 2.5 0.00 0.30 0.15 0.24 0.32 0.26 1st 2nd 3rd 4th 5th 6th 1.5 1.5 0.5 0.5 -0.5 -0.5 -1.5 -1.5 -2.5 1st 2nd 3rd 4th 2.5 0.10 6th -2.5 0.12 0.15 0.13 MIN = 0.00, MAX = 0.16, pk-pk = 0.16 DIFFERENTIAL PHASE (DEGREE) MIN = 0.00, MAX = 0.20, pk-pk = 0.20 DIFFERENTIAL PHASE (DEGREE) 0.00 5th 0.10 2.5 0.00 0.09 1st 2nd 0.13 0.16 3rd 4th 0.12 0.14 5th 6th 1.5 1.5 0.5 0.5 -0.5 -0.5 -1.5 -1.5 -2.5 1st 2nd AVERAGE 32 3rd 4th 5th 6th -2.5 AVERAGE 32 32 Figure 129. NTSC DG DP Measurement LUMINANCE NONLINEARITY (NTSC) Figure 131. PAL DG DP Measurement LUMINANCE NONLINEARITY (PAL) MOD 5 STEP WFM pk-pk = 0.4 LUMINANCE NONLINEARITY (PERCENT) 111 WFM MOD 5 STEP LINE = 570 FIELD = 2, LINE = 77 99.90 32 99.90 99.60 100.0 99.90 113 109 111 107 109 105 107 103 105 101 103 99 pk-pk = 0.8 LUMINANCE NONLINEARITY (PERCENT) 99.6 99.9 100.0 2nd 3rd 99.6 99.9 101 97 99 95 97 93 95 91 93 89 1st AVERAGE 32 2nd 3rd 4th 91 5th 1st 32 AVERAGE 32 Figure 130. NTSC Luminance Nonlinearity REV. B 4th 32 Figure 132. PAL Luminance Nonlinearity -65- 5th ADV7190/ADV7191 CHROMINANCE NONLINEARITY(NTSC) WFM FIELD = 2, LINE = 217 CHROMINANCE AMPLITUDE ERROR (PERCENT) 0.5 CHROMINANCE NONLINEARITY(PAL) WFM LINE = 572 CHROMINANCE AMPLITUDE ERROR (PERCENT) NTSC-7 COMBINATION REF = 40IRE PACKET 0.0 -0.3 10 10 0 0 -10 -10 20IRE 40IRE 80IRE CHROMINANCE PHASE ERROR (DEGREE) -0.0 5 REF = 40IRE PACKET 0.0 0 -5 -5 40IRE 80IRE CHROMINANCE LUMINANCE INTERMODULATION (PERCENT OF 714mV) 0.0 0.1 REF = 420mV PACKET 0.6 0.0 -0.4 140mV 420mV 700mV CHROMINANCE PHASE ERROR (DEGREE) 0.0 0 20IRE MOD 3 STEP REF = 420mV PACKET -0.3 0.0 -0.3 140mV 420mV 700mV CHROMINANCE LUMINANCE INTERMODULATION (PERCENT OF 700mV) 0.1 0.0 0.0 0.1 420mV 700mV 0.2 0.2 0.1 0.0 0.0 -0.1 -0.2 -0.2 20IRE AVERAGE 32 40IRE 80IRE 140mV AVERAGE 32 32 Figure 133. NTSC Chrominance Nonlinearity CHROMINANCE AM/PM (NTSC) FIELD = 2, LINE = 217 WFM Figure 135. PAL Chrominance Nonlinearity RED FIELD CHROMINANCE AM/PM (PAL) LINE = 572 BANDWIDTH 10kHz TO 100kHz -86.5dB RMS -90 -85 -80 -75 PM NOISE -95 -70 AM NOISE -65 -60 dB RMS -85 APPROPRIATE -80 -75 -70 -84.2dB RMS -95 -82.7dB RMS -90 WFM BANDWIDTH 10kHz TO 100kHz AM NOISE -95 32 -90 -85 -80 -75 PM NOISE -65 -60 dB RMS -65 -60 dB RMS -65 -60 dB RMS -80.5dB RMS -95 (0dB = 714mV p-p WITH AGC FOR 100% CHROMINANCE LEVEL) -70 -90 -85 -80 -75 -70 (0dB = 700mV p-p WITH AGC FOR 100% CHROMINANCE LEVEL) Figure 134. NTSC Chrominance AM/PM Figure 136. PAL Chrominance AM/PM -66- REV. B ADV7190/ADV7191 NOISE SPECTRUM (NTSC) PEDESTAL WFM NOISE SPECTRUM (PAL) FIELD = 2, LINE = 223 PEDESTAL WFM LINE = 511 NOISE LEVEL = -79.7dB RMS AMPLITUDE (0dB = 714mV p-p) NOISE LEVEL = -79.1dB RMS AMPLITUDE (0dB = 714mV p-p) BANDWIDTH 10kHz TO FULL BANDWIDTH 10kHz TO FULL 20 0 0 -20 -20 -40 -40 -60 -60 -80 -80 -100 -100 1 2 3 MHz 4 5 6 1 4 5 6 7 Figure 139. PAL Noise Spectrum: Pedestal RAMP WFM NOISE SPECTRUM (PAL) FIELD = 2, LINE = 217 RAMP WFM LINE = 572 NOISE LEVEL = -63.1dB RMS AMPLITUDE (0dB = 714mV p-p) NOISE LEVEL = -62.3dB RMS AMPLITUDE (0dB = 700mV p-p) BANDWIDTH 100kHz TO FULL (TILT NULL) BANDWIDTH 100kHz TO FULL (TILT NULL) 0 0 -10 -10 -20 -20 -30 -30 -40 -40 -50 -50 -60 -60 -70 -70 -80 -80 -90 -90 -100 -100 1 2 3 MHz 4 5 6 1 2 3 4 5 6 MHz Figure 138. NTSC Noise Spectrum: Ramp REV. B 3 MHz Figure 137. NTSC Noise Spectrum: Pedestal NOISE SPECTRUM (NTSC) 2 Figure 140. PAL Noise Spectrum: Ramp -67- 7 ADV7190/ADV7191 APPENDIX 10 VECTOR PLOTS V APL = 39.6% SYSTEM LINE L608 ANGLE (DEG) 0.0 GAIN 1.000 0.000dB 625 LINE PAL BURST FROM SOURCE DISPLAY +V AND -V cy R g M g 75% 100% YI b U yl B G Cy m g r SOUND IN SYNC OFF Figure 141. PAL Vector Plot R-Y APL = 45.1% SYSTEM LINE L76F1 ANGLE (DEG) 0.0 GAIN 1.000 0.000dB 525 LINE NTSC BURST FROM SOURCE cy I R M g YI Q b 100% B-Y 75% B G Cy -Q -I SETUP 7.5% Figure 142. NTSC Vector Plot -68- REV. B ADV7190/ADV7191 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 64-Lead Quad Flatpack [LQFP] (ST-64) 0.640 (16.25) 0.630 (16.00) SQ 0.620 (15.75) 0.063 (1.60) MAX 0.030 (0.75) 0.024 (0.60) 0.018 (0.45) SEATING PLANE 64 49 1 48 12 TYP 0.555 (14.10) 0.551 (14.00) SQ 0.547 (13.90) TOP VIEW (PINS DOWN) 0.004 (0.102) MAX LEAD COPLANARITY 10 6 2 16 33 32 17 0.031 (0.80) BSC 0.007 (0.17) MAX 7 0 REV. B -69- 0.014 (0.35) 0.057 (1.45) 0.055 (1.40) 0.053 (1.35) ADV7190/ADV7191 Revision History Location Page 5/02--Data Sheet changed from REV. A to REV. B. Added Figure 46b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Changes to Color Bar Control (MR46) section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 -70- REV. B -71- -72- PRINTED IN U.S.A. C00230-0-5/02(B)