September 2013 Doc ID 022515 Rev 2 1/43
1
VND5E050ACJ-E
VND5E050ACK-E
Double channel high-side driver with analog current sense
for automotive applications
Features
■
General
– Inrush current active management by
power limitation
– Very low standby current
– 3.0 V CMOS compatible inputs
– Optimized electromagnetic emissions
– Very low electromagnetic susceptibility
– Compliance with European directive
2002/95/EC
– Very low current sense leakage
■
Diagnostic functions
– Proportional load current sense
– High current sense precision for wide
currents range
– Current sense disable
– Off-state open load detection
– Output short to V
CC
detection
– Overload and short to ground (power
limitation) indication
– Therm al sh utdow n indica tion
■
Protections
– Undervoltage shutdown
– Overvoltage clamp
– Load current limitation
– Self limiting of fast thermal transients
– Protection against loss of ground and loss
of V
CC
– Overtemperature shutdown with auto
restart (thermal shutdown)
– Reverse battery protected
– Electros tatic disc harge protection
Applications
■
All types of resistive, inductive and capacitive
loads
■
Suitable as LED driver
Description
The VND5E050ACJ-E and VND5E050ACK-E are
double channel high-side drivers manufactured
using ST propr ie tary VIPowe r
®
M0-5 technology
and housed in PowerSSO-12 and PowerSSO-24
packages. The devices are designed to drive 12 V
automotive grounded loads, and to provide
protection and diagnostics. They also implement
a 3 V and 5 V CMOS-compatible interface for use
with any microcontroller.
The devices integrate advanced protective
functions such as load current limitation, inrush
and overload active management by power
limitation, overtemperature shut-off with
auto-restart and overvoltage active clamp. A
dedicated analog current sense pin is associated
with every output channel providing enhanced
diagnostic functions including fast detection of
overload and short-circuit to ground through
power limitation indication, overtemperature
indication, short-circuit to V
CC
diagnosis on-state
and off-state open-load detection.
The current sensing and diagnostic feedback of
the whole device can be disabled by pulling the
CS_DIS pin high to share the external sense
resistor with similar devices.
Max transient supply voltage V
CC
41 V
Operati ng vol tage range V
CC
4.5 to 28 V
Max On-state resistance (per ch.) R
ON
50 mΩ
Current lim itation (typ) I
LIMH
27 A
Off-st a te sup ply current I
S
2 µA
(1)
1. Typical value with all loads connected.
PowerSSO-24
PowerSSO-12
www.st.com
Contents VND5E050ACJ-E, VND5E050ACK-E
2/43 Doc ID 022515 Rev 2
Contents
1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3 Elect rical char acteristi c s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.5 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.1 GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 24
3.1.1 Solution 1: resistor in the ground line (RGND only) . . . . . . . . . . . . . . . . 24
3.1.2 Solution 2: diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . . . 25
3.2 Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.3 MCU I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.4 Curre nt sense and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.4.1 Short to VCC and off-state open-load detection . . . . . . . . . . . . . . . . . . 26
3.5 Maximum demagneti zation energy (VCC = 13.5V) . . . . . . . . . . . . . . . . . 28
4 Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.1 PowerSSO-12 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.2 PowerSSO-24 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.1 ECOPACK
®
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.2 PowerSSO-12 package informat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.3 PowerSSO-24 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.4 PowerSSO-12 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.5 PowerSSO-24 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
6 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
VND5E050ACJ-E, VND5E050ACK-E List of tables
Doc ID 022515 Rev 2 3/43
List of tables
Table 1. Pin function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 2. Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 4. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 5. Power section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 6. Switching (VCC = 13V; Tj = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 7. Logic inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 8. Protections and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 9. Current sense (8 V < V
CC
< 18 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 10. Open load detection (8V<V
CC
<18V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 11. Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 12. Electrical transient requirements (part 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 13. Electrical transient requirements (part 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 14. Electrical transient requirements (part 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 15. Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 16. Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 17. PowerSSO-12 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 18. PowerSSO-24 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 19. Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 20. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
List of figures VND5E050ACJ-E, VND5E050ACK-E
4/43 Doc ID 022515 Rev 2
List of figures
Figure 1. Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4. Current sense delay characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 5. Open load off-state delay timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 6. Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 7. Delay response time between rising edge of output current and rising edge of current
sense (CS enabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 8. Output voltage drop limitation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 9. I
OUT
/I
SENSE
vs I
OUT
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 10. Maximum current sense ratio drift vs load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 11. Normal operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 12. Overload or short to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 13. Intermittent overload. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 14. Off-state open load with external circuitry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 15. Short to V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 16. T
J
evolution in overload or short to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 17. Off-state output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 18. High level input current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 19. Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 20. Input low level. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 21. Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 22. Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 23. On-state resistance vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 24. On-state resistance vs VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 25. Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 26. Turn-on voltage slope. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 27. ILIMH vs Tcase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 28. Turn-off voltage slope. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 29. CS_DIS high level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 30. CS_DIS clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 31. CS_DIS low level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 32. Application schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 33. Current sense and diagnostic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 34. Maximum turn-off current versus inductance (for each channel) . . . . . . . . . . . . . . . . . . . . 28
Figure 35. PowerSSO-12 PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 36. Rthj-amb Vs. PCB copper area in open box free air condition (one channel ON) . . . . . . . 29
Figure 37. PowerSSO-12 thermal impedance junction ambient single pulse (one channel ON). . . . . 30
Figure 38. Thermal fitting model of a double channel HSD in PowerSSO-12
. . . . . . . . . . . . . . . . . . . 30
Figure 39. PowerSSO-24 PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 40. Rthj-amb vs PCB copper area in open box free air condition (one channel ON) . . . . . . . . 32
Figure 41. PowerSSO-24 thermal impedance junction ambient single pulse (one channel ON). . . . . 33
Figure 42. Thermal fitting model of a double channel HSD in PowerSSO-24
. . . . . . . . . . . . . . . . . . . 33
Figure 43. PowerSSO-12 package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 44. PowerSSO-24 package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 45. PowerSSO-12 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 46. PowerSSO-12 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 47. PowerSS0-24
tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
VND5E050ACJ-E, VND5E050ACK-E List of figures
Doc ID 022515 Rev 2 5/43
Figure 48. PowerSSO-24 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Block diagram and pin description VND5E050ACJ-E, VND5E050ACK-E
6/43 Doc ID 022515 Rev 2
1 Block diagram and pin description
Figure 1. Block diagram
Table 1. Pin function
Name Function
V
CC
Battery connec ti on.
OUTPUT
1,2
Power output.
GND Ground con nec tio n. Mu st be rev ers e batt ery protec ted by an external diode/ res ist or
network.
INPUT
1,2
Voltage controlled input pin with hysteresis, CMOS compatible. Controls output
switch state.
CURRENT
SENSE
1,2
Analog current sense pin, delivers a current proportional to the load current.
CS_DIS Active high CMOS compatible pin, to disable the current sense pin.
V
CC
CH 1
Control & Diagnosti c 1
LOGIC
DRIVER
V
ON
Limitation
Current
Limitation
Power
Clamp
OFF St at e
Open load
Over
temp.
Undervoltage
V
SENSEH
Current
Sense
CH 2
OVERLOAD PROTECTION
(ACTIVE POWER LIMITATION)
IN1
IN2
CS1
CS2
CS_
DIS
GND
OUT2
OUT1
Signal Clamp
CON TROL & DI AGNO ST IC
Channels 2
VND5E050ACJ-E, VND5E0 50ACK -E Block diagram and pin descr ipt ion
Doc ID 022515 Rev 2 7/43
Figure 2. Configuration diagram (top view)
Table 2. Suggested connections for unused and not connected pin s
Connection / pin Current sense N.C. Output Input CS_DIS
Floating Not allowed X X X X
To ground Through 1 KΩ
resistor XThrough 22 KΩ
resistor Through 10 KΩ
resistor Through 10 KΩ
resistor
PowerSSO-12
TAB = V
cc
V
cc
OUTPUT2
OUTPUT1
OUTPUT1
V
cc
OUTPUT2
12
11
10
9
8
7
1
2
3
4
5
6
CS_DIS
GND
INPUT1
CURRENT SENSE1
INPUT2
CURRENT SENSE2
N.C.
INPUT1
GND
V
CC
N.C.
INPUT2
CS_DIS.
V
CC
CURRENT SENSE1
N.C.
N.C.
CURRENT SENSE2
OUTPUT2
OUTPUT2
OUTPUT2
OUTPUT2
OUTPUT2
OUTPUT2
OUTPUT1
OUTPUT1
OUTPUT1
OUTPUT1
OUTPUT1
OUTPUT1
PowerSSO-24
T AB = V
CC
Electrical specifications VND5E050ACJ-E, VND5E050ACK-E
8/43 Doc ID 022515 Rev 2
2 Electrical specifications
Figure 3. Current and voltage conventions
Note: V
Fn
= V
OUTn
- V
CC
during reverse battery condition.
2.1 Absolute maximum ratings
Stressing the device above the rating listed in the “Absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to the conditions in the table for extended periods
may affect device reliability.
I
S
I
GND
V
CC
V
CC
V
SENSE2
OUTPUT1 I
OUT1
CURRENT I
SENSE1
INPUT1
I
IN1
V
IN2
V
OUT2
GND
CS_DIS
I
CSD
V
CSD
INPUT2
I
IN2
V
IN1
SENSE1
OUTPUT2 I
OUT2
CURRENT I
SENSE2
SENSE2
V
SENSE1
V
OUT1
V
Fn
Table 3. Absolute maximum ratings
Symbol Parameter Value Unit
V
CC
DC supply voltage 41 V
-V
CC
Reverse DC supply voltage 0.3 V
-I
GND
DC reverse ground pin current 200 mA
I
OUT
DC output current Internally limited A
-I
OUT
Reverse DC output current 20 A
I
IN
DC input current -1 to 10 mA
I
CSD
DC current sense disable input current -1 to 10 mA
-I
CSENSE
DC reverse CS pin current 200 mA
V
CSENSE
Current sense maximum voltage V
CC
- 41 to
+V
CC
V
VND5E050ACJ-E, VND5E0 50ACK -E Electrical specif ica tions
Doc ID 022515 Rev 2 9/43
2.2 Thermal data
2.3 Electrical characteristics
Values specified in this section are for 8 V<V
CC
<28V; -40°C<T
j
<150 °C, unless otherwise
stated.
E
MAX
Maximum switching energy (single pulse)
(L = 3mH; R
L
=0Ω; V
bat
=13.5V; T
jstart
=150°C; I
OUT
104 mJ
V
ESD
Electrostatic discharge
(human body model: R=1.5KΩ; C=100pF)
– Input
– Current sen se
– CS_DIS
–Output
–V
CC
4000
2000
4000
5000
5000
V
V
V
V
V
V
ESD
Charge devic e mod el (CDM-AEC -Q10 0-011 ) 750 V
T
j
Junction operating temperature -40 to 150 °C
T
stg
Storage temperature -55 to 150 °C
Table 3. Absolute maximum ratings (continued)
Symbol Parameter Value Unit
Table 4. Thermal data
Symbol Parameter Max value Unit
PowerSSO-12 PowerSSO-24
R
thj-case
Thermal res is t anc e jun cti on- cas e (with
one channel ON) 2.7 2.7 °C/W
R
thj-amb
Thermal res is t anc e jun cti on- am bie nt See Figure 36 See Figure 40 °C/W
Table 5. Power section
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
CC
Operating supply
voltage 4.5 13 28 V
V
USD
Undervoltage shutdown 3.5 4.5 V
V
USDhyst
Undervoltage shutdown
hysteresis 0.5 V
R
ON
On-state resistance
(1)
I
OUT
= 2 A; T
j
= 25°C 50
mΩI
OUT
= 2 A; T
j
= 150°C 100
I
OUT
= 2A; V
CC
=5V; T
j
=25°C 65
V
clamp
Clamp voltage I
S
=20mA 41 46 52 V
Electrical specifications VND5E050ACJ-E, VND5E050ACK-E
10/43 Doc ID 022515 Rev 2
I
S
Supply current
Off-state; V
CC
=13V; T
j
=25°C;
V
IN
=V
OUT
=V
SENSE
=V
CSD
=0V 2
(2)
5
(2)
µA
On-st a te; V
CC
=13V; V
IN
=5V;
I
OUT
=0A 36mA
I
L(off1)
Off-state output current
(1)
V
IN
=V
OUT
= 0V; V
CC
=13V;
T
j
=25°C 00.013 µA
V
IN
=V
OUT
=0V; V
CC
=13V;
T
j
= 125°C 05
V
F
Output - V
CC
diode
voltage
(1)
-I
OUT
= 4 A; T
j
= 150°C 0.7 V
1. For each channel.
2. PowerMOS leakage included.
Table 6. Switching (V
CC
= 13V; T
j
= 25°C)
Symbol Parameter Test conditions Min. Typ. Max. Unit
t
d(on)
Turn-on delay time R
L
=6.5Ω (see Figure 6)— 20 — µs
t
d(off)
Turn-off delay time R
L
=6.5Ω (see Figure 6)— 45 — µs
dV
OUT
/dt
(on)
Turn-on voltage slope R
L
=6.5Ω—See
Figure 26 —V/µs
dV
OUT
/dt
(off)
Turn-off voltage slope R
L
=6.5Ω—See
Figure 28 —V/µs
W
ON
Switching energy
losses duri ng t
won
R
L
=6.5Ω (see Figure 6) — 0.15 — mJ
W
OFF
Switching energy
losses duri ng t
woff
R
L
=6.5Ω (see Figure 6)— 0.3 —mJ
Table 7. Logic inputs
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
IL
Input low level voltage 0.9 V
I
IL
Low level input cu rrent V
IN
=0.9V 1 µA
V
IH
Input high level voltage 2.1 V
I
IH
High level input current V
IN
=2.1V 10 µA
V
I(hyst)
Input hysteresis voltage 0.25 V
V
ICL
Input clamp voltage I
IN
=1mA 5.5 7 V
I
IN
=-1mA -0.7
V
CSDL
CS_DIS low level voltage 0.9 V
I
CSDL
Low level CS_DIS current V
CSD
=0.9V 1 µA
V
CSDH
CS_DIS high level voltage 2.1 V
Table 5. Power section (continued)
Symbol Parameter Test conditions Min. Typ. Max. Unit
VND5E050ACJ-E, VND5E0 50ACK -E Electrical specif ica tions
Doc ID 022515 Rev 2 11/43
I
CSDH
High level CS_DIS current V
CSD
=2.1V 10 µA
V
CSD(hyst)
CS_DIS hysteresis voltage 0.25 V
V
CSCL
CS_ DIS clamp voltage I
CSD
=1mA 5.5 7 V
I
CSD
=-1mA -0.7
Table 8. Protec tions and diagnostics
(1)
1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related
diagnostic signals must be used together with a proper software strategy. If the device is subjected to
abnormal conditions, this software must limit the duration and number of activation cycles.
Symbol Parameter Test conditions Min. Typ. Max. Unit
I
limH
DC short circuit current V
CC
= 13 V 19 27 38 A
5V<V
CC
< 28V 38 A
I
limL
Short circuit curr ent
during thermal cycling V
CC
=13V;
T
R
<T
j
<T
TSD
7A
T
TSD
Shutdown temperature 150 175 200 °C
T
R
Reset temperature T
RS
+1 T
RS
+5 °C
T
RS
Thermal reset of status 135 °C
T
HYST
Thermal hysteresis
(T
TSD
-T
R
)
7°C
V
DEMAG
Turn-off output voltage
clamp I
OUT
= 2 A; V
IN
=0;
L=6mH V
CC
-41 V
CC
-46 V
CC
-52 V
V
ON
Output voltage drop
limitation
I
OUT
= 0.1 A;
T
j
= -40°C...+150°C
(see Figure 8)25 mV
Table 9. Current sense (8 V < V
CC
<18V)
Symbol Parameter Test conditions Min. Typ. Max. Unit
K
0
I
OUT
/I
SENSE
I
OUT
= 0.05 A;
V
SENSE
=0.5V;V
CSD
=0V;
T
j
= -40°C...150°C 1440 2250 3630
K
1
I
OUT
/I
SENSE
I
OUT
= 1 A; V
SENSE
=4V;V
CSD
=0V;
T
j
= -40°C...150°C
T
j
= 25°C...150°C 1740
1750 2070
2070 2820
2562
dK
1
/K
1(1)
Current sens e r atio
drift I
OUT
= 1 A; V
SENSE
=4V; V
CSD
=0V;
T
J
= -40 °C to 150 °C -15 15 %
K
2
I
OUT
/I
SENSE
I
OUT
= 2 A; V
SENSE
=4V;V
CSD
=0V;
T
j
= -40°C...150°C
T
j
= 25°C...150°C 1900
1899 2000
2000 2395
2282
dK
2
/K
2(1)
Current sens e r atio
drift I
OUT
= 2 A; V
SENSE
=4V; V
CSD
=0V;
T
J
= -40 °C to 150 °C -9 9 %
Table 7. Logic inputs (continued)
Symbol Parameter Test conditions Min. Typ. Max. Unit
Electrical specifications VND5E050ACJ-E, VND5E050ACK-E
12/43 Doc ID 022515 Rev 2
K
3
I
OUT
/I
SENSE
I
OUT
= 4 A; V
SENSE
=4V; V
CSD
=0V;
T
j
= -40°C...150°C
T
j
= 25°C...150°C 1969
1950 1990
1990 2210
2153
dK
3
/K
3(1)
Current sens e r atio
drift I
OUT
= 4 A; V
SENSE
=4V; V
CSD
=0V;
T
J
= -40 °C to 150 °C -6 6 %
I
SENSE0
Analog sense
leakage current
I
OUT
= 0 A; V
SENSE
=0V; V
CSD
=5V;
V
IN
=0V; T
j
= -40°C...150°C 01
µA
I
OUT
= 0 A; V
SENSE
=0V; V
CSD
=0V;
V
IN
=5V; T
j
= -40°C...150°C 02
I
OUT
= 2 A; V
SENSE
=0V; V
CSD
=5V;
V
IN
=5V; T
j
= -40°C...150°C 01
I
OL
Open load on-state
current detection
threshold
V
IN
=5V; 8V<V
CC
<18V;
I
SENSE
=5µA 420mA
V
SENSE
Max ana log sens e
output voltage I
OUT
= 4 A; V
CSD
=0V 5 V
V
SENSEH
Analog sense
output voltage in
fault condition
(2)
V
CC
=13V; R
SENSE
=3.9KΩ8V
I
SENSEH
Analog sense
output current in
fault condition
(2)
V
CC
=13V; V
SENSE
=5V 9 mA
t
DSENSE1H
Delay r es pon se
time from falling
edge of CS_DIS
pin
V
SENSE
<4V; 0.5A<I
OUT
< 4 A;
I
SENSE
=90% of I
SENSEMAX
(see Figure 4)40 100 µs
t
DSENSE1L
Delay r es pon se
time from rising
edge of CS_DIS
pin
V
SENSE
<4V; 0.5A<I
OUT
< 4 A;
I
SENSE
=10% of I
SENSEMAX
(see Figure 4)520µs
t
DSENSE2H
Delay r es pon se
time from rising
edge of INPUT pin
V
SENSE
<4V; 0.5A<I
OUT
< 4 A;
I
SENSE
=90% of I
SENSEMAX
(see Figure 4)80 250 µs
Δt
DSEN
SE
2H
Delay r es pon se
time betwee n rising
edge of output
current and rising
edge of current
sense
V
SENSE
<4V;
I
SENSE
= 90% of I
SENSEMAX,
I
OUT
= 90% of I
OUTMAX
I
OUTMAX
= 2A (see Figure 7)
40 µs
t
DSENSE2L
Delay r es pon se
time from falling
edge of INPUT pin
V
SENSE
<4V; 0.5A<I
OUT
< 4 A;
I
SENSE
=10% of I
SENSEMAX
(see Figure 4)80 250 µs
1. Parameter guaranteed by design; it is not tested.
2. Fault condition includes: power limitation, over temperature and open load off-state detection.
Table 9. Current sense (8 V < V
CC
< 18 V) (continued)
Symbol Parameter Test conditions Min. Typ. Max. Unit
VND5E050ACJ-E, VND5E0 50ACK -E Electrical specif ica tions
Doc ID 022515 Rev 2 13/43
Figure 4. Current sense delay characteristics
Figure 5. Open load off-state delay timing
Table 10. Open load detection (8V<V
CC
<18V)
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
OL
Open load off-state
volt a ge dete cti on
threshold V
IN
=0V 2 See
Figure 5 4V
t
DSTKON
Output short circuit to
V
CC
detection delay at
turn-off See Figure 5 180 1200 µs
I
L(off2)r
Off-state output current
at V
OUT
=4V V
IN
=0V; V
SENSE
=0V;
V
OUT
rising from 0 V to 4 V -120 0 µA
I
L(off2)f
Off-state output current
at V
OUT
=2V V
IN
=0V; V
SENSE
=V
SENSEH
V
OUT
falling from V
CC
to 2 V -50 90 µA
td_vol
Delay response from
output rising edge to
V
SENSE
rising edge in
open load
V
OUT
=4V; V
IN
=0V;
V
SENSE
= 90% of V
SENSEH
20 µs
SENSE CURRENT
INPUT
LOAD CURRENT
CS_DIS
t
DSENSE2H
t
DSENSE2L
t
DSENSE1L
t
DSENSE1H
V
IN
V
CS
t
DSTKON
OUTPUT STUCK TO V
CC
V
OUT
> V
OL
V
SENSEH
Electrical specifications VND5E050ACJ-E, VND5E050ACK-E
14/43 Doc ID 022515 Rev 2
Figure 6. Switching characteristics
Figure 7. Delay response time between rising edge of output current and rising
edge of current sense (CS enabled)
V
OUT
dV
OUT
/dt
(on)
t
r
80%
10% t
f
dV
OUT
/dt
(off)
t
d(off)
t
d(on)
INPUT
t
t
90%
t
Won
t
Woff
V
IN
I
OUT
I
SENSE
I
OUTMAX
I
SENSEMAX
90% I
SENSEMAX
90% I
OUTMAX
Δ
t
DSENSE2H
t
t
t
VND5E050ACJ-E, VND5E0 50ACK -E Electrical specif ica tions
Doc ID 022515 Rev 2 15/43
Figure 8. Output voltage drop limitation
Figure 9. I
OUT
/I
SENSE
vs I
OUT
V
on
I
out
V
cc
-V
out
T
j
=150
o
CT
j
=25
o
C
T
j
=-40
o
C
V
on
/R
on(T)
1200
1400
1600
1800
2000
2200
2400
2600
2800
3000
11,522,533,54
I
OUT
(A)
I
out
/ I
sense
max Tj = -40 °C to 150 °C
max Tj = 25 °C t o 15 0 ° C
min Tj = 25 °C to 150 °C
min Tj = -40 °C to 150 °C
typical value
Electrical specifications VND5E050ACJ-E, VND5E050ACK-E
16/43 Doc ID 022515 Rev 2
Figure 10. Maximum current sense ratio drift vs load current
Note: Parameter guaranteed by design; it is not tested.
-20
-15
-10
-5
0
5
10
15
20
1234
I
OUT
(A)
dk/k(%)
Table 11. Truth table
Conditions Input Output Sense (V
CSD
=0V)
(1)
1. If the V
CSD
is high, the SENSE output is at high impedance; its potential depends on leakage currents and
external circuits.
Normal operati on L
HL
H0
Nominal
Overtemperature L
HL
L0
V
SENSEH
Undervoltage L
HL
L0
0
Overload
H
H
X
(no power limitation)
Cycling
(power lim it a tio n)
Nominal
V
SENSEH
Short circuit to GND
(power limitation) L
HL
L0
V
SENSEH
Open load off-state (with
external pul l-up ) LHV
SENSEH
Short circuit to V
CC
(external pul l-up
disconnected)
L
HH
HV
SENSEH
< Nominal
Negative output voltage
clamp LL0
VND5E050ACJ-E, VND5E0 50ACK -E Electrical specif ica tions
Doc ID 022515 Rev 2 17/43
Table 12. Electrical transient requirements (part 1)
ISO 7637 -2:
2004(E)
test pulse
Test levels
(1)
1. The above test levels must be considered referred to V
CC
= 13.5V except for pulse 5b.
Number of
pulses or
test times
Burst cycle/p ulse
repetition time Delays and
Impedance
III IV Min. Max.
1 -75V -100V 5000 pulses 0.5s 5s 2 ms, 10Ω
2a +37V +50V 5000 pulses 0.2s 5s 50µs, 2Ω
3a -100V -150V 1h 90 ms 1 00m s 0.1µs, 50Ω
3b + 75V +100V 1h 90ms 100ms 0.1µs, 50Ω
4 -6V -7V 1 pulse 100ms, 0.01Ω
5b
(2)
2. Valid in case of external load dump clamp: 40V maximum referred to ground.
+65V +87V 1 pulse 400ms, 2Ω
Table 13. Electrical transient requirements (part 2)
ISO 7637-2:
2004E
test pulse
Test level results
III VI
1C C
2a C C
3a C C
3b C C
4C C
5b
(1)
1. Valid in case of external load dump clamp: 40V maximum referred to ground.
CC
Table 14. Electrical transient requirements (part 3)
Class Contents
C All functions of the device performed as designed after exposure to disturbance.
EOne or mo re funct ions of the devi ce did n ot perform as des igned after e xposu re to
disturbance and cannot be returned to proper operation without replacing the
device.
Electrical specifications VND5E050ACJ-E, VND5E050ACK-E
18/43 Doc ID 022515 Rev 2
2.4 Waveforms
Figure 11. Normal operation
Figure 12. Overload or short to GND
I
OUT
V
SENSE
V
CS_DIS
INPUT
Nominal load Nominal load
Normal operation
Power Limitation
I
LimH
>
I
LimL
>
I
OUT
V
SENSE
V
CS_DIS
INPUT
Thermal cycling
Overload or Short to GND
VND5E050ACJ-E, VND5E0 50ACK -E Electrical specif ica tions
Doc ID 022515 Rev 2 19/43
Figure 13. Intermittent overload
Figure 14. Off-state open load with external circuitry
I
OUT
V
SENSE
V
CS_DIS
INPUT
I
LimH
>Nominal load
Intermittent Overload
I
LimL
>
Overload
V
SENSEH
>
Electrical specifications VND5E050ACJ-E, VND5E050ACK-E
20/43 Doc ID 022515 Rev 2
Figure 15. Short to V
CC
Figure 16. T
J
evolution in overload or short to GND
t
DSTK(on)
V
OUT
> V
OL
Resistive
Short to V
CC
Hard
Short to V
CC
Short to V
CC
I
OUT
V
CS_DIS
V
OUT
V
OL
t
DSTK(on)
T
TSD
T
R
T
J
evolution in
Overload or Short to GND
I
LimH
>
< I
LimL
T
J_START
T
HYST
Power Limitation
Self-limitation of fast thermal transients
INPUT
I
OUT
T
J
VND5E050ACJ-E, VND5E0 50ACK -E Electrical specif ica tions
Doc ID 022515 Rev 2 21/43
2.5 Electrical characteristics curves
Figure 17. Off-state output current Figure 18. High level input current
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
50
100
150
200
250
300
350
400
450
500
550
Iloff (nA)
Off State
Vcc=13V
Vin=Vout=0V
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
0,5
1
1,5
2
2,5
3
3,5
4
4,5
5
Iih (µA)
Vin=2.1V
Figure 19. Input clamp voltage Figure 20. Input low level
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
5
5,2
5,4
5,6
5,8
6
6,2
6,4
6,6
6,8
7
Vicl (V)
lin=1mA
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
0,2
0,4
0,6
0,8
1
1,2
1,4
1,6
1,8
2
Vil (V)
Figure 21. Input high level Figure 22. Input hysteresis voltage
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
0,5
1
1,5
2
2,5
3
3,5
4
Vih (V)
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
0,1
0,2
0,3
0,4
0,5
0,6
0,7
0,8
0,9
1
Vihyst (V)
Electrical specifications VND5E050ACJ-E, VND5E050ACK-E
22/43 Doc ID 022515 Rev 2
Figure 23. On-state resistance vs T
case
Figure 24. On-state resistance vs V
CC
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
50
100
150
200
250
300
Ron (mOhm)
Iout= 2A
Vcc=13V
0 5 10 15 20 25 30 35 40
Vcc (V)
0
20
40
60
80
100
Ron (mOhm)
Tc=-40°C
Tc=25°C
Tc=125°C
Tc=150°C
Figure 25. Undervoltage shutdown Figure 26. Turn-on voltage slope
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
2
4
6
8
10
12
14
16
Vusd (V)
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
100
200
300
400
500
600
700
800
900
1000
(dVout/dt )On (V/ms)
Vcc=13V
RI=6.5 Ohm
Figure 27. I
LIMH
vs T
case
Figure 28. Turn-off voltage slope
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
10
15
20
25
30
35
40
Ilimh (A)
Vcc=13V
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
50
100
150
200
250
300
350
400
450
500
550
600
(dVout/dt )Off (V/ms)
Vcc=13V
RI= 6.5 Ohm
VND5E050ACJ-E, VND5E0 50ACK -E Electrical specif ica tions
Doc ID 022515 Rev 2 23/43
Figure 29. CS_DIS high level voltage Figure 30. CS_DIS clamp voltage
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
0,5
1
1,5
2
2,5
3
3,5
4
Vcsdh (V)
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
1
2
3
4
5
6
7
8
9
10
Vcsdcl(V)
Icsd = 1 mA
Figure 31. CS_DIS low level voltage
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
0,5
1
1,5
2
2,5
3
Vcsdl (V)
Application information VND5E050ACJ-E, VND5E050ACK-E
24/43 Doc ID 022515 Rev 2
3 Application information
Figure 32. Application schematic
Note: Channel 2 has the same internal circuit as channel 1.
3.1 GND protection network against reverse battery
This section provides two solutions for implementing a ground protection network against
reverse battery.
3.1.1 Solution 1: resistor in the ground line (R
GND
only)
This can be used with any type of load.
The following is an indication on how to resize the R
GND
resistor.
1. R
GND
≤ 600 mV / (I
S(on)max
)
2. R
GND
≥ (−V
CC
) / (-I
GND
)
where -I
GND
is the DC reverse ground pin current and can be found in the absolute
maximum rating section of the device datasheet.
Power dissipation in R
GND
(when V
CC
< 0: during reverse battery situations) is:
P
D
= (-V
CC
)
2
/R
GND
This resistor can be shared amongst several different HSDs. Please note that the value of
this resistor should be calculated with formula (1) where I
S(on)max
becomes the sum of the
maximum on-state currents of the different devices.
Please note that if the microprocessor ground is not shared by the device ground then the
R
GND
produces a shift (I
S(on)max
* R
GND
) in the input thresholds and the status output
values. This shift varies depending on how many devices are on in case of several high side
drivers sharing the sa me R
GND
.
V
CC
GND
OUTPUT
D
GND
R
GND
D
ld
Μ
CU
+5V
V
GND
CS_DIS
INPUT
R
prot
R
prot
CURRENT SENSE
R
SENSE
R
prot
C
EXT
VND5E050ACJ-E, VND5E050ACK-E Application information
Doc ID 022515 Rev 2 25/43
If the calculated power dissipation leads to a large resistor or several devices have to share
the same resistor then ST suggests to utilize Section 3.1.2: Solution 2: diode (DGND) in the
ground line.
3.1.2 Sol ution 2: diode (D
GND
) in the ground line
A resistor (R
GND
=1kΩ) should be inserted in parallel to D
GND
if the device drives an
inductive load.
This small signal diode can be safely shared amongst several different HSDs. Also in this
case, the presence of the ground network will produce a shift (≈600mV) in the input
threshold and in the status output values if the microprocessor ground is not common to the
device ground. This shift will not vary if more than one HSD shares the same diode/resistor
network.
3.2 Load dump protection
D
ld
is necessary (voltage transient suppressor) if the load dump peak voltage exceeds the
V
CC
maximum DC rating. The same applies if the device is subject to transients on the V
CC
line that are greater than the ones shown in the ISO 7637-2: 2004(E) table.
3.3 MCU I/Os protection
If a ground protection network is used and negative transients are present on the V
CC
line,
the control pins are pulled negative.
ST suggests to insert a resistor (R
prot
) in line to prevent the microcontroller I/O pins from
latching-up.
The value of these resistors is a compromise between the leakage current of microcontroller
and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of
microcontroller I/Os:
-V
CCpeak
/I
latchup
≤ R
prot
≤ (V
OHμC
-V
IH
-V
GND
) / I
IHmax
Calculation example:
For V
CCpeak
= - 100V and I
latchup
≥ 20mA; V
OHµC
≥ 4.5V
5kΩ ≤ R
prot
≤ 180kΩ
Recommended values: R
prot
=10kΩ, C
EXT
=10nF.
3.4 Current sense and diagnostic
The current sense pin performs a double function (see Figure 33: Current sense and
diagnostic):
●
Current mirror of the load current in normal operation, deliveri ng a curre nt
proportional to the load current according to a known ratio K
X
.
The current I
SENSE
can be easily converted to a voltage V
SENSE
by means of an
external resistor R
SENSE
. Linearity between I
OUT
and V
SENSE
is ensured up to 5V
minimum (see parameter V
SENSE
in Table 9: Current sense (8 V < V
CC
<18V)). The
current sense accuracy depends on the output current (refer to current sense electrical
Application information VND5E050ACJ-E, VND5E050ACK-E
26/43 Doc ID 022515 Rev 2
characteristics Table 9: Current sense (8 V < V
CC
<18V)).
●
Diagnostic flag in fault conditions, delivering a fixed voltage V
SENSEH
up to a
maximum current I
SENSEH
in case of the following fault conditions (refer to
Table 11: Truth table):
– Power limitation activation
– Overtemperature
– Short to V
CC
in off-state
– Open-load in off-state with additional external components.
A logic level high on the CS_DIS pin simultaneously sets all the current sense pins of the
device in a high impedance state, thus disabling the current monitoring and diagnostic
detection. This feature allows multiplexing of the microcontroller analog inputs by sharing
the sense resistance and ADC line among different devices.
Figure 33. Current sense and diagnostic
3.4. 1 Short to V
CC
and off-state open-load detection
Short to V
CC
A short circuit between V
CC
and output is indicated by the relevant current sense pin set to
V
SENSEH
during the device off-state. Little or no current is delivered by the current sense
during the on-state depending on the nature of the short circuit.
Off-state open-load with external circuitry
Detection of an open-load in of f mode requires an external pull-up resistor (R
PU
) connecting
the output to a positive supply voltage (V
PU
).
Main MOSn
41V
OUTn
ILoff2r
RSENSE
RPROT
To uC ADC
RPD
RPU
VPU
Pwr_Lim
VSENSE
PU_CMD
Overtemperature
OL OFF
+
-
V
OL
CURRENT
SENSEn
IOUT/KX
ISENSEH
VBAT
ILoff2f
VSENSEH
Load
INPUTn
VCC
GND
CS_DIS
VND5E050ACJ-E, VND5E050ACK-E Application information
Doc ID 022515 Rev 2 27/43
It is preferable that V
PU
is switched off during the module standby mode to avoid an increase
in overall standby current consumption in normal conditions, that is, when the load is
connected.
An external pull-down resistor (R
PD
) connected between output and GND is mandatory to
avoid misdetection in case of floating outputs in off-state (see Figure 33: Current sense and
diagnostic).
R
PD
must be selected in order to ensure V
OUT
<
V
OLmin
unless pulled up by the external
circuitry:
R
PD
≤ 22 K
Ω
is reco mme nde d.
For proper open load detection in off-state, the external pull-up resistor must be selected
according to the following formula:
For the values of V
OLmin
,V
OLmax
,
I
L(off2)r
and I
L(off2)f
see Table 10: Open load detection
(8V<V
CC
<18V).
VVIRV
OLfoffLPD
OFFupPull
OUT
2
min)2(
_
=<⋅=
−
VV
RR
IRRVR
V
OL
PDPU
roffLPDPUPUPD
ONupPull
OUT
4
max
)2(
_
=>
+
⋅⋅−⋅
=
−
Application information VND5E050ACJ-E, VND5E050ACK-E
28/43 Doc ID 022515 Rev 2
3.5 Maximum demagnetization energy (V
CC
= 13.5V)
Figure 34. Maximum turn-off current versus inductance (for each channel)
Note: Values are generated with R
L
=0 Ω.In case of repetitive pulses, T
jstart
(at the beginning of
each demagnetization) of every pulse must not exceed the temperature specified above for
curves A and B.
1
10
100
0,1 1 10 100L (m H)
I (A)
C: T
jstart
= 125°C repetitive pulse
A: T
jstart
= 150°C single pulse
B: T
jstart
= 100°C repetitive pulse
Demagnetization Demagnetization Demagnetization
t
V
IN
, I
L
AB
C
VND5E050ACJ-E, VND5E050ACK-E Package and PCB thermal data
Doc ID 022515 Rev 2 29/43
4 Package and PCB thermal data
4.1 PowerSSO-12 thermal data
Figure 35. PowerSSO-12 PC board
Note: Layout condition of R
th
and Z
th
measurements (PCB: double layer, thermal vias, FR4 area=
77mm x 86mm,PCB thickness=1.6mm, Cu thickness=70µm (front and back side), copper
areas: from minim um pad lay-out to 8cm
2
).
Figure 36. R
thj-amb
Vs. PCB copper area in open box free air condition (one channel
ON)
30
35
40
45
50
55
60
65
70
0246810
RTHj_amb(°C/ W)
PCB Cu heatsink area (cm^2)
Package and PCB thermal data VND5E050ACJ-E, VND5E050ACK-E
30/43 Doc ID 022515 Rev 2
Figure 37. PowerSSO-12 thermal impedance junction ambient single pulse (one
channel ON )
Equation 1: pulse calculation formula
Figure 38. Thermal fitting model of a double channel HSD in PowerSSO-12
1. The fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded
protections (power limitation or thermal cycling during thermal shutdown) are not triggered.
0,1
1
10
100
0,0001 0,001 0,01 0,1 1 10 100 1000
Time (s)
ZTH (°C/ W )
Footprint
8 cm
2
2 cm
2
Z
THδ
R
TH
δZ
THtp
1δ–()+⋅=
where
δt
p
T⁄=
VND5E050ACJ-E, VND5E050ACK-E Package and PCB thermal data
Doc ID 022515 Rev 2 31/43
4.2 PowerSSO-24 thermal data
Figure 39. PowerSSO-24 PC board
Note: Layout condition of R
th
and Z
th
measurements (PCB: double layer, thermal vias, FR4 area=
77mm x 86mm, PCB thickness=1.6mm, Cu thickness=70µm (front and back side), copper
areas: from minim um pad lay-out to 8cm
2
).
Table 15. Thermal parameters
Area/island (cm
2
)Footprint28
R1=R7 (°C/W) 0.7
R2=R8 (°C/W) 2.8
R3 (°C/W) 4
R4 (°C/W) 8 8 7
R5 (°C/W) 22 15 10
R6 (°C/W) 26 20 15
C1=C7 (W.s/°C) 0.001
C2=C8 (W.s/°C) 0.0025
C3 (W.s/°C) 0.05
C4 (W.s/°C) 0.2 0 .1 0.1
C5 (W.s/°C) 0.27 0.8 1
C6 (W.s/°C) 3 6 9
Package and PCB thermal data VND5E050ACJ-E, VND5E050ACK-E
32/43 Doc ID 022515 Rev 2
Figure 40. R
thj-amb
vs PCB copper area in open box free air condition (one channel
ON)
30
35
40
45
50
55
0246810
RTHj_amb(°C/W)
PCB Cu heat si nk ar ea ( cm ^ 2)
VND5E050ACJ-E, VND5E050ACK-E Package and PCB thermal data
Doc ID 022515 Rev 2 33/43
Figure 41. PowerSSO-24 thermal impedance junction ambient single pulse (one
channel ON )
Equation 2: pulse calculation formula
Figure 42. Thermal fitting model of a double channel HSD in PowerSSO-24
1. The fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded
protections (power limitation or thermal cycling during thermal shutdown) are not triggered.
Z
THδ
R
TH
δZ
THtp
1δ–()+⋅=
where
δt
p
T⁄=
Package and PCB thermal data VND5E050ACJ-E, VND5E050ACK-E
34/43 Doc ID 022515 Rev 2
Table 16. Thermal parameters
Area / island (cm
2
)Footprint 2 8
R1 = R7 (°C/W) 0.4
R2= R8 (°C/W) 2
R3 (°C/W) 6
R4 (°C/W) 7.7
R5 (°C/W) 9 9 8
R6 (°C/W) 28 17 10
C1 = C7 (W.s/°C) 0.001
C2 = C8 (W.s/°C) 0.0022
C3 (W.s/°C) 0.025
C4 (W.s/°C) 0.75
C5 (W.s/°C) 1 4 9
C6 (W.s/°C) 2.2 5 17
VND5E0 50A CJ-E, VND5 E0 50ACK -E Packag e and packing infor mat ion
Doc ID 022515 Rev 2 35/43
5 Package and packing information
5.1 ECOPACK
®
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
5.2 PowerSSO-12
package information
Figure 43. PowerSSO-12 package dimensions
Package and packing information VND5E050ACJ-E, VND5E050ACK-E
36/43 Doc ID 022515 Rev 2
Table 17. PowerSSO-12 mechanical data
Symbol Millimeters
Min. Typ. Max.
A1.25 1.62
A1 0 0.1
A2 1.10 1.65
B0.23 0.41
C0.19 0.25
D4.8 5.0
E3.8 4.0
e0.8
H5.8 6.2
h 0.25 0.5
L 0.4 1.27
k0° 8°
X1.9 2.5
Y3.6 4.2
ddd 0.1
VND5E0 50A CJ-E, VND5 E0 50ACK -E Packag e and packing infor mat ion
Doc ID 022515 Rev 2 37/43
5.3 PowerSSO-24 package information
Figure 44. PowerSSO-24 package dimensions
Package and packing information VND5E050ACJ-E, VND5E050ACK-E
38/43 Doc ID 022515 Rev 2
Table 18. PowerSSO-24 mechanical data
(1)
(2)
1. No intrusion allowed inwards the leads.
2. Flash or bleeds on exposed die pad shall not exceed 0.5 mm per side
Symbol Millimeters
Min. Typ. Max.
A2.45
A2 2.15 2.35
a1 0 0.1
b 0.33 0.51
c 0.23 0.32
D
(3)
3. “D and E” do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.15 mm
per side
10.10 10.50
E
(3)
7.40 7.60
e0.8
e3 8.8
F2.3
G0.1
H10.1 10.5
h0.4
k0° 8°
L 0.55 0.85
O1.2
Q0.8
S2.9
T3.65
U1.0
N10°
X4.1 4.7
Y6.5 7.1
VND5E0 50A CJ-E, VND5 E0 50ACK -E Packag e and packing infor mat ion
Doc ID 022515 Rev 2 39/43
5.4 PowerSSO-12 packing infor mation
Figure 45. PowerSSO-12 tube shipment (no suffix)
Figure 46. PowerSSO-12 tape and reel shipment (suffix “TR”)
All dimensions are in mm.
Base q.ty 100
Bulk q.ty 2 000
Tube length (± 0.5) 532
A1.85
B6.75
C (± 0.1) 0.6
A
C
B
Base q.ty 2500
Bulk q.ty 2500
A (max) 330
B (min) 1.5
C (± 0.2) 13
F20.2
G (+ 2 / -0) 12.4
N (min) 60
T (max) 18.4
REEL DIMENSIONS
TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
All dimensions are in mm.
Tape width W 12
Tape hole spacing P0 (± 0.1) 4
Comp one nt spac i ng P 8
Hole diameter D (± 0.05) 1.5
Hole diameter D1 (min) 1.5
Hole position F ( ± 0.1) 5.5
Compartment depth K (max) 4.5
Hole spacing P1 (± 0.1) 2
Top
cover
tape
End
Start
No componentsNo components Components
500mm min
500mm mi n
Empty components pockets
saled with cover tape.
User direction of feed
Package and packing information VND5E050ACJ-E, VND5E050ACK-E
40/43 Doc ID 022515 Rev 2
5.5 PowerSSO-24 packing infor mation
Figure 47. PowerSS0-24
tube shipment (no suffix)
Figure 48. PowerSSO-24 tape and reel shipment (suffix “TR”)
All dimensions are in mm.
Base qty 49
Bulk qty 1225
Tube length (±0.5) 532
A3.5
B13.8
C (±0.1) 0.6
A
CB
Base qty 1000
Bulk qty 1000
A (max) 330
B (min) 1.5
C (±0. 2) 13
F20.2
G (+2 / -0) 24.4
N (min) 100
T (max) 30.4
REEL DIMENSIONS
TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
All dimensions are in mm.
Tape width W 24
Tape hole spacing P0 (±0.1) 4
Component sp acing P 12
Hole diameter D (±0.05) 1.55
Hole diameter D1 (min) 1.5
Hole po sition F (±0.1) 11.5
Compartment depth K (max) 2.85
Hole spacing P1 (±0.1) 2
Top
cover
tape
End
Start
No componentsNo components Components
500mm mi n 500mm min
Empty components pockets
sealed with cover tape.
User direction of feed
VND5E050ACJ-E, VND5 E050ACK -E Order codes
Doc ID 022515 Rev 2 41/43
6 Order codes
Table 19. Device summary
Package Order codes
Tube Tape and reel
PowerSSO-12 VND5E050ACJ-E VND5E050ACJTR-E
PowerSSO-24 VND5E050ACK-E VND5E050ACKTR-E
Revision history VND5E050ACJ-E, VND5E050ACK-E
42/43 Doc ID 022515 Rev 2
7 Revision history
Table 20. Doc ument revision history
Date Revision Changes
18-Nov-2 011 1 Initi al rele as e.
18-Sep-2013 2 Updated disclaimer.
VND5E050A CJ-E, VND5E050ACK -E
Doc ID 022515 Rev 2 43/43
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