1 Hm
VIN
CIN
COUT
4.7 Fm
VOUT 5 V
L
2.2 Fm
L
VIN
EN
VOUT
FB
GND
TPS61240
TPS61240, TPS61241
www.ti.com
SLVS806B –APRIL 2009–REVISED FEBRUARY 2012
3.5-MHz High Efficiency Step-Up Converter
Check for Samples: TPS61240, TPS61241
1FEATURES DESCRIPTION
•Efficiency >90% at Nominal Operating The TPS6124x device is a high efficient synchronous
Conditions step up DC-DC converter optimized for products
•Total DC Output Voltage Accuracy 5.0V±2% powered by either a three-cell alkaline, NiCd or
•Typical 30 μA Quiescent Current NiMH, or one-cell Li-Ion or Li-Polymer battery. The
TPS6124x supports output currents up to 450mA.
•Best in Class Line and Load Transient The TPS61240 has an input valley current limit of
•Wide VIN Range From 2.3V to 5.5V 500mA, and the TPS61241 has an input valley
•Output current up to 450mA current of 600mA.
•Automatic PFM/PWM Mode transition With an input voltage range of 2.3V to 5.5V the
•Low Ripple Power Save Mode for Improved device supports batteries with extended voltage
Efficiency at Light Loads range and are ideal to power portable applications
like mobile phones and other portable equipment.
•Internal Softstart, 250μs typical Start-Up time The TPS6124x boost converter is based on a
•3.5MHz Typical Operating Frequency quasi-constant on-time valley current mode control
•Load Disconnect During Shutdown scheme.
•Current Overload and Thermal Shutdown The TPS6124x presents a high impedance at the
Protection VOUT pin when shut down. This allows for use in
applications that require the regulated output bus to
•Three Surface-Mount External Components be driven by another supply while the TPS6124x is
Required (One MLCC Inductor, Two Ceramic shut down.
Capacitors)
•Total Solution Size <13 mm2During light loads the device will automatically pulse
skip allowing maximum efficiency at lowest quiescent
•Available in a 6-pin WCSP and 2×2-SON currents. In the shutdown mode, the current
Package consumption is reduced to less than 1μA.
TPS6124x allows the use of small inductors and
APPLICATIONS capacitors to achieve a small solution size. During
•USB-OTG Applications shutdown, the load is completely disconnected from
•Portable HDMI Applications the battery. The TPS6124x is available in a 6-pin
WCSP and 2×2 SON package.
•Cell Phones, Smart-Phones
•PDAs, Pocket PCs
•Portable Media Players
•Digital Cameras
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright ©2009–2012, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPS61240, TPS61241
SLVS806B –APRIL 2009–REVISED FEBRUARY 2012
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
OUTPUT PACKAGE
DEVICE
PART NUMBER(1) PACKAGE ORDERING
SPECIFIC FEATURES
VOLTAGE MARKING
6-WCSP TPS61240YFF GM
TPS61240 6-QFN TPS61240DRV OCJ
Supports 5V, up to 300mA loading
5V
TPS61241 6-WCSP TPS61241YFF NF
down to 3.2V input voltage
Optimized to drive
TPS61242(2) 6-WCSP TPS61242YFF RY
an inductive load
(1) The YFF package is available in tape on reel. Add R suffix (TPS61240YFFR) to order quantities of 3000 parts per reel. Add a T suffix
(TPS61240YFFT) to order quantities of 250 parts.
(2) Product preview.Contact TI factory for more information
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1) (2)
VALUE UNIT
VIInput voltage range on VIN, L, EN –0.3 to 7 V
Voltage on VOUT –2.0 to 7 V
Voltage on FB –2.0 to 14 V
Peak output current Internally limited A
Human Body Model 4000 V
ESD rating(3) CDM Charged Device Model 500 V
Machine Model 200 V
TJMaximum operating junction temperature –40 to 125 °C
Tstg Storage temperature range –65 to 150 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
(3) The human body model is a 100pF capacitor discharged through a 1.5 kΩresistor into each pin. The machine model is a 200pF
capacitor discharged directly into each pin.
DISSIPATION RATINGS TABLE(1)
POWER RATING DERATING FACTOR ABOVE
PACKAGE RθJA TA≤25°C TA= 25°C
DRV 76°C/W 1300mW 13mW/°C
YFF 125°C/W 800mW 8mW/°C
(1) Maximum power dissipation is a function of TJ(max), θJA and TA. The maximum allowable power dissipation
at any allowable ambient temperature is PD= [TJ(max)-TA] / θJA.
(2) This thermal data is measured with high-K board (4 layer board according to JESD51-7 JEDEC standard).
2Copyright ©2009–2012, Texas Instruments Incorporated
TPS61240, TPS61241
www.ti.com
SLVS806B –APRIL 2009–REVISED FEBRUARY 2012
RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT
VIN Input voltage range 2.3 5.5 V
L Inductance 0.4 1 1.5 µH
TPS61240 1 20 µF
TPS61241
COOutput capacitance TPS61242 0.8 10 µF
TAOperating ambient temperature –40 85 °C
TJOperating junction temperature –40 125 °C
ELECTRICAL CHARACTERISTICS
Over full operating ambient temperature range, typical values are at TA= 25°C. Unless otherwise noted, specifications apply
for condition VIN = EN = 3.6V. External components CIN = 2.2μF, COUT = 4.7μF 0603, L = 1μH, refer to PARAMETER
MEASUREMENT INFORMATION.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DC/DC STAGE
VIN Input voltage range 2.3 5.5 V
VOUT Fixed output voltage range 2.3 V ≤VIN ≤5.5 V, 0 mA ≤IOUT ≤200 mA 4.9 5.0 5.1 V
VO_Ripple Ripple voltage, PWM mode ILOAD = 150 mA 20 mVpp
Output current VIN 2.3 V to 5.5 V 200 mA
VOUT = VGS = 5.0 V (TPS61240) 500 600
Switch valley current limit mA
VOUT = VGS = 5.0 V (TPS61241, TPS61242) 600 700
Short circuit current VOUT = VGS = 5.0 V 200 350 mApk
High side MOSFET on-resistance(1) VIN = VGS = 5.0V, TA= 25°C(1) 290 mΩ
Low Side MOSFET on-resistance(1) VIN = VGS = 5.0 V, TA= 25°C(1) 250 mΩ
Operating quiescent current IOUT = 0 mA, Power save mode 30 40 μA
ISW Shutdown current EN = GND 1.5 μA
Reverse leakage current VOUT EN = 0, VOUT = 5 V 2.5 μA
Leakage current from battery to EN = GND 2.5 μA
VOUT VIN 600 mVp-p AC square wave, 200Hz,
Line transient response ±25 ±50 mVpk
12.5% DC at 50/200mA load
0–50 mA, 50–0 mA VIN = 3.6V TRise = TFall = 0.1μs 50
Load transient response mVpk
50–200 mA, 200–50 mA, VIN = 3.6 V, TRise = TFall = 0.1μs 150
IIN Input bias current, EN EN = GND or VIN 0.01 1.0 μA
Falling 2.0 2.1 V
VUVLO Undervoltage lockout threshold Rising 2.1 2.2 V
CONTROL STAGE
VIH High level input voltage, EN 2.3 V ≤VIN ≤5.5 V 1.0 V
VIL Low level input voltage, EN 2.3 V ≤VIN ≤5.5 V 0.4 V
Falling 5.9
OVC Input over-voltage threshold V
Rising 6.0
Time from active EN to start switching, no-load until VOUT
tStart Start-up time 300 μs
is stable 5V
DC/DC STAGE
Freq See Figure 7 (Frequency Dependancy vs IOUT) 3.5 MHz
Thermal shutdown Increasing junction temperature 140 °C
TSD Thermal shutdown hysteresis Decreasing junction temperature 20 °C
(1) DRV package has an increased RDSon of about 40mΩdue to bond wire resistance.
Copyright ©2009–2012, Texas Instruments Incorporated 3
A1 A2
B1 B2
C1 C2
TOP VIEW
A2 A1
B2 B1
C2 C1
BOTTOM VIEW
1
2
3 4
5
6
PowerPad
TPS61240, TPS61241
SLVS806B –APRIL 2009–REVISED FEBRUARY 2012
www.ti.com
PIN ASSIGNMENTS
WCSP PACKAGE
QFN PACKAGE (TOP VIEW)
PIN FUNCTIONS
PIN NO. PIN NAME FUNCTION REMARKS
QFN WCSP
2 B2 VOUT Output Connected to load
6 A1 VIN Supply voltage Supply from battery
5 B1 L Boost and rectifying switch input Inductor connection to FETs
4 C1 EN Enable Positive polarity. Low = IC shutdown.
3 C2 FB Feedback input Feedback for regulation.
1 A2 GND Ground Power ground and IC ground
4Copyright ©2009–2012, Texas Instruments Incorporated
L
Error Amp.
+
_
-
+
VIN
EN
GateDrive
Softstart
Control
Logic
Thermal
Shutdown
Undervoltage
Lockout
Current
Sense
R1
R2
Int.
Resistor
Network
VREF
GND
GND
FB
VOUT
1 Hm
VIN
CIN
COUT
4.7 Fm
VOUT 5 V
L
2.2 Fm
L
VIN
EN
VOUT
FB
GND
TPS61240
TPS61240, TPS61241
www.ti.com
SLVS806B –APRIL 2009–REVISED FEBRUARY 2012
FUNCTIONAL BLOCK DIAGRAM
PARAMETER MEASUREMENT INFORMATION
List of Components
COMPONENT PART NUMBER MANUFACTURER VALUE
REFERENCE
CIN JMK105BJ225MV Taiyo Yuden 2.2 μF, X5R, 6.3 V, 0402
COUT JDK105BJ475MV Taiyo Yuden 4.7 μF, X5R, 6.3 V, 0402
L MDT2012-CH1R0AN TOKO 1.0 μH, 900mA, 0805
Copyright ©2009–2012, Texas Instruments Incorporated 5
0
10
20
30
40
50
60
70
80
90
100
Efficiency-%
0.00001 0.001 0.01 0.1 1
I -OutputCurrent- A
O
0.0001
V =2.3V
I
V =3V
I
V =3.6V
I
V =4.2V
I
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
I -OutputCurrent- A
O
2 2.5 3 3.5 4 4.5 5 5.5 6
V -InputVoltage-V
I
-40°C
25°C
85°C
TPS61240, TPS61241
SLVS806B –APRIL 2009–REVISED FEBRUARY 2012
www.ti.com
TYPICAL CHARACTERISTICS
Table of Graphs
Table 1.
Figure
Maximum Output Current vs Input Voltage 1
vs Output Current, Vout = 5V, Vin = [2.3V; 3.0V; 3.6V; 4.2V] 2
Efficiency vs Input Voltage, Vout = 5V, Iout = [100uA; 1mA; 10mA; 100mA; 200mA] 3
Input Current at No Output Load, Device Disabled 4
vs Output Current, Vout = 5V, Vin = [2.3V; 3.0V; 3.6V; 4.2V] 5
Output Voltage vs Input Voltage 6
Frequency vs Output Load, Vout = 5V, Vin = [3.0V; 4.0V; 5.0V] 7
Output Voltage Ripple, PFM Mode, Iout = 10mA 8
Output Voltage Ripple, PWM Mode, Iout = 150mA 9
Load Transient Response, Vin = 3.6V, 0 - 50mA 10
Load Transient Response, Vin = 3.6V, 50 - 200mA 11
Waveforms Line Transient Response, Vin = 3.6V - 4.2V, Iout = 50mA 12
Line Transient Response, Vin = 3.6V - 4.2V, Iout = 200mA 13
Startup after Enable, Vin = 3.6V, Vout = 5V, Load = 5KΩ14
Startup after Enable, Vin = 3.6V, Vout = 5V, Load = 16.5Ω15
Startup and Shutdown, Vin = 3.6V, Vout = 5V, Load = 16.5Ω16
Figure 1. Maximum Output Current vs Input Voltage Figure 2. Efficiency vs Output Current
6Copyright ©2009–2012, Texas Instruments Incorporated
0
10
20
30
40
50
60
70
80
90
100
2.3 2.8 3.3 3.8 4.3 4.8 5.3
V -InputVoltage-V
IN
Efficiency-%
I =100 A
Om
I =1mA
O
I =10mA
O
I =100mA
O
I =200mA
O
0
0.010
0.020
0.030
0.040
0.050
0.060
0.070
-40°C
85°C
25°C
I -InputCurrent-mA
I
2 2.5 3 3.5 4 4.5 5 5.5 6
V -InputVoltage-V
I
4.90
4.95
5
5.05
5.10
V -OutputVoltageDC-V
O
0.01 0.1 1 10 100 1000
I -OutputCurrent-mA
O
V =2.3V
I
V =3V
I
V =3.6V
I
V =4.2V
I
TPS61240, TPS61241
www.ti.com
SLVS806B –APRIL 2009–REVISED FEBRUARY 2012
Figure 3. Efficiency vs Input Voltage Figure 4. Input at No Output Load
Figure 5. Output Voltage vs Output Current Figure 6. Output Voltage vs Input Voltage
Copyright ©2009–2012, Texas Instruments Incorporated 7
V =3.6V,V =5V,I =10mA
IN OUT OUT
V =20mV/div
OUT
SW=5V/div
I =200mA/div
COIL
t-TimeBase-1 s/divm
3
3.5
4
4.5
5
5.5
f-Frequency-MHz
100 150 200 250 300 350 400 450 500
I -OutputCurrent-mA
O
3V
4V
5V
V =3.6V,V =5V,I =150mA
IN OUT OUT
V =10mV/div
OUT
SW=5V/div
I =200mA/div
COIL
t-TimeBase-20 s/divm
V =100mV/dIV
OUT
I =100mA/dIV
COIL
V =3.6V
I =0-50mA
IN
OUT
V =5V
OUT
0mA
50mA
I =100mA/div
OUT
t-TimeBase-20 s/divm
TPS61240, TPS61241
SLVS806B –APRIL 2009–REVISED FEBRUARY 2012
www.ti.com
Figure 7. Frequency vs Output Load Figure 8. Output Voltage Ripple –PFM Mode
Figure 9. Output Voltage Ripple –PWM Mode Figure 10. Load Transient Response 0mA–50mA and
50mA–0mA
8Copyright ©2009–2012, Texas Instruments Incorporated
V =1V/div
IN
I =200mA/div
COIL
V =50mv/div
OUT
V =3.6V-4.2V
I =50mA
IN
OUT
V =5V
OUT
t-TimeBase-100 s/divm
V =200mV/div
OUT
I =200mA/div
COIL
V =3.6V
I =50-200mA
IN
OUT
V =5V
OUT
50mA
200mA
I =200mA/div
OUT
t-TimeBase-20 s/divm
V =3.6V
I =10mA
IN
OUT
V =5V
OUT
EN=5V/div
I =200mA/div
COIL
V =1V/div
OUT
t-TimeBase-50 s/divm
V =1V/div
IN
I =200mA/div
COIL
V =50mv/div
OUT
V =3.6V-4.2V
I =200mA
IN
OUT
V =5V
OUT
t-TimeBase-100 s/divm
TPS61240, TPS61241
www.ti.com
SLVS806B –APRIL 2009–REVISED FEBRUARY 2012
Figure 11. Load Transient Response 0mA–200mA and Figure 12. Line Transient Response 3.6V–4.2V at 50mA
200mA–0mA Load
Figure 13. Line Transient Response 3.6V–4.2V at 200mA Figure 14. Startup After Enable –No Load
Load
Copyright ©2009–2012, Texas Instruments Incorporated 9
V =3.6V
I =150mA
IN
OUT
V =5V
OUT
EN=5V/div
I =200mA/div
COIL
V =2V/div
OUT
t-TimeBase-100 s/divm
V =3.6V
I =150mA
IN
OUT
V =5V
OUT
EN=5V/div
I =200mA/div
COIL
V =1V/div
OUT
V =1V/div
IN
t-TimeBase-200 s/divm
-
- ´ D D ´ » OUT IN
IN
OUT(CL) VALLEY L L
OUT
V V
1 V D
I = (1 D) (I + I ) with I = and D
2 L f V
TPS61240, TPS61241
SLVS806B –APRIL 2009–REVISED FEBRUARY 2012
www.ti.com
Figure 15. Startup After Enable –With Load Figure 16. Startup and Shutdown
DETAILED DESCRIPTION
OPERATION
The TPS6124x Boost Converter operates with typically 3.5MHz fixed frequency pulse width modulation (PWM) at
moderate to heavy load currents. At light load currents the converter will automatically enter Power Save Mode
and operates then in PFM (Pulse Frequency Modulation) mode. During PWM operation the converter uses a
unique fast response quasi-constant on-time valley current mode controller scheme which allows “Best in Class”
line and load regulation allowing the use of small ceramic input and output capacitors.
Based on the VIN/VOUT ratio, a simple circuit predicts the required on-time. At the beginning of the switching
cycle, the low-side N-MOS switch is turned-on and the inductor current ramps up to a defined peak current. In
the second phase, once the peak current is reached, the current comparator trips, the on-timer is reset turning off
the switch, and the current through the inductor then decays to an internally set valley current limit. Once this
occurs, the on-timer is set to turn the boost switch back on again and the cycle is repeated.
CURRENT LIMIT OPERATION
The current limit circuit employs a valley current sensing scheme. Current limit detection occurs during the off
time through sensing of the voltage drop across the synchronous rectifier.
The output voltage is reduced as the power stage of the device operates in a constant current mode. The
maximum continuous output current (IOUT(CL)), before entering current limit operation, can be defined by
Equation 1 as shown.
(1)
Figure 17 illustrates the inductor and rectifier current waveforms during current limit operation. The output
current, IOUT, is the average of the rectifier ripple current waveform. When the load current is increased such that
the lower peak is above the current limit threshold, the off time is lengthened to allow the current to decrease to
this threshold before the next on-time begins (so called frequency fold-back mechanism).
10 Copyright ©2009–2012, Texas Instruments Incorporated
f
D
L
V
ΔI IN
L×=
I =I
VALLEY LIM
IL
f
IPEAK
Rectifier
Current
IOUT(DC)
Inductorr
Current
Increased
LoadCurrent
IIN(DC)
IIN(DC)
CurrentLimit
Threshold
IOUT(CL)
DIL
DIL
PFMmodeatlightload
PWMmodeatheavyload
Output
Voltage
PFMrippleabout0.015xVOUT
1.006xVOUT NOM.
VOUT NOM.
TPS61240, TPS61241
www.ti.com
SLVS806B –APRIL 2009–REVISED FEBRUARY 2012
Figure 17. Inductor/Rectifier Currents in Current Limit Operation
POWER-SAVE MODE
The TPS6124x family of devices integrates a power save mode to improve efficiency at light load. In power save
mode the converter only operates when the output voltage trips below a set threshold voltage. It ramps up the
output voltage with several pulses and goes into power save mode once the output voltage exceeds the set
threshold voltage.
The PFM mode is left and PWM mode entered in case the output current can not longer be supported in PFM
mode.
UNDER-VOLTAGE LOCKOUT
The under voltage lockout circuit prevents the device from malfunctioning at low input voltages and from
excessive discharge of the battery. It disables the output stage of the converter once the falling VIN trips the
under-voltage lockout threshold VUVLO. The under-voltage lockout threshold VUVLO for falling VIN is typically 2.0V.
The device starts operation once the rising VIN trips under-voltage lockout threshold VUVLO again at typ. 2.1V.
INPUT OVER-VOLTAGE PROTECTION
In the event of an overvoltage condition appearing on the input rail, the output voltage will also experience the
overvoltage due to being in dropout condition. A input overvoltage protection feature has been implemented into
the TPS6124x which has an input overvoltage threshold of 6.0V. Once this level is triggered, the device will go
into a shutdown mode to protect itself. If the voltage drops to 5.9V or below, the device will startup once more
into normal operation.
Copyright ©2009–2012, Texas Instruments Incorporated 11
TPS61240, TPS61241
SLVS806B –APRIL 2009–REVISED FEBRUARY 2012
www.ti.com
ENABLE
The device is enabled setting EN pin to high. At first, the internal reference is activated and the internal analog
circuits are settled. Afterwards, the soft start is activated and the output voltage is ramped up. The output
voltages reaches its nominal value in typically 250 μs after the device has been enabled.
The EN input can be used to control power sequencing in a system with various DC/DC converters. The EN pin
can be connected to the output of another converter, to drive the EN pin high and getting a sequencing of supply
rails. With EN = GND, the device enters shutdown mode.
SOFT START
The TPS6124x has an internal soft start circuit that controls the ramp up of the output voltage. The output
voltages reaches its nominal value within tStart of typically 250μs after EN pin has been pulled to high level. The
output voltage ramps up from 5% to its nominal value within tRAMP of typ. 300μs.
This limits the inrush current in the converter during start up and prevents possible input voltage drops when a
battery or high impedance power source is used.
During soft start, the switch current limit is reduced to 300mA until the output voltage reaches VIN. Once the
output voltage trips this threshold, the device operates with its nominal current limit ILIMF.
LOAD DISCONNECT
Load disconnect electrically removes the output from the input of the power supply when the supply is disabled.
This is especially important during shutdown. In shutdown of a boost converter, the load is still connected to the
input through the inductor and catch diode. Since the input voltage is still connected to the output, a small current
continues to flow, even when the supply is disabled. Even small leakage currents significantly reduce battery life
during extended periods of off time.
The benefit of this implemented feature for the system design engineer is that the battery is not depleted during
shutdown of the converter. No additional components must be added to the design to make sure that the battery
is disconnected from the output of the converter.
THERMAL SHUTDOWN
As soon as the junction temperature, TJ, exceeds 140°C (typical) the device goes into thermal shutdown. In this
mode, the High Side and Low Side MOSFETs are turned-off. When the junction temperature falls below the
thermal shutdown hysteresis, the device continuous operation.
12 Copyright ©2009–2012, Texas Instruments Incorporated
1 Hm
VIN
CIN
COUT
4.7 Fm
VOUT 5 V
L
2.2 Fm
L
VIN
EN
VOUT
FB
GND
TPS61240
1 Hm
VIN
CIN COUT
4.7 Fm
VOUT 5 V
L
2.2 Fm
L
VIN
EN
FB
VOUT
GND
TPS61240
1 Hm
VIN
CIN
COUT
L
VIN
EN
VOUT
FB
GND
TPS61242
L
4.7 F 6.3V X5R
(0402)
m
5 VOUT
L = TOKO MDT1608-CH1R0N
C = muRata GRM155R60J155M
IN
C = muRata GRM155R60J475M
OUT
1.5 F 6.3V X5R
(0402)
m
EN
DRV2603
PWM
OUT+
OUT-
VDD
GND
ERM/LRA
PWM
Modulation
DC Motor
Vibrator
TPS61240, TPS61241
www.ti.com
SLVS806B –APRIL 2009–REVISED FEBRUARY 2012
APPLICATION INFORMATION
Figure 18. TPS61240 Fixed 5.0V for HDMI / USB-OTG Applications
Figure 19. TPS61240 Fixed 5.0V With Schottky Diode for Output Overvoltage Protection
Figure 20. DRV2603 + TPS61242 Haptic Driver Solution featuring PWM Modulation Control
Copyright ©2009–2012, Texas Instruments Incorporated 13
» ´ ´
OUT
L_MAX OUT
IN
V
I I η V
( )
´ -
»D ´ ´
IN OUT IN
MIN
L OUT
V V V
LI f V
OUT OUT ININ
L(peak)
OUT
I V VV D
I = + with D =
2 f L (1 D) η V
-´
´ ´ - ´
TPS61240, TPS61241
SLVS806B –APRIL 2009–REVISED FEBRUARY 2012
www.ti.com
DESIGN PROCEDURE
PROGRAMMING THE OUTPUT VOLTAGE
The output voltage is set by a resistor divider internally. The FB pin is used to sense the output voltage. To
configure the output properly, the FB pin needs to be connected directly as shown in Figure 18 and Figure 19.
INDUCTOR SELECTION
To make sure that the TPS6124x devices can operate, an inductor must be connected between pin VIN and pin
L. A boost converter normally requires two main passive components for storing energy during the conversion. A
boost inductor and a storage capacitor at the output are required. To select the boost inductor, it is
recommended to keep the possible peak inductor current below the current limit threshold of the power switch in
the chosen configuration. The highest peak current through the inductor and the switch depends on the output
load, the input (VIN), and the output voltage (VOU T). Estimation of the maximum average inductor current can be
done using Equation 2.
(2)
For example, for an output current of 200mA at 5.0V VOUT, at least 540mA of average current flows through the
inductor at a minimum input voltage of 2.3V.
The second parameter for choosing the inductor is the desired current ripple in the inductor. Normally, it is
advisable to work with a ripple of less than 20% of the average inductor current. A smaller ripple reduces the
magnetic hysteresis losses in the inductor, as well as output voltage ripple and EMI. But in the same way,
regulation time at load changes rises. In addition, a larger inductor increases the total system size and cost. With
these parameters, it is possible to calculate the value of the minimum inductance by using Equation 3.
(3)
Parameter f is the switching frequency and ΔILis the ripple current in the inductor, i.e., 20% x IL. In this example,
the desired inductor has the value of 1.7 μH. With this calculated value and the calculated currents, it is possible
to choose a suitable inductor. In typical applications a 1.0 μH inductance is recommended. The device has been
optimized to operate with inductance values between 1.0 μH and 2.2 μH. It is recommended that inductance
values of at least 1.0 μH is used, even if Equation 3 yields something lower. Care has to be taken that load
transients and losses in the circuit can lead to higher currents as estimated in Equation 3. Also, the losses in the
inductor caused by magnetic hysteresis losses and copper losses are a major parameter for total circuit
efficiency.,
With the chosen inductance value, the peak current for the inductor in steady state operation can be calculated.
Equation 4 shows how to calculate the peak current I.
(4)
This would be the critical value for the current rating for selecting the inductor. It also needs to be taken into
account that load transients and error conditions may cause higher inductor currents.
Table 2. Table 1. List of Inductors
Manufacturer Series Dimensions
MDT2012-CH1R0AN 2.0 x 1.2 x 1.0 max. height
TOKO MDT1608-CH1R0N 1.6 x 0.8 x 0.95 max. height
KSLI-201210AG-1R0 2.0 x 1.2 x 1.0 max. height
Hitachi Metals KSLI-201610AG-1R0 2.0 x 1.6 x 1.0 max. height
muRata LQM21PN1R0MC0 2.0 x 1.2 x 0.55 max. height
FDK MIPS2012D1R0-X2 2.0 x 1.2 x 1.0 max. height
14 Copyright ©2009–2012, Texas Instruments Incorporated
( )
OUT OUT IN
min
OUT
I V V
C = f V V
´ -
´ D ´
TPS61240, TPS61241
www.ti.com
SLVS806B –APRIL 2009–REVISED FEBRUARY 2012
INPUT CAPACITOR
At least 2.2μF input capacitor is recommended to improve transient behavior of the regulator and EMI behavior
of the total power supply circuit. It is recommended to place a ceramic capacitor as close as possible to the VIN
and GND pins
OUTPUT CAPACITOR
For the output capacitor, it is recommended to use small ceramic capacitors placed as close as possible to the
VOUT and GND pins of the IC. If, for any reason, the application requires the use of large capacitors which can
not be placed close to the IC, using a smaller ceramic capacitor in parallel to the large one is recommended.
This small capacitor should be placed as close as possible to the VOUT and GND pins of the IC. To get an
estimate of the recommended minimum output capacitance, Equation 5 can be used.
(5)
Parameter f is the switching frequency and ΔV is the maximum allowed ripple.
With a chosen ripple voltage of 10 mV, a minimum effective capacitance of 2.7 μF is needed. The total ripple is
larger due to the ESR of the output capacitor. This additional component of the ripple can be calculated using
ΔVESR = IOUT x RESR
A capacitor with a value in the range of the calculated minimum should be used. This is required to maintain
control loop stability. There are no additional requirements regarding minimum ESR. There is no upper limit for
the output capacitance value. Larger capacitors cause lower output voltage ripple as well as lower output voltage
drop during load transients.
Note that ceramic capacitors have a DC Bias effect, which will have a strong influence on the final effective
capacitance needed. Therefore the right capacitor value has to be chosen carefully. Package size and voltage
rating in combination with material are responsible for differences between the rated capacitor value and the
effective capacitance.
CHECKING LOOP STABILITY
The first step of circuit and stability evaluation is to look from a steady-state perspective at the following signals:
•Switching node, SW
•Inductor current, IL
•Output ripple voltage, VO(AC)
These are the basic signals that need to be measured when evaluating a switching converter. When the
switching waveform shows large duty cycle jitter or the output voltage or inductor current shows oscillations, the
regulation loop may be unstable. This is often a result of board layout and/or L-C combination.
As a next step in the evaluation of the regulation loop, the load transient response is tested. The time between
the application of the load transient and the turn on of the P-channel MOSFET, the output capacitor must supply
all of the current required by the load. VOimmediately shifts by an amount equal to ΔI(LOAD) ×ESR, where ESR is
the effective series resistance of CO.ΔI(LOAD) begins to charge or discharge COgenerating a feedback error
signal used by the regulator to return VOto its steady-state value. The results are most easily interpreted when
the device operates in PWM mode. During this recovery time, VOcan be monitored for settling time, overshoot or
ringing that helps judge the converter’s stability. Without any ringing, the loop has usually more than 45°of phase
margin. Because the damping factor of the circuitry is directly related to several resistive parameters (e.g.,
MOSFET rDS(on)) that are temperature dependant, the loop stability analysis has to be done over the input voltage
range, load current range, and temperature range.
Copyright ©2009–2012, Texas Instruments Incorporated 15
VIN GND
VOUT
L
CI
CO
EN
TPS61240, TPS61241
SLVS806B –APRIL 2009–REVISED FEBRUARY 2012
www.ti.com
LAYOUT CONSIDERATIONS
As for all switching power supplies, the layout is an important step in the design, especially at high peak currents
and high switching frequencies. If the layout is not carefully done, the regulator could show stability problems as
well as EMI problems. Therefore, use wide and short traces for the main current path and for the power ground
tracks. The input and output capacitor, as well as the inductor should be placed as close as possible to the IC.
Use a common ground node for power ground and a different one for control ground to minimize the effects of
ground noise. Connect these ground nodes at any place close to one of the ground pins of the IC. The feedback
divider should be placed as close as possible to the control ground pin of the IC. To lay out the control ground, it
is recommended to use short traces as well, separated from the power ground traces. This avoids ground shift
problems, which can occur due to superimposition of power ground current and control ground current.
LAYOUT GUIDELINES
Figure 21. Suggested Layout (Top)
16 Copyright ©2009–2012, Texas Instruments Incorporated
A2 A1
B2 B1
C2 C1
D
E
A1
YMSCC
LLLL
Code:
• YM- YearMonthdatecode
• S- Assemblysitecode
• CC-ChipCode
• LLLL -Lottracecode
ChipScalePackage
(BottomView)
ChipScalePackage
(TopView)
TPS61240, TPS61241
www.ti.com
SLVS806B –APRIL 2009–REVISED FEBRUARY 2012
THERMAL INFORMATION
Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires
special attention to power dissipation. Many system-dependant issues such as thermal coupling, airflow, added
heat sinks, and convection surfaces, and the presence of other heat-generating components, affect the
power-dissipation limits of a given component.
Three basic approaches for enhancing thermal performance are listed below:
•Improving the power dissipation capability of the PCB design
•Improving the thermal coupling of the component to the PCB
•Introducing airflow into the system
The maximum recommended junction temperature (TJ) of the TPS6124x devices is 105°C. The thermal
resistance of the 6-pin CSP package (YFF-6) is RθJA = 125°C/W. Regulator operation is specified to a maximum
steady-state ambient temperature TAof 85°C. Therefore, the maximum power dissipation is about 160 mW.
PD(Max) = [TJ(max)-TA] / θJA = [105°C - 85°C] / 125°C/W = 160mW
CHIP SCALE PACKAGE DIMENSIONS
The TPS6124x device is available in a 6-bump chip scale package (YFF, NanoFreeTM). The package dimensions
are given as:
D E
Max = 1280 µm Max = 890 µm
Min = 1220 µm Min = 830 µm
Copyright ©2009–2012, Texas Instruments Incorporated 17
PACKAGE OPTION ADDENDUM
www.ti.com 5-Oct-2011
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPS61240DRVR ACTIVE SON DRV 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS61240DRVT ACTIVE SON DRV 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS61240YFFR ACTIVE DSBGA YFF 6 3000 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM
TPS61240YFFT ACTIVE DSBGA YFF 6 250 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM
TPS61241YFFR ACTIVE DSBGA YFF 6 3000 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM
TPS61241YFFT ACTIVE DSBGA YFF 6 250 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
PACKAGE OPTION ADDENDUM
www.ti.com 5-Oct-2011
Addendum-Page 2
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS61240 :
•Automotive: TPS61240-Q1
NOTE: Qualified Version Definitions:
•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS61240DRVR SON DRV 6 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2
TPS61240DRVT SON DRV 6 250 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2
TPS61240YFFR DSBGA YFF 6 3000 180.0 8.4 0.98 1.41 0.69 4.0 8.0 Q1
TPS61240YFFT DSBGA YFF 6 250 180.0 8.4 0.98 1.41 0.69 4.0 8.0 Q1
TPS61241YFFR DSBGA YFF 6 3000 180.0 8.4 0.98 1.41 0.69 4.0 8.0 Q1
TPS61241YFFT DSBGA YFF 6 250 180.0 8.4 0.98 1.41 0.69 4.0 8.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 11-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS61240DRVR SON DRV 6 3000 203.0 203.0 35.0
TPS61240DRVT SON DRV 6 250 203.0 203.0 35.0
TPS61240YFFR DSBGA YFF 6 3000 210.0 185.0 35.0
TPS61240YFFT DSBGA YFF 6 250 210.0 185.0 35.0
TPS61241YFFR DSBGA YFF 6 3000 210.0 185.0 35.0
TPS61241YFFT DSBGA YFF 6 250 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 11-Jul-2012
Pack Materials-Page 2
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