ISL54062IRUZ-T - RENESAS TECHNOLOGY

FN6581 Rev 1.00 Page 1 of 16

Nov 3, 2009

FN6581

Rev 1.00

Nov 3, 2009

ISL54062

Negative Signal Swing, Sub-ohm, Dual SPDT with Click and Pop Elimination

Single Supply Switch

DATASHEET

The Intersil ISL54062 device is a low ON-resistance, low

voltage, bidirectional, dual single-pole/double-throw (SPDT)

analog switch. It is designed to operate from a single +1.8V to

+6.5V supply and pass signals that swing down to 6.5V below

the positive supply rail. Targeted applications include battery

powered equipment that benefit from low rON (0.56low

power consumption (20nA) and fast switching speeds

(tON = 55ns, tOFF = 18ns). The digital inputs are 1.8V

logic-compatible up to a +3V supply. The ISL54062 also

features integrated circuitry to eliminate click and pop noise to

an audio speaker. The ISL54062 is offered in a small form

factor package, alleviating board space limitations. It is

available in a tiny 10 Ld 1.8x1.4mm µTQFN or 10 Ld 3x3mm

TDFN package.

The ISL54062 is a committed dual single-pole/double-throw

(SPDT) that consist of two normally open (NO) and two

normally closed (NC) switches with independent logic control.

This configuration can be used as a dual 2-to-1 multiplexer.

Features

• Pb-free (RoHS Compliant)

• Negative Signal Swing (Max 6.5V Below V+)

• Audio Click and Pop Elimination Circuitry

• ON-Resistance (rON)

- V+ = +4.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.55

- V+ = +4.3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.57

- V+ = +2.7V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.82

- V+ = +1.8V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.8

•r

ON Matching Between Channels . . . . . . . . . . . . . . . . .10m

•r

ON Flatness Across Signal Range . . . . . . . . . . . . . . . .0.35

• Low THD+N @ 32Load . . . . . . . . . . . . . . . . . . . . . . 0.02%

• Single Supply Operation. . . . . . . . . . . . . . . . . +1.8V to +6.5V

• Low Power Consumption @ 3V (PD) . . . . . . . . . . . 24nW

• Fast Switching Action (V+ = +4.3V)

-t

ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43ns

-t

OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23ns

• ESD HBM Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >6kV

• Guaranteed Break-before-Make

• 1.8V Logic Compatible (+3V supply)

• Low I+ Current when VINH is not at the V+ Rail

• Available in 10 Ld µTQFN 1.8x1.4mm and 10 Ld 3x3mm

TDFN

Applications

• Audio and Video Switching

• Battery powered, Handheld, and Portable Equipment

- MP3 and Multimedia Players

- Cellular/mobile Phones

- Pagers

- Laptops, Notebooks, Palmtops

• Portable Test and Measurement

• Medical Equipment

Related Literature

• Technical Brief TB363 “Guidelines for Handling and

Processing Moisture Sensitive Surface Mount Devices

(SMDs)”

• Application Note AN557 “Recommended Test Procedures

for Analog Switches”

TABLE 1. FEATURES AT A GLANCE

ISL54062

Number of Switches 2

SW SPDT or 2-to-1 MUX

4.3V rON 0.57

4.3V tON/tOFF 43ns/23ns

2.7V rON 0.82

2.7V tON/tOFF 55ns/18ns

1.8V rON 1.8

1.8V tON/tOFF 145ns/28ns

Packages 10 Ld µTQFN, 10 Ld TDFN

rON ()

VCOM (V)

012 3 45

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

-1

-2-3

-4

-5

-6

ICOM = 100mA V+ = 1.8V

V+ = 2.7V

V+ = 4.5V

ON-RESISTANCE vs SUPPLY VOLTAGE vs

SWITCH VOLTAGE

ISL54062

FN6581 Rev 1.00 Page 2 of 16

Nov 3, 2009

Pinout (Note 1)

ISL54062

(10 LD TDFN)

TOP VIEW

ISL54062

(10 LD µTQFN)

TOP VIEW

NOTE:

1. Switches Shown for INx = Logic “0”.

IN1

NO1

COM1

NC1

GND

IN2

NO2

COM2

NC2

V+

CLICK

AND POP

CIRCUITRY

GND V+

NC2

COM2

NO2

NC1

COM1

NO1

IN1 IN2

CLICK

AND POP

CIRCUITRY

Truth Table

IN1 IN2 NC1 NO1 NC2 NO2

0 0 ON OFF ON OFF

0 1 ON OFF OFF ON

10OFFONONOFF

1 1 OFF ON OFF ON

NOTE: Logic “0” 0.5V. Logic “1” 1.4V with a 3V supply.

Pin Descriptions

PIN FUNCTION

V+ IC Power Supply (+1.8V to +6.5V). Decouple V+ to

ground by placing a 0.1µF capacitor at the V+ and GND

supply lines as near as the IC as possible.

GND Ground Connection

INx Digital Control Input

COMx Analog Switch Common Pin

NOx Analog Switch Normally Open Pin

NCx Analog Switch Normally Closed Pin

Ordering Information

PART

NUMBER

PART

MARKING

TEMP. RANGE

(°C)

PACKAGE

(Pb-Free)

PKG.

DWG. #

ISL54062IRTZ

(Note 3)

4062 -40 to +85 10 Ld 3x3 TDFN L10.3x3A

ISL54062IRTZ-T

(Notes 2, 3)

4062 -40 to +85 10 Ld 3x3 TDFN (Tape and Reel) L10.3x3A

ISL54062IRUZ-T

(Notes 2, 4)

8 -40 to +85 10 Ld Thin µTQFN (Tape and Reel) L10.1.8x1.4A

NOTES:

2. Please refer to TB347 for details on reel specifications.

3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte

tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil

Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-

020.

4. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu

plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products

are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

ISL54062

FN6581 Rev 1.00 Page 3 of 16

Nov 3, 2009

Absolute Maximum Ratings Thermal Information

V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 7.0V

Input Voltages

NOx, NCx (Note 5) . . . . . . . . . . . . . . . . (V+ - 7V) to ((V+) + 0.5V)

INx (Note 5) . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to ((V+) + 0.5V)

Output Voltages

COMx (Note 5) . . . . . . . . . . . . . . . . . . . (V+ - 7V) to ((V+) + 0.5V)

Continuous Current NOx, NCx, or COMx. . . . . . . . . . . . . ±300mA

Peak Current NOx, NCx, or COMx

(Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . . . ±500mA

ESD Rating:

Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>6kV

Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>400V

Charged Device Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . >1.5kV

Thermal Resistance (Typical) JA (°C/W) JC (°C/W)

10 Ld 3x3 TDFN Package (Notes 6, 8) 55 18

10 Ld µTQFN Package (Note 7) . . . . . 155 N/A

Maximum Junction Temperature (Plastic Package). . . . . . . +150°C

Maximum Storage Temperature Range . . . . . . . . . . . -65°C to +150°C

Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

Operating Conditions

Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C

Power Supply Range . . . . . . . . . . . . . . . . . . . . . . . . +1.8V to +6.5V

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and

result in failures not covered by warranty.

NOTES:

5. Signals on NC, NO, IN, or COM exceeding V+ or GND by specified amount are clamped by internal diodes. Limit forward diode current to

maximum current ratings.

6. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See

Tech Brief TB379.

7. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

8. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.

Electrical Specifications - 5V Supply Test Conditions: V+ = +4.5V to +5.5V, GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 9), Unless

Otherwise Specified.

PARAMETER TEST CONDITIONS

TEMP

(°C)

MIN

(Notes 10, 11) TYP

MAX

(Notes 10, 11) UNITS

ANALOG SWITCH CHARACTERISTICS

ON-Resistance, rON V+ = 4.5V, ICOM = 100mA, VNO or VNC = (V+ - 6.5)

to V+ (see Figure 5)

25 - 0.55 - 

Full - 0.68 - 

rON Matching Between Channels,

rON

V+ = 4.5V, ICOM = 100mA, VNO or VNC = Voltage at

max rON, (Note 13)

25 - 15 - m

Full - 30 - m

rON Flatness, RFLAT(ON) V+ = 4.5V, ICOM = 100mA, VNO or VNC = (V+ - 6.5)

to V+, (Note 12)

25 - 0.11 - 

Full - 0.14 - 

COM ON Leakage Current,

ICOM(ON)

V+ = 5V, VCOM = -1.5V, 5V, VNO or VNC = Float 25 - 49 - nA

Full - 0.7 - µA

DYNAMIC CHARACTERISTICS

Turn-ON Time, tON V+ = 4.5V, VNO or VNC = 3.0V, RL = 50,

CL= 35pF (see Figure 1)

25 - 35 - ns

Full - 50 - ns

Turn-OFF Time, tOFF V+ = 4.5V, VNO or VNC = 3.0V, RL = 50,

CL= 35pF (see Figure 1)

25 - 16 - ns

Full - 22 - ns

Break-Before-Make Time Delay, tDV+ = 5.5V, VNO or VNC = 3.0V, RL = 50,

CL= 35pF (see Figure 3)

Full - 18 - ns

Charge Injection, Q VG = 0V, RG = 0, CL = 1.0nF (see Figure 2) 25 - 170 - pC

OFF-Isolation RL = 50, CL = 5pF, f = 100kHz, VCOM = 1VRMS

(see Figure 4)

25 - 60 - dB

Crosstalk (Channel-to-Channel) RL = 50, CL = 5pF, f = 1MHz, VCOM = 1VRMS

(see Figure 6)

25 - -75 - dB

Total Harmonic Distortion f = 20Hz to 20kHz, VCOM = 0.5VP-P

, RL = 3225 - 0.02 - %

-3dB Bandwidth VCOM = 1VRMS, RL = 50CL = 5pF 25 - 60 - MHz

NO x or NCx OFF Capacitance,

COFF

f = 1MHz 25 - 36 - pF

ISL54062

FN6581 Rev 1.00 Page 4 of 16

Nov 3, 2009

COMx ON Capacitance,

CCOM(ON)

f = 1MHz (see Figure 7) 25 - 88 - pF

POWER SUPPLY CHARACTERISTICS

Positive Supply Current, I+ V+ = 5.5V, VIN = 0V or V+ 25 - 0.02 0.1 µA

Full - 2.5 - µA

DIGITAL INPUT CHARACTERISTICS

Input Voltage Low, VINL Full - - 0.8 V

Input Voltage High, VINH Full 2.4 - - V

Input Current, IINH, IINL V+ = 5.5V, VIN = 0V or V+ 25 -0.1 - 0.1 µA

Full - 0.89 - µA

Electrical Specifications - 4.3V SupplyTest Conditions: V+ = +3.9V to +4.5V, GND = 0V, VINH = 1.6V, VINL = 0.5V (Note 9), Unless

Otherwise Specified.

PARAMETER TEST CONDITIONS

TEMP

(°C)

MIN

(Notes 10, 11) TYP

MAX

(Notes 10, 11) UNITS

ANALOG SWITCH CHARACTERISTICS

ON-Resistance, rON V+ = 4.3V, ICOM = 100mA, VNO or VNC = (V+ - 6.5V)

to V+, (See Figure 5)

25 - 0.57 - 

Full - 0.68 - 

rON Matching Between

Channels, rON

V+ = 4.3V, ICOM = 100mA, VNO or VNC = Voltage at

max rON, (Note 12)

25 - 15 - m

Full - 30 - m

rON Flatness, RFLAT(ON) V+ = 4.3V, ICOM = 100mA, VNO or VNC = (V+ - 6.5V)

to V+, (Note 13)

25 - 0.1 - 

Full - 0.14 - 

COM ON Leakage Current,

ICOM(ON)

V+ = 4.3V, VCOM = -1.2V, 4.3V, VNO or VNC = Float 25 -0.1 - 0.1 µA

Full - 1.1 - µA

DYNAMIC CHARACTERISTICS

Turn-ON Time, tON V+ = 3.9V, VNO or VNC = 3.0V, RL = 50, CL = 35pF

(see Figure 1)

25 - 43 - ns

Full - 50 - ns

Turn-OFF Time, tOFF V+ = 3.9V, VNO or VNC = 3.0V, RL = 50, CL = 35pF

(see Figure 1)

25 - 23 - ns

Full - 23 - ns

Break-Before-Make Time Delay,

V+ = 4.5V, VNO or VNC = 3.0V, RL = 50, CL = 35pF

(see Figure 3)

Full - 22 - ns

Charge Injection, Q CL = 1.0nF, VG = 0V, RG = 0see Figure 2) 25 - 200 - pC

OFF-Isolation RL = 50, CL = 5pF, f = 100kHz, VCOM = 1VRMS

(see Figure 4)

25 - 60 - dB

Crosstalk (Channel-to-Channel) RL = 50, CL = 5pF, f = 1MHz, VCOM = 1VRMS

(see Figure 6)

25 - -75 - dB

Total Harmonic Distortion f = 20Hz to 20kHz, VCOM = 2VP-P

, RL = 3225 - 0.04 - %

NOx or NCx OFF Capacitance,

COFF

f = 1MHz 25 - 36 - pF

COMx ON Capacitance,

CCOM(ON)

f = 1MHz (see Figure 7) 25 - 88 - pF

Electrical Specifications - 5V Supply Test Conditions: V+ = +4.5V to +5.5V, GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 9), Unless

Otherwise Specified. (Continued)

PARAMETER TEST CONDITIONS

TEMP

(°C)

MIN

(Notes 10, 11) TYP

MAX

(Notes 10, 11) UNITS

ISL54062

FN6581 Rev 1.00 Page 5 of 16

Nov 3, 2009

POWER SUPPLY CHARACTERISTICS

Positive Supply Current, I+ V+ = +4.5V, VIN = 0V or V+ 25 - 0.003 0.1 µA

Full - 2.6 - µA

Positive Supply Current, I+ V+ = +4.2V, VIN = 2.85V 25 - 0.89 12 µA

DIGITAL INPUT CHARACTERISTICS

Input Voltage Low, VINL Full - - 0.5 V

Input Voltage High, VINH Full 1.6 - - V

Input Current, IINH, IINL V+ = 4.5V, VIN = 0V or V+ 25 -0.5 - 0.5 µA

Full - 0.5 - µA

Electrical Specifications - 3V Supply Test Conditions: V+ = +2.7V to +3.3V, GND = 0V, VINH = 1.4V, VINL = 0.5V (Note 9), Unless

Otherwise Specified.

PARAMETER TEST CONDITIONS

TEMP

(°C)

MIN

(Notes 10, 11) TYP

MAX

(Notes 10, 11) UNITS

ANALOG SWITCH CHARACTERISTICS

ON-Resistance, rON V+ = 2.7V, ICOM = 100mA, VNO or VNC = (V+ - 6.5V)

to V+ (see Figure 5)

25 - 0.82 - 

Full - 0.94 - 

rON Matching Between

Channels, rON

V+ = 2.7V, ICOM = 100mA, VNO or VNC = Voltage at

max rON (Note 13)

25 - 10 - m

Full - 30 - m

rON Flatness, RFLAT(ON) V+ = 2.7V, ICOM = 100mA, VNO or VNC = (V+ - 6.5V)

to V+ (Notes 12, 14)

25 - 0.35 0.5 

Full - 0.4 0.55 

DYNAMIC CHARACTERISTICS

Turn-ON Time, tON V+ = 2.7V, VNO or VNC = 1.5V, RL = 50, CL = 35pF

(see Figure 1)

25 - 55 - ns

Full - 82 - ns

Turn-OFF Time, tOFF V+ = 2.7V, VNO or VNC = 1.5V, RL = 50, CL = 35pF

(see Figure 1)

25 - 18 - ns

Full - 24 - ns

Break-Before-Make Time Delay,

V+ = 3.3V, VNO or VNC = 1.5V, RL = 50, CL = 35pF

(see Figure 3)

Full - 30 - ns

Charge Injection, Q CL = 1.0nF, VG = 0V, RG = 0see Figure 2) 25 - 150 - pC

OFF-Isolation RL = 50, CL = 5pF, f = 100kHz, VCOM = 1VRMS

(see Figure 4)

25 - 60 - dB

Crosstalk (Channel-to-Channel) RL = 50, CL = 5pF, f = 1MHz, VCOM = 1VRMS

(see Figure 6)

25 - -75 - dB

Total Harmonic Distortion f = 20Hz to 20kHz, VCOM = 0.5VP-P

, RL = 3225 - 0.04 - %

NOx or NCx OFF Capacitance,

COFF

f = 1MHz 25 - 36 - pF

COMx ON Capacitance,

CCOM(ON)

f = 1MHz (see Figure 7) 25 - 88 - pF

DIGITAL INPUT CHARACTERISTICS

Input Voltage Low, VINL 25 - - 0.5 V

Input Voltage High, VINH 25 1.4 - - V

Input Current, IINH, IINL V+ = 3.3V, VIN = 0V or V+ 25 -0.5 - 0.5 µA

Full - 0.4 - µA

Electrical Specifications - 4.3V SupplyTest Conditions: V+ = +3.9V to +4.5V, GND = 0V, VINH = 1.6V, VINL = 0.5V (Note 9), Unless

Otherwise Specified. (Continued)

PARAMETER TEST CONDITIONS

TEMP

(°C)

MIN

(Notes 10, 11) TYP

MAX

(Notes 10, 11) UNITS

ISL54062

FN6581 Rev 1.00 Page 6 of 16

Nov 3, 2009

Electrical Specifications - 1.8V Supply Test Conditions: V+ = +1.8V, GND = 0V, VINH = 1.0V, VINL = 0.4V (Note 9), Unless Otherwise

Specified.

PARAMETER TEST CONDITIONS

TEMP

(°C)

MIN

(Notes 10, 11) TYP

MAX

(Notes 10, 11) UNITS

ANALOG SWITCH CHARACTERISTICS

ON-Resistance, rON V+ = 1.8V, ICOM = 100mA, VNO or VNC = (V+ - 6.5V)

to V+, (see Figure 5)

25 - 1.87 - 

Full - 1.97 - 

rON Matching Between

Channels, rON

V+ = 1.8V, ICOM = 100mA, VNO or VNC = Voltage at

max rON (Note 13)

25 - 16 - m

Full - 30 - m

rON Flatness, RFLAT(ON) V+ = 1.8V, ICOM = 100mA, VNO or VNC = (V+ - 6.5V)

to V+ (Note 12)

25 - 1.34 - 

Full - 1.43 - 

DYNAMIC CHARACTERISTICS

Turn-ON Time, tON V+ = 1.8V, VNO or VNC = 1.8V, RL = 50, CL = 35pF

(see Figure 1)

25 - 145 - ns

Full - 150 - ns

Turn-OFF Time, tOFF V+ = 1.8V, VNO or VNC = 1.8V, RL = 50, CL = 35pF

(see Figure 1)

25 - 20 - ns

Full - 22 - ns

Break-Before-Make Time Delay,

V+ = 1.8V, VNO or VNC = 1.8V, RL = 50, CL = 35pF

(see Figure 3)

Full - 130 - ns

Charge Injection, Q CL = 1.0nF, VG = 0V, RG = 0see Figure 2) 25 - 40 - pC

-3dB Bandwidth VCOM = 1VRMS, RL = 50CL = 5pF 25 - 60 - MHz

NOx or NCx OFF Capacitance,

COFF

f = 1MHz 25 - 36 - pF

COMx ON Capacitance,

CCOM(ON)

f = 1MHz (see Figure 7) 25 - 88 - pF

DIGITAL INPUT CHARACTERISTICS

Input Voltage Low, VINL 25 - - 0.4 V

Input Voltage High, VINH 25 1.0 - - V

Input Current, IINH, IINL V+ = 2.0V, VIN = 0V or V+ 25 -0.5 - 0.5 µA

Input Current, IINH, IINL V+ = 2.0V, VIN = 0V or V+ Full - 0.38 - µA

NOTES:

9. VIN = input voltage to perform proper function.

10. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.

11. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by

characterization and are not production tested.

12. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range.

13. rON matching between channels is calculated by subtracting the channel with the highest max rON value from the channel with lowest max rON

value, between NC1 and NC2 or between NO1 and NO2.

14. Limits established by characterization and are not production tested.

ISL54062

FN6581 Rev 1.00 Page 7 of 16

Nov 3, 2009

Test Circuits and Waveforms

Logic input waveform is inverted for switches that have the opposite

logic sense.

FIGURE 1A. MEASUREMENT POINTS

Repeat test for all switches. CL includes fixture and stray

capacitance.

FIGURE 1B. TEST CIRCUIT

FIGURE 1. SWITCHING TIMES

FIGURE 2A. MEASUREMENT POINTS FIGURE 2B. TEST CIRCUIT

FIGURE 2. CHARGE INJECTION

FIGURE 3A. MEASUREMENT POINTS

Repeat test for all switches. CL includes fixture and stray

capacitance.

FIGURE 3B. TEST CIRCUIT

FIGURE 3. BREAK-BEFORE-MAKE TIME

50%

tr < 5ns

tf < 5ns

tOFF

90%

V+

VNO

tON

LOGIC

INPUT

SWITCH

INPUT

SWITCH

OUTPUT

90%

VOUT

VOUT V(NO or NC)

RLrON

------------------------

SWITCH

INPUT

LOGIC

INPUT

VOUT

RL CL

COM

NO OR NC

5035pF

GND

V+ C

VOUT

VOUT

OFF

Q = VOUT x CL

SWITCH

OUTPUT

LOGIC

INPUT

V+

VOUT

VGGND

COM

NO OR NC

V+ C

LOGIC

INPUT

Repeat test for all switches.

90%

V+

tBBM

LOGIC

INPUT

SWITCH

OUTPUT

VOUT

LOGIC

INPUT

COM

RLCL

VOUT

35pF

50

V+

GND

VNX

ISL54062

FN6581 Rev 1.00 Page 8 of 16

Nov 3, 2009

FIGURE 4. OFF-ISOLATION TEST CIRCUIT FIGURE 5. rON TEST CIRCUIT

FIGURE 6. CROSSTALK TEST CIRCUIT FIGURE 7. ON CAPACITANCE TEST CIRCUIT

Test Circuits and Waveforms (Continued)

ANALYZER

SIGNAL

GENERATOR

V+

0V OR V+

NO OR NC

COM

GND

Signal direction through switch is reversed, worst case values

are recorded. Repeat test for all switches.

*50 SOURCE

V+

0V OR V+

NO OR NC

COM

GND

VNX

rON = V1/100mA

100mA

Repeat test for all switches.

0V OR V+

ANALYZER

V+

NO1 OR NC1

SIGNAL

GENERATOR

GND

INX

COM1 50

COM2 NC2 OR NO2

Signal direction through switch is reversed, worst case values

are recorded. Repeat test for all switches.

*50 SOURCE

V+

GND

NO OR NC

COM

IMPEDANCE

ANALYZER

0V OR V+

ISL54062

FN6581 Rev 1.00 Page 9 of 16

Nov 3, 2009

Detailed Description

The ISL54062 is a bi-directional, dual single pole-double throw

(SPDT) analog switch that offers precise switching from a

single 1.8V to 6.5V supply with low ON-resistance (0.83),

high speed operation (tON = 55ns, tOFF = 18ns) and negative

signal swing capability. The device is especially well suited for

portable battery powered equipment due to its low operating

supply voltage (1.8V), low power consumption (20nA @ 3V),

and a tiny 1.8mmx1.4mm µTQFN package or a 3x3 TDFN

package. The low ON-resistance and rON flatness provide very

low insertion loss and signal distortion for applications that

require signal switching with minimal interference by the switch.

Supply Sequencing and Overvoltage Protection

With any CMOS device, proper power supply sequencing is

required to protect the device from excessive input currents

which might permanently damage the IC. The ISL54062

contains ESD protection diodes on each pin of the IC

(see Figure 9). These diodes connect to either a +Ring or

-Ring for ESD protection. To prevent forward biasing the ESD

diodes to the +Ring, V+ must be applied before any input

signals, and the input signal voltages must remain between

recommended operating range.

If these conditions cannot be guaranteed, then precautions

must be implemented to prohibit the current and voltage at the

logic pin and signal pins from exceeding the maximum ratings

of the switch. The following two methods can be used to

provided additional protection to limit the current in the event

that the voltage at a logic pin or switch terminal goes above the

V+ rail.

Logic inputs can be protected by adding a 1k resistor in

series with the logic input (see Figure 9). The resistor limits the

input current below the threshold that produces permanent

damage.

This method is not acceptable for the signal path inputs.

Adding a series resistor to the switch input defeats the purpose

of using a low rON switch. Alternatively, connecting external

Schottky diodes from the V+ rail to the signal pins will shunt the

fault current through the Schottky diode instead of through the

internal ESD diodes, thereby protecting the switch. These

Schottky diodes must be sized to handle the expected fault

current.

Power-Supply Considerations

The ISL54062 construction is typical of most single supply

CMOS analog switches which have two supply pins: V+ and

GND. V+ and GND provide the CMOS switch bias and sets

their analog voltage limits. Unlike switches with a 5.5V

maximum supply voltage, the ISL54062’s 6.5V maximum

supply voltage provides plenty of head room for the 10%

tolerance of 5V supplies due to overshoot and noise spikes.

The minimum recommended supply voltage is 1.8V. It is

important to note that the input signal range, switching times,

and ON-resistance degrade at lower supply voltages. Refer to

FIGURE 8A. CLICK AND POP WAVEFORM

FIGURE 8B. CLICK AND POP TEST CIRCUIT

FIGURE 8. CLICK AND POP ELIMINATION

Test Circuits and Waveforms (Continued)

VDC

VINx*

*VINx waveform for Click and Pop Elimination on NOx terminal.

For Click and Pop Elimination on NCx terminal invert VINx.

tD = 200ms measured at 50% points.

CLICK AND POP

CIRCUITRY

220uF

INx

COMx

NCx

NOx

VDC

GND

VCOMx VNCx

V+

LOGIC

INPUTS

VNOx

-RING

+RING

CLAMP

1k

FIGURE 9. OVERVOLTAGE PROTECTION

ISL54062

FN6581 Rev 1.00 Page 10 of 16

Nov 3, 2009

the “Electrical Specifications” tables, beginning on page 3, and

“Typical Performance Curves”, beginning on page 11, for

details.

V+ and GND also power the internal logic and level shifters.

The level shifters convert the input logic levels to V+ and GND

signals levels to drive the analog switch gate terminals. A high

frequency decoupling capacitor placed as close to the V+ and

GND pin as possible is recommended for proper operation of

the switch. A value of 0.1µF is highly recommended.

Negative Signal Swing Capability

The ISL54062 contains circuitry that allows the analog switch

signal to swing below ground. The device has an analog signal

range of 6.5V below V+ up to the V+ rail (see Figure 16) while

maintaining low rON performance. For example, if V+ = 5V,

then the analog input signal range is from -1.5V to +5V. If V+ =

2.7V then the range is from -3.8V to +2.7V.

Click and Pop Operation

The ISL54062 contains circuitry that prevents audible click and

pop noises that may occur when audio sources are powered

on or off. Single supply audio sources are biased at a DC offset

that can generate transients during power on/off. A DC

blocking capacitor is needed to remove the DC bias at the

speaker load. For 32 headphones, a 220µF capacitor is

typically used to preserve the audio bandwidth. The power

on/off transients are AC coupled by the 220µF capacitor to the

speaker load causing a click and pop noise.

The ISL54062 has shunt switches on the NO and NC pins to

eliminate click and pop transients (see Figure 10). These

switches are driven complimentary to the main switch. When

NC is connected to COM, the shunt switch is active on the NO

pin (and vice versa). The shunt switches connect an

impedance (140typical, see Figure 24) from the NO/NC pin

to ground to discharge any transients that may appear on the

NO or NC pins.

When a DC bias becomes active at the source, the NO and NC

terminals will also have a DC offset due to capacitor dv/dt

principle. The DC offset will be discharged through the shunt

impedance on the NO and NC terminals instead of the

speaker, eliminating click and pop noise.

*Under high impedance loads such as the input impedance of

pre-amplifiers (20k, the COM terminal voltage may rise due

to small leakage currents charging the COM capacitance. This

is not seen when low impedance loads such as headphones

(32) are used because the small leakage currents does not

result in significant potential drop across the load. If the user

desires to reduce the voltage build up on the COM pin, a 1k

resistor to ground may be placed on the COM pin. This

impedance is small enough to reduce the voltage build up

significantly while not increasing the power dissipation

dramatically. Current consumption considerations will need to

be taken for driving a smaller load impedance under this

scenario.

Click and Pop Elimination with INx Pin

Audio click and pop elimination can be driven with the Input

Select (INx) pin. When INx = 0, the NOx terminals are

connected to the shunt impedance. When INx = 1, the NCx

terminals are connected to the shunt impedance. In this

situation, only one of the source transient voltages will be

shunted to ground, depending on the Input Select state. The

Input Select pin should be driven 200ms after any source

transients occurs to prevent audible transients at the speaker

load.

Logic-Level Thresholds

This switch family is 1.8V CMOS compatible (0.45V VOLMAX

and 1.35V VOHMIN) over a supply range of 1.8V to 3.3V (see

Figure 18). At 3.3V the VIL level is 0.5V maximum. This is still

below the 1.8V CMOS guaranteed low output maximum level

of 0.45V, but noise margin is reduced to approximately 50mV.

At 3.3V the VIH level is 1.4V minimum. While this is above the

1.8V CMOS guaranteed high output minimum of 1.35V, under

most operating conditions the switch will recognize this as a

valid logic high.

The digital input stages draw supply current whenever the

digital input voltage is not at one of the supply rails. Driving the

digital input signals from GND to V+ with a fast transition time

minimizes power dissipation. The ISL54062 has been

designed to minimize the supply current whenever the digital

input voltage is not driven to the supply rails (0V to V+). For

example, driving the device with 2.85V logic high while

operating with a 4.2V supply the device draws only 1µA of

current.

High-Frequency Performance

In 50 systems, the ISL54062 has an ON switch -3dB

bandwidth of 60MHz (see Figure 21). The frequency response

COM

220µF

32

V+

GND

AUDIO

SOURCE A

220µF

AUDIO

SOURCE B RSH

ISL54062

FIGURE 10. CLICK AND POP OPERATION

ISL54062

FN6581 Rev 1.00 Page 11 of 16

Nov 3, 2009

is very consistent over a wide V+ range, and for varying analog

signal levels.

An OFF switch acts like a capacitor across the open terminals

and AC couples higher frequencies, resulting in signal feed-

through from a switch’s input to its output. Off-Isolation is the

resistance to this feed-through. Crosstalk indicates the amount

of feed-through from one switch channel to another switch

channel. Figure 22 details the high Off-Isolation and Crosstalk

rejection provided by this part. At 100kHz, Off-Isolation is about

60dB in 50 systems, decreasing approximately 20dB per

decade as frequency increases. At 1MHz, Crosstalk is about -

75dB in 50 systems, decreasing approximately 20dB per

decade as frequency increases.

Leakage Considerations

Reverse ESD protection diodes are internally connected between

each analog-signal pin, V+ and GND. One of these diodes

conducts if any analog signal exceeds the recommended analog

signal range.

Virtually all the analog switch leakage current comes from the

ESD diodes and reversed biased junctions in the switch cell.

Although the ESD diodes on a given signal pin are identical and

therefore fairly well balanced, they are reverse biased differently.

Each is biased to either the +Ring or -Ring and the analog input

signal. This means their leakages will vary as the signal varies.

The difference in the two diode leakages to the +Ring or -Ring

and the reverse biased junctions at the internal switch cell

constitutes the analog-signal-path leakage current.

Typical Performance Curves TA = +25°C, Unless Otherwise Specified

FIGURE 11. ON-RESISTANCE vs SUPPLY VOLTAGE vs

SWITCH VOLTAGE

FIGURE 12. ON-RESISTANCE vs SWITCH VOLTAGE

FIGURE 13. ON-RESISTANCE vs SWITCH VOLTAGE FIGURE 14. ON-RESISTANCE vs SWITCH VOLTAGE

rON ()

VCOM (V)

012 3 45

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

-1

-2-3

-4

-5

-6

ICOM = 100mA V+ = 1.8V

V+ = 2.7V

V+ = 4.5V

0.30

rON ()

VCOM (V)

0.35

0.40

0.45

0.50

0.60

0.65

0.70

0.75

0.80

0.85

0.95

0.90

1.00

0.55

-3-2-1 12345

ICOM = 100mA

V+ = 4.5V

T = +85°C

T = +25°C

T = -40°C

rON ()

VCOM (V)

0.30

0.35

0.40

0.45

0.50

0.60

0.65

0.70

0.75

0.80

0.85

0.95

0.90

0.55

-3-2-1 12345

1.00

ICOM = 100mA

V+ = 4.3V

T = +85°C

T = +25°C

T = -40°C

rON ()

VCOM (V)

1.05

0.35

0.45

0.65

0.75

0.85

0.95

0.55

-3 -2 -1 1 2 3 4-5 -4

1.15

1.25

ICOM = 100mA

V+ = 2.7V

T = +85°C

T = +25°C

T = -40°C

ISL54062

FN6581 Rev 1.00 Page 12 of 16

Nov 3, 2009

FIGURE 15. ON-RESISTANCE vs SWITCH VOLTAGE FIGURE 16. ANALOG SIGNAL RANGE vs SUPPLY VOLTAGE

FIGURE 17. CHARGE INJECTION vs SWITCH VOLTAGE FIGURE 18. DIGITAL SWITCHING POINT vs SUPPLY VOLTAGE

FIGURE 19. TURN-ON TIME vs SUPPLY VOLTAGE FIGURE 20. TURN-OFF TIME vs SUPPLY VOLTAGE

Typical Performance Curves TA = +25°C, Unless Otherwise Specified (Continued)

rON ()

VCOM (V)

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

2.2

0-3 -2 -1 1 2 36-5-4

ICOM = 100mA

V+ = 1.8V

T = +85°C

T = -40°C

T = +25°C

-6

-5

-4

-3

-2

-1

1.52.02.53.03.54.04.55.05.56.0

ANALOG SIGNAL RANGE (V)

SUPPLY VOLTAGE (V)

SIGNAL MAX

SIGNAL MIN

Q (pC)

VCOM (V)

100

150

012345-1-2-3-4-5 6

V+ = 4.5V

V+ = 3.3V

V+ = 2.0V

ABSOLUTE VALUES

V+ = 5.5V

200

250

300

350

400

450

500

550

600

650

700

ABSOLUTE VALUES

V+ (V)

VINH AND VINL (V)

1.52.02.53.03.54.04.5

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

1.1 VINH

VINL

0.2

0.1

1.6

1.5

1.4

1.3

1.2

tON (ns)

V+ (V)

T = +85°C

T = -40°C

T = +25°C

1.8 3.3 4.5 5.5

100

120

140

160

tOFF (ns)

V+ (V)

1.8 3.3 4.5 5.5

T = +85°C

T = -40°C

T = +25°C

ISL54062

FN6581 Rev 1.00 Page 13 of 16

Nov 3, 2009

FIGURE 21. FREQUENCY RESPONSE FIGURE 22. CROSSTALK AND OFF-ISOLATION

FIGURE 23. TOTAL HARMONIC DISTORTION vs FREQUENCY FIGURE 24. SHUNT RESISTANCE vs SWITCH VOLTAGE

Typical Performance Curves TA = +25°C, Unless Otherwise Specified (Continued)

FREQUENCY (Hz)

-1

NORMALIZED GAIN (dB)

VIN = 1VRMS @ 0VDC OFFSET

RL = 50

V+ = 1.8V TO 5.5V

-2

-3

-4

-5

1k 100k 1M 100M10k 10M 1G

FREQUENCY (Hz)

-110

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

CROSSTALK (dB)

OFF-ISOLATION

CROSSTALK

VIN = 1VRMS @ 0VDC OFFSET

RL = 50

V+ = 1.8V TO 5.5V

1k 100k 1M 100M10k 10M

FREQUENCY (Hz)

20 100 200 1k 2k 10k 20k

VBIAS = 0VDC

RL =32

V+ = 3.3V

707mVRMS

177mVRMS

0.01

0.02

0.03

0.04

0.05

THD+N (%)

360mVRMS

100

125

150

175

200

225

250

275

300

325

350

-5 -4 -3 -2 -1 0 1 2 3 4 5 6

SWITCH VOLTAGE (V)

V+ = 4.3V

V+ = 3V

V+ = 1.8V

V+ = 5V

FN6581 Rev 1.00 Page 14 of 16

Nov 3, 2009

ISL54062

Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted

in the quality certifications found at www.intersil.com/en/support/qualandreliability.html

Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such

modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are

current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its

subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

For additional products, see www.intersil.com/en/products.html

All trademarks and registered trademarks are the property of their respective owners.

FIGURE 25. CLICK AND POP ELIMINATION 20k LOAD

200ms DELAY

FIGURE 26. CLICK AND POP ELIMINATION 32 LOAD 200ms

DELAY

Die Characteristics

SUBSTRATE POTENTIAL (POWERED UP):

GND (DFN Paddle Connection: Tie to GND or Float)

TRANSISTOR COUNT:

432

PROCESS:

Submicron CMOS

Typical Performance Curves TA = +25°C, Unless Otherwise Specified (Continued)

(1V/DIV)

INx (1V/DIV)

(500mV/DIV)

TIME ( 200ms/DIV)

= 1.5VDC

= 20k



V+ = 3V

*See CLICK AND POP OPERATION

COM

(10mV/DIV)

TIME ( 200ms/DIV)

VDC (1V/DIV)

INx (1V/DIV)

VNO (500mV/DIV)

VCOM (10mV/DIV)

VDC = 1.5VDC

RL = 32

V+ = 3V

ISL54062

FN6581 Rev 1.00 Page 15 of 16

Nov 3, 2009

Thin Dual Flat No-Lead Plastic Package (TDFN)

NX (b)

SECTION "C-C"

FOR ODD TERMINAL/SIDE

TERMINAL TIP

(A1)

BOTTOM VIEW

AREA

INDEX

0.10

0.08

SIDE VIEW

0.10

C0.10

TOP VIEW

AREA

INDEX

NX L

E2/2

REF.

(Nd-1)Xe

(DATUM A)

(DATUM B)

0.10

BAC

N-1

PLANE

SEATING

NX b

D2/2

NX k

L10.3x3A

10 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE

SYMBOL

MILLIMETERS

NOTESMIN NOMINAL MAX

A 0.70 0.75 0.80 -

A1 - - 0.05 -

A3 0.20 REF -

b 0.20 0.25 0.30 5, 8

D 2.95 3.0 3.05 -

D2 2.25 2.30 2.35 7, 8

E 2.95 3.0 3.05 -

E2 1.45 1.50 1.55 7, 8

e 0.50 BSC -

k0.25- - -

L 0.25 0.30 0.35 8

N102

Nd 5 3

Rev. 3 3/06

NOTES:

1. Dimensioning and tolerancing conform to ASME Y14.5-1994.

2. N is the number of terminals.

3. Nd refers to the number of terminals on D.

4. All dimensions are in millimeters. Angles are in degrees.

5. Dimension b applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

6. The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 identifier may be

either a mold or mark feature.

7. Dimensions D2 and E2 are for the exposed pads which provide

improved electrical and thermal performance.

8. Nominal dimensions are provided to assist with PCB Land

Pattern Design efforts, see Intersil Technical Brief TB389.

9. Compliant to JEDEC MO-229-WEED-3 except for D2

dimensions.

ISL54062

FN6581 Rev 1.00 Page 16 of 16

Nov 3, 2009

Ultra Thin Quad Flat No-Lead Plastic Package (UTQFN)

0.10 C

0.05 CA

0.10 C

SEATING PLANE

INDEX AREA

TOP VIEW

SIDE VIEW

NX (b)

SECTION "C-C" e

TERMINAL TIP

(A1)

0.10 C

NX L

BOTTOM VIEW

PIN #1 ID

(DATUM A)

(DATUM B)

0.10 M CAB

0.05 M C

NX b

10X

0.50

0.20

0.40

1.80

0.40

0.20

2.20

1.00

0.60

1.00

LAND PATTERN

L10.1.8x1.4A

10 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC

PACKAGE

SYMBOL

MILLIMETERS

NOTESMIN NOMINAL MAX

A 0.45 0.50 0.55 -

A1 - - 0.05 -

A3 0.127 REF -

b 0.15 0.20 0.25 5

D 1.75 1.80 1.85 -

E 1.35 1.40 1.45 -

e 0.40 BSC -

L 0.35 0.40 0.45 -

L1 0.45 0.50 0.55 -

N102

Nd 2 3

Ne 3 3

0-124

Rev. 3 6/06

NOTES:

1. Dimensioning and tolerancing conform to ASME Y14.5-1994.

2. N is the number of terminals.

3. Nd and Ne refer to the number of terminals on D and E side,

respectively.

4. All dimensions are in millimeters. Angles are in degrees.

5. Dimension b applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

6. The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 identifier may be

either a mold or mark feature.

7. Maximum package warpage is 0.05mm.

8. Maximum allowable burrs is 0.076mm in all directions.

9. JEDEC Reference MO-255.

10. For additional information, to assist with the PCB Land Pattern

Design effort, see Intersil Technical Brief TB389.