Intel(R) Arria(R) 10 Device Datasheet Subscribe Send Feedback A10-DATASHEET | 2018.11.29 Latest document on the web: PDF | HTML Contents Contents Intel(R) Arria(R) 10 Device Datasheet............................................................................................................................................. 3 Electrical Characteristics...................................................................................................................................................... 3 Operating Conditions.................................................................................................................................................. 3 Switching Characteristics....................................................................................................................................................23 Transceiver Performance Specifications....................................................................................................................... 24 Core Performance Specifications.................................................................................................................................35 Periphery Performance Specifications.......................................................................................................................... 45 HPS Specifications....................................................................................................................................................54 Configuration Specifications................................................................................................................................................ 82 POR Specifications....................................................................................................................................................82 JTAG Configuration Timing.........................................................................................................................................83 FPP Configuration Timing.......................................................................................................................................... 84 AS Configuration Timing............................................................................................................................................88 DCLK Frequency Specification in the AS Configuration Scheme....................................................................................... 89 PS Configuration Timing............................................................................................................................................89 Initialization............................................................................................................................................................ 91 Configuration Files....................................................................................................................................................91 Minimum Configuration Time Estimation......................................................................................................................93 Remote System Upgrades......................................................................................................................................... 95 User Watchdog Internal Circuitry Timing Specifications..................................................................................................95 I/O Timing....................................................................................................................................................................... 95 Programmable IOE Delay................................................................................................................................................... 96 Glossary.......................................................................................................................................................................... 97 Document Revision History for the Intel Arria 10 Device Datasheet.........................................................................................100 Intel(R) Arria(R) 10 Device Datasheet 2 Send Feedback A10-DATASHEET | 2018.11.29 Send Feedback Intel(R) Arria(R) 10 Device Datasheet This datasheet describes the electrical characteristics, switching characteristics, configuration specifications, and I/O timing for Intel(R) Arria(R) 10 devices. Intel Arria 10 devices are offered in extended and industrial grades. Extended devices are offered in -E1 (fastest), -E2, and - E3 speed grades. Industrial grade devices are offered in the -I1, -I2, and -I3 speed grades. The suffix after the speed grade denotes the power options offered in Intel Arria 10 devices. * L--Low static power * S--Standard power * V--Supported with the SmartVID feature (lowest static power) * H--High performance power Related Information Intel Arria 10 Device Overview Provides more information about the densities and packages of devices in the Intel Arria 10 family. Electrical Characteristics The following sections describe the operating conditions and power consumption of Intel Arria 10 devices. Operating Conditions Intel Arria 10 devices are rated according to a set of defined parameters. To maintain the highest possible performance and reliability of the Intel Arria 10 devices, you must consider the operating requirements described in this section. Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others. ISO 9001:2015 Registered Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 Absolute Maximum Ratings This section defines the maximum operating conditions for Intel Arria 10 devices. The values are based on experiments conducted with the devices and theoretical modeling of breakdown and damage mechanisms. The functional operation of the device is not implied for these conditions. Caution: Conditions outside the range listed in the following table may cause permanent damage to the device. Additionally, device operation at the absolute maximum ratings for extended periods of time may have adverse effects on the device. Table 1. Absolute Maximum Ratings for Intel Arria 10 Devices Symbol Description Condition Minimum Maximum Unit V VCC Core voltage power supply -- -0.50 1.21 VCCP Periphery circuitry and transceiver fabric interface power supply -- -0.50 1.21 V VCCERAM Embedded memory power supply -- -0.50 1.36 V VCCPT Power supply for programmable power technology and I/O pre-driver -- -0.50 2.46 V VCCBAT Battery back-up power supply for design security volatile key register -- -0.50 2.46 V VCCPGM Configuration pins power supply (1) -0.50 2.46 V VCCIO I/O buffers power supply 3 V I/O -0.50 4.10 V LVDS I/O -0.50 2.46 V VCCA_PLL Phase-locked loop (PLL) analog power supply -- -0.50 2.46 V VCCT_GXB Transmitter power supply -- -0.50 1.34 V VCCR_GXB Receiver power supply -- -0.50 1.34 V VCCH_GXB Transceiver output buffer power supply -- -0.50 2.46 V VCCL_HPS HPS core voltage and periphery circuitry power supply -- -0.50 1.27 V VCCIO_HPS HPS I/O buffers power supply 3 V I/O -0.50 4.10 V LVDS I/O -0.50 2.46 V -- -0.50 2.46 VCCIOREF_HPS HPS I/O pre-driver power supply V continued... (1) The LVDS I/O values are applicable to all dedicated and dual-function configuration I/Os. Intel(R) Arria(R) 10 Device Datasheet 4 Send Feedback Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 Symbol VCCPLL_HPS Description HPS PLL power supply Condition Minimum Maximum Unit -- -0.50 2.46 V 25 mA -25 (2)(3)(4)(5) IOUT DC output current per pin -- TJ Operating junction temperature -- -55 125 C TSTG Storage temperature (no bias) -- -65 150 C (6) Related Information * AN 692: Power Sequencing Considerations for Intel Cyclone 10 GX, Intel Arria 10, and Intel Stratix 10 Devices Provides the power sequencing requirements for Intel Arria 10 devices. * Power-Up and Power-Down Sequences, Power Management in Intel Arria 10 Devices chapter Provides the power sequencing requirements for Intel Arria 10 devices. Maximum Allowed Overshoot and Undershoot Voltage During transitions, input signals may overshoot to the voltage listed in the following table and undershoot to -2.0 V for input currents less than 100 mA and periods shorter than 20 ns. The maximum allowed overshoot duration is specified as a percentage of high time over the lifetime of the device. A DC signal is equivalent to 100% duty cycle. For example, a signal that overshoots to 2.70 V for LVDS I/O can only be at 2.70 V for ~4% over the lifetime of the device. (2) The maximum current allowed through any LVDS I/O bank pin when the device is not turned on or during power-up/power-down conditions is 10 mA. (3) Total current per LVDS I/O bank must not exceed 100 mA. (4) Voltage level must not exceed 1.89 V. (5) Applies to all I/O standards and settings supported by LVDS I/O banks, including single-ended and differential I/Os. (6) Applies only to LVDS I/O banks. 3 V I/O banks are not covered under this specification and must be implemented as per the power sequencing requirement. For more details, refer to AN 692: Power Sequencing Considerations for Intel Cyclone(R) 10 GX, Intel Arria 10, and Intel Stratix(R) 10 Devices and Power Management in Intel Arria 10 Devices chapter. Send Feedback Intel(R) Arria(R) 10 Device Datasheet 5 Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 Table 2. Maximum Allowed Overshoot During Transitions for Intel Arria 10 Devices This table lists the maximum allowed input overshoot voltage and the duration of the overshoot voltage as a percentage of device lifetime. The LVDS I/O values are applicable to the VREFP_ADC and VREFN_ADC I/O pins. Symbol Description Condition (V) LVDS I/O Vi (AC) AC input voltage (7) Overshoot Duration as % at TJ = 100C Unit 3 V I/O 2.50 3.80 100 % 2.55 3.85 42 % 2.60 3.90 18 % 2.65 3.95 9 % 2.70 4.00 4 % > 2.70 > 4.00 No overshoot allowed % For an overshoot of 2.5 V, the percentage of high time for the overshoot can be as high as 100% over a 10-year period. Percentage of high time is calculated as ([delta T]/T) x 100. This 10-year period assumes that the device is always turned on with 100% I/O toggle rate and 50% duty cycle signal. (7) The LVDS I/O values are applicable to all dedicated and dual-function configuration I/Os. Intel(R) Arria(R) 10 Device Datasheet 6 Send Feedback Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 Figure 1. Intel Arria 10 Devices Overshoot Duration 2.71 V 2.7V 1.8 V DT T Recommended Operating Conditions This section lists the functional operation limits for the AC and DC parameters for Intel Arria 10 devices. Send Feedback Intel(R) Arria(R) 10 Device Datasheet 7 Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 Recommended Operating Conditions Table 3. Recommended Operating Conditions for Intel Arria 10 Devices This table lists the steady-state voltage values expected from Intel Arria 10 devices. Power supply ramps must all be strictly monotonic, without plateaus. Symbol VCC Description Core voltage power supply Condition Standard and low power Periphery circuitry and transceiver fabric interface power supply VCCERAM Embedded memory power supply (11) Battery back-up power supply (For design security volatile key register) (8) Unit V 0.92 0.95 0.98 V 0.82 -- 0.93 V 0.87 0.9 0.93 V 0.92 0.95 0.98 V 0.82 -- 0.93 V 1.8 V 1.71 1.8 1.89 V 1.5 V 1.425 1.5 1.575 V 1.2 V 1.14 1.2 1.26 V 0.87 0.9 0.93 V 0.92 0.95 0.98 V 1.14 -- 1.89 V 0.9 V 0.95 V VCCBAT Maximum 0.93 (10) Standard and low power Configuration pins power supply Typical 0.9 SmartVID VCCPGM (9) (8) 0.87 SmartVID VCCP Minimum -- (10) (9) (9) (9) continued... (8) This value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the PDN tool for the additional budget for the dynamic tolerance requirements. (9) You can operate -1 and -2 speed grade devices at 0.9 V or 0.95 V typical value. You can operate -3 speed grade device only at 0.9 V typical value. Operating at 0.95 V results in higher core performance and higher power consumption. Refer to core performance in this datasheet for different typical values. For more information about the power consumption of different typical values, refer to the Intel Quartus(R) Prime software, Power Analyzer report, and Early Power Estimator (EPE). (10) SmartVID is supported in devices with -3V speed grades only. (11) If you do not use the design security feature in Intel Arria 10 devices, connect VCCBAT to a 1.5-V to 1.8-V power supply. Intel Arria 10 power-on reset (POR) circuitry monitors VCCBAT. Intel Arria 10 devices do not exit POR if VCCBAT is not powered up. Intel(R) Arria(R) 10 Device Datasheet 8 Send Feedback Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 Symbol VCCPT Power supply for programmable power technology and I/O pre-driver VCCIO I/O buffers power supply Condition Minimum (8) Typical Maximum (8) Unit 1.8 V 1.71 1.8 1.89 V 3.0 V (for 3 V I/O only) 2.85 3.0 3.15 V 2.5 V (for 3 V I/O only) 2.375 2.5 2.625 V 1.8 V 1.71 1.8 1.89 V 1.5 V 1.425 1.5 1.575 V 1.35 V (12) 1.35 (12) V 1.25 V 1.19 1.25 1.31 V V 1.2 V (12) 1.2 (12) VCCA_PLL PLL analog voltage regulator power supply -- 1.71 1.8 1.89 V VREFP_ADC Precision voltage reference for voltage sensor -- 1.2475 1.25 1.2525 V 3 V I/O -0.3 -- 3.3 V LVDS I/O -0.3 -- 2.19 V -- 0 -- VCCIO V Extended 0 -- 100 C Industrial -40 -- 100 C Standard POR 200 s -- 100 ms -- Fast POR 200 s -- 4 ms -- VI (13)(14) DC input voltage VO Output voltage TJ Operating junction temperature tRAMP (8) Description (15)(16) Power supply ramp time This value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the PDN tool for the additional budget for the dynamic tolerance requirements. (12) For minimum and maximum voltage values, refer to the I/O Standard Specifications section. (13) The LVDS I/O values are applicable to all dedicated and dual-function configuration I/Os. (14) This value applies to both input and tri-stated output configuration. Pin voltage should not be externally pulled higher than the maximum value. Send Feedback Intel(R) Arria(R) 10 Device Datasheet 9 Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 Related Information I/O Standard Specifications on page 18 Transceiver Power Supply Operating Conditions Table 4. Transceiver Power Supply Operating Conditions for Intel Arria 10 GX/SX Devices Symbol VCCT_GXB [L1,R4] [C, D, E, F, G, H, I, J] (19) VCCR_GXB[L1,R4] [C, D, E, F, G, H, I, J] (19) VCCH_GXB[L,R] Description Transmitter power supply Receiver power supply Transceiver output buffer power supply Condition (17) Minimum (18) Typical Maximum (18) Unit Chip-to-Chip 17.4 Gbps Or Backplane (20) 12.5 Gbps 1.0 1.03 1.06 V Chip-to-Chip 11.3 Gbps 0.92 0.95 0.98 V Chip-to-Chip 17.4 Gbps Or Backplane (20) 12.5 Gbps 1.0 1.03 1.06 V Chip-to-Chip 11.3 Gbps 0.92 0.95 0.98 V -- 1.710 1.8 1.890 V (15) This is also applicable to HPS power supply. For HPS power supply, refer to tRAMP specifications for standard POR when HPS_PORSEL = 0 and tRAMP specifications for fast POR when HPS_PORSEL = 1. (16) tramp is the ramp time of each individual power supply, not the ramp time of all combined power supplies. (17) These data rate ranges vary depending on the transceiver speed grade. Refer to Transceiver Performance for Intel Arria 10 GX/SX Devices for exact data rate ranges. (18) This value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the PDN tool for the additional budget for the dynamic tolerance requirements. (19) To support PCIe* Gen3, this pin must be 1.03 V ( 30 mV) or higher. (20) Backplane applications assume advanced equalization circuitry, such as decision feedback equalization (DFE), is enabled to compensate for signal impairments. Chip-to-chip links are assumed to be applications with short reach channels that do not require DFE. Intel(R) Arria(R) 10 Device Datasheet 10 Send Feedback Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 Note: Most VCCR_GXB and VCCT_GXB pins associated with unused transceiver channels can be grounded on a per-side basis to minimize power consumption. Refer to the Intel Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines and the Intel Quartus Prime pin report for information about pinning out the package to minimize power consumption for your specific design. Table 5. Transceiver Power Supply Operating Conditions for Intel Arria 10 GT Devices Symbol VCCT_GXB[L,R] Description Transmitter power supply VCCR_GXB[L,R] Receiver power supply VCCH_GXB[L,R] Transceiver output buffer power supply Condition (21) Minimum (22) Chip-to-Chip 25.8 Gbps Or Backplane (20) 12.5 Gbps (18) Typical Maximum (18) Unit 1.10 1.12 1.14 V Chip-to-Chip 15 Gbps Or Backplane (20) 12.5 Gbps 1.0 1.03 1.06 V Chip-to-Chip 11.3 Gbps 0.92 0.95 0.98 V Chip-to-Chip 25.8 Gbps Or Backplane (20) 12.5 Gbps 1.10 1.12 1.14 V Chip-to-Chip 15 Gbps Or Backplane (20) 12.5 Gbps 1.0 1.03 1.06 V Chip-to-Chip 11.3 Gbps 0.92 0.95 0.98 V -- 1.710 1.8 1.890 V Related Information * Transceiver Performance for Intel Arria 10 GT Devices on page 26 Provides the data rate ranges for different transceiver speed grades. * Transceiver Performance for Intel Arria 10 GX/SX Devices on page 24 Provides the data rate ranges for different transceiver speed grades. (21) These data rate ranges vary depending on the transceiver speed grade. Refer to Transceiver Performance for Intel Arria 10 GT Devices table for exact data rate ranges. (22) 25.8 Gbps is the maximum data rate for GT channels. 17.4 Gbps is the maximum data rate for GX channels. Send Feedback Intel(R) Arria(R) 10 Device Datasheet 11 Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 * Intel Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines HPS Power Supply Operating Conditions Table 6. HPS Power Supply Operating Conditions for Intel Arria 10 SX Devices This table lists the steady-state voltage and current values expected from Intel Arria 10 system-on-a-chip (SoC) devices with ARM*-based hard processor system (HPS). Power supply ramps must all be strictly monotonic, without plateaus. Refer to Recommended Operating Conditions for Intel Arria 10 Devices table for the steady-state voltage values expected from the FPGA portion of the Intel Arria 10 SoC devices. Description Symbol VCCL_HPS HPS core voltage and periphery circuitry power supply VCCIO_HPS HPS I/O buffers power supply (23) Minimum (24) 0.87 0.9 0.93 V 0.92 0.95 0.98 V 3.0 V 2.85 3.0 3.15 V 2.5 V 2.375 2.5 2.625 V 1.8 V 1.71 1.8 1.89 V 0.9 V 0.95 V (24) Typical Maximum (23) Condition Unit VCCIOREF_HPS HPS I/O pre-driver power supply -- 1.71 1.8 1.89 V VCCPLL_HPS HPS PLL analog voltage regulator power supply -- 1.71 1.8 1.89 V Related Information * Recommended Operating Conditions on page 8 Provides the steady-state voltage values for the FPGA portion of the device. * HPS Clock Performance on page 56 Provides the maximum HPS clock frequencies. (23) This value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the PDN tool for the additional budget for the dynamic tolerance requirements. (24) VCCL_HPS options are valid under the operating conditions specified in the Maximum HPS Clock Frequencies table. Intel(R) Arria(R) 10 Device Datasheet 12 Send Feedback Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 DC Characteristics Supply Current and Power Consumption Intel offers two ways to estimate power for your design--the Excel-based Early Power Estimator (EPE) and the Intel Quartus Prime Power Analyzer feature. Use the Excel-based EPE before you start your design to estimate the supply current for your design. The EPE provides a magnitude estimate of the device power because these currents vary greatly with the usage of the resources. The Intel Quartus Prime Power Analyzer provides better quality estimates based on the specifics of the design after you complete place-and-route. The Power Analyzer can apply a combination of user-entered, simulation-derived, and estimated signal activities that, when combined with detailed circuit models, yield very accurate power estimates. Related Information * Early Power Estimator for Intel Arria 10 User Guide Provides more information about power estimation tools. * Power Analysis and Optimization User Guide: Intel Quartus Prime Pro Edition Provides more information about power estimation tools. I/O Pin Leakage Current Table 7. I/O Pin Leakage Current for Intel Arria 10 Devices If VO = VCCIO to VCCIOMAX, 300 A of leakage current per I/O is expected. Symbol Description Condition Min Max Unit II Input pin VI = 0 V to VCCIOMAX -80 80 A IOZ Tri-stated I/O pin VO = 0 V to VCCIOMAX -80 80 A Bus Hold Specifications The bus-hold trip points are based on calculated input voltages from the JEDEC* standard. Send Feedback Intel(R) Arria(R) 10 Device Datasheet 13 Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 Table 8. Bus Hold Parameters for Intel Arria 10 Devices Parameter Symbol Condition VCCIO (V) 1.2 1.5 Unit 1.8 2.5 3.0 Min Max Min Max Min Max Min Max Min Max Bus-hold, low, sustaining current ISUSL VIN > VIL (max) 8 (25), 26 (26) -- 12 (25), 32 (26) -- 30 (25), 55 (26) -- 60 -- 70 -- A Bus-hold, high, sustaining current ISUSH VIN < VIH (min) -8 (25), -26 (26) -- -12 (25), -32 (26) -- -30 (25), -55 (26) -- -60 -- -70 -- A Bus-hold, low, overdrive current IODL 0 V < VIN < VCCIO -- 125 -- 175 -- 200 -- 300 -- 500 A Bus-hold, high, overdrive current IODH 0 V < VIN < VCCIO -- -125 -- -175 -- -200 -- -300 -- -500 A Bus-hold trip point VTRIP -- 0.3 0.9 0.38 1.13 0.68 1.07 0.70 1.7 0.8 2 V OCT Calibration Accuracy Specifications If you enable on-chip termination (OCT) calibration, calibration is automatically performed at power up for I/Os connected to the calibration block. (25) This value is only applicable for LVDS I/O bank. (26) This value is only applicable for 3 V I/O bank. Intel(R) Arria(R) 10 Device Datasheet 14 Send Feedback Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 Table 9. OCT Calibration Accuracy Specifications for Intel Arria 10 Devices Calibration accuracy for the calibrated on-chip series termination (RS OCT) and on-chip parallel termination (RT OCT) are applicable at the moment of calibration. When process, voltage, and temperature (PVT) conditions change after calibration, the tolerance may change. Symbol Condition (V) Resistance Tolerance Unit -E1, -I1 -E2, -I2 -E3, -I3 25- and 50- RS Internal series termination with calibration (25- and 50- setting) VCCIO = 1.8, 1.5, 1.2 15 15 15 % 34- and 40- RS Internal series termination with calibration (34- and 40- setting) VCCIO = 1.5, 1.25, 1.2 15 15 15 % VCCIO = 1.35 20 20 20 % 48-, 60-, 80-, and 120- RS Internal series termination with calibration (48-, 60-, 80-, and 120- setting) VCCIO = 1.2 15 15 15 % 240- RS Internal series termination with calibration (240- setting) VCCIO = 1.2 20 20 20 % 30- RT Internal parallel termination with calibration (30- setting) VCCIO = 1.5, 1.35, 1.25 -10 to +40 -10 to +40 -10 to +40 % 34-, 48-, 80-, and 240- RT Internal parallel termination with calibration (34-, 48-, 80-, and 240- setting) VCCIO = 1.2 15 15 15 % 40-, 60-, and 120- RT Internal parallel termination with calibration (40-, 60-, and 120- setting) VCCIO = 1.5, 1.35, 1.25, 1.2 -10 to +40 -10 to +40 -10 to +40 % (27) 15 15 15 % Internal parallel termination with calibration (80- setting) VCCIO = 1.2 15 15 15 % 80- RT (27) Description VCCIO = 1.2 Only applicable to POD12 I/O standard. Send Feedback Intel(R) Arria(R) 10 Device Datasheet 15 Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 OCT Without Calibration Resistance Tolerance Specifications Table 10. OCT Without Calibration Resistance Tolerance Specifications for Intel Arria 10 Devices This table lists the Intel Arria 10 OCT without calibration resistance tolerance to PVT changes. Symbol 25- and 50- RS Description Internal series termination without calibration (25- and 50- setting) Condition (V) Resistance Tolerance Unit -E1, -I1 -E2, -I2 -E3, -I3 VCCIO = 3.0, 2.5 -40 to +30 40 40 % VCCIO = 1.8, 1.5, 1.2 -50 to +30 50 50 % 34- and 40- RS Internal series termination without calibration (34- and 40- setting) VCCIO = 1.5, 1.35, 1.25, 1.2 -50 to +30 50 50 % 48- and 60- RS Internal series termination without calibration (48- and 60- setting) VCCIO = 1.2 -50 to +30 50 50 % 120- Rs Internal series termination without calibration (120- setting) VCCIO = 1.2 -50 to +30 50 50 % 100- RD Internal differential termination (100- setting) VCCIO = 1.8 25 35 40 % Pin Capacitance Table 11. Pin Capacitance for Intel Arria 10 Devices Symbol Description Maximum Unit CIO_COLUMN Input capacitance on column I/O pins 2.5 pF COUTFB Input capacitance on dual-purpose clock output/feedback pins 2.5 pF Internal Weak Pull-Up and Weak Pull-Down Resistor All I/O pins, except configuration, test, and JTAG pins, have an option to enable weak pull-up. The weak pull-down feature is only available for the pins as described in the Internal Weak Pull-Down Resistor Values for Intel Arria 10 Devices table. Intel(R) Arria(R) 10 Device Datasheet 16 Send Feedback Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 Table 12. Internal Weak Pull-Up Resistor Values for Intel Arria 10 Devices Symbol RPU Description Condition (V) Value of the I/O pin pull-up resistor before and during configuration, as well as user mode if you have enabled the programmable pull-up resistor option. Table 13. (28) Value (29) Unit VCCIO = 3.0 5% 25 k VCCIO = 2.5 5% 25 k VCCIO = 1.8 5% 25 k VCCIO = 1.5 5% 25 k VCCIO = 1.35 5% 25 k VCCIO = 1.25 5% 25 k VCCIO = 1.2 5% 25 k Internal Weak Pull-Down Resistor Values for Intel Arria 10 Devices Pin Name Description Condition (V) Value (29) Unit nIO_PULLUP Dedicated input pin that determines the internal pull-ups on user I/O pins and dual-purpose I/O pins. VCC = 0.9 3.33% 25 k TCK Dedicated JTAG test clock input pin. VCCPGM = 1.8 5 % 25 k VCCPGM = 1.5 5% 25 k VCCPGM = 1.2 5% 25 k VCCPGM = 1.8 5% 25 k VCCPGM = 1.5 5% 25 k VCCPGM = 1.2 5% 25 k Configuration input pins that set the configuration scheme for the FPGA device. MSEL[0:2] Related Information Intel Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines Provides more information about the pins that support internal weak pull-up and internal weak pull-down features. (28) Pin pull-up resistance values may be lower if an external source drives the pin higher than VCCIO. (29) Valid with 25% tolerances to cover changes over PVT. Send Feedback Intel(R) Arria(R) 10 Device Datasheet 17 Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 I/O Standard Specifications Tables in this section list the input voltage (VIH and VIL), output voltage (VOH and VOL), and current drive characteristics (IOH and IOL) for various I/O standards supported by Intel Arria 10 devices. For minimum voltage values, use the minimum VCCIO values. For maximum voltage values, use the maximum VCCIO values. You must perform timing closure analysis to determine the maximum achievable frequency for general purpose I/O standards. Related Information Recommended Operating Conditions on page 8 Single-Ended I/O Standards Specifications Table 14. Single-Ended I/O Standards Specifications for Intel Arria 10 Devices I/O Standard (30) VCCIO (V) VIH (V) VOL (V) VOH (V) IOL (30) (mA) IOH (30) (mA) Min Typ Max Min Max Min Max Max Min 3.0-V LVTTL 2.85 3 3.15 -0.3 0.8 1.7 3.3 0.4 2.4 2 -2 3.0-V LVCMOS 2.85 3 3.15 -0.3 0.8 1.7 3.3 0.2 VCCIO - 0.2 0.1 -0.1 2.5 V 2.375 2.5 2.625 -0.3 0.7 1.7 3.3 0.4 2 1 -1 1.8 V 1.71 1.8 1.89 -0.3 0.35 x VCCIO 0.65 x VCCIO VCCIO + 0.3 0.45 VCCIO - 0.45 2 -2 1.5 V 1.425 1.5 1.575 -0.3 0.35 x VCCIO 0.65 x VCCIO VCCIO + 0.3 0.25 x VCCIO 0.75 x VCCIO 2 -2 1.2 V 1.14 1.2 1.26 -0.3 0.35 x VCCIO 0.65 x VCCIO VCCIO + 0.3 0.25 x VCCIO 0.75 x VCCIO 2 -2 To meet the IOL and IOH specifications, you must set the current strength settings accordingly. For example, to meet the 3.0-V LVTTL specification (2 mA), you should set the current strength settings to 2 mA. Setting at lower current strength may not meet the IOL and IOH specifications in the datasheet. Intel(R) Arria(R) 10 Device Datasheet 18 VIL (V) Send Feedback Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications Table 15. Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications for Intel Arria 10 Devices I/O Standard VCCIO (V) VREF (V) VTT (V) Min Typ Max Min Typ Max Min Typ Max SSTL-18 Class I, II 1.71 1.8 1.89 0.833 0.9 0.969 VREF - 0.04 VREF VREF + 0.04 SSTL-15 Class I, II 1.425 1.5 1.575 0.49 x VCCIO 0.5 x VCCIO 0.51 x VCCIO 0.49 x VCCIO 0.5 x VCCIO 0.51 x VCCIO SSTL-135/ SSTL-135 Class I, II 1.283 1.35 1.418 0.49 x VCCIO 0.5 x VCCIO 0.51 x VCCIO 0.49 x VCCIO 0.5 x VCCIO 0.51 x VCCIO SSTL-125/ SSTL-125 Class I, II 1.19 1.25 1.31 0.49 x VCCIO 0.5 x VCCIO 0.51 x VCCIO 0.49 x VCCIO 0.5 x VCCIO 0.51 x VCCIO SSTL-12/ SSTL-12 Class I, II 1.14 1.2 1.26 0.49 x VCCIO 0.5 x VCCIO 0.51 x VCCIO 0.49 x VCCIO 0.5 x VCCIO 0.51 x VCCIO HSTL-18 Class I, II 1.71 1.8 1.89 0.85 0.9 0.95 -- VCCIO/2 -- HSTL-15 Class I, II 1.425 1.5 1.575 0.68 0.75 0.9 -- VCCIO/2 -- HSTL-12 Class I, II 1.14 1.2 1.26 0.47 x VCCIO 0.5 x VCCIO 0.53 x VCCIO -- VCCIO/2 -- HSUL-12 1.14 1.2 1.3 0.49 x VCCIO 0.5 x VCCIO 0.51 x VCCIO -- -- -- POD12 1.16 1.2 1.24 0.69 x VCCIO 0.7 x VCCIO 0.71 x VCCIO -- VCCIO -- Send Feedback Intel(R) Arria(R) 10 Device Datasheet 19 Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications Table 16. Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications for Intel Arria 10 Devices I/O Standard VIL(DC) (V) VIH(DC) (V) VIL(AC) (V) VIH(AC) (V) VOL (V) VOH (V) IOL (31) IOH (31) (mA) (mA) Min Max Min Max Max Min Max Min SSTL-18 Class I -0.3 VREF -0.125 VREF + 0.125 VCCIO + 0.3 VREF - 0.25 VREF + 0.25 VTT - 0.603 VTT + 0.603 6.7 -6.7 SSTL-18 Class II -0.3 VREF -0.125 VREF + 0.125 VCCIO + 0.3 VREF - 0.25 VREF + 0.25 0.28 VCCIO -0.28 13.4 -13.4 SSTL-15 Class I -- VREF - 0.1 VREF + 0.1 -- VREF - 0.175 VREF + 0.175 0.2 x VCCIO 0.8 x VCCIO 8 -8 SSTL-15 Class II -- VREF - 0.1 VREF + 0.1 -- VREF - 0.175 VREF + 0.175 0.2 x VCCIO 0.8 x VCCIO 16 -16 SSTL-135/ SSTL-135 Class I, II -- VREF - 0.09 VREF + 0.09 -- VREF - 0.16 VREF + 0.16 0.2 x VCCIO 0.8 x VCCIO -- -- SSTL-125/ SSTL-125 Class I, II -- VREF - 0.09 VREF + 0.09 -- VREF - 0.15 VREF + 0.15 0.2 x VCCIO 0.8 x VCCIO -- -- SSTL-12/ SSTL-12 Class I, II -- VREF - 0.10 VREF + 0.10 -- VREF - 0.15 VREF + 0.15 0.2 x VCCIO 0.8 x VCCIO -- -- HSTL-18 Class I -- VREF -0.1 VREF + 0.1 -- VREF - 0.2 VREF + 0.2 0.4 VCCIO - 0.4 8 -8 HSTL-18 Class II -- VREF - 0.1 VREF + 0.1 -- VREF - 0.2 VREF + 0.2 0.4 VCCIO - 0.4 16 -16 HSTL-15 Class I -- VREF - 0.1 VREF + 0.1 -- VREF - 0.2 VREF + 0.2 0.4 VCCIO - 0.4 8 -8 HSTL-15 Class II -- VREF - 0.1 VREF + 0.1 -- VREF - 0.2 VREF + 0.2 0.4 VCCIO -0.4 16 -16 -0.15 VREF - 0.08 VREF + 0.08 VCCIO + 0.15 VREF - 0.15 VREF + 0.15 0.25 x VCCIO 0.75 x VCCIO 8 -8 HSTL-12 Class I continued... (31) To meet the IOL and IOH specifications, you must set the current strength settings accordingly. For example, to meet the SSTL15CI specification (8 mA), you should set the current strength settings to 8 mA. Setting at lower current strength may not meet the IOL and IOH specifications in the datasheet. Intel(R) Arria(R) 10 Device Datasheet 20 Send Feedback Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 I/O Standard HSTL-12 Class II HSUL-12 POD12 VIL(DC) (V) VIH(DC) (V) VIL(AC) (V) VIH(AC) (V) VOL (V) VOH (V) IOL (31) IOH (31) (mA) (mA) Min Max Min Max Max Min Max Min -0.15 VREF - 0.08 VREF + 0.08 VCCIO + 0.15 VREF - 0.15 VREF + 0.15 0.25 x VCCIO 0.75 x VCCIO 16 -16 -- VREF - 0.13 VREF + 0.13 -- VREF - 0.22 VREF + 0.22 0.1 x VCCIO 0.9 x VCCIO -- -- -0.15 VREF - 0.08 VREF + 0.08 VCCIO + 0.15 VREF - 0.15 VREF + 0.15 (0.7 - 0.15) x VCCIO (0.7 + 0.15) x VCCIO -- -- Differential SSTL I/O Standards Specifications Table 17. Differential SSTL I/O Standards Specifications for Intel Arria 10 Devices I/O Standard VCCIO (V) VSWING(DC) (V) VSWING(AC) (V) VIX(AC) (V) Min Typ Max Min Max Min Max Min Typ Max SSTL-18 Class I, II 1.71 1.8 1.89 0.25 VCCIO + 0.6 0.5 VCCIO + 0.6 VCCIO/2 - 0.175 -- VCCIO/2 + 0.175 SSTL-15 Class I, II 1.425 1.5 1.575 0.2 (32) 2(VIH(AC) - VREF) 2(VREF - VIL(AC)) VCCIO/2 - 0.15 -- VCCIO/2 + 0.15 SSTL-135/ SSTL-135 Class I, II 1.283 1.35 1.45 0.18 (32) 2(VIH(AC) - VREF) 2(VIL(AC) - VREF) VCCIO/2 - 0.15 VCCIO/2 VCCIO/2 + 0.15 SSTL-125/ SSTL-125 Class I, II 1.19 1.25 1.31 0.18 (32) 2(VIH(AC) - VREF) 2(VIL(AC) - VREF) VCCIO/2 - 0.15 VCCIO/2 VCCIO/2 + 0.15 SSTL-12/ SSTL-12 Class I, II 1.14 1.2 1.26 0.16 (32) 2(VIH(AC) - VREF) 2(VIL(AC) - VREF) VREF - 0.15 VCCIO/2 VREF + 0.15 POD12 1.16 1.2 1.24 0.16 -- 0.3 -- VREF - 0.08 -- VREF + 0.08 (31) To meet the IOL and IOH specifications, you must set the current strength settings accordingly. For example, to meet the SSTL15CI specification (8 mA), you should set the current strength settings to 8 mA. Setting at lower current strength may not meet the IOL and IOH specifications in the datasheet. (32) The maximum value for VSWING(DC) is not defined. However, each single-ended signal needs to be within the respective single-ended limits (VIH(DC) and VIL(DC)). Send Feedback Intel(R) Arria(R) 10 Device Datasheet 21 Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 Differential HSTL and HSUL I/O Standards Specifications Table 18. Differential HSTL and HSUL I/O Standards Specifications for Intel Arria 10 Devices I/O Standard VCCIO (V) VDIF(DC) (V) VDIF(AC) (V) VIX(AC) (V) VCM(DC) (V) Min Typ Max Min Max Min Max Min Typ Max Min Typ Max HSTL-18 Class I, II 1.71 1.8 1.89 0.2 -- 0.4 -- 0.78 -- 1.12 0.78 -- 1.12 HSTL-15 Class I, II 1.425 1.5 1.575 0.2 -- 0.4 -- 0.68 -- 0.9 0.68 -- 0.9 HSTL-12 Class I, II 1.14 1.2 1.26 0.16 VCCIO + 0.3 0.3 VCCIO + 0.48 -- 0.5 x VCCIO -- 0.4 x VCCIO 0.5 x VCCIO 0.6 x VCCIO HSUL-12 1.14 1.2 1.3 2(VIH(DC) - VREF) 2(VREF - VIH(DC)) 2(VIH(AC) - VREF) 2(VREF - VIH(AC)) 0.5 x VCCIO - 0.12 0.5 x VCCIO 0.5 x VCCIO +0.12 0.4 x VCCIO 0.5 x VCCIO 0.6 x VCCIO Differential I/O Standards Specifications Table 19. Differential I/O Standards Specifications for Intel Arria 10 Devices Differential inputs are powered by VCCPT which requires 1.8 V. I/O Standard LVDS (35) VCCIO (V) VID (mV) (33) VICM(DC) (V) VOD (V) (34) VOCM (V) (34) Min Typ Max Min Condition Max Min Condition Max Min Typ Max Min Typ Max 1.71 1.8 1.89 100 VCM = 1.25 V -- 0 DMAX 700 Mbps 1.85 0.247 -- 0.6 1.125 1.25 1.375 1 DMAX >700 Mbps 1.6 continued... (33) The minimum VID value is applicable over the entire common mode range, VCM. (34) RL range: 90 RL 110 . (35) For optimized LVDS receiver performance, the receiver voltage input range must be within 1.0 V to 1.6 V for data rates above 700 Mbps and 0 V to 1.85 V for data rates below 700 Mbps. Intel(R) Arria(R) 10 Device Datasheet 22 Send Feedback Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 I/O Standard RSDS (HIO) (36) Mini-LVDS (HIO) (37) LVPECL (38) VCCIO (V) VID (mV) (33) VICM(DC) (V) VOD (V) (34) VOCM (V) (34) Min Typ Max Min Condition Max Min Condition Max Min Typ Max Min Typ Max 1.71 1.8 1.89 100 VCM = 1.25 V -- 0.3 -- 1.4 0.1 0.2 0.6 0.5 1.2 1.4 1.71 1.8 1.89 200 -- 600 0.4 -- 1.325 0.25 -- 0.6 1 1.2 1.4 1.71 1.8 1.89 300 -- -- 0.6 DMAX 700 Mbps 1.7 -- -- -- -- -- -- 1 DMAX >700 Mbps 1.6 Related Information Transceiver Specifications for Intel Arria 10 GX, SX, and GT Devices on page 28 Provides the specifications for transmitter, receiver, and reference clock I/O pin. Switching Characteristics This section provides the performance characteristics of Intel Arria 10 core and periphery blocks for extended grade devices. (33) The minimum VID value is applicable over the entire common mode range, VCM. (34) RL range: 90 RL 110 . (36) For optimized RSDS receiver performance, the receiver voltage input range must be between 0.25 V to 1.45 V. (37) For optimized Mini-LVDS receiver performance, the receiver voltage input range must be between 0.1 V to 1.625 V. (38) For optimized LVPECL receiver performance, the receiver voltage input range must be within 0.85 V to 1.75 V for data rates above 700 Mbps and 0.45 V to 1.95 V for data rates below 700 Mbps. Send Feedback Intel(R) Arria(R) 10 Device Datasheet 23 Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 Transceiver Performance Specifications Transceiver Performance for Intel Arria 10 GX/SX Devices Table 20. Transmitter and Receiver Data Rate Performance Symbol/Description Chip-to-Chip (39) Transceiver Speed Transceiver Speed Transceiver Speed Transceiver Speed Grade 1 Grade 2 Grade 3 Grade 4 Condition Maximum data rate VCCR_GXB = VCCT_GXB = 1.03 V 17.4 15 14.2 12.5 Gbps Maximum data rate VCCR_GXB = VCCT_GXB = 0.95 V 11.3 11.3 11.3 11.3 Gbps Minimum Data Rate Backplane 1.0 Maximum data rate VCCR_GXB = VCCT_GXB = 1.03 V (39) 12.5 (40) 12.5 Minimum Data Rate Table 21. Unit Gbps 12.5 1.0 10.3125 (40) Gbps Gbps ATX PLL Performance Symbol/Description Supported Output Frequency Condition Maximum Frequency Minimum Frequency Transceiver Speed Grade 1 Transceiver Speed Grade 2 Transceiver Speed Grade 3 Transceiver Speed Grade 4 Unit 8.7 7.5 7.1 6.25 GHz 500 MHz (39) Backplane applications assume advanced equalization circuitry, such as decision feedback equalization (DFE), is enabled to compensate for signal impairments. Chip-to-chip links are assumed to be applications with short reach channels that do not require DFE. (40) Intel Arria 10 transceivers can support data rates down to 125 Mbps with over sampling. Intel(R) Arria(R) 10 Device Datasheet 24 Send Feedback Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 Table 22. Fractional PLL Performance Symbol/Description Supported Output Frequency Table 23. Condition Maximum Frequency Transceiver Speed Grade 1 Transceiver Speed Grade 2 Transceiver Speed Grade 3 Transceiver Speed Grade 4 Unit 6.25 6.25 6.25 6.25 GHz Minimum Frequency 500 MHz CMU PLL Performance Symbol/Description Supported Output Frequency Condition Maximum Frequency Transceiver Speed Grade 1 Transceiver Speed Grade 2 Transceiver Speed Grade 3 Transceiver Speed Grade 4 Unit 5.15625 5.15625 5.15625 5.15625 GHz Minimum Frequency 2450 MHz Related Information Transceiver Power Supply Operating Conditions on page 10 High-Speed Serial Transceiver-Fabric Interface Performance for Intel Arria 10 GX/SX Devices Table 24. High-Speed Serial Transceiver-Fabric Interface Performance for Intel Arria 10 GX/SX Devices The frequencies listed are the maximum frequencies. Symbol/Description Condition (V) Core Speed Grade with Power Options Unit -E1H -E2 / -I2 -E3 / -I3 20-bit interface - FIFO VCC = 0.9/0.95 516 400 400 MHz 20-bit interface - Registered VCC = 0.9/0.95 491 400 400 MHz 32-bit interface - FIFO VCC = 0.9/0.95 441 404 335 MHz 32-bit interface - Registered VCC = 0.9/0.95 441 404 335 MHz 64-bit interface - FIFO VCC = 0.9/0.95 272 234 222 MHz 64-bit interface - Registered VCC = 0.9/0.95 272 234 222 MHz PCIe Gen3 HIP-Fabric interface VCC = 0.9/0.95 300 250 125 MHz Send Feedback Intel(R) Arria(R) 10 Device Datasheet 25 Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 Transceiver Performance for Intel Arria 10 GT Devices Table 25. Transmitter and Receiver Data Rate Performance Symbol/Description Chip-to-chip Condition (41) Maximum data rate VCCR_GXB = VCCT_GXB = 1.12 V Transceiver Speed Transceiver Speed Grade 1 Grade 2 GT Channel (42) 25.8 25.8 Gbps GX Channel 17.4 15 Gbps Maximum data rate VCCR_GXB = VCCT_GXB = 1.03 V GX Channel 16 14.2 Gbps Maximum data rate VCCR_GXB = VCCT_GXB = 0.95 V GX Channel 11.3 11.3 Gbps Minimum data rate GT Channel 1.0 GX Channel Backplane Table 26. (41) Unit (43) Gbps Maximum data rate VCCR_GXB = VCCT_GXB = 1.12 V GX Channel 12.5 12.5 Gbps Maximum data rate VCCR_GXB = VCCT_GXB = 1.03 V GX Channel 12.5 12.5 Gbps Minimum data rate GX Channel 1.0 (43) Gbps ATX PLL Performance Symbol/Description Supported Output Frequency Condition Transceiver Speed Grade 1 Transceiver Speed Grade 2 Unit Maximum frequency 12.9 GHz Minimum frequency 500 MHz (41) Backplane applications assume advanced equalization circuitry, such as decision feedback equalization (DFE), is enabled to compensate for signal impairments. Chip-to-chip links are assumed to be applications with short reach channels that do not require DFE. (42) GT channels can only achieve 25.8 Gbps when VCCT_GXB = 1.12 V and VCCR_GXB = 1.12 V. (43) Intel Arria 10 transceivers can support data rates down to 125 Mbps with over sampling. Intel(R) Arria(R) 10 Device Datasheet 26 Send Feedback Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 Table 27. Fractional PLL Performance Symbol/Description Supported Output Frequency Table 28. Condition Transceiver Speed Grade 1 Transceiver Speed Grade 2 Unit Maximum frequency 6.25 GHz Minimum frequency 500 MHz CMU PLL Performance Symbol/Description Supported Output Frequency Condition Transceiver Speed Grade 1 Transceiver Speed Grade 2 Unit Maximum frequency 5.15625 GHz Minimum frequency 2450 MHz Related Information Transceiver Power Supply Operating Conditions on page 10 High-Speed Serial Transceiver-Fabric Interface Performance for Intel Arria 10 GT Devices Table 29. High-Speed Serial Transceiver-Fabric Interface Performance for Intel Arria 10 GT Devices The frequencies listed are the maximum frequencies. Symbol/Description Condition (V) Core Speed Grade with Power Options -1 Unit -2 20-bit interface - FIFO VCC = 0.9/0.95 400 MHz 20-bit interface - Registered VCC = 0.9/0.95 400 MHz 32-bit interface - FIFO VCC = 0.9/0.95 404 MHz 32-bit interface - Registered VCC = 0.9/0.95 404 MHz 64-bit interface - FIFO VCC = 0.9/0.95 407 MHz 64-bit interface - Registered VCC = 0.9/0.95 407 MHz PCIe Gen3 HIP-Fabric interface VCC = 0.9/0.95 250 MHz Send Feedback Intel(R) Arria(R) 10 Device Datasheet 27 Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 Transceiver Specifications for Intel Arria 10 GX, SX, and GT Devices Table 30. Reference Clock Specifications Symbol/Description Condition All Transceiver Speed Grades Min Supported I/O Standards Dedicated reference clock pin Typ Unit Max CML, Differential LVPECL, LVDS, and HCSL RX reference clock pin CML, Differential LVPECL, and LVDS Input Reference Clock Frequency (CMU PLL) 61 -- 800 MHz Input Reference Clock Frequency (ATX PLL) 100 -- 800 MHz Input Reference Clock Frequency (fPLL PLL) 25 (44) / 50 (45) -- 800 MHz Rise time 20% to 80% -- -- 400 ps Fall time 80% to 20% -- -- 400 ps Duty cycle -- 45 -- 55 % Spread-spectrum modulating clock frequency PCIe 30 -- 33 kHz Spread-spectrum downspread PCIe -- 0 to -0.5 -- % On-chip termination resistors -- -- 100 -- Absolute VMAX Dedicated reference clock pin -- -- 1.6 V RX reference clock pin -- -- 1.2 V Absolute VMIN -- -0.4 -- -- V Peak-to-peak differential input voltage -- 200 -- 1600 mV VICM (AC coupled) VCCR_GXB = 0.95 V -- 0.95 -- V continued... (44) This specification is for HDMI mode only. (45) This specification is for other non-HDMI modes. Intel(R) Arria(R) 10 Device Datasheet 28 Send Feedback Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 Symbol/Description Condition Unit Min Typ Max VCCR_GXB = 1.03 V -- 1.03 -- V VCCR_GXB = 1.12 V -- 1.12 -- V 250 -- 550 mV 100 Hz -- -- -70 dBc/Hz 1 kHz -- -- -90 dBc/Hz 10 kHz -- -- -100 dBc/Hz 100 kHz -- -- -110 dBc/Hz 1 MHz -- -- -120 dBc/Hz Transmitter REFCLK Phase Jitter (100 MHz) 1.5 MHz to 100 MHz (PCIe) -- -- 4.2 ps (rms) RREF -- -- 2.0 k 1% -- TSSC-MAX-PERIOD-SLEW Max SSC df/dt VICM (DC coupled) HCSL I/O standard for PCIe reference clock Transmitter REFCLK Phase Noise (622 MHz) Table 31. (46) 0.75 Transceiver Clocks Specifications Symbol/Description CLKUSR pin for transceiver calibration reconfig_clk (46) All Transceiver Speed Grades Condition All Transceiver Speed Grades Unit Min Typ Max Transceiver Calibration 100 -- 125 MHz Reconfiguration interface 100 -- 125 MHz To calculate the REFCLK phase noise requirement at frequencies other than 622 MHz, use the following formula: REFCLK phase noise at f (MHz) = REFCLK phase noise at 622 MHz + 20*log(f/622). Send Feedback Intel(R) Arria(R) 10 Device Datasheet 29 Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 Table 32. Transceiver Clock Network Maximum Data Rate Specifications Clock Network Maximum Performance (47) Channel Span Unit ATX fPLL CMU x1 17.4 12.5 10.3125 6 channels in a single bank Gbps x6 17.4 12.5 N/A 6 channels in a single bank Gbps PLL feedback compensation mode 17.4 12.5 N/A Side-wide Gbps xN at 0.95 V VCCR_GXB/ VCCT_GXB 10.5 10.5 N/A Up two banks and down two banks (47) (48) Gbps xN at 1.03 V VCCR_GXB/ VCCT_GXB 15.0 12.5 N/A Up two banks and down two banks(47) (48) Gbps xN at 1.12 V VCCR_GXB/ VCCT_GXB 16.0 12.5 N/A Up two banks and down two banks(47) (48) Gbps Table 33. Receiver Specifications Symbol/Description Condition All Transceiver Speed Grades Min Typ Max Unit High Speed Differential I/O, CML , Differential LVPECL , and LVDS(49) Supported I/O Standards -- Absolute VMAX for a receiver pin (50) -- -- -- 1.2 V Absolute VMIN for a receiver pin (50) -- -0.4 -- -- V continued... (47) The maximum data rate depends on speed grade. (48) For more information, refer to the PLLs and Clock Networks chapter of the Intel Arria 10 Transceiver PHY User Guide. (49) CML, Differential LVPECL, and LVDS are only used on AC coupled links. (50) The device cannot tolerate prolonged operation at this absolute maximum. Intel(R) Arria(R) 10 Device Datasheet 30 Send Feedback Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 Symbol/Description Maximum peak-to-peak differential input voltage VID (diff p-p) before device configuration Maximum peak-to-peak differential input voltage VID (diff p-p) after device configuration Minimum differential eye opening at receiver serial input pins (51) Differential on-chip termination resistors VICM (AC and DC coupled) (52) Condition All Transceiver Speed Grades Unit Min Typ Max -- -- -- 1.6 V VCCR_GXB = 1.12 V -- -- 2.0 V VCCR_GXB = 1.03 V -- -- 2.0 V VCCR_GXB = 0.95 V -- -- 2.4 V -- 50 -- -- mV 85- setting -- 85 30% -- 100- setting -- 100 30% -- VCM = 0.65 V -- 600 -- mV VCM = 0.7 V -- 700 -- mV VCM = 0.75 V -- 700 -- mV tLTR(53) -- -- -- 10 s tLTD(54) -- 4 -- -- s tLTD_manual(55) -- 4 -- -- s tLTR_LTD_manual(56) -- 15 -- -- s continued... (51) The differential eye opening specification at the receiver input pins assumes that Receiver Equalization is disabled. If you enable Receiver Equalization, the receiver circuitry can tolerate a lower minimum eye opening, depending on the equalization level. (52) Intel Arria 10 devices only support DC coupling when using the Hybrid Memory Cube (HMC) or the Intel QuickPath Interconnect (QPI) specifications. (53) tLTR is the time required for the receive CDR to lock to the input reference clock frequency after coming out of reset. (54) tLTD is time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodata signal goes high. Send Feedback Intel(R) Arria(R) 10 Device Datasheet 31 Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 Symbol/Description Run Length CDR PPM tolerance Condition -- PCIe-only All other protocols All Transceiver Speed Grades Unit Min Typ Max -- -- 200 UI -300 -- 300 PPM -1000 -- 1000 PPM Programmable DC Gain Setting = 0-4 0 -- 10 dB Programmable AC Gain at High Gain mode and Data Rate 6 Gbps with 0.95 V VCCR Setting = 0-28 0 -- 19 dB Programmable AC Gain at High Gain mode and Data Rate 6 Gpbs with 1.03 V VCCR Setting = 0-28 0 -- 21 dB Programmable AC Gain at High Gain mode and Data Rate 17.4 Gpbs with 1.03 V VCCR Setting = 0-28 0 -- 17 dB Programmable AC Gain at High Data Rate mode Setting = 0-15 0 -- 8 dB (55) tLTD_manual is the time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodata signal goes high when the CDR is functioning in the manual mode. (56) tLTR_LTD_manual is the time the receiver CDR must be kept in lock to reference (LTR) mode after the rx_is_lockedtoref signal goes high when the CDR is functioning in the manual mode. Intel(R) Arria(R) 10 Device Datasheet 32 Send Feedback Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 Table 34. Transmitter Specifications Symbol/Description Supported I/O Standards Differential on-chip termination resistors VOCM (AC coupled) VOCM (DC coupled) Rise time Fall time (58) (58) Intra-differential pair skew (59) Condition All Transceiver Speed Grades Min -- Typ High Speed Differential I/O Unit Max (57) -- 85- setting -- 85 20% -- 100- setting -- 100 20% -- VCCT = 0.95 V -- 450 -- mV VCCT = 1.03 V -- 500 -- mV VCCT = 1.12 V -- 550 -- mV VCCT = 0.95 V -- 450 -- mV VCCT = 1.03 V -- 500 -- mV VCCT = 1.12 V -- 550 -- mV 20% to 80% 20 -- 130 ps 80% to 20% 20 -- 130 ps TX VCM = 0.5 V and slew rate setting of SLEW_R5 (60) -- -- 15 ps (57) High Speed Differential I/O is the dedicated I/O standard for the transmitter in Intel Arria 10 transceivers. (58) The Intel Quartus Prime software automatically selects the appropriate slew rate depending on the design configurations. (59) In QPI mode, if VCM < 0.17 V, the input Vid must be greater than 100 mV. If VCM > 0.17 V, the input Vid must be greater than 70 mV. (60) SLEW_R1 is the slowest and SLEW_R5 is the fastest. SLEW_R6 and SLEW_R7 are not used. Send Feedback Intel(R) Arria(R) 10 Device Datasheet 33 Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 Table 35. Typical Transmitter VOD Settings Symbol VOD differential value = VOD-to-VCCT ratio x VCCT Intel(R) Arria(R) 10 Device Datasheet 34 VOD Setting VOD-to-VCCT Ratio 31 1.00 30 0.97 29 0.93 28 0.90 27 0.87 26 0.83 25 0.80 24 0.77 23 0.73 22 0.70 21 0.67 20 0.63 19 0.60 18 0.57 17 0.53 16 0.50 15 0.47 14 0.43 13 0.40 12 0.37 Send Feedback Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 Table 36. Transmitter Channel-to-channel Skew Specifications Mode Channel Span Maximum Skew Unit x6 Clock Up to 6 channels in one bank 61 ps xN Clock Within 2 banks 230 ps Up 2 banks and down 2 banks 500 Side-wide 1600 PLL Feedback Compensation (61), (62), (63) ps Related Information PLLs and Clock Networks Core Performance Specifications Clock Tree Specifications Table 37. Clock Tree Performance for Intel Arria 10 Devices Parameter Performance (All Speed Grades) Unit Global clock, regional clock, and small periphery clock 644 MHz Large periphery clock 525 MHz (61) refclk is set to 125 MHz during the test. (62) You can reduce the lane-to-lane skew by increasing the reference clock frequency. (63) The middle refclk location provides the lowest lane-to-lane skew. Send Feedback Intel(R) Arria(R) 10 Device Datasheet 35 Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 PLL Specifications Fractional PLL Specifications Table 38. Fractional PLL Specifications for Intel Arria 10 Devices Symbol Parameter Condition Min Typ Max 800 (64) Unit fIN Input clock frequency -- 30 -- MHz fINPFD Input clock frequency to the phase frequency detector (PFD) -- 30 -- 700 MHz fCASC_INPFD Input clock frequency to the PFD of destination cascade PLL -- 30 -- 60 MHz fVCO PLL voltage-controlled oscillator (VCO) operating range -- 6 -- 14.025 GHz tEINDUTY Input clock duty cycle -- 45 -- 55 % fOUT Output frequency for internal global or regional clock -- -- -- 644 MHz fDYCONFIGCLK Dynamic configuration clock for -- -- -- 100 MHz -- -- -- 1 ms reconfig_clk tLOCK Time required to lock from end-of-device configuration or deassertion of pll_powerdown tDLOCK Time required to lock dynamically (after switchover or reconfiguring any non-postscale counters/delays) -- -- -- 1 ms fCLBW PLL closed-loop bandwidth -- 0.3 -- 4 MHz tPLL_PSERR Accuracy of PLL phase shift Non-SmartVID -- -- 50 ps SmartVID -- -- 75 ps continued... (64) This specification is limited by the I/O maximum frequency. The maximum achievable I/O frequency is different for each I/O standard and is depends on design and system specific factors. Ensure proper timing closure in your design and perform HSPICE/IBIS simulations based on your specific design and system setup to determine the maximum achievable frequency in your system. Intel(R) Arria(R) 10 Device Datasheet 36 Send Feedback Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 Symbol tARESET Minimum pulse width on the pll_powerdown signal tINCCJ (65)(66) tOUTPJ (67) tOUTCCJ Parameter Input clock cycle-to-cycle jitter Period jitter for clock output (67) Cycle-to-cycle jitter for clock output dKBIT Bit number of Delta Sigma Modulator (DSM) Condition Min Typ Max Unit -- 10 -- -- ns FREF 100 MHz -- -- 0.13 UI (p-p) FREF < 100 MHz -- -- 650 ps (p-p) FOUT 100 MHz -- -- 600 ps (p-p) FOUT < 100 MHz -- -- 60 mUI (p-p) FOUT 100 MHz -- -- 600 ps (p-p) FOUT < 100 MHz -- -- 60 mUI (p-p) -- -- 32 -- bit Related Information * Memory Output Clock Jitter Specifications on page 53 Provides more information about the external memory interface clock output jitter specifications. * KDB link: How do I compensate for the jitter of PLL cascading or non-dedicated clock path for Intel Arria 10 PLL reference clock? For the Intel Quartus Prime software version prior to 17.1, the fPLL output may experience additional jitter. The additional jitter occurs if you source the reference clock from a cascaded PLL output, global clock, or core clock. To compensate for the jitter, the designs require additional constraints. This issue has been fixed in the Intel Quartus Prime software version 17.1. (65) A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source with jitter < 120 ps. (66) FREF is fIN/N, specification applies when N = 1. (67) External memory interface clock output jitter specifications use a different measurement method, which are available in Memory Output Clock Jitter Specification for Intel Arria 10 Devices table. Send Feedback Intel(R) Arria(R) 10 Device Datasheet 37 Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 I/O PLL Specifications Table 39. I/O PLL Specifications for Intel Arria 10 Devices Symbol fIN Parameter Input clock frequency Condition Min Typ -1 speed grade 10 -- 800 Max (68) Unit MHz -2 speed grade 10 -- 700 (68) MHz -3 speed grade 10 -- 650 (68) MHz fINPFD Input clock frequency to the PFD -- 10 -- 325 MHz fCASC_INPFD Input clock frequency to the PFD of destination cascade PLL -- 10 -- 60 MHz fVCO PLL VCO operating range -1 speed grade 600 -- 1600 MHz -2 speed grade 600 -- 1434 MHz -3 speed grade 600 -- 1250 MHz fCLBW PLL closed-loop bandwidth -- 0.1 -- 8 MHz tEINDUTY Input clock or external feedback clock input duty cycle -- 40 -- 60 % fOUT Output frequency for internal global or regional clock (C counter) -1, -2, -3 speed grade -- -- 644 MHz fOUT_EXT Output frequency for external clock output -1 speed grade -- -- 800 MHz -2 speed grade -- -- 720 MHz -3 speed grade -- -- 650 MHz Non-SmartVID 45 50 55 % SmartVID 42 50 58 % -- -- -- 10 tOUTDUTY tFCOMP Duty cycle for dedicated external clock output (when set to 50%) External feedback clock compensation time ns continued... (68) This specification is limited by the I/O maximum frequency. The maximum achievable I/O frequency is different for each I/O standard and is depends on design and system specific factors. Ensure proper timing closure in your design and perform HSPICE/IBIS simulations based on your specific design and system setup to determine the maximum achievable frequency in your system. Intel(R) Arria(R) 10 Device Datasheet 38 Send Feedback Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 Symbol fDYCONFIGCLK Parameter Condition Min Typ Max Unit Dynamic configuration clock for mgmt_clk and -- -- -- 100 MHz scanclk tLOCK Time required to lock from end-of-device configuration or deassertion of areset -- -- -- 1 ms tDLOCK Time required to lock dynamically (after switchover or reconfiguring any non-post-scale counters/delays) -- -- -- 1 ms tPLL_PSERR Accuracy of PLL phase shift -- -- -- 50 ps Minimum pulse width on the areset signal -- 10 -- -- ns FREF 100 MHz -- -- 0.15 UI (p-p) FREF < 100 MHz -- -- 750 ps (p-p) FOUT 100 MHz -- -- 175 ps (p-p) FOUT < 100 MHz -- -- 17.5 mUI (p-p) FOUT 100 MHz -- -- 175 ps (p-p) tARESET tINCCJ (69)(70) tOUTPJ_DC Input clock cycle-to-cycle jitter Period jitter for dedicated clock output tOUTCCJ_DC Cycle-to-cycle jitter for dedicated clock output tOUTPJ_IO (71) Period jitter for clock output on the regular I/O tOUTCCJ_IO (71) tCASC_OUTPJ_DC Cycle-to-cycle jitter for clock output on the regular I/O Period jitter for dedicated clock output in cascaded PLLs FOUT < 100 MHz -- -- 17.5 mUI (p-p) FOUT 100 MHz -- -- 600 ps (p-p) FOUT < 100 MHz -- -- 60 mUI (p-p) FOUT 100 MHz -- -- 600 ps (p-p) FOUT < 100 MHz -- -- 60 mUI (p-p) FOUT 100 MHz -- -- 175 ps (p-p) FOUT < 100 MHz -- -- 17.5 mUI (p-p) (69) A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source with jitter < 120 ps. (70) FREF is fIN/N, specification applies when N = 1. (71) External memory interface clock output jitter specifications use a different measurement method, which are available in Memory Output Clock Jitter Specification for Intel Arria 10 Devices table. Send Feedback Intel(R) Arria(R) 10 Device Datasheet 39 Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 Related Information * Memory Output Clock Jitter Specifications on page 53 Provides more information about the external memory interface clock output jitter specifications. * KDB link: How do I compensate for the jitter of PLL cascading or non-dedicated clock path for Intel Arria 10 PLL reference clock? For the Intel Quartus Prime software version prior to 17.1, the I/O PLL output may experience additional jitter. The additional jitter occurs if you source the reference clock from a cascaded PLL output, global clock, or core clock. To compensate for the jitter, the designs require additional constraints. This issue has been fixed in the Intel Quartus Prime software version 17.1. DSP Block Specifications Table 40. DSP Block Performance Specifications for Intel Arria 10 Devices (VCC and VCCP at 0.9 V Typical Value) Mode Unit -E1S, -E1H -I1S, -I1H -E2L, -E2S -I2L, -I2S -E3S, -E3V -I3S, -I3V Fixed-point 18 x 19 multiplication mode 548 528 456 438 364 346 MHz Fixed-point 27 x 27 multiplication mode 541 522 450 434 358 344 MHz Fixed-point 18 x 18 multiplier adder mode 548 529 459 440 370 351 MHz Fixed-point 18 x 18 multiplier adder summed with 36-bit input mode 539 517 444 422 349 326 MHz Fixed-point 18 x 19 systolic mode 548 529 459 440 370 351 MHz Complex 18 x 19 multiplication mode 548 528 456 438 364 346 MHz Floating point multiplication mode 548 527 447 427 347 326 MHz Floating point adder or subtract mode 488 471 388 369 288 266 MHz Floating point multiplier adder or subtract mode 483 465 386 368 290 270 MHz Floating point multiplier accumulate mode 510 490 418 393 326 294 MHz Floating point vector one mode 502 482 404 382 306 282 MHz Floating point vector two mode 474 455 383 367 293 278 MHz Intel(R) Arria(R) 10 Device Datasheet 40 Performance Send Feedback Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 Table 41. DSP Block Performance Specifications for Intel Arria 10 Devices (VCC and VCCP at 0.95 V Typical Value) Mode Performance Unit -I1S, -I1H -I2L, -I2S Fixed-point 18 x 19 multiplication mode 635 517 MHz Fixed-point 27 x 27 multiplication mode 633 517 MHz Fixed-point 18 x 18 multiplier adder mode 635 516 MHz Fixed-point 18 x 18 multiplier adder summed with 36-bit input mode 631 509 MHz Fixed-point 18 x 19 systolic mode 635 516 MHz Complex 18 x 19 multiplication mode 635 517 MHz Floating point multiplication mode 635 501 MHz Floating point adder or subtract mode 564 468 MHz Floating point multiplier adder or subtract mode 564 475 MHz Floating point multiplier accumulate mode 581 482 MHz Floating point vector one mode 574 471 MHz Floating point vector two mode 550 450 MHz Memory Block Specifications To achieve the maximum memory block performance, use a memory block clock that comes through global clock routing from an on-chip PLL and set to 50% output duty cycle. Use the Intel Quartus Prime software to report timing for the memory block clocking schemes. When you use the error detection cyclical redundancy check (CRC) feature, there is no degradation in fMAX. Send Feedback Intel(R) Arria(R) 10 Device Datasheet 41 Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 Table 42. Memory Block Performance Specifications for Intel Arria 10 Devices (VCC and VCCP at 0.9 V Typical Value) Memory MLAB M20K Block Table 43. Mode Performance -E1S, -E1H -I1S, -I1H -E2L, -E2S, - I2L, -I2S -E3S, -E3V -I3S, -I3V Unit Single port, all supported widths (x16/x32) 700 660 570 490 490 MHz Simple dual-port, all supported widths (x16/x32) 700 660 570 490 490 MHz Simple dual-port with the read-during-write option set to Old Data, all supported widths 460 450 400 330 330 MHz ROM, all supported width (x16/x32) 700 660 570 490 490 MHz Single-port, all supported widths 730 690 625 530 510 MHz Simple dual-port, all supported widths 730 690 625 530 510 MHz Simple dual-port with the read-during-write option set to Old Data, all supported widths 550 520 470 410 410 MHz Simple dual-port with ECC enabled, 512 x 32 470 450 410 360 360 MHz Simple dual-port with ECC and optional pipeline registers enabled, 512 x 32 620 590 520 470 470 MHz True dual port, all supported widths 730 690 600 480 480 MHz ROM, all supported widths 730 690 625 530 510 MHz Memory Block Performance Specifications for Intel Arria 10 Devices (VCC and VCCP at 0.95 V Typical Value) Memory MLAB M20K Block Mode Performance -I1S, -I1H -I2L, -I2S Unit Single port, all supported widths (x16/x32) 706 610 MHz Simple dual-port, all supported widths (x16/x32) 706 610 MHz Simple dual-port with read and write at the same address 482 428 MHz ROM, all supported width (x16/x32) 706 610 MHz Single-port, all supported widths 735 670 MHz continued... Intel(R) Arria(R) 10 Device Datasheet 42 Send Feedback Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 Memory Mode Performance -I1S, -I1H -I2L, -I2S Unit Simple dual-port, all supported widths 735 670 MHz Simple dual-port with the read-during-write option set to Old Data, all supported widths 555 500 MHz Simple dual-port with ECC enabled, 512 x 32 480 440 MHz Simple dual-port with ECC and optional pipeline registers enabled, 512 x 32 630 555 MHz True dual port, all supported widths 735 640 MHz ROM, all supported widths 735 670 MHz Temperature Sensing Diode Specifications Internal Temperature Sensing Diode Specifications Table 44. Internal Temperature Sensing Diode Specifications for Intel Arria 10 Devices Temperature Range Accuracy Offset Calibrated Option Sampling Rate Conversion Time Resolution -40 to 125C 5C No 1 MHz < 5 ms 10 bits Related Information Transfer Function for Internal TSD Provides the transfer function for the internal TSD. Send Feedback Intel(R) Arria(R) 10 Device Datasheet 43 Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 External Temperature Sensing Diode Specifications Table 45. External Temperature Sensing Diode Specifications for Intel Arria 10 Devices * The typical value is at 25C. * Diode accuracy improves with lower injection current. * Absolute accuracy is dependent on third party external diode ADC and integration specifics. Description Min Typ Max Unit Ibias, diode source current 10 -- 100 A Vbias, voltage across diode 0.3 -- 0.9 V Series resistance -- -- <1 Diode ideality factor -- 1.03 -- -- Internal Voltage Sensor Specifications Table 46. Internal Voltage Sensor Specifications for Intel Arria 10 Devices Parameter Minimum Typical Maximum Unit Resolution -- -- 6 Bit Sampling rate -- -- 500 Ksps Differential non-linearity (DNL) -- -- 1 LSB Integral non-linearity (INL) -- -- 1 LSB Gain error -- -- 1 % Offset error -- -- 1 LSB Input capacitance -- 20 -- pF 0.1 -- 11 MHz Input signal range for Vsigp 0 -- 1.5 V Common mode voltage on Vsign 0 -- 0.25 V Input signal range for Vsigp - Vsign 0 -- 1.25 V Clock frequency Unipolar Input Mode Intel(R) Arria(R) 10 Device Datasheet 44 Send Feedback Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 Periphery Performance Specifications This section describes the periphery performance, high-speed I/O, and external memory interface. Actual achievable frequency depends on design and system specific factors. Ensure proper timing closure in your design and perform HSPICE/IBIS simulations based on your specific design and system setup to determine the maximum achievable frequency in your system. High-Speed I/O Specifications Table 47. High-Speed I/O Specifications for Intel Arria 10 Devices When serializer/deserializer (SERDES) factor J = 3 to 10, use the SERDES block. For LVDS applications, you must use the PLLs in integer PLL mode. You must calculate the leftover timing margin in the receiver by performing link timing closure analysis. You must consider the board skew margin, transmitter channel-to-channel skew, and receiver sampling margin to determine the leftover timing margin. The Intel Arria 10 devices support the following output standards using true LVDS output buffer types on all I/O banks: * True RSDS output standard with data rates of up to 360 Mbps * True mini-LVDS output standard with data rates of up to 400 Mbps Symbol Condition -E1S(72), -E1H, -I1S(72), -I1H -E2L, -E2S(72), -I2L, - I2S(72) -E3L, -E3S(72), -E3V, - I3L, -I3S(72), -I3V Min Typ Max Min Typ Max Min Typ Max Unit fHSCLK_in (input clock frequency) True Differential I/O Standards Clock boost factor W = 1 to 40 (73) 10 -- 800 10 -- 700 10 -- 625 MHz fHSCLK_in (input clock frequency) Single Ended I/O Standards Clock boost factor W = 1 to 40 (73) 10 -- 625 10 -- 625 10 -- 525 MHz -- -- -- -- -- -- -- fHSCLK_OUT (output clock frequency) 800 (74) 700 (74) 625 (74) MHz continued... (72) This speed grade is applicable to VCC = 0.95 V specifications. (73) Clock Boost Factor (W) is the ratio between the input data rate and the input clock rate. (74) This is achieved by using the PHY clock network. Send Feedback Intel(R) Arria(R) 10 Device Datasheet 45 Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 Symbol Condition -E1S(72), -E1H, -I1S(72), -I1H Min Transmitter -E3L, -E3S(72), -E3V, - I3L, -I3S(72), -I3V Max Min Max Min Typ Max -- 1434 (78) -- 1250 Mbps 1076 (78) -- 938 Mbps Typ Unit SERDES factor J = 4 to 10 (76) (78) -- 1600 (78) SERDES factor J = 3 (76)(77)(78) (78) -- 1200 (78) -- SERDES factor J = 2, uses DDR registers (78) -- 333 (79) (78) -- 275 (79) (78) -- 250 (79) Mbps SERDES factor J = 1, uses DDR registers (78) -- 333 (79) (78) -- 275 (79) (78) -- 250 (79) Mbps Total jitter for data rate, 600 Mbps - 1.6 Gbps -- -- 160 -- -- 200 -- -- 250 ps Total jitter for data rate, < 600 Mbps -- -- 0.1 -- -- 0.12 -- -- 0.15 UI TX output clock duty cycle for Differential I/O Standards 45 50 55 45 50 55 45 50 55 % tRISE & & tFALL (77)(81) True Differential I/O Standards -- -- 160 -- -- 180 -- -- 200 ps (80)(75) True Differential I/O Standards -- -- 150 -- -- 150 -- -- 150 ps SERDES factor J = 4 to 10 (76)(77)(78) 150 -- 1600 150 -- 1434 150 -- 1250 Mbps SERDES factor J = 3 (76)(77)(78) 150 -- 1200 150 -- 1076 150 -- 938 Mbps True Differential I/O Standards fHSDR (data rate) (75) tx Jitter - True Differential I/O Standards tDUTY TCCS Receiver Typ -E2L, -E2S(72), -I2L, - I2S(72) (80) True Differential I/O (77)(78) continued... (75) Requires package skew compensation with PCB trace length. (76) The Fmax specification is based on the fast clock used for serial data. The interface Fmax is also dependent on the parallel clock domain which is design dependent and requires timing analysis. (77) The VCC and VCCP must be on a combined power layer and a maximum load of 5 pF for chip-to-chip interface. Intel(R) Arria(R) 10 Device Datasheet 46 Send Feedback Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 Symbol Condition -E1S(72), -E1H, -I1S(72), -I1H -E2L, -E2S(72), -I2L, - I2S(72) -E3L, -E3S(72), -E3V, - I3L, -I3S(72), -I3V Unit Min Typ Max Min Typ Max Min Typ Max SERDES factor J = 3 to 10 (78) -- (82) (78) -- (82) (78) -- (82) Mbps SERDES factor J = 2, uses DDR registers (78) -- (79) (78) -- (79) (78) -- (79) Mbps SERDES factor J = 1, uses DDR registers (78) -- (79) (78) -- (79) (78) -- (79) Mbps Standards fHSDRDPA (data rate) fHSDR (data rate) (without DPA) (75) DPA (FIFO mode) DPA run length -- -- -- 10000 -- -- 10000 -- -- 10000 UI DPA (soft CDR mode) DPA run length SGMII/GbE protocol -- -- 5 -- -- 5 -- -- 5 UI continued... (72) This speed grade is applicable to VCC = 0.95 V specifications. (78) The minimum specification depends on the clock source (for example, the PLL and clock pin) and the clock routing resource (global, regional, or local) that you use. The I/O differential buffer and serializer do not have a minimum toggle rate. (79) The maximum ideal data rate is the SERDES factor (J) x the PLL maximum output frequency (fOUT) provided you can close the design timing and the signal integrity meets the interface requirements. (80) Not applicable for DIVCLK = 1. (81) This applies to default pre-emphasis and VOD settings only. (82) You can estimate the achievable maximum data rate for non-DPA mode by performing link timing closure analysis. You must consider the board skew margin, transmitter delay margin, and receiver sampling margin to determine the maximum data rate supported. Send Feedback Intel(R) Arria(R) 10 Device Datasheet 47 Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 Symbol Condition -E1S(72), -E1H, -I1S(72), -I1H -E2L, -E2S(72), -I2L, - I2S(72) -E3L, -E3S(72), -E3V, - I3L, -I3S(72), -I3V Unit Min Typ Max Min Typ Max Min Typ Max All other protocols -- -- 50 data transition per 208 UI -- -- 50 data transition per 208 UI -- -- 50 data transition per 208 UI -- Soft CDR mode Soft-CDR ppm tolerance -- -- -- 300 -- -- 300 -- -- 300 ppm Non DPA mode Sampling Window -- -- -- 300 -- -- 300 -- -- 300 ps DPA Lock Time Specifications Figure 2. DPA Lock Time Specifications with DPA PLL Calibration Enabled rx_reset DPA Lock Time rx_dpa_locked 256 data transitions (72) 256 data transitions 96 core clock cycles 256 data transitions This speed grade is applicable to VCC = 0.95 V specifications. Intel(R) Arria(R) 10 Device Datasheet 48 96 core clock cycles Send Feedback Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 Table 48. DPA Lock Time Specifications for Intel Arria 10 Devices The specifications are applicable to both extended and industrial grades. The DPA lock time is for one channel. One data transition is defined as a 0-to-1 or 1-to-0 transition. Standard SPI-4 Parallel Rapid I/O Miscellaneous (83) Training Pattern Number of Data Transitions in One Repetition of the Training Pattern Number of Repetitions per 256 Data Transitions (83) Maximum Data Transition 00000000001111111111 2 128 640 00001111 2 128 640 10010000 4 64 640 10101010 8 32 640 01010101 8 32 640 This is the number of repetitions for the stated training pattern to achieve the 256 data transitions. Send Feedback Intel(R) Arria(R) 10 Device Datasheet 49 Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specifications Figure 3. LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specifications for a Data Rate Equal to 1.6 Gbps LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specification Jitter Amphlitude (UI) 25 8.5 0.28 0.1 F1 F3 F2 F4 Jitter Frequency (Hz) Table 49. LVDS Soft-CDR/DPA Sinusoidal Jitter Mask Values for a Data Rate Equal to 1.6 Gbps Jitter Frequency (Hz) F1 10,000 25.00 F2 17,565 25.00 F3 1,493,000 0.28 F4 50,000,000 0.28 Intel(R) Arria(R) 10 Device Datasheet 50 Sinusoidal Jitter (UI) Send Feedback Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 Figure 4. LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specifications for a Data Rate Less than 1.6 Gbps Sinusoidal Jitter Amplitude 20db/dec 0.1 UI P-P 20 MHz baud/1667 Frequency Memory Standards Supported by the Hard Memory Controller Table 50. Memory Standards Supported by the Hard Memory Controller for Intel Arria 10 Devices This table lists the overall capability of the hard memory controller. For specific details, refer to the External Memory Interface Spec Estimator. Memory Standard Rate Support Ping Pong PHY Support Maximum Frequency (MHz) DDR4 SDRAM Quarter rate Yes 1,200 DDR3 SDRAM Quarter rate Yes 1,066 DDR3L SDRAM Quarter rate Yes 933 LPDDR3 SDRAM Quarter rate -- 800 Related Information External Memory Interface Spec Estimator Provides the specific details of the memory standards supported. Send Feedback Intel(R) Arria(R) 10 Device Datasheet 51 Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 Memory Standards Supported by the Soft Memory Controller Table 51. Memory Standards Supported by the Soft Memory Controller for Intel Arria 10 Devices This table lists the overall capability of the soft memory controller. For specific details, refer to the External Memory Interface Spec Estimator. Memory Standard RLDRAM QDR IV 3(84) SRAM(84) Rate Support Maximum Frequency (MHz) Quarter rate 1,200 Quarter rate 1,066 QDR II SRAM Half rate 633 QDR II+ SRAM Half rate 633 QDR II+ Xtreme SRAM Half rate 633 Related Information External Memory Interface Spec Estimator Provides the specific details of the memory standards supported. Memory Standards Supported by the HPS Hard Memory Controller Table 52. Memory Standards Supported by the HPS Hard Memory Controller for Intel Arria 10 Devices This table lists the overall capability of the hard memory controller. For specific details, refer to the External Memory Interface Spec Estimator. Memory Standard Rate Support Maximum Frequency (MHz) DDR4 SDRAM Half rate 1,200 DDR3 SDRAM Half rate 1,066 DDR3L SDRAM Half rate 933 Related Information External Memory Interface Spec Estimator Provides the specific details of the memory standards supported. (84) Intel Arria 10 devices support this external memory interface using hard PHY with soft memory controller. Intel(R) Arria(R) 10 Device Datasheet 52 Send Feedback Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 DLL Range Specifications Table 53. DLL Frequency Range Specifications for Intel Arria 10 Devices Intel Arria 10 devices support memory interface frequencies lower than 600 MHz, although the reference clock that feeds the DLL must be at least 600 MHz. To support interfaces below 600 MHz, multiply the reference clock feeding the DLL to ensure the frequency is within the supported range. Parameter Performance (for All Speed Grades) Unit 600 - 1333 MHz DLL operating frequency range DQS Logic Block Specifications Table 54. DQS Phase Shift Error Specifications for DLL-Delayed Clock (tDQS_PSERR) for Intel Arria 10 Devices This error specification is the absolute maximum and minimum error. Symbol Performance (for All Speed Grades) Unit 5 ps tDQS_PSERR Memory Output Clock Jitter Specifications Table 55. Memory Output Clock Jitter Specifications for Intel Arria 10 Devices The clock jitter specification applies to the memory output clock pins clocked by an I/O PLL, or generated using differential signal-splitter and double data I/O circuits clocked by a PLL output routed on a PHY clock network as specified. Intel recommends using PHY clock networks for better jitter performance. The memory output clock jitter is applicable when an input jitter of 10 ps peak-to-peak is applied with bit error rate (BER) 10-12, equivalent to 14 sigma. Protocol DDR3 DDR4 Parameter Non-SmartVID SmartVID (-3V Speed Grade) Data Rate (Mbps) Min Max Data Rate (Mbps) Min Max Unit Clock period jitter tJIT(per) 2,133 -40 40 1,600 -70 70 ps Cycle-to-cycle period jitter tJIT(cc) 2,133 -40 40 1,600 -70 70 ps Duty cycle jitter tJIT(duty) 2,133 -40 40 1,600 -100 100 ps Clock period jitter tJIT(per) 2,400 -40 40 1,600 -63 63 ps Cycle-to-cycle period jitter tJIT(cc) 2,400 -40 40 1,600 -63 63 ps tJIT(duty) 2,400 -40 40 1,600 -100 100 ps Duty cycle jitter Send Feedback Symbol Intel(R) Arria(R) 10 Device Datasheet 53 Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 OCT Calibration Block Specifications Table 56. OCT Calibration Block Specifications for Intel Arria 10 Devices Symbol Description Min Typ Max Unit -- -- 20 MHz > 2000 -- -- Cycles OCTUSRCLK Clock required by OCT calibration blocks TOCTCAL Number of OCTUSRCLK clock cycles required for RS OCT /RT OCT calibration TOCTSHIFT Number of OCTUSRCLK clock cycles required for OCT code to shift out -- 32 -- Cycles TRS_RT Time required between the dyn_term_ctrl and oe signal transitions in a bidirectional I/O buffer to dynamically switch between RS OCT and RT OCT -- 2.5 -- ns Figure 5. Timing Diagram for on oe and dyn_term_ctrl Signals RX Tristate TX Tristate RX oe dyn_term_ctrl TRS_RT TRS_RT HPS Specifications This section provides HPS specifications and timing for Intel Arria 10 devices. If you are using the early I/O release configuration flow, you cannot initially use SmartVID to power your device. Instead, you can use a fixed power supply until after the FPGA is configured. When the FPGA is configured, you can then enable SmartVID. Intel(R) Arria(R) 10 Device Datasheet 54 Send Feedback Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 HPS Reset Input Requirements Table 57. HPS Reset Input Requirements for Intel Arria 10 Devices Description Min Max Unit 600 -- ns 600 -- ns -- 1000 osc1_clk cycles Cold reset deassertion to BSEL sampling, using secure clock, without RAM clearing -- 100 s Cold reset deassertion to BSEL sampling, using secure clock, with RAM clearing -- 50 ms HPS cold reset pulse width HPS warm reset pulse width Cold reset deassertion to BSEL sampling, using osc1_clk (85) (85) osc1_clk is supplied from the HPS_CLK1 pin. Send Feedback Intel(R) Arria(R) 10 Device Datasheet 55 Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 HPS Clock Performance Table 58. Maximum HPS Clock Frequencies Across Device Speed Grades for Intel Arria 10 Devices HPS Clock Temperature Grade VCCL_HPS = 0.9 V (typical) VCCL_HPS = 0.95 V (typical) (86) -1 Speed Grade -2 Speed Grade -3 Speed Grade -1 Speed Grade -2 Speed Grade -3 Speed Grade Unit mpu_base_clk All 1,200 1,000 800 1,500 1,200 1,000 MHz noc_base_clk All 400 400 300 500 400 300 MHz All 600 533 467 600 533 467 MHz hmc_free_clk (87) Related Information * Clock Select, Intel Arria 10 Hard Processor System Technical Reference Manual Provides information on the Clock Select (CSEL) values that require higher voltage operation. * SoC Security chapter, Intel Arria 10 Hard Processor System Technical Reference Manual Provides information about programming fuses. * External Memory Interface Spec Estimator Provides the specific details of the maximum allowed SDRAM operating frequency, which is twice the frequency of hmc_free_clk. HPS PLL Specifications HPS PLL Input Requirements The HPS main PLL receives the clock signal from the HPS_CLK1 pin. For details on this pin, refer to the Intel Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines. (86) You must use 0.95 V VCCL_HPS for CSEL values of 0x7 - 0xE. (87) The hmc_free_clk is 1/2 of the SDRAM interface clock. For the external memory interface clock specifications, refer to the External Memory Interface Spec Estimator. Intel(R) Arria(R) 10 Device Datasheet 56 Send Feedback Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 Table 59. HPS PLL Input Requirements for Intel Arria 10 Devices Description Min Typ Max Unit Clock input range 10 -- 50 MHz Clock input jitter tolerance -- -- 2 % Clock input duty cycle 45 50 55 % Related Information Intel Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines Provides more information about the HPS_CLK1 pin. HPS PLL Performance Table 60. HPS PLL Performance for Intel Arria 10 Devices Description VCCL_HPS -1 Speed Grade -2 Speed Grade -3 Speed Grade Unit Min Max Min Max Min Max 0.95 V 320 3,000 320 2,400 320 2,000 MHz 0.90 V 320 2,400 320 2,000 320 1,600 MHz h2f_user0_clk -- -- 400 -- 400 -- 400 MHz h2f_user1_clk -- -- 400 -- 400 -- 400 MHz HPS PLL VCO output HPS PLL Output Specifications Table 61. HPS PLL Output Specifications for Intel Arria 10 Devices Description Min Max Max Unit -2.5 -- 2.5 % 45 50 55 % Clock rise time 350 -- 1075 ps Clock fall time 200 -- 450 ps -- -- 3.6 ms Clock jitter tolerance Clock duty cycle HPS PLL lock time Send Feedback Intel(R) Arria(R) 10 Device Datasheet 57 Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 Quad SPI Flash Timing Characteristics Table 62. Quad Serial Peripheral Interface (SPI) Flash Timing Requirements for Intel Arria 10 Devices Note that the Intel Arria 10 HPS boot loader calibrates the input timing automatically. Symbol Description Min Typ Max Unit 2.5 -- -- ns 9.25 -- -- ns QSPI_CLK duty cycle 45 50 55 % QSPI_SS asserted to first QSPI_CLK edge 3.6 -- 5.25 ns Last QSPI_CLK edge to QSPI_SS deasserted -1 -- 1 ns 0 -- 2.6 ns Tqspi_ref_clk QSPI_REF_CLK clock period Tclk QSPI_CLK clock period Tdutycycle Tdssfrst Tdsslst (88) (88) Tdo QSPI_DATA output delay Tsu Input setup with respect to QSPI_CLK capture edge 6.5 - (Rdelay x Tqspi_ref_clk) (89) -- -- ns Th Input hold with respect to QSPI_CLK capture edge (Rdelay + 1) x Tqspi_ref_clk (89) -- -- ns 1 -- -- QSPI_CLK Tdssb2b (88) Figure 6. Minimum delay of slave select deassertion between two backto-back transfer Quad SPI Flash Serial Output Timing Diagram Tdssfrst Tdo (min) QSPI_SS Tdsslst Tdo (max) QSPI_CLK QSPI_DATA OUT0 OUT1 OUTn (88) This delay is programmable in whole QSPI_REF_CLK increments using the delay register in the Quad SPI module. (89) Rdelay is programmable in whole QSPI_REF_CLK increments using the delay field in the rddatacap register in the Quad SPI module. Intel(R) Arria(R) 10 Device Datasheet 58 Send Feedback Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 Figure 7. Quad SPI Flash Serial Input Timing Diagram QSPI_SS QSPI_CLK Tsu QSPI_DATA IN0 IN1 INn Th SPI Timing Characteristics Table 63. SPI Master Timing Requirements for Intel Arria 10 Devices You can adjust the input delay timing by programming the rx_sample_dly register. Symbol Description Min Typ Max Unit 16.67 -- -- ns 45 50 55 % 1.5 x TSPI_CLK - 2 -- -- ns Last SPI_CLK edge to SPI_SS deasserted TSPI_CLK - 2 -- -- ns Master-out slave-in (MOSI) output delay -1 -- 1 Tclk SPI_CLK clock period Tdutycycle SPI_CLK duty cycle Tdssfrst Tdsslst (90) (90) Tdio SPI_SS asserted to first SPI_CLK edge ns continued... (90) SPI_SS behavior differs depending on Motorola SPI, TI SSP or Microwire operational mode. Send Feedback Intel(R) Arria(R) 10 Device Datasheet 59 Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 Symbol Tsu (91) Description Min Typ Max Unit 16 - (rx_sample_dly x Tspi_ref_clk) (92) -- -- ns Input hold in respect to SPI_CLK capture edge 0 -- -- ns Minimum delay of slave select deassertion between two backto-back transfers (frames) 1 -- -- SPI_CLK Input setup in respect to SPI_CLK capture edge (93) Th (91) Tdssb2b (91) The capture edge differs depending on the operational mode. For Motorola SPI, the capture edge can be the rising or falling edge depending on the scpol register bit; for TI SSP, the capture edge is the falling edge; for Microwire, the capture edge is the rising edge. (92) A rx_sample_dly value of 0 is an invalid setting. (93) SPI_REF_CLK is the internal reference clock of the SPI Slave, which is l4_main_clk. Intel(R) Arria(R) 10 Device Datasheet 60 Send Feedback Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 Figure 8. SPI Master Output Timing Diagram scph = 0 Tdssfrst (min) SPI_SS Tdsslst (min) Tdio (max) Tdio (min) SPI_CLK (scpol = 0) SPI_CLK (scpol = 1) SPI_MOSI OUT0 OUT1 OUTn SPI_MISO scph = 1 SPI_SS Tdssfrst (min) Tdio (max) Tdsslst (min) Tdio (min) SPI_CLK (scpol = 0) SPI_CLK (scpol = 1) SPI_MOSI OUT0 OUT1 OUTn SPI_MISO Send Feedback Intel(R) Arria(R) 10 Device Datasheet 61 Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 Figure 9. SPI Master Input Timing Diagram scph* = 0 SPI_SS SPI_CLK (scpol = 0) SPI_CLK (scpol = 1) SPI_MOSI Tsu SPI_MISO IN0 Th IN1 INn scph* = 1 SPI_SS SPI_CLK (scpol = 0) SPI_CLK (scpol = 1) SPI_MOSI Tsu SPI_MISO IN0 IN1 Th INn *Serial clock phase configuration bit, in the SPI controller's CTRLR0 register Intel(R) Arria(R) 10 Device Datasheet 62 Send Feedback Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 Table 64. SPI Slave Timing Requirements for Intel Arria 10 Devices Symbol (94) Description Min Typ Max Unit Tclk SPI_CLK clock period 20 -- -- ns Tdutycycle SPI_CLK duty cycle 45 50 55 % Ts SPI slave input setup time 5 -- -- ns Th SPI slave input hold time 8 -- -- ns Tsuss SPI_SS asserted to first SCLK_IN edge 5 -- -- ns Thss Last SCLK_IN edge to SPI_SS deasserted 5 -- -- ns Td Master-in slave-out (MISO) output delay 2 x Tspi_ref_clk + 5.3 (94) -- 3 x Tspi_ref_clk + 11.8 (94) ns SPI_REF_CLK is the internal reference clock of the SPI Slave, which is l4_main_clk. Send Feedback Intel(R) Arria(R) 10 Device Datasheet 63 Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 Figure 10. SPI Slave Output Timing Diagram scph* = 0 Td (max) SPI_SS Td (min) SPI_CLK (scpol = 0) SPI_CLK (scpol = 1) SPI_MISO OUT0 OUT1 OUTn SPI_MOSI scph* = 1 Td (max) SPI_SS Td (min) SPI_CLK (scpol = 0) SPI_CLK (scpol = 1) SPI_MISO OUT0 OUT1 OUTn SPI_MOSI *Serial clock phase configuration bit, in the SPI controller's CTRLR0 register Intel(R) Arria(R) 10 Device Datasheet 64 Send Feedback Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 Figure 11. SPI Slave Input Timing Diagram scph* = 0 Tsuss SPI_SS Thss SPI_CLK (scpol = 0) SPI_CLK (scpol = 1) SPI_MISO SPI_MOSI IN0 scph* = 1 SPI_SS Th Ts IN1 INn Tsuss Thss SPI_CLK (scpol = 0) SPI_CLK (scpol = 1) SPI_MISO SPI_MOSI Ts IN0 IN1 Th INn *Serial clock phase configuration bit, in the SPI controller's CTRLR0 register Send Feedback Intel(R) Arria(R) 10 Device Datasheet 65 Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 SD/MMC Timing Characteristics Table 65. Secure Digital (SD)/MultiMediaCard (MMC) Timing Requirements for Intel Arria 10 Devices These timings apply to SD, MMC, and embedded MMC cards operating at 1.8 V and 3.0 V. Symbol Tsdmmc_cclk Tdutycycle Description Min Typ Max Unit SDMMC_CCLK clock period (Identification mode) -- 2500 -- ns SDMMC_CCLK clock period (Standard SD mode) -- 40 -- ns SDMMC_CCLK clock period (High speed SD mode) -- 20 -- ns SDMMC_CCLK duty cycle 45 50 55 % 7 - (l4_mp_clk x smplsel/2) -- -- ns -2.5 + (l4_mp_clk x smplsel/2) -- -- ns -1 + (l4_mp_clk x drvsel/2) (97) -- 4 + (l4_mp_clk x drvsel/2) (97) ns (95) Tsu SDMMC_CMD/SDMMC_D[7:0] input setup Th SDMMC_CMD/SDMMC_D[7:0] input hold Td SDMMC_CMD/SDMMC_D[7:0] output delay (95) (96) (95) When smplsel is set to 2 (in the system manager) and the reference clock (l4_mp_clk) is 200 MHz for example, the setup time is 2 ns and the hold time is 2.5 ns. The Boot ROM uses a smplsel setting of 0 and U-Boot can adjust this setting later in the boot process. (96) When drvsel is set to 3 (in the system manager) and the reference clock (l4_mp_clk) is 200 MHz for example, the output delay time is 6.5 to 11.5 ns. The Boot ROM uses a drvsel setting of 3 and the Intel Quartus Prime software can adjust this setting later in the boot process. drvsel set to 0 is not a valid setting. (97) l4_mp_clk is the SD/MMC controller reference clock. Intel(R) Arria(R) 10 Device Datasheet 66 Send Feedback Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 Figure 12. SD/MMC Timing Diagram SDMMC_CCLK Td SDMMC_CMD and SDMMC_D (Out) Command/Data Out TSU Th SDMMC_CMD and SDMMC_D (In) Command/Data In USB ULPI Timing Characteristics Table 66. USB 2.0 Transceiver Macrocell Interface Plus (UTMI+) Low Pin Interface (ULPI) Timing Requirements for Intel Arria 10 Devices Symbol (98) Description Min Typ Max Unit -- 16.667 -- ns 1.5 -- 8 ns Tclk USB_CLK clock period Td(98) Clock to USB_STP/USB_DATA[7:0] output delay Tsu Setup time for USB_DIR/USB_NXT/USB_DATA[7:0] 2 -- -- ns Th Hold time for USB_DIR/USB_NXT/USB_DATA[7:0] 1 -- -- ns For the maximum trace length, refer to the Intel Arria 10 SoC Device Design Guidelines. Send Feedback Intel(R) Arria(R) 10 Device Datasheet 67 Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 Figure 13. USB ULPI Timing Diagram USB_CLK USB_STP Td To PHY USB_DATA[7:0] From PHY TSU USB_DIR and USB_NXT Th Related Information USB Interface Design Guidelines, Intel Arria 10 SoC Device Design Guidelines Ethernet Media Access Controller (EMAC) Timing Characteristics Table 67. Reduced Gigabit Media Independent Interface (RGMII) TX Timing Requirements for Intel Arria 10 Devices Symbol Typ Max Unit TX_CLK clock period -- 8 -- ns Tclk (100Base-T) TX_CLK clock period -- 40 -- ns Tclk (10Base-T) TX_CLK clock period -- 400 -- ns Tdutycycle TX_CLK duty cycle 45 50 55 % -0.5 -- 0.5 ns (99) TX_CLK to TXD/TX_CTL output data delay Rise and fall times depend on the I/O standard, drive strength, and loading. Intel recommends simulating your configuration. Intel(R) Arria(R) 10 Device Datasheet 68 Min Tclk (1000Base-T) Td (99) Description Send Feedback Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 Figure 14. RGMII TX Timing Diagram TX_CLK TX_D[3:0] D0 D1 Td TX_CTL Table 68. RGMII RX Timing Requirements for Intel Arria 10 Devices Symbol Description Min Typ Max Unit Tclk (1000Base-T) RX_CLK clock period -- 8 -- ns Tclk (100Base-T) RX_CLK clock period -- 40 -- ns Tclk (10Base-T) RX_CLK clock period -- 400 -- ns Tsu RX_D/RX_CTL setup time 1 -- -- ns RX_D/RX_CTL hold time 1 -- -- ns Th (100) Figure 15. RGMII RX Timing Diagram RX_CLK TSU RX_D[3:0] Th D0 D1 RX_CTL (100 ) For more information, refer to the Intel Arria 10 SoC Device Design Guidelines. Send Feedback Intel(R) Arria(R) 10 Device Datasheet 69 Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 Table 69. Reduced Media Independent Interface (RMII) Clock Timing Requirements for Intel Arria 10 Devices Symbol Description Typ Max Unit Tclk (100Base-T) TX_CLK clock period -- 20 -- ns Tclk (10Base-T) TX_CLK clock period -- 20 -- ns Tdutycycle Clock duty cycle, internal clock source 35 50 65 % Tdutycycle Clock duty cycle, external clock source 35 50 65 % Min Typ Max Unit 7 -- 10 ns Min Typ Max Unit 1 -- -- ns 0.4 -- -- ns Table 70. RMII TX Timing Requirements for Intel Arria 10 Devices Symbol Description Td TX_CLK to TXD/TX_CTL output data delay Table 71. RMII RX Timing Requirements for Intel Arria 10 Devices Symbol Description Tsu RX_D/RX_CTL setup time Th RX_D/RX_CTL hold time Table 72. Management Data Input/Output (MDIO) Timing Requirements for Intel Arria 10 Devices Symbol Description Min Typ Max Unit -- 400 -- ns 10.2 -- 20 ns Tclk MDC clock period Td MDC to MDIO output data delay Tsu Setup time for MDIO data 10 -- -- ns Th Hold time for MDIO data 10 -- -- ns Intel(R) Arria(R) 10 Device Datasheet 70 Min Send Feedback Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 Figure 16. MDIO Timing Diagram MDC Td MDIO_OUT Dout0 Dout1 TSU Th Din0 MDIO_IN Related Information I/O Pin Timing, Intel Arria 10 SoC Device Design Guidelines I2C Timing Characteristics Table 73. I2C Timing Requirements for Intel Arria 10 Devices Symbol Tclk tHIGH tLOW (101) (104) tSU;DAT Description Standard Mode Fast Mode Unit Min Max Min Max Serial clock (SCL) clock period 10 -- 2.5 -- SCL high period 4 (102) SCL low period 4.7 Setup time for serial data line (SDA) data to SCL (105) 0.25 -- 0.6 (103) -- 1.3 (106) -- 0.1 s -- s -- s -- s continued... (101 ) (102 ) (103 ) You can adjust Tclkhigh using the ic_ss_scl_hcnt or ic_fs_scl_hcnt register. The recommended minimum setting for ic_ss_scl_hcnt is 440. The recommended minimum setting for ic_fs_scl_hcnt is 71. Send Feedback Intel(R) Arria(R) 10 Device Datasheet 71 Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 Symbol tHD;DAT(107) Description Standard Mode SCL to SDA output data delay tSU;STA Setup time for a repeated start condition tHD;STA Unit Min Max Min Max 0 3.15 0 0.6 Hold time for SCL to SDA data tVD;DAT and tVD;ACK (108) Fast Mode -- 3.45 (109) -- 0.9 (110) s s 4.7 -- 0.6 -- s Hold time for a repeated start condition 4 -- 0.6 -- s tSU;STO Setup time for a stop condition 4 -- 0.6 -- s tBUF SDA high pulse duration between STOP and START 4.7 -- 1.3 -- s -- 1000 20 300 tr (111) SCL rise time ns continued... (104 ) (105 ) (106 ) (107 ) (108 ) (109 ) (110 ) (111 ) You can adjust Tclklow using the ic_ss_scl_lcnt or ic_fs_scl_lcnt register. The recommended minimum setting for ic_ss_scl_lcnt is 500. The recommended minimum setting for ic_fs_scl_lcnt is 141. THD;DAT is affected by the rise and fall time. tVD;DAT and tVD;ACK is affected by the rise and fall time, in addition to the SDA hold time that is set by adjusting the ic_sda_hold register. Use maximum SDA_HOLD = 240 to be within the specification. Use maximum SDA_HOLD = 60 to be within the specification. Rise and fall time parameters vary depending on the external factors such as: characteristics of IO driver, pull-out resistor value, and total capacitance on the transmission line. Intel(R) Arria(R) 10 Device Datasheet 72 Send Feedback Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 Symbol (112 ) Description Standard Mode Fast Mode Unit Min Max Min Max SCL fall time -- 300 20 x (Vdd / 5.5) 300 ns tf (111) tr (111) SDA rise time -- 1000 20 300 ns tf (111) SDA fall time -- 300 20 x (Vdd / 5.5) (112) 300 ns (112) Vdd is the I2C bus voltage. Send Feedback Intel(R) Arria(R) 10 Device Datasheet 73 Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 Figure 17. I2C Timing Diagram tf tr tSU;DAT 70% 30% SDA tHD;DAT tf tHIGH tr tVD;DAT 70% 30% SCL tHD;STA Tclk tLOW tBUF 70% 30% SDA tSU;STA SCL Intel(R) Arria(R) 10 Device Datasheet 74 tHD;STA tVD;ACK tSU;STO 70% 30% Send Feedback Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 NAND Timing Characteristics Table 74. NAND ONFI 1.0 Timing Requirements for Intel Arria 10 Devices Symbol tWP(113) (113) tWH (113) tRP tREH (113) Write enable hold time Read enable pulse width Read enable hold time Command latch enable to write enable setup time tCLH(113) Command latch enable to write enable hold time tCS(113) Chip enable to write enable setup time (113) tALS(113) (113) Chip enable to write enable hold time Address latch enable to write enable setup time Min Max Unit 10 -- ns 7 -- ns 10 -- ns 7 -- ns 10 -- ns 5 -- ns 15 -- ns 5 -- ns 10 -- ns tALH Address latch enable to write enable hold time 5 -- ns tDS(113) Data to write enable setup time 7 -- ns (113) ) Write enable pulse width tCLS(113) tCH (113 Description tDH Data to write enable hold time 5 -- ns tCEA Chip enable to data access time -- 100 ns tREA Read enable to data access time -- 40 ns tRHZ Read enable to data high impedance -- 200 ns tRR Ready to read enable low 20 -- ns tWB(113) Write enable high to R/B low -- 200 ns This timing is software programmable. Send Feedback Intel(R) Arria(R) 10 Device Datasheet 75 Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 Figure 18. NAND Command Latch Timing Diagram CLE tCLS tCLH tCS tCH CE tWP WE tALS tALH ALE tDS IO0-7 R/B Intel(R) Arria(R) 10 Device Datasheet 76 tDH Command tWB Send Feedback Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 Figure 19. NAND Address Latch Timing Diagram tCLS CLE tCS CE tWP WE ALE IO0-7 Send Feedback tWH tALS tALH tDS tDH Address Intel(R) Arria(R) 10 Device Datasheet 77 Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 Figure 20. NAND Data Output Cycle Timing Diagram tCLH CLE tCH CE tWP WE tWH tALS ALE tDS tDH tDS DOUT 0 IOx Figure 21. tWP tWP tDH tDS DOUT 1 tDH DOUT n NAND Data Input Cycle Timing Diagram tCEA CE tRP tRP RE tREH tRR R/B IOx Intel(R) Arria(R) 10 Device Datasheet 78 tRP tREA tRHZ DIN 0 tREA tRHZ DIN 1 tREA tRHZ DIN n Send Feedback Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 Figure 22. NAND Data Input Timing Diagram for Extended Data Output (EDO) Cycle CE tRP RE tREH tRR tREA R/B tREA tRHZ IOx DIN 0 DIN 1 DIN n tCEA Send Feedback Intel(R) Arria(R) 10 Device Datasheet 79 Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 Figure 23. NAND Read Status Timing Diagram CLE tCLS tCLH tCS tCH tCEA CE WE RE IO0-7 tWP tRHZ tDS tDH 70h Status tREA Intel(R) Arria(R) 10 Device Datasheet 80 Send Feedback Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 Figure 24. NAND Read Status Enhanced Timing Diagram tCLS CLE tCLH tCH tCS tCEA CE tWP WE tALH tWP tALS tWH tALH ALE RE tDS 78h IO0-7 tREA tDH R1 R2 R3 tRHZ Status Trace Timing Characteristics Table 75. Trace Timing Requirements for Intel Arria 10 Devices To increase the trace bandwidth, Intel recommends routing the trace interface to the FPGA in the HPS Platform Designer (Standard) component. The FPGA trace interface offers a 32-bit single data rate path that can be converted to double data rate to minimize FPGA I/O usage. Depending on the trace module that you connect to the HPS trace interface, you may need to include board termination to achieve the maximum sampling speed possible. Refer to your trace module datasheet for termination recommendations. Description Symbol Min Typ Max Unit Tclk CLK clock period 10 -- -- ns Tdutycycle CLK maximum duty cycle 45 50 55 % Td CLK to D0-D3 output data delay -0.5 -- 1 ns Send Feedback Intel(R) Arria(R) 10 Device Datasheet 81 Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 Figure 25. Trace Timing Diagram Clock (DDR) Trace Data (DDR) Tsu td Th GPIO Interface The general-purpose I/O (GPIO) interface has debounce circuitry included to remove signal glitches. The debounce clock frequency ranges from 125 Hz to 32 kHz. The minimum pulse width is one debounce clock cycle and the minimum detectable GPIO pulse width is 62.5 s (at 32 kHz). Any pulses shorter than two debounce clock cycles are filtered by the GPIO peripheral. If the external signal is less than one clock cycle, the external signal is filtered. If the external signal is between one and two clock cycles, the external signal may or may not be filtered depending on the phase of the signal. If the external signal is more than two clock cycles, the external signal will not be filtered. To ensure that the external signal is correctly debounced, set the debounce clock low enough so that by the time two debounce clock periods have passed, the signal has settled. Configuration Specifications This section provides configuration specifications and timing for Intel Arria 10 devices. POR Specifications Power-on reset (POR) delay is defined as the delay between the time when all the power supplies monitored by the POR circuitry reach the minimum recommended operating voltage to the time when the nSTATUS is released high and your device is ready to begin configuration. Intel(R) Arria(R) 10 Device Datasheet 82 Send Feedback Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 Table 76. Fast and Standard POR Delay Specification for Intel Arria 10 Devices POR Delay Minimum Fast 4 Standard 100 Maximum 12 Unit (114) ms 300 ms Related Information MSEL Pin Settings Provides more information about POR delay based on MSEL pin settings for each configuration scheme. JTAG Configuration Timing Table 77. JTAG Timing Parameters and Values for Intel Arria 10 Devices Symbol (114 ) (115 ) Description Min 30, 167 (115) Max Unit -- ns tJCP TCK clock period tJCH TCK clock high time 14 -- ns tJCL TCK clock low time 14 -- ns tJPSU (TDI) TDI JTAG port setup time 2 -- ns tJPSU (TMS) TMS JTAG port setup time 3 -- ns tJPH JTAG port hold time 5 -- ns tJPCO JTAG port clock to output -- 11 ns tJPZX JTAG port high impedance to valid output -- 14 ns tJPXZ JTAG port valid output to high impedance -- 14 ns The maximum pulse width of the fast POR delay is 12 ms, providing enough time for the PCIe hard IP to initialize after the POR trip. The minimum TCK clock period is 167 ns if VCCBAT is within the range 1.2 V - 1.5 V when you perform the volatile key programming. Send Feedback Intel(R) Arria(R) 10 Device Datasheet 83 Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 Related Information Glossary on page 97 Provides the JTAG configuration timing waveforms in the JTAG Timing Specifications term. FPP Configuration Timing DCLK-to-DATA[] Ratio (r) for FPP Configuration Fast passive parallel (FPP) configuration requires a different DCLK-to-DATA[] ratio when you turn on encryption or the compression feature. Depending on the DCLK-to-DATA[] ratio, the host must send a DCLK frequency that is r times the DATA[] rate in byte per second (Bps) or word per second (Wps). For example, in FPP x16 where the r is 2, the DCLK frequency must be 2 times the DATA[] rate in Wps. Table 78. DCLK-to-DATA[] Ratio for Intel Arria 10 Devices You cannot turn on encryption and compression at the same time for Intel Arria 10 devices. Configuration Scheme FPP (8-bit wide) FPP (16-bit wide) FPP (32-bit wide) Encryption Compression DCLK-to-DATA[] Ratio (r) Off Off 1 On Off 1 Off On 2 Off Off 1 On Off 2 Off On 4 Off Off 1 On Off 4 Off On 8 FPP Configuration Timing when DCLK-to-DATA[] = 1 Note: When you enable decompression or the design security feature, the DCLK-to-DATA[] ratio varies for FPP x8, FPP x16, and FPP x32. For the respective DCLK-to-DATA[] ratio, refer to the DCLK-to-DATA[] Ratio for Intel Arria 10 Devices table. Intel(R) Arria(R) 10 Device Datasheet 84 Send Feedback Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 Table 79. FPP Timing Parameters When the DCLK-to-DATA[] Ratio is 1 for Intel Arria 10 Devices Use these timing parameters when the decompression and design security features are disabled. Symbol Parameter Minimum Maximum Unit tCF2CD nCONFIG low to CONF_DONE low -- 1,440 ns tCF2ST0 nCONFIG low to nSTATUS low -- 960 ns tCFG nCONFIG low pulse width 2 -- s tSTATUS tCF2ST1 nSTATUS low pulse width nCONFIG high to nSTATUS high 268 -- 3,000 (116) s 3,000 (117) s tCF2CK (118) nCONFIG high to first rising edge on DCLK 3,010 -- s tST2CK (118) nSTATUS high to first rising edge of DCLK 10 -- s tDSU DATA[] setup time before rising edge on DCLK 5.5 -- ns tDH DATA[] hold time after rising edge on DCLK 0 -- ns tCH DCLK high time 0.45 x 1/fMAX -- s tCL DCLK low time 0.45 x 1/fMAX -- s tCLK DCLK period 1/fMAX -- s fMAX DCLK frequency (FPP x8/x16/x32) -- 100 MHz continued... (116 ) (117 ) (118 ) This value is applicable if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width. This value is applicable if you do not delay configuration by externally holding the nSTATUS low. If nSTATUS is monitored, follow the tST2CK specification. If nSTATUS is not monitored, follow the tCF2CK specification. Send Feedback Intel(R) Arria(R) 10 Device Datasheet 85 Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 Symbol Parameter Minimum Maximum Unit 175 830 s 4 x maximum DCLK period -- -- tCD2CU + (600 x CLKUSR period) -- -- (119) tCD2UM CONF_DONE high to user mode tCD2CU CONF_DONE high to CLKUSR enabled tCD2UMC CONF_DONE high to user mode with CLKUSR option on Related Information FPP Configuration Timing Provides the FPP configuration timing waveforms. FPP Configuration Timing when DCLK-to-DATA[] >1 Table 80. FPP Timing Parameters When the DCLK-to-DATA[] Ratio is >1 for Intel Arria 10 Devices Use these timing parameters when you use the decompression and design security features. Symbol Parameter Minimum Maximum Unit tCF2CD nCONFIG low to CONF_DONE low -- 1,440 ns tCF2ST0 nCONFIG low to nSTATUS low -- 960 ns tCFG nCONFIG low pulse width 2 -- s tSTATUS nSTATUS low pulse width tCF2ST1 nCONFIG high to nSTATUS high tCF2CK (121) nCONFIG high to first rising edge on DCLK 268 3,000 (120) -- 3,000 (120) 3,010 -- s s s continued... (119 ) (120 ) (121 ) The minimum and maximum numbers apply only if you chose the internal oscillator as the clock source for initializing the device. You can obtain this value if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width. If nSTATUS is monitored, follow the tST2CK specification. If nSTATUS is not monitored, follow the tCF2CK specification. Intel(R) Arria(R) 10 Device Datasheet 86 Send Feedback Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 Symbol tST2CK (121) tDSU Parameter Minimum Maximum Unit nSTATUS high to first rising edge of DCLK 10 -- s DATA[] setup time before rising edge on DCLK 5.5 -- ns (122) -- s tDH DATA[] hold time after rising edge on DCLK N-1/fDCLK tCH DCLK high time 0.45 x 1/fMAX -- s tCL DCLK low time 0.45 x 1/fMAX -- s tCLK DCLK period 1/fMAX -- s fMAX DCLK frequency (FPP x8/x16/x32) -- 100 MHz 175 830 s 4 x maximum DCLK period -- -- tCD2CU + (600 x CLKUSR period) -- -- (123) tCD2UM CONF_DONE high to user mode tCD2CU CONF_DONE high to CLKUSR enabled tCD2UMC CONF_DONE high to user mode with CLKUSR option on Related Information FPP Configuration Timing Provides the FPP configuration timing waveforms. (122 ) (123 ) N is the DCLK-to-DATA ratio and fDCLK is the DCLK frequency the system is operating. The minimum and maximum numbers apply only if you use the internal oscillator as the clock source for initializing the device. Send Feedback Intel(R) Arria(R) 10 Device Datasheet 87 Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 AS Configuration Timing Table 81. AS Timing Parameters for AS x1 and AS x4 Configurations in Intel Arria 10 Devices The minimum and maximum numbers apply only if you choose the internal oscillator as the clock source for initializing the device. The tCF2CD, tCF2ST0, tCFG, tSTATUS, and tCF2ST1 timing parameters are identical to the timing parameters for passive serial (PS) mode listed in PS Timing Parameters for Intel Arria 10 Devices table. Symbol Parameter Minimum Maximum Unit tCO DCLK falling edge to AS_DATA0/ASDO output -- 2 ns tSU Data setup time before falling edge on DCLK 1 -- ns tDH Data hold time after falling edge on DCLK 1.5 -- ns tCD2UM CONF_DONE high to user mode 175 830 s tCD2CU CONF_DONE high to CLKUSR enabled 4 x maximum DCLK period -- -- tCD2UMC CONF_DONE high to user mode with CLKUSR option on tCD2CU + (600 x CLKUSR period) -- -- Related Information * PS Configuration Timing on page 89 * AS Configuration Timing Provides the AS configuration timing waveform. Intel(R) Arria(R) 10 Device Datasheet 88 Send Feedback Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 DCLK Frequency Specification in the AS Configuration Scheme Table 82. DCLK Frequency Specification in the AS Configuration Scheme This table lists the internal clock frequency specification for the AS configuration scheme. The DCLK frequency specification applies when you use the internal oscillator as the configuration clock source. The AS multi-device configuration scheme does not support DCLK frequency of 100 MHz. You can only set 12.5, 25, 50, and 100 MHz in the Intel Quartus Prime software. Parameter Minimum Typical Maximum Intel Quartus Prime Software Settings Unit 5.3 7.5 9.7 12.5 MHz 10.5 15.0 19.3 25.0 MHz 21.0 30.0 38.5 50.0 MHz 42.0 60.0 77.0 100.0 MHz DCLK frequency in AS configuration scheme PS Configuration Timing Table 83. PS Timing Parameters for Intel Arria 10 Devices Symbol Parameter Minimum Maximum Unit tCF2CD nCONFIG low to CONF_DONE low -- 1,440 ns tCF2ST0 nCONFIG low to nSTATUS low -- 960 ns tCFG nCONFIG low pulse width 2 -- s tSTATUS nSTATUS low pulse width tCF2ST1 nCONFIG high to nSTATUS high 268 3,000 (124) -- 3,000 (125) s s continued... (124 ) This value is applicable if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width. Send Feedback Intel(R) Arria(R) 10 Device Datasheet 89 Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 Symbol Minimum Maximum Unit nCONFIG high to first rising edge on DCLK 3,010 -- s nSTATUS high to first rising edge of DCLK 10 -- s tDSU DATA[] setup time before rising edge on DCLK 5.5 -- ns tDH DATA[] hold time after rising edge on DCLK 0 -- ns tCH DCLK high time 0.45 x 1/fMAX -- s tCL DCLK low time 0.45 x 1/fMAX -- s tCLK DCLK period 1/fMAX -- s fMAX DCLK frequency -- 125 MHz 175 830 s 4 x maximum DCLK period -- -- tCD2CU + (600 x CLKUSR period) -- -- tCF2CK (126) tST2CK (126) Parameter (127) tCD2UM CONF_DONE high to user mode tCD2CU CONF_DONE high to CLKUSR enabled tCD2UMC CONF_DONE high to user mode with CLKUSR option on Related Information PS Configuration Timing Provides the PS configuration timing waveform. (125 ) (126 ) (127 ) This value is applicable if you do not delay configuration by externally holding the nSTATUS low. If nSTATUS is monitored, follow the tST2CK specification. If nSTATUS is not monitored, follow the tCF2CK specification. The minimum and maximum numbers apply only if you choose the internal oscillator as the clock source for initializing the device. Intel(R) Arria(R) 10 Device Datasheet 90 Send Feedback Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 Initialization Table 84. Initialization Clock Source Option and the Maximum Frequency for Intel Arria 10 Devices Initialization Clock Source Internal Oscillator CLKUSR (128)(129) Configuration Scheme Maximum Frequency (MHz) Number of Clock Cycles for Initialization AS, PS, and FPP 12.5 600 AS, PS, and FPP 100 Configuration Files There are two types of configuration bit stream formats for different configuration schemes: * PS and FPP--Raw Binary File (.rbf) * AS--Raw Programming Data File (.rpd) The .rpd file size follows the Intel configuration devices capacity. However, the actual configuration bit stream size for .rpd file is the same as .rbf file. (128 ) (129 ) To enable CLKUSR as the initialization clock source, in the Intel Quartus Prime software, select Device and Pin Options General Device initialization clock source CLKUSR pin. If you use the CLKUSR pin for AS and transceiver calibration simultaneously, the only allowed frequency is 100 MHz. Send Feedback Intel(R) Arria(R) 10 Device Datasheet 91 Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 Table 85. Configuration Bit Stream Sizes for Intel Arria 10 Devices Use this table to estimate the file size before design compilation. Different configuration file formats, such as a hexadecimal file (.hex) or tabular text file (.ttf) format, have different file sizes. For the different types of configuration file and file sizes, refer to the Intel Quartus Prime software. However, for a specific version of the Intel Quartus Prime software, any design targeted for the same device has the same uncompressed configuration file size. I/O configuration shift register (IOCSR) is a long shift register that facilitates the device I/O peripheral settings. The IOCSR bit stream is part of the uncompressed configuration bit stream, and it is specifically for the Configuration via Protocol (CvP) feature. Uncompressed configuration bit stream sizes are subject to change for improvements and optimizations in the configuration algorithm. Variant Product Line Uncompressed Configuration Bit Stream Size (bits) IOCSR Bit Stream Size (bits) Recommended EPCQ-L Serial Configuration Device Intel Arria 10 GX GX 160 91,729,632 2,507,264 EPCQ-L256 or higher density GX 220 91,729,632 2,507,264 EPCQ-L256 or higher density GX 270 132,638,432 2,507,264 EPCQ-L256 or higher density GX 320 132,638,432 2,507,264 EPCQ-L256 or higher density GX 480 189,710,176 2,695,680 EPCQ-L256 or higher density GX 570 252,959,072 2,884,096 EPCQ-L256 or higher density GX 660 252,959,072 2,884,096 EPCQ-L256 or higher density GX 900 351,292,512 2,756,096 EPCQ-L512 or higher density GX 1150 351,292,512 2,756,096 EPCQ-L512 or higher density GT 900 351,292,512 2,756,096 EPCQ-L512 or higher density GT 1150 351,292,512 2,756,096 EPCQ-L512 or higher density SX 160 91,729,632 2,507,264 EPCQ-L256 or higher density SX 220 91,729,632 2,507,264 EPCQ-L256 or higher density SX 270 132,638,432 2,507,264 EPCQ-L256 or higher density SX 320 132,638,432 2,507,264 EPCQ-L256 or higher density Intel Arria 10 GT Intel Arria 10 SX continued... Intel(R) Arria(R) 10 Device Datasheet 92 Send Feedback Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 Variant Product Line Uncompressed Configuration Bit Stream Size (bits) IOCSR Bit Stream Size (bits) Recommended EPCQ-L Serial Configuration Device SX 480 189,710,176 2,695,680 EPCQ-L256 or higher density SX 570 252,959,072 2,884,096 EPCQ-L256 or higher density SX 660 252,959,072 2,884,096 EPCQ-L256 or higher density Minimum Configuration Time Estimation Table 86. Minimum Configuration Time Estimation for Intel Arria 10 Devices The estimated values are based on the uncompressed configuration bit stream sizes in the Configuration Bit Stream Sizes for Intel Arria 10 Devices table Variant Intel Arria 10 GX Product Line Active Serial (130) Fast Passive Parallel (131) Width DCLK (MHz) Minimum Configuration Time (ms) Width DCLK (MHz) Minimum Configuration Time (ms) GX 160 4 100 204.81 32 100 25.60 GX 220 4 100 204.81 32 100 25.60 GX 270 4 100 306.48 32 100 38.31 GX 320 4 100 306.48 32 100 38.31 GX 480 4 100 443.35 32 100 55.42 GX 570 4 100 632.08 32 100 79.01 GX 660 4 100 632.08 32 100 79.01 GX 900 4 100 883.20 32 100 110.40 GX 1150 4 100 883.20 32 100 110.40 continued... (130 ) (131 ) The minimum configuration time is calculated based on DCLK frequency of 100 MHz. Only external CLKUSR may guarantee the frequency accuracy of 100 MHz. If you use internal oscillator of 100 MHz, you may not get the actual frequency of 100 MHz. For the DCLK frequency using internal oscillator, refer to the DCLK Frequency Specification in the AS Configuration Scheme table. Maximum FPGA FPP bandwidth may exceed bandwidth available from some external storage or control logic. Send Feedback Intel(R) Arria(R) 10 Device Datasheet 93 Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 Variant Product Line Intel Arria 10 GT Intel Arria 10 SX Active Serial (130) Fast Passive Parallel (131) Width DCLK (MHz) Minimum Configuration Time (ms) Width DCLK (MHz) Minimum Configuration Time (ms) GT 900 4 100 883.20 32 100 110.40 GT 1150 4 100 883.20 32 100 110.40 SX 160 4 100 204.81 32 100 25.60 SX 220 4 100 204.81 32 100 25.60 SX 270 4 100 306.48 32 100 38.31 SX 320 4 100 306.48 32 100 38.31 SX 480 4 100 443.35 32 100 55.42 SX 570 4 100 632.08 32 100 79.01 SX 660 4 100 632.08 32 100 79.01 Related Information (130 ) (131 ) * Configuration Files on page 91 * DCLK Frequency Specification in the AS Configuration Scheme on page 89 Provides the DCLK frequency using internal oscillator. The minimum configuration time is calculated based on DCLK frequency of 100 MHz. Only external CLKUSR may guarantee the frequency accuracy of 100 MHz. If you use internal oscillator of 100 MHz, you may not get the actual frequency of 100 MHz. For the DCLK frequency using internal oscillator, refer to the DCLK Frequency Specification in the AS Configuration Scheme table. Maximum FPGA FPP bandwidth may exceed bandwidth available from some external storage or control logic. Intel(R) Arria(R) 10 Device Datasheet 94 Send Feedback Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 Remote System Upgrades Table 87. Remote System Upgrade Circuitry Timing Specifications for Intel Arria 10 Devices Parameter Minimum Maximum Unit fMAX_RU_CLK (132) -- 40 MHz tRU_nCONFIG (133) 250 -- ns 250 -- ns tRU_nRSTIMER (134) Related Information * Remote System Upgrade State Machine Provides more information about configuration reset (RU_CONFIG) signal. * User Watchdog Timer Provides more information about reset_timer (RU_nRSTIMER) signal. User Watchdog Internal Circuitry Timing Specifications Table 88. User Watchdog Internal Oscillator Frequency Specifications for Intel Arria 10 Devices Parameter User watchdog internal oscillator frequency Minimum Typical Maximum Unit 5.3 7.9 12.5 MHz I/O Timing I/O timing data is typically used prior to designing the FPGA to get an estimate of the timing budget as part of the timing analysis. You may generate the I/O timing report manually using the Timing Analyzer or using the automated script. (132 ) (133 ) (134 ) This clock is user-supplied to the remote system upgrade circuitry. If you are using the Remote Update Intel FPGA IP core, the clock user-supplied to the Remote Update Intel FPGA IP core must meet this specification. This is equivalent to strobing the reconfiguration input of the Remote Update Intel FPGA IP core high for the minimum timing specification. This is equivalent to strobing the reset_timer input of the Remote Update Intel FPGA IP core high for the minimum timing specification. Send Feedback Intel(R) Arria(R) 10 Device Datasheet 95 Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 The Intel Quartus Prime Timing Analyzer provides a more accurate and precise I/O timing data based on the specifics of the design after you complete place-and-route. Related Information AN 775: I/O Timing Information Generation Guidelines Provides the techniques to generate I/O timing information using the Intel Quartus Prime software. Programmable IOE Delay Table 89. IOE Programmable Delay for Intel Arria 10 Devices For the exact values for each setting, use the latest version of the Intel Quartus Prime software. The values in the table show the delay of programmable IOE delay chain with maximum offset settings after excluding the intrinsic delay (delay at minimum offset settings). Programmable IOE delay settings are only applicable for I/O buffers and do not apply for any other delay elements in the PHYLite for Parallel Interfaces Intel Arria 10 FPGA IP core. Parameter (135 ) (136 ) (135) Maximum Offset Minimum Offset (136) Input Delay Chain Setting (IO_IN_DLY_CHN) 63 Output Delay Chain Setting (IO_OUT_DLY_CHN) 15 Slow Model Unit Extended Industrial -E1S, -E1H, - I1S, -I1H -E2L, -E2S, -I2L, -I2S -E3L, -E3S, -I3L, -I3S 0 2.012 2.003 4.541 5.241 6.035 ns 0 0.478 0.475 1.088 1.263 1.462 ns You can set this value in the Intel Quartus Prime software by selecting Input Delay Chain Setting or Output Delay Chain Setting in the Assignment Name column. Minimum offset does not include the intrinsic delay. Intel(R) Arria(R) 10 Device Datasheet 96 Fast Model Send Feedback Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 Glossary Table 90. Glossary Term Differential I/O Standards Definition Receiver Input Waveforms Single-Ended Waveform Positive Channel (p) = VIH VID Negative Channel (n) = VIL VCM Ground Differential Waveform VID p-n=0V VID Transmitter Output Waveforms Single-Ended Waveform Positive Channel (p) = VOH VOD Negative Channel (n) = VOL VCM Ground Differential Waveform VOD p-n=0V VOD fHSCLK I/O PLL input clock frequency. fHSDR High-speed I/O block--Maximum/minimum LVDS data transfer rate (fHSDR = 1/TUI), non-DPA. continued... Send Feedback Intel(R) Arria(R) 10 Device Datasheet 97 Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 Term Definition fHSDRDPA High-speed I/O block--Maximum/minimum LVDS data transfer rate (fHSDRDPA = 1/TUI), DPA. J High-speed I/O block--Deserialization factor (width of parallel data bus). JTAG Timing Specifications JTAG Timing Specifications: TMS TDI t JCH t JCP t JCL t JPSU tJPH TCK tJPZX t JPXZ tJPCO TDO RL Receiver differential input discrete resistor (external to the Intel Arria 10 device). Sampling window (SW) Timing Diagram--the period of time during which the data must be valid in order to capture it correctly. The setup and hold times determine the ideal strobe position in the sampling window, as shown: Bit Time 0.5 x TCCS Single-ended voltage referenced I/O standard RSKM Sampling Window (SW) RSKM 0.5 x TCCS The JEDEC standard for the SSTL and HSTL I/O defines both the AC and DC input signal values. The AC values indicate the voltage levels at which the receiver must meet its timing specifications. The DC values indicate the voltage levels at which the final logic state of the receiver is unambiguously defined. After the receiver input has crossed the AC value, the receiver changes to the new logic state. The new logic state is then maintained as long as the input stays beyond the DC threshold. This approach is intended to provide predictable receiver timing in the presence of input waveform ringing. Single-Ended Voltage Referenced I/O Standard continued... Intel(R) Arria(R) 10 Device Datasheet 98 Send Feedback Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 Term Definition V CCIO V OH V IH(AC) V REF V IH(DC) V IL(DC) V IL(AC) V OL V SS tC High-speed receiver/transmitter input and output clock period. TCCS (channel-to-channel-skew) The timing difference between the fastest and slowest output edges, including the tCO variation and clock skew, across channels driven by the same PLL. The clock is included in the TCCS measurement (refer to the Timing Diagram figure under SW in this table). tDUTY High-speed I/O block--Duty cycle on high-speed transmitter output clock. tFALL Signal high-to-low transition time (80-20%) tINCCJ Cycle-to-cycle jitter tolerance on the PLL clock input tOUTPJ_IO Period jitter on the GPIO driven by a PLL tOUTPJ_DC Period jitter on the dedicated clock output driven by a PLL tRISE Signal low-to-high transition time (20-80%) Timing Unit Interval (TUI) The timing budget allowed for skew, propagation delays, and the data sampling window. (TUI = 1/(Receiver Input Clock Frequency Multiplication Factor) = tC/w). VCM(DC) DC Common mode input voltage. VICM Input Common mode voltage--The common mode of the differential signal at the receiver. VID Input differential voltage swing--The difference in voltage between the positive and complementary conductors of a differential transmission at the receiver. VDIF(AC) AC differential input voltage--Minimum AC input differential voltage required for switching. VDIF(DC) DC differential input voltage-- Minimum DC input differential voltage required for switching. VIH Voltage input high--The minimum positive voltage applied to the input which is accepted by the device as a logic high. continued... Send Feedback Intel(R) Arria(R) 10 Device Datasheet 99 Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 Term Definition VIH(AC) High-level AC input voltage VIH(DC) High-level DC input voltage VIL Voltage input low--The maximum positive voltage applied to the input which is accepted by the device as a logic low. VIL(AC) Low-level AC input voltage VIL(DC) Low-level DC input voltage VOCM Output Common mode voltage--The common mode of the differential signal at the transmitter. VOD Output differential voltage swing--The difference in voltage between the positive and complementary conductors of a differential transmission line at the transmitter. VSWING Differential input voltage VIX Input differential cross point voltage VOX Output differential cross point voltage W High-speed I/O block--Clock Boost Factor Document Revision History for the Intel Arria 10 Device Datasheet Document Version Changes 2018.11.29 Removed tR and tF specifications in the FPP Timing Parameters When the DCLK-to-DATA[] Ratio is >1 for Intel Arria 10 Devices table. 2018.09.24 Removed specifications for automotive-grade devices (-A3 speed grade). 2018.06.15 * * * * 2018.04.06 * * Added Intel Arria 10 Devices Overshoot Duration figure and description. Removed Equation for OCT Variation Without Recalibration. Updated the descriptions for Tdssfrst, Tdsslst, Tsu, and Th in the Quad Serial Peripheral Interface (SPI) Flash Timing Requirements for Intel Arria 10 Devices table. Updated the column header from "Minimum Number of Clock Cycles" to "Number of Clock Cycles for Initialization" in the Initialization Clock Source Option and the Maximum Frequency for Intel Arria 10 Devices table. Added notes to IOUT specification in the Absolute Maximum Ratings for Intel Arria 10 Devices table. Updated the maximum frequency for DDR3L SDRAM in the Memory Standards Supported by the HPS Hard Memory Controller for Intel Arria 10 Devices table. Intel(R) Arria(R) 10 Device Datasheet 100 Send Feedback Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 Date January 2018 Version 2018.01.09 Changes * * * * * * * Corrected the clock name from "osc1 clock" to osc1_clk and added a note in the HPS Reset Input Requirements for Intel Arria 10 Devices table. * Added description about the HPS_CLK1 pin in the HPS PLL Input Requirements section. * Updated the note for Tsu and Th in the Secure Digital (SD)/MultiMediaCard (MMC) Timing Requirements for Intel Arria 10 Devices table. * Updated the note to CLKUSR in the Initialization Clock Source Option and the Maximum Frequency for Intel Arria 10 Devices table. Updated the I/O Timing section on the I/O timing information generation guidelines. Updated the description and maximum offset values in the IOE Programmable Delay for Intel Arria 10 Devices table. * * June 2017 2017.06.16 Added -E1H and -I1H speed grades. Removed -E2V and -I2V speed grades. Added a note to the -A3 speed grade to state that the specifications for automotive-grade devices are preliminary, pending characterization. Updated the Recommended Operating Conditions for Intel Arria 10 Devices table. -- Added a note to VI -- Removed the note to TJ for Industrial and Automotive devices. Note removed: -40C is only applicable to Start of Test, when the device is powered-on. The device does not stay at the minimum junction temperature for a long time. Updated the note to RSDS (HIO) and Mini-LVDS (HIO) in the Differential I/O Standards Specifications for Intel Arria 10 Devices table. Added KDB link on PLL jitter compensation in the following tables: -- Fractional PLL Specifications for Intel Arria 10 Devices -- I/O PLL Specifications for Intel Arria 10 Devices * * * * * * * * Added specifications for automotive-grade devices. Removed -E1L and -I1L speed grades. Clarified the voltage requirement footnote for PCIe Gen3 support in the "Transceiver Power Supply Operating Conditions for Intel Arria 10 GX/SX Devices" table. Added notes for TJ for Industrial and Automotive devices in Recommended Operating Conditions for Intel Arria 10 Devices table. Updated the description for VCCH_GXB in the following tables: -- Absolute Maximum Ratings for Intel Arria 10 Devices -- Transceiver Power Supply Operating Conditions for Intel Arria 10 GX/SX Devices -- Transceiver Power Supply Operating Conditions for Intel Arria 10 GT Devices Added full pin names in the "Transceiver Power Supply Operating Conditions for Intel Arria 10 GX/SX Devices" table. Clarified that the channel span for the x1 and x6 clock networks is six channels in a single bank in the "Transceiver Clock Network Maximum Data Rate Specifications" table. Updated fVCO specifications in Fractional PLL Specifications for Intel Arria 10 Devices table. continued... Send Feedback Intel(R) Arria(R) 10 Device Datasheet 101 Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 Date Version Changes * * * * * May 2017 2017.05.08 * * * * * * * * * * * March 2017 2017.03.15 * * * * Updated the following tables to keep only the maximum frequencies: -- Memory Standards Supported by the Hard Memory Controller for Intel Arria 10 Devices -- Memory Standards Supported by the Soft Memory Controller for Intel Arria 10 Devices -- Memory Standards Supported by the HPS Hard Memory Controller for Intel Arria 10 Devices Updated the description for Memory Output Clock Jitter Specifications for Intel Arria 10 Devices table. Updated the unit for "Cold reset deassertion to BSEL sampling, using osc1 clock" in HPS Reset Input Requirements for Intel Arria 10 Devices table. Updated the name of the internal reference clock to SPI_REF_CLK in the footnote in the following tables: -- SPI Master Timing Requirements for Intel Arria 10 Devices -- SPI Slave Timing Requirements for Intel Arria 10 Devices Updated maximum values for tCF2CD from 600 ns to 1,440 ns and tCF2ST0 from 600 ns to 960 ns in the following tables: -- FPP Timing Parameters When the DCLK-to-DATA[] Ratio is 1 for Intel Arria 10 Devices -- FPP Timing Parameters When the DCLK-to-DATA[] Ratio is >1 for Intel Arria 10 Devices -- PS Timing Parameters for Intel Arria 10 Devices Updated VCCBAT specifications in Recommended Operating Conditions for Intel Arria 10 Devices table. Changed the maximum skew specification for the xN clock line in the "Transmitter Channel-to-channel Skew Specifications" table. Changed the PCIe Gen3 HIP-Fabric interface spec for E3S and I3S devices in the "High-Speed Serial Transceiver-Fabric Interface Performance for Intel Arria 10 GX/SX Devices" table. Changed the conditions for VICM in the "Receiver Specifications" table. Removed the DC Coupling specifications footnote from the "Receiver Specifications" table. Changed the conditions for the differential on-chip termination resistors parameter in the "Transmitter Specifications" table. Updated the footnote for VICM (AC and DC coupled) parameter in the "Receiver Specifications" table. Added footnotes to the minimum specifications for the fPLL input reference clock frequency in the "Reference Clock Specifications" table depending on the selected mode. Changed the Core Speed Grade options in the "High-Speed Serial Transceiver-Fabric Interface Performance for Intel Arria 10 GX/SX Devices" table. Added information on power supply using early I/O release configuration flow in HPS Specifications section. Added description in the Configuration Bit Stream Sizes for Intel Arria 10 Devices table. Changed the minimum value for the fPLL input reference clock frequency in the "Reference Clock Specifications" table. Added a footnote to the Supported I/O Standards parameter in the "Receiver Specifications" table. Added a footnote to VCCR_GXB[L, R] and VCCT_GXB[L, R] in the "Transceiver Power Supply Operating Conditions for Arria 10 GX/SX Devices" table. Added fCASC_INPFD specification in the following tables: -- Fractional PLL Specifications for Intel Arria 10 Devices -- I/O PLL Specifications for Intel Arria 10 Devices continued... Intel(R) Arria(R) 10 Device Datasheet 102 Send Feedback Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 Date Version Changes * * * * * * * * October 2016 2016.10.31 * * * * * * * * June 2016 2016.06.24 * * * * * Updated links to the External Memory Interface Spec Estimator in the following sections: -- Memory Standards Supported by the Hard Memory Controller -- Memory Standards Supported by the Soft Memory Controller -- Memory Standards Supported by the HPS Hard Memory Controller Updated Maximum HPS Clock Frequencies Across Device Speed Grades for Intel Arria 10 Devices table. -- Removed temperature ranges. -- Updated mpu_base_clk specification from 1,000 MHz to 1,200 MHz in -1 speed grade for VCCL_HPS = 0.9 V (typical). Updated HPS PLL VCO output maximum specification from 2,000 MHz to 2,400 MHz in -1 speed grade for VCCL_HPS = 0.9 V in HPS PLL Performance for Intel Arria 10 Devices table. Updated links to the Intel Arria 10 SoC Device Design Guidelines in the following sections: -- USB ULPI Timing Characteristics -- Ethernet Media Access Controller (EMAC) Timing Characteristics Updated uncompressed configuration bit stream size (bits) in Configuration Bit Stream Sizes for Intel Arria 10 Devices table. Added descriptions for Programmable IOE Delay. Removed PowerPlay text from tool name. Rebranded as Intel. Added reference to the Intel Arria 10 SoC Device Design Guidelines for the USB 2.0 Transceiver Macrocell Interface Plus (UTMI+) Low Pin Interface (ULPI) Timing Requirements for Intel Arria 10 Devices table. Added reference to the Intel Arria 10 SoC Device Design Guidelines for the RGMII RX Timing Requirements for Intel Arria 10 Devices table. Updated the fVCO values in the Fractional PLL Specifications for Intel Arria 10 Devices table. Updated the tOUTPJ_DC and tOUTCCJ_DC values in the I/O PLL Specifications for Intel Arria 10 Devices table. Updated the description to the DPA Lock Time Specifications for Intel Arria 10 Devices table as the specifications are applicable to both extended and industrial grades. Updated the description to the Maximum HPS Clock Frequencies Across Device Speed Grades for Intel Arria 10 Devices table as the specifications are applicable to both extended and industrial temperatures. Removed Preliminary tag for the Trace Timing Requirements for Intel Arria 10 Devices table. Changed the condition for the slew rate setting in the "Transmitter Specifications" table. Updated VCCL_HPS specifications in HPS Power Supply Operating Conditions for Intel Arria 10 SX Devices table. Restructured the following tables: -- OCT Calibration Accuracy Specifications for Intel Arria 10 Devices -- OCT Without Calibration Resistance Tolerance Specifications for Intel Arria 10 Devices Removed PCML information in Differential I/O Standards Specifications for Intel Arria 10 Devices table. Changed values in the "Transmitter and Receiver Data Rate Performance" table. Updated specifications for memory standards supported by the hard memory controller, soft memory controller, and HPS hard memory controller. continued... Send Feedback Intel(R) Arria(R) 10 Device Datasheet 103 Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 Date Version Changes * * * * * * * * * * * * * * * Updated DLL operating frequency range in DLL Frequency Range Specifications for Intel Arria 10 Devices table. Updated Memory Output Clock Jitter Specifications for Intel Arria 10 Devices table. Updated HPS Clock Performance specifications. Updated HPS PLL Performance for Intel Arria 10 Devices table. -- Updated HPS PLL VCO output -3 speed grade maximum specification for 0.95 V VCCL_HPS. -- Added HPS PLL VCO output specifications for 0.90 V VCCL_HPS. -- Added h2f_user0_clk and h2f_user1_clk specifications. Added a new table for HPS PLL Output Specifications. Updated Quad Serial Peripheral Interface (SPI) Flash Timing Requirements for Intel Arria 10 Devices table. -- Updated QSPI_CLK clock name. -- Updated Tclk, Tdssfrst, Tdsslst, and Tdo specifications. -- Added Tsu and Th specifications. -- Removed Tdin_start and Tdin_end specifications. Updated Tdssfrst, Tdsslst, Tdio, and Tsu specifications in SPI Master Timing Requirements for Intel Arria 10 Devices table. Updated Th and Td specifications in SPI Slave Timing Requirements for Intel Arria 10 Devices table. Updated Tsu, Th, and Td specifications in Secure Digital (SD)/MultiMediaCard (MMC) Timing Requirements for Intel Arria 10 Devices table. Added a note to Td in Reduced Gigabit Media Independent Interface (RGMII) TX Timing Requirements for Intel Arria 10 Devices table. Updated Th specifications in RGMII RX Timing Requirements for Intel Arria 10 Devices table. Updated Td specifications in RMII TX Timing Requirements for Intel Arria 10 Devices table. Added notes in I2C Timing Requirements for Intel Arria 10 Devices table. Updated Trace Timing Requirements for Intel Arria 10 Devices table. -- Added description about increasing trace bandwidth. -- Updated Tclk minimum specification from 5 ns to 10 ns. Updated the information on GPIO interface. continued... Intel(R) Arria(R) 10 Device Datasheet 104 Send Feedback Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 Date Version Changes * * * * * * May 2016 2016.05.02 * * * * * * * * Updated the following timing diagrams: -- Quad SPI Flash Serial Output Timing Diagram -- Quad SPI Flash Serial Input Timing Diagram -- SPI Master Output Timing Diagram -- SPI Master Input Timing Diagram -- SPI Slave Output Timing Diagram -- SPI Slave Input Timing Diagram -- I2C Timing Diagram -- NAND Address Latch Timing Diagram -- NAND Data Input Timing Diagram for Extended Data Output (EDO) Cycle -- NAND Read Status Timing Diagram -- Trace Timing Diagram Updated DCLK Frequency Specification in the AS Configuration Scheme table. Updated IOCSR bit stream sizes in Configuration Bit Stream Sizes for Intel Arria 10 Devices table. Corrected product line naming in the following tables: -- Configuration Bit Stream Sizes for Intel Arria 10 Devices -- Minimum Configuration Time Estimation for Intel Arria 10 Devices Updated IOE Programmable Delay for Intel Arria 10 Devices table. Removed Preliminary tags for all tables, except Trace Timing Requirements for Intel Arria 10 Devices table. Updated Recommended Operating Conditions for Intel Arria 10 Devices table. -- Added specifications for 0.95 V typical value for VCC, VCCP, and VCCERAM. -- Updated SmartVID specifications for VCC and VCCP. -- Updated notes to VCC, VCCP, VCCERAM, and VCCBAT. Updated specifications for SSTL-12 240- RS, SSTL-135 34- RS, and SSTL-135 40- RS in OCT Calibration Accuracy Specifications for Intel Arria 10 Devices table. Removed the condition VCCIO = 1.5 for 100- RD in OCT Without Calibration Resistance Tolerance Specifications for Intel Arria 10 Devices table. Changed pin capacitance to maximum values. Added SSTL-135 Class I, II, SSTL-125 Class I, II, and SSTL-12 Class I, II I/O standards in the following tables: -- Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications for Intel Arria 10 Devices -- Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications for Intel Arria 10 Devices -- Differential SSTL I/O Standards Specifications for Intel Arria 10 Devices Corrected VOD specifications for Mini-LVDS (HIO) to 0.6 V in Differential I/O Standards Specifications for Intel Arria 10 Devices table. Changed the backplane data rates in the "Transceiver Power Supply Operating Conditions for Intel Arria 10 GX/SX Devices" table. Changed the conditions and backplane data rates in the "Transceiver Power Supply Operating Conditions for Intel Arria 10 GT Devices" table. continued... Send Feedback Intel(R) Arria(R) 10 Device Datasheet 105 Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 Date Version Changes * * * * * * * * * * * * * * * * * * * February 2016 2016.02.11 * * * * * * Changed the backplane data rates in the "Transceiver Performance for Intel Arria 10 GX/SX Devices" section. Changed the backplane data rates in the "Transceiver Performance for Intel Arria 10 GT Devices" section. Changed the minimum frequency in the "CMU PLL Performance" table. Changed the conditions and added a description to the "High-Speed Serial Transceiver-Fabric Interface Performance for Intel Arria 10 GX/SX Devices" table. Removed transceiver speed grade 5 from all tables in the "Transceiver Performance for Intel Arria 10 GX/SX Devices" section. Changed the notes in the "Transmitter and Receiver Data Rate Performance" table. Added a description to the "High-Speed Serial Transceiver-Fabric Interface Performance for Intel Arria 10 GT Devices" table. Changed the clock network names in the "Transceiver Clock Network Maximum Data Rate Specifications" table. Changed the conditions in the "High-Speed Serial Transceiver-Fabric Interface Performance for Intel Arria 10 GT Devices" table. Changed the channel span specifications in the "Transmitter Channel-to-channel Skew Specifications" table. Updated fVCO, fCLBW, tPLL_PSERR, and jitter specifications in Fractional PLL Specifications for Intel Arria 10 Devices table. Updated tOUTDUTY and jitter specifications in I/O PLL Specifications for Intel Arria 10 Devices table. Updated the note to fIN specifications for fPLL and IOPLL. Updated High-Speed I/O Specifications for Intel Arria 10 Devices table. -- Added true RSDS and true mini-LVDS output standards data rates. -- Updated speed grades to reflect SmartVID specifications. -- Updated Transmitter fHSDR and Receiver fHSDRDPA specifications. -- Added minimum data rate for Receiver fHSDRDPA specifications. Updated LVDS I/O bank and 3 V I/O bank specifications, and added SmartVID specifications in Memory Standards Supported by the Hard Memory Controller for Intel Arria 10 Devices and Memory Standards Supported by the Soft Memory Controller for Intel Arria 10 Devices tables. Added new table: Memory Standards Supported by the HPS Hard Memory Controller for Intel Arria 10 Devices. Updated tCO from 4 ns to 2 ns in AS Timing Parameters for AS x1 and AS x4 Configurations in Intel Arria 10 Devices table. Added IOCSR definition and updated column heading from "IOCSR .rbf Size (bits)" to "IOCSR Bit Stream Size (bits)" in Configuration Bit Stream Sizes for Intel Arria 10 Devices table. Removed M suffix and VCC PowerManager feature. Changed the datarates in the "Transceiver Power Supply Operating Conditions for Intel Arria 10 GT Devices" table. Changed the available speed grades and datarates in the "Transceiver Performance for Intel Arria 10 GT Devices" table. Changed the available speed grades and datarates in the "ATX PLL Performance" table. Changed the available speed grades and datarates in the "Fractional PLL Performance" table. Changed the available speed grades in the "CMU PLL Performance" table. Changed the available speed grades and frequencies in the "High-Speed Serial Transceiver-Fabric Interface Performance for Arria 10 GT Devices" table. continued... Intel(R) Arria(R) 10 Device Datasheet 106 Send Feedback Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 Date December 2015 Version 2015.12.31 Changes * * Updated M20K block specifications for "True dual port, all supported widths" and "ROM, all supported widths" in the Memory Clock Performance Specifications (VCC and VCCP at 0.9 V Typical Value) table. Updated maximum resolution from 8 bit 6 bit and added minimum clock frequency of 0.1 MHz in Internal Voltage Sensor Specifications for Intel Arria 10 Devices table. Updated the sinusoidal jitter from 0.35 UI to 0.28 UI in LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specifications. * December 2015 2015.12.18 * * Changed the minimum specifications in the "Transceiver Power Supply Operating Conditions for Arria 10 GT Devices" table. Changed conditions in the "Transmitter and Receiver Data Rate Performance" table. November 2015 2015.11.02 * * Added power option V which is supported with the SmartVID feature (lowest static power). Added note for SmartVID in Recommended Operating Conditions for Intel Arria 10 Devices table. Note: SmartVID is supported in devices with -2V and -3V speed grades only. Removed 20- RT in OCT Calibration Accuracy Specifications for Intel Arria 10 Devices table. Updated specifications in OCT Without Calibration Resistance Tolerance Specifications for Intel Arria 10 Devices table. Updated the note for Value column in the Internal Weak Pull-Up Resistor Values for Intel Arria 10 Devices table. Added Internal Weak Pull-Down Resistor Values for Intel Arria 10 Devices table. Updated fractional PLL specifications: -- Updated fIN minimum from 50 MHz to 30 MHz and maximum from 1000 MHz to 800 MHz for all speed grades. -- Updated fINPFD minimum from 50 MHz to 30 MHz and maximum from 325 MHz to 700 MHz. -- Updated fVCO minimum from 3.125 GHz to 3.5 GHz and maximum from 6.25 GHz to 7.05 GHz. -- Updated tEINDUTY minimum from 40% to 45% and maximum from 60% to 55%. -- Removed the conditions for fOUT and fCLBW. -- Updated the descriptions for fDYCONFIGCLK, tLOCK, and tARESET. Added -E2V, -I2V, -E3V, and -I3V speed grades in DSP Block Performance Specifications for Intel Arria 10 Devices (VCC and VCCP at 0.9 V Typical Value) table. Updated Memory Block Performance Specifications for Intel Arria 10 Devices table for VCC and VCCP at 0.9 V typical value. Added memory block performance specifications for VCC and VCCP at 0.95 V typical value. Removed the "Minimum Resolution with no Missing Codes" column in Internal Temperature Sensing Diode Specifications for Intel Arria 10 Devices table. Added a link in the Internal Temperature Sensing Diode Specifications section: Transfer Function for Internal TSD topic in the Power Management in Intel Arria 10 Devices chapter, Intel Arria 10 Core Fabric and General Purpose I/Os Handbook. Added descriptions to External Temperature Sensing Diode Specifications for Intel Arria 10 Devices table. Updated Internal Voltage Sensor Specifications for Intel Arria 10 Devices table. -- Updated maximum resolution from 12 bits to 8 bits. Removed minimum resolution value. -- Updated maximum integral non-linearity (INL) from 3 LSB to 1 LSB. -- Updated maximum clock frequency from 20 MHz to 11 MHz. -- Added gain error and offset error specifications. -- Removed signal to noise and distortion ratio (SNR) specifications. -- Removed Bipolar input mode specifications. * * * * * * * * * * continued... Send Feedback Intel(R) Arria(R) 10 Device Datasheet 107 Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 Date Version Changes * * * * * * * * * * * Updated "slow clock" to "core clock" in DPA Lock Time Specifications with DPA PLL Calibration Enabled diagram. Updated the maximum values of the following conditions for Transmitter True Differential I/O Standards - fHSDR (data rate) parameter in High-Speed I/O Specifications for Intel Arria 10 Devices table. -- SERDES factor J = 2, uses DDR registers -- SERDES factor J = 1, uses DDR registers Added the following tables: -- Memory Standards Supported by the Hard Memory Controller for Intel Arria 10 Devices -- Memory Standards Supported by the Soft Memory Controller for Intel Arria 10 Devices Updated minimum TOCTCAL value from 1000 cycles to 2000 cycles in OCT Calibration Block Specifications for Intel Arria 10 Devices table. Updated the hmc_free_clk specifications for the following speed grades in HPS Clock Performance for Intel Arria 10 Devices table: -- -1 speed grade: Updated from 667 MHz to 533 MHz. -- -2 speed grade: Updated from 544 MHz to 533 MHz. Changed from Tsclk to Tclk and added the following specifications in the Quad Serial Peripheral Interface (SPI) Flash Timing Requirements for Intel Arria 10 Devices table. -- Tqspi_clk -- Tdin_start -- Tdin_end Updated SPI Master Timing Requirements for Intel Arria 10 Devices table. -- Changed the symbol from Tspi_clk to Tclk. -- Added note to Tdssfrst, Tdsslst, and Th. -- Updated note to Tsu. -- Updated the description for Tsu and Th. Updated the note to Tssfsu, Tssfh, Tsslsu, and Tsslh in the SPI Slave Timing Requirements for Intel Arria 10 Devices table. Updated the following timing diagrams: -- Quad SPI Flash Serial Output Timing Diagram -- SPI Master Output Timing Diagram -- SPI Slave Output Timing Diagram Added the following timing diagrams: -- Quad SPI Flash Serial Input Timing Diagram -- SPI Master Input Timing Diagram -- SPI Slave Input Timing Diagram Updated Secure Digital (SD)/MultiMediaCard (MMC) Timing Requirements for Intel Arria 10 Devices table. -- Changed Tclk to Tsdmmc_clk_out and TMMC_CLK to TSDMMC_CLK_OUT. -- Updated Td min from 5.5 ns to 8.5 ns and max from 12.5 ns to 11.5 ns. -- Updated note to Td. continued... Intel(R) Arria(R) 10 Device Datasheet 108 Send Feedback Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 Date Version Changes * * * * * * * * * * * * Changed the title and symbols in the following timing diagrams: -- Changed from "NAND Data Input Cycle Timing Diagram" to "NAND Data Output Cycle Timing Diagram". Changed from DIN to DOUT. -- Changed from "NAND Data Output Cycle Timing Diagram" to "NAND Data Input Cycle Timing Diagram". Changed from DOUT to DIN. -- Changed from "NAND Extended Data Output (EDO) Cycle Timing Diagram" to "NAND Data Input Timing Diagram for Extended Data Output (EDO) Cycle". Changed from DOUT to DIN. Changed from "ARM Trace Timing Characteristics" to "Trace Timing Characteristics". Updated the description in the GPIO Interface topic. Updated FPP Timing Parameters When the DCLK-to-DATA[] Ratio is 1 for Intel Arria 10 Devices table. -- Updated the maximum value for tSTATUS and tCF2ST1 from 1,506 s to 3,000 s. -- Updated fMAX for FPP x8/x16 from 125 MHz to 100 MHz. -- Updated the minimum value for tCF2CK from 1,506 s to 3,010 s. -- Updated the minimum value for tST2CK from 2 s to 10 s. -- Updated the maximum value for tCD2UM from 437 s to 830 s. Updated FPP Timing Parameters When the DCLK-to-DATA[] Ratio is >1 for Intel Arria 10 Devices table. -- Updated the maximum value for tSTATUS and tCF2ST1 from 1,506 s to 3,000 s. -- Updated fMAX for FPP x8/x16 from 125 MHz to 100 MHz. -- Updated the minimum value for tCF2CK from 1,506 s to 3,010 s. -- Updated the minimum value for tST2CK from 2 s to 10 s. -- Updated the maximum value for tCD2UM from 437 s to 830 s. Updated maximum value for tCD2UM from 437 s to 830 s in AS Timing Parameters for AS x1 and AS x4 Configurations in Intel Arria 10 Devices table. Updated PS Timing Parameters for Intel Arria 10 Devices table. -- Updated the maximum value for tSTATUS and tCF2ST1 from 1,506 s to 3,000 s -- Updated the minimum value for tCF2CK from 1,506 s to 3,010 s. -- Updated the minimum value for tST2CK from 2 s to 10 s. -- Updated the maximum value for tCD2UM from 437 s to 830 s. Added description about .rbf and .rpd files in the Configuration Files section. Changed the table title from "Uncompressed Uncompressed .rbf Sizes Sizes for Intel Arria 10 Devices" to "Configuration Bit Stream Sizes for Intel Arria 10 Devices". Updated the note to Active Serial in Minimum Configuration Time Estimation for Intel Arria 10 Devices table. Note: The minimum configuration time is calculated based on DCLK frequency of 100 MHz. Only external CLKUSR may guarantee the frequency accuracy of 100 MHz. If you use internal oscillator of 100 MHz, you may not get the actual frequency of 100 MHz. For the DCLK frequency using internal oscillator, refer to the DCLK Frequency Specification in the AS Configuration Scheme table. Changed instances of Quartus II to Quartus Prime. Changed voltages and conditions in the "Transceiver Power Supply Operating Conditions for Arria 10 GX/SX Devices" table. Changed maximum data rate conditions in the "Transmitter and Receiver Data Rate Performance" table. continued... Send Feedback Intel(R) Arria(R) 10 Device Datasheet 109 Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 Date Version Changes * * * * * * * * * June 2015 2015.06.12 * Changed conditions in the "Transmitter and Receiver Data Rate Performance" table in the Transceiver Performance for Arria 10 GT Devices section. Changed conditions in the "Reference Clock Specifications" table. Changed the clock networks in the "Transceiver Clock Network Maximum Data Rate Specifications" table. Changed conditions in the "Receiver Specifications" table. Changed conditions in the "Transmitter Specifications" table. Changed the minimum frequency in the "ATX PLL Performance," "Fractional PLL Performance," and "CMU PLL Performance" tables in the Transceiver Performance for Intel Arria 10 GX/SX Devices section. Changed the minimum frequeny in the "ATX PLL Performance," "Fractional PLL Performance," and "CMU PLL Performance" tables in the Transceiver Performance for Intel Arria 10 GT Devices section. Added a parameter to the "Reference Clock Specifications" table. Added footnote to the "Transmitter Specifications" table. Changed the specifications for the backplane maximum data rate condition in the "Transmitter and Receiver Data Rate Performance" table for Intel Arria 10 GX/SX devices. * Changed the specifications for transmitter REFCLK phase noise in the "Reference Clock Specifications" table. * Added note in the following tables: -- Absolute Maximum Ratings for Intel Arria 10 Devices: VCCPGM -- Maximum Allowed Overshoot During Transitions for Intel Arria 10 Devices: LVDS I/O -- Recommended Operating Conditions for Intel Arria 10 Devices: VI Added HPS Specifications. Updated recommended EPCQ-L serial configuration devices in the Uncompressed .rbf Sizes table. * * May 2015 2015.05.08 Made the following changes: * Changed the specifications for the VICM (AC coupled) parameter in the "Reference Clock Specifications" table. * Changed the maximum frequency in the "CMU PLL Performance" table in the Transceiver Performance for GT Devices section. * Added a footnote to the transceiver speed grade 5 column in the "Transmitter and Receiver Data Rate Performance" table. May 2015 2015.05.04 * * * * Updated the Maximum Allowed Overshoot During Transitions for Intel Arria 10 Devices table. Added a note to tramp in the Recommended Operating Conditions for Intel Arria 10 Devices table. Note: tramp is the ramp time of each individual power supply, not the ramp time of all combined power supplies. Changed the minimum, typical, and maximum values for the transmitter and receiver power supply in the "Transceiver Power Supply Operating Conditions for Intel Arria 10 GT Devices" table. Added -1 speed grade in the condition column for VCCL_HPS at 0.95 V in HPS Power Supply Operating Conditions for Intel Arria 10 SX Devices table. continued... Intel(R) Arria(R) 10 Device Datasheet 110 Send Feedback Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 Date Version Changes * * * * * * * * * * * * * * * Added -I1S, -I2S, and -E2S speed grades to the following tables: -- Clock Tree Performance for Intel Arria 10 Devices -- DSP Block Performance Specifications for Intel Arria 10 Devices -- Memory Block Performance Specifications for Intel Arria 10 Devices -- High-Speed I/O Specifications for Intel Arria 10 Devices -- Memory Output Clock Jitter Specifications for Intel Arria 10 Devices Updated fIN minimum value from 27 MHz to 50 MHz for all speed grades in the Fractional PLL Specifications for Intel Arria 10 Devices table. Changed the description for fINPFD to "Input clock frequency to the PFD" in the I/O PLL Specifications for Intel Arria 10 Devices table. Updated DSP Block Performance Specifications for Intel Arria 10 Devices table for VCC and VCCP at 0.9 V typical value. Added DSP specifications for VCC and VCCP at 0.95 V typical value. Updated Ibias minimum value from 8 A to 10 A and maximum value from 200 A to 100 A in the External Temperature Sensing Diode Specifications for Intel Arria 10 Devices table. Added DPA (soft CDR mode) specifications in High-Speed I/O Specifications for Intel Arria 10 Devices table. Added description in POR Specifications section: Power-on reset (POR) delay is defined as the delay between the time when all the power supplies monitored by the POR circuitry reach the minimum recommended operating voltage to the time when the nSTATUS is released high and your device is ready to begin configuration. Moved the following timing diagrams to the Configuration, Design Security, and Remote System Upgrades in Arria 10 Devices chapter. -- FPP Configuration Timing Waveform When the DCLK-to-DATA[] Ratio is 1 -- FPP Configuration Timing Waveform When the DCLK-to-DATA[] Ratio is >1 -- AS Configuration Timing Waveform -- PS Configuration Timing Waveform Removed the DCLK-to-DATA[] ratio when both encryption and compression are turned on. Added description to the table: You cannot turn on encryption and compression at the same time for Intel Arria 10 devices. Updated the AS Timing Parameters for AS x1 and AS x4 Configurations in Intel Arria 10 Devices table as follows: -- Changed the symbol for data hold time from tH to tDH. -- Updated the minimum value for tSU from 0 ns to 1 ns. -- Updated the minimum value for tDH from 2.5 ns to 1.5 ns. Added a note to the DCLK Frequency Specification in the AS Configuration Scheme table. Note: You can only set 12.5, 25, 50, and 100 MHz in the Intel Quartus Prime software. Added a note to the Initialization Clock Source Option and the Maximum Frequency for Intel Arria 10 Devices. Note: If you use the CLKUSR pin for AS and transceiver calibration simultaneously, the only allowed frequency is 100 MHz. Changed Intel Arria 10 GS to Intel Arria 10 SX in Uncompressed .rbf Sizes and Minimum Configuration Time Estimation tables. Added IO_IN_DLY_CHN and IO_OUT_DLY_CHN in the IOE Programmable Delay table. Changed the Min/Typ/Max description for the VICM (AC coupled) parameter in the "Reference Clock Specifications" table. continued... Send Feedback Intel(R) Arria(R) 10 Device Datasheet 111 Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 Date Version Changes * * * * * * * * * January 2015 2015.01.23 Changed the Min/Typ/Max values in the "Transceiver Power Supply Operating Conditions for Arria 10 GX/SX Devices" table. Changed the Min/Typ/Max values in the "Transceiver Power Supply Operating Conditions for Arria 10 GT Devices" table. Added a footnote to the maximum data rate for GT channels in the "Transceiver Performance for GT Devices" section. Made the following changes to the "Transceiver Performance for Arria 10 GX/SX Devices" section. -- Changed the maximum data rate condition for chip-to-chip and backplane in the "Transmitter and Receiver Data Rate Performance" table. -- Added TX minimum data rate to the "Transmitter and Receiver Data Rate Performance" table. -- Changed the minimum frequency in the "ATX PLL Performance" table. -- Changed the minimum frequency in the "Fractional PLL Performance" table. -- Changed the minimum and maximum frequency in the "CMU PLL Performance" table. Made the following changes to the "Transceiver Performance for Arria 10 GT Devices" section. -- Added TX minimum data rate to the "Transmitter and Receiver Data Rate Performance" table. -- Changed the maximum data rate condition for chip-to-chip and backplane in the "Transmitter and Receiver Data Rate Performance" table. -- Changed the minimum frequency in the "ATX PLL Performance" table. -- Changed the minimum frequency in the "Fractional PLL Performance" table. -- Changed the minimum frequency in the "CMU PLL Performance" table. Added voltage condition to the maximum peak-to-peak diff p-p after configuration and to the VICM specifications in the "Receiver Specifications" table. Changed the voltage conditions for VOCM in the "Transmitter Specifications" table. Changed the VOD/VCCT Ratios in the "Typical Transmitter VOD Settings" table. Added the "Transceiver Clock Network Maximum Data Rate Specifications" table. * * Added a note in the "Transceiver Power Supply Operating Conditions" section. Made the following changes to the "Reference Clock Specifications" table: -- Added the input reference clock frequency parameters for the CMU PLL, ATX PLL, and fPLL PLL. -- Changed the maximum specification for rise time and fall time. -- Added the VICM (AC and DC coupled) parameters. -- Changed the maximum value for Transmitter REFCLK Phase Noise (622 MHz) when 1 MHz. * Changed the Min, Typ, and Max values for the reconfig_clk signal in the "Transceiver Clocks Specifications" table. * Made the following changes to the "Receiver Specifications" table: -- Added the maximum peak-to-peak differential input voltage after device configuration specifications. -- Changed the minimum specification for the minimum differential eye opening at receiver serial input pins parameter. -- Removed the 120-ohm and 150-ohm conditions for the differential on-chip termination resistors parameter. -- Added the VICM (AC and DC coupled) parameter. -- Added the Programmable DC Gain parameter. continued... Intel(R) Arria(R) 10 Device Datasheet 112 Send Feedback Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 Date Version Changes * * * * * * * * * * * * Made the following changes to the "Transmitter Specifications" table: -- Added the VOCM (AC coupled) parameter. -- Added the VOCM (DC coupled) parameter. -- Changed the rise and fall time minimum and maximum specifications. Added the "Typical Transmitter VOD Settings" table. Added a note to VCC, VCCP, and VCCERAM typical values in Recommended Operating Conditions table. Note: You can operate -1 and -2 speed grade devices at 0.9 V or 0.95 V typical value. You can operate -3 speed grade device at only 0.9 V typical value. Core performance shown in this datasheet is applicable for the operation at 0.9 V. Operating at 0.95 V results in higher core performance and higher power consumption. For more information about the performance and power consumption of 0.95 V operation, refer to the Intel Quartus Prime software timing reports and Early Power Estimator (EPE). Removed military grade operating junction temperature specifications (TJ) in Recommended Operating Conditions table. Updated the VCCIO range for HSTL-18 I/O standard in Differential HSTL and HSUL I/O Standards for Arria 10 Devices table as follows: -- Min: Updated from 1.425 V to 1.71 V -- Typ: Updated from 1.5 V to 1.8 V -- Max: Updated from 1.575 V to 1.89 V Added a statement to Differential I/O Standards Specifications for Intel Arria 10 Devices table: Differential inputs are powered by VCCPT which requires 1.8 V. Added statement in I/O Standard Specifications: You must perform timing closure analysis to determine the maximum achievable frequency for general purpose I/O standards. Updated fractional PLL specifications. -- Updated fOUT_C to fOUT and updated the maximum value to 644 MHz for all speed grades. -- Updated fVCO minimum value from 2.4 GHz to 3.125 GHz. -- Removed fOUT_L, kVALUE, and fRES parameters. Updated I/O PLL specifications. -- Updated fOUT_C to fOUT and updated the maximum value to 644 MHz for all speed grades. -- Updated fOUT_EXT maximum value to 800 MHz (-1 speed grade), 720 MHz (-2 speed grade), and 650 MHz (-3 speed grade). -- Removed fRES parameter. Updated the description in Periphery Performance Specifications to mention that proper timing closure is required in design. Updated AS Timing Parameters for AS x1 and AS x4 Configurations in Intel Arria 10 Devices. -- Updated tSU minimum value from 1.5 ns to 0 ns. -- Updated tH minimum value from 0 ns to 2.5 ns. Updated CLKUSR initialization clock source maximum frequency from 125 MHz to 100 MHz for passive configuration schemes (PS and FPP). continued... Send Feedback Intel(R) Arria(R) 10 Device Datasheet 113 Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 Date Version Changes * Added uncompressed .rbf sizes and minimum configuration time estimation for Intel Arria 10 GX and GS devices. * Updated uncompressed .rbf sizes for Intel Arria 10 GX 900 and 1150 devices, and Intel Arria 10 GT 900 and 1150 devices. -- Updated configuration .rbf size from 335,106,890 bits to 351,292,512 bits. -- Updated IOCSR .rbf size from 6,702,138 bits to 1,885,396 bits. August 2014 2014.08.18 * Updated minimum configuration time estimation for Intel Arria 10 GX 900 and 1150 devices, and Intel Arria 10 GT 900 and 1150 devices for the following configuration modes: -- Active serial: Updated from 837.77 ms to 883.20 ms. -- Fast Passive Parallel: Updated from 104.72 ms to 110.40 ms. * * Changed the 3 V I/O conditions in Table 2. Table 3: -- Added a note to the Minimum and Maximum operating conditions. -- Changed VCCERAM values. -- Changed the Maximum recommended operating conditions for 3 V I/O VI. Added a note to the I/O pin pull-up tolerance in Table 12. Changed the VIH values for LVTTL, LVCMOS and 2.5 I/O standards in Table 13. Table 14, Table 15, and Table 16: -- Added SSTL-12 I/O standard. -- Removed Class I, II for SSTL-135 and SSTL-125 I/O standards. Table 19: -- Changed the minimum data rate specification for transmitter and receiver data rates. -- Changed the minimum frequency specification for the fractional PLL. -- Changed the minimum frequency specification for the CMU PLL. Changed the Core Speed Grade with Power Options section in Table 20. Table 21: -- Changed the minimum data rate specification for transmitter and receiver data rates. -- Changed the minimum frequency specification for the Fractional PLL. -- Changed the minimum frequency specification for the CMU PLL. -- Changed the minimum frequency of the ATX PLL. Table 23: -- Added a note to the High Speed Differential I/O standard. -- Changed the specifications for CLKUSR pin. Added columns in Table 29. Changed the maximum fHSCLK_in and txJitter in Table 32. Changed the minimum formula for tCD2UMC in Table 42, Table 43, Table 44, and Table 46. Changed the CLKUSR maximum frequency and minimum number of cycles in Table 47. * * * * * * * * * * * continued... Intel(R) Arria(R) 10 Device Datasheet 114 Send Feedback Intel(R) Arria(R) 10 Device Datasheet A10-DATASHEET | 2018.11.29 Date Version Changes * * * * Table 48: -- Changed the IOCSR .rbf size. -- Added Recommended EPCQ-L Serial Configuration Device. Changed the DCLK frequency and minimum configuration time for FPP in Table 49. Added the following tables: -- External Temperature Sensing Diode Specifications for Intel Arria 10 Devices -- IOE Programmable Delay for Intel Arria 10 Devices Removed the following figures: -- CTLE Response in High Gain Mode for Intel Arria 10 Devices with Data Rates 8 Gbps -- Removed the CTLE Response in High Gain Mode for Intel Arria 10 Devices with Data Rates < 8 Gbps March 2014 2014.03.14 Updated Table 3, Table 5, Table 21, Table 23, Table 24, Table 32, and Table 41. December 2013 2013.12.06 Updated Figure 1 and Figure 2. December 2013 2013.12.02 Initial release. Send Feedback Intel(R) Arria(R) 10 Device Datasheet 115