IRFD9220 Data Sheet July 1999 0.6A, 200V, 1.500 Ohm, P-Channel Power MOSFET File Number 2286.3 Features * 0.6A, 200V This P-Channel enhancement mode silicon gate power field effect transistor is an advanced power MOSFET designed, tested, and guaranteed to withstand a specified level of energy in the breakdown avalanche mode of operation. All of these power MOSFETs are designed for applications such as switching regulators, switching convertors, motor drivers, relay drivers, and drivers for high power bipolar switching transistors requiring high speed and low gate drive power. These types can be operated directly from integrated circuits. * rDS(ON) = 1.500 * Single Pulse Avalanche Energy Rated * SOA is Power Dissipation Limited * Nanosecond Switching Speeds * Linear Transfer Characteristics * High Input Impedance Symbol Formerly developmental type TA17502. D Ordering Information PART NUMBER IRFD9220 PACKAGE HEXDIP G BRAND IRFD9220 S NOTE: When ordering, use the entire part number. Packaging HEXDIP DRAIN GATE SOURCE 4-51 CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999 IRFD9220 Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDS Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDGR Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Pulse Avalanche Energy Rating (Note 4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg IRFD9220 -200 -200 -0.6 -4.8 20 1.0 0.008 290 -55 to 150 UNITS V V A A V W W/oC mJ oC 300 260 oC oC CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 125oC Electrical Specifications TC = 25oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Drain to Source Breakdown Voltage BVDSS ID = -250A, VGS = 0V, (Figure 9) -200 - - V Gate to Threshold Voltage VGS(TH) VGS = VDS, ID = -250A -2.0 - -4.0 V VDS = Rated BVDSS, VGS = 0V - - -25 A VDS = 0.8 x Rated BVDSS, VGS = 0V, TC = 125oC - - -250 A Zero Gate Voltage Drain Current IDSS On-State Drain Current (Note 2) ID(ON) Gate to Source Leakage Current IGSS On Resistance (Note 2) rDS(ON) Forward Transconductance (Note 2) Turn-On Delay Time gfs td(ON) Rise Time tr Turn-Off Delay Time td(OFF) Fall Time tf Total Gate Charge (Gate to Source + Gate to Drain) Gate to Source Charge Qg(TOT) Qgs VDS > ID(ON) x rDS(ON)MAX, VGS = -10V -0.6 - - A VGS = 20V - - 500 nA ID = -0.3A, VGS = -10V, (Figures 7, 8) - 1.000 1.500 VDS < 50V, ID = -0.3A, (Figure 11) 0.6 1.0 - S VDD = 0.5 x Rated BVDSS, ID 0.6A, RG = 9.1 VGS = -10V, (Figures 16, 17) RL = 165 for VDD = 100V MOSFET Switching Times are Essentially Independent of Operating Temperature. - 15 40 ns - 25 50 ns - 80 120 ns - 50 75 ns VGS = -10V, ID = -0.6A, VDS = 0.8 x Rated BVDSS, IG(REF) = 1.5mA, (Figures 13, 18, 19) Gate Charge is Essentially Independent of Operating Temperature - 16 22 nC - 10 - nC - 4 - nC VDS = -25V, VGS = 0V, f = 1MHz, (Figure 10) - 350 - pF Gate to Drain "Miller" Charge Qgd Input Capacitance CISS Output Capacitance COSS - 100 - pF Reverse Transfer Capacitance CRSS - 30 - pF - 4.0 - nH - 6.0 - nH - - 120 oC/W Internal Drain Inductance LD Measured From the Drain Lead, 2.0mm (0.08in) From Header to Center of Die Internal Source Inductance LS Measured From the Source Lead, 0.2mm (0.08in) From Header to Source Bonding Pad Modified MOSFET Symbol Showing the Internal Devices Inductances D LD G LS S Thermal Resistance Junction to Ambient 4-52 RJA Typical Socket Mount IRFD9220 Source to Drain Diode Specifications PARAMETER SYMBOL Continuous Source to Drain Current Pulse Source to Drain Current (Note 3) TEST CONDITIONS ISD MIN TYP MAX UNITS - - -0.6 A - - -4.8 A TC = 25oC, ISD = -0.6A, VGS = 0V (Figure 12) - - -1.5 V TJ = 150oC, ISD = -0.6A, dISD/dt = 100A/s TJ = 150oC, ISD = -0.6A, dISD/dt = 100A/s - 150 - ns - 0.5 - C 100 125 Modified MOSFET Symbol Showing the Integral Reverse P-N Junction Diode ISDM D G S Source to Drain Diode Voltage (Note 2) Reverse Recovery Time VSD trr Reverse Recovery Charge QRR NOTES: 2. Pulse test: pulse width 300s, duty cycle 2%. 3. Repetitive rating: pulse width limited by maximum junction temperature. 4. VDD = 25V, starting TJ = 25oC, L = 1210mH, RG = 25, Peak IAS = 0.6A (Figures 14, 15). Typical Performance Curves Unless Otherwise Specified -0.6 IDS, DRAIN TO SOURCE CURRENT (A) POWER DISSIPATION MULTIPLIER 1.2 1.0 0.8 0.6 0.4 0.2 -0.4 -0.2 0 25 0 0 25 125 50 75 100 TA , AMBIENT TEMPERATURE (oC) 150 10s 100s 1ms 10ms -0.01 -0.002 -0.2 TC = 25oC TJ = MAX RATED SINGLE PULSE 100ms ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A) -5 OPERATION IN THIS AREA IS LIMITED BY rDS(ON) -10V -9V -4 VGS = -7V VGS = -8V PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX. -3 VGS = -6V -2 VGS = -5V -1 DC VGS = -4V 0 -1.0 -10 -100 VDS, DRAIN TO SOURCE VOLTAGE (V) -500 FIGURE 3. FORWARD BIAS SAFE OPERATING AREA 4-53 150 FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs AMBIENT TEMPERATURE -10 -0.1 75 TA, AMBIENT TEMPERATURE (oC) FIGURE 1. NORMALIZED POWER DISSIPATION vs AMBIENT TEMPERATURE -1.0 50 0 -10 -20 -30 -40 VDS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 4. OUTPUT CHARACTERISTICS -50 IRFD9220 Unless Otherwise Specified (Continued) IDS, DRAIN TO SOURCE CURRENT (A) -5 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX. -4 VGS = -7V VGS = -8V VGS = -9V -3 VGS = -10V VGS = -6V -2 VGS = -5V -1 VGS = -4V 0 0 -2 -1 -3 -5 -4 -5 IDS(ON), DRAIN TO SOURCE CURRENT (A) Typical Performance Curves PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDS I D(ON) x rDS(ON) MAX -4 TJ = 125oC TJ = 25oC -3 TJ = -55oC -2 -1 0 0 -2 -4 -6 -8 VGS, GATE TO SOURCE VOLTAGE (V) VDS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 5. SATURATION CHARACTERISTICS -10 FIGURE 6. TRANSFER CHARACTERISTICS 1.5 NORMALIZED DRAIN TO SOURCE ON RESISTANCE ON RESISTANCE () rDS(ON), DRAIN TO SOURCE 2.0s PULSE TEST VGS = - 10V 1.0 VGS = - 20V 0.5 0 0 -1 -2 -3 -4 -5 PULSE DURATION = 80s -2.5 DUTY CYCLE = 0.5% MAX. VGS = -10V, ID = -0.3A -2.0 -1.5 -1.0 -0.5 0 -40 ID, DRAIN CURRENT (A) NOTE: Effect of 2.0s pulse is minimal. FIGURE 7. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT 40 80 120 160 FIGURE 8. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE 500 1.15 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS = CDS + CGD ID = 250A 1.10 400 C, CAPACITANCE (pF) NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE 0 TJ , JUNCTION TEMPERATURE (oC) 1.05 1.00 0.95 CISS 300 200 COSS 100 0.90 CRSS 0.85 -80 -40 0 40 80 120 160 TJ , JUNCTION TEMPERATURE (oC) FIGURE 9. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE 4-54 0 0 -10 -20 -30 -40 -50 VDS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 10. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE IRFD9220 Typical Performance Curves -100 VDS ID(ON) x rDS(ON)MAX PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX. 3 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX. ISD, DRAIN CURRENT (A) gfs, TRANSCONDUCTANCE (S) 4 Unless Otherwise Specified (Continued) TJ = -55oC TJ = 25oC 2 TJ = 125oC 1 0 0 -1 -2 -3 I D , DRAIN CURRENT (A) -4 -10 TJ = 25oC -1.0 -0.1 -0.4 -5 TJ = 150oC -0.6 -0.8 -1.0 -1.2 -1.4 -1.6 VSD, SOURCE TO DRAIN VOLTAGE (V) FIGURE 11. TRANSCONDUCTANCE vs DRAIN CURRENT FIGURE 12. SOURCE TO DRAIN DIODE VOLTAGE 0 VGS, GATE TO SOURCE (V) ID = -3.6A -5 -10 VDS = -40V VDS = -100V VDS = -160V -15 -20 0 4 8 12 16 20 Qg(TOT) , TOTAL GATE CHARGE (nC) FIGURE 13. GATE TO SOURCE VOLTAGE vs GATE CHARGE Test Circuits and Waveforms VDS tAV L VARY tP TO OBTAIN REQUIRED PEAK IAS 0 + RG 0V VGS DUT tP IAS VDD IAS VDS tP 0.01 FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT 4-55 VDD BVDSS FIGURE 15. UNCLAMPED ENERGY WAVEFORMS -1.8 IRFD9220 Test Circuits and Waveforms (Continued) tON tOFF td(OFF) td(ON) tf tr 0 RL - DUT VGS VDS VDD RG + 10% 10% VGS 0 90% 90% 10% 50% 50% PULSE WIDTH 90% FIGURE 16. SWITCHING TIME TEST CIRCUIT FIGURE 17. RESISTIVE SWITCHING WAVEFORMS -VDS (ISOLATED SUPPLY) CURRENT REGULATOR 0 VDS DUT 12V BATTERY 0.2F 50k 0.3F Qgs Qg(TOT) DUT G VGS Qgd D VDD 0 S IG(REF) IG CURRENT SAMPLING RESISTOR +VDS ID CURRENT SAMPLING RESISTOR FIGURE 18. GATE CHARGE TEST CIRCUIT 0 IG(REF) FIGURE 19. GATE CHARGE WAVEFORMS All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. 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