General Description
The MAX6715–MAX6729 are ultra-low-voltage microproces-
sor (µP) supervisory circuits designed to monitor two or three
system power-supply voltages. These devices assert a sys-
tem reset if any monitored supply falls below its factory-
trimmed or adjustable threshold and maintain reset for a
minimum timeout period after all supplies rise above their
thresholds. The integrated dual/triple supervisory circuits sig-
nificantly improve system reliability and reduce size com-
pared to separate ICs or discrete components.
These devices monitor primary supply voltages (VCC1) from
1.8V to 5.0V and secondary supply voltages (VCC2) from
0.9V to 3.3V with factory-trimmed reset threshold voltage
options (see Reset Voltage Threshold Suffix Guide). An
externally adjustable RSTIN input option allows customers to
monitor a third supply voltage down to 0.62V. These devices
are guaranteed to be in the correct reset output logic state
when either VCC1 or VCC2 remains greater than 0.8V.
A variety of push-pull or open-drain reset outputs along with
watchdog input, manual reset input, and power-fail input/out-
put features are available (see Selector Guide). Select reset
timeout periods from 1.1ms to 1120ms (min) (see Reset
Timeout Period Suffix Guide). The MAX6715–MAX6729 are
available in small 5, 6, and 8-pin SOT23 packages and oper-
ate over the -40°C to +85°C temperature range.
Applications
Multivoltage Systems
Telecom/Networking Equipment
Computers/Servers
Portable/Battery-Operated Equipment
Industrial Equipment
Printer/Fax
Set-Top Boxes
Features
♦VCC1 (primary supply) Reset Threshold Voltages
from 1.58V to 4.63V
♦VCC2 (secondary supply) Reset Threshold
Voltages from 0.79V to 3.08V
♦Externally Adjustable RSTIN Threshold for
Auxiliary/Triple-Voltage Monitoring
(0.62V internal reference)
♦Watchdog Timer Option
35s (min) Long Startup Period
1.12s (min) Normal Timeout Period
♦Manual Reset Input Option
♦Power-Fail Input/Power-Fail Output Option
(Push-Pull and Open-Drain Active-Low)
♦Guaranteed Reset Valid Down to VCC1 or
VCC2 = 0.8V
♦Reset Output Logic Options
♦Immune to Short VCC Transients
♦Low Supply Current 14µA (typ) at 3.6V
♦Small 5, 6, and 8-Pin SOT23 Packages
MAX6715–MAX6729
Dual/Triple Ultra-Low-Voltage SOT23 µP
Supervisory Circuits
________________________________________________________________ Maxim Integrated Products 1
Ordering Information
IN
OUT2
OUT1
DC/DC
CONVERTER
UNREGULATED
DC
R1
R2
VCC1V
CC2
RSTIN/PFI
MR
RST
WDI
PFO
MAX67_ _
PUSHBUTTON
SWITCH
I/O
SUPPLY
CORE
SUPPLY
RESET
I/O
NMI
µP
1.8V 0.9V
Typical Operating Circuit
19-2325; Rev 5; 12/05
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Pin Configurations and Selector Guide appear at end of
data sheet.
PART
TEMP RANGE
PIN-PACKAGE
MAX6715UT_ _D_ -T
-40°C to +85°C
6 SOT23-6
MAX6716UT_ _D_ -T
-40°C to +85°C
6 SOT23-6
MAX6717UK_ _D_ -T
-40°C to +85°C
5 SOT23-5
MAX6718UK_ _D_ -T
-40°C to +85°C
5 SOT23-5
MAX6719UT_ _D_ -T
-40°C to +85°C
6 SOT23-6
MAX6720UT_ _D_ -T
-40°C to +85°C
6 SOT23-6
Note: The first “_ _” are placeholders for the threshold voltage
levels of the devices. Desired threshold levels are set by the part
number suffix found in the Reset Voltage Threshold Suffix Guide.
The “_” after the D is a placeholder for the reset timeout delay
time. Desired delay time is set using the timeout period suffix
found in the Reset Timeout Period Suffix Guide. For example the
MAX6716UTLTD3-T is a dual-voltage supervisor VTH1 = 4.625V,
VTH2 = 3.075V, and 210ms (typ) timeout period.
Devices are available in both leaded and lead-free packaging.
Specify lead-free by replacing "-T" with "+T" when ordering.
Ordering Information continued at end of data sheet.
MAX6715–MAX6729
Dual/Triple Ultra-Low-Voltage SOT23 µP
Supervisory Circuits
2_______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VCC1 = VCC2 = 0.8V to 5.5V, GND = 0, TA= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Terminal Voltage (with respect to GND)
VCC1, VCC2..........................................................-0.3V to +6V
Open-Drain RST, RST1, RST2, PFO, RST ................-0.3V to +6V
Push-Pull RST, RST1, PFO, RST...............-0.3V to (VCC1 + 0.3V)
Push-Pull RST2 .........................................-0.3V to (VCC2 + 0.3V)
RSTIN, PFI, MR, WDI ................................................-0.3V to +6V
Input Current/Output Current (all pins) ...............................20mA
Continuous Power Dissipation (TA= +70°C)
5-Pin SOT23-5 (derate 7.1mW/°C above +70°C) ........571mW
6-Pin SOT23-6 (derate 8.7mW/°C above +70°C) ........696mW
8-Pin SOT23-8 (derate 8.9mW/°C above +70°C) ........714mW
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Junction Temperature......................................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
Supply Voltage VCC 0.8 5.5 V
VCC1 < 5.5V, all I/O pins open 15 39
ICC1 VCC1 < 3.6V, all I/O pins open 10 28
VCC2 < 3.6V, all I/O pins open 4 11
Supply Current
ICC2 VCC2 < 2.75V, all I/O pins open 3 9
µA
L (falling)
4.500 4.625 4.750
M (falling)
4.250 4.375 4.500
T (falling)
3.000 3.075 3.150
S (falling)
2.850 2.925 3.000
R (falling)
2.550 2.625 2.700
Z (falling)
2.250 2.313 2.375
Y (falling)
2.125 2.188 2.250
W (falling)
1.620 1.665 1.710
VCC1 Reset Threshold VTH1
V (falling)
1.530 1.575 1.620
V
T (falling)
3.000 3.075 3.150
S (falling)
2.850 2.925 3.000
R (falling)
2.550 2.625 2.700
Z (falling)
2.250 2.313 2.375
Y (falling)
2.125 2.188 2.250
W (falling)
1.620 1.665 1.710
V (falling)
1.530 1.575 1.620
I (falling)
1.350 1.388 1.425
H (falling)
1.275 1.313 1.350
G (falling)
1.080 1.110 1.140
F (falling)
1.020 1.050 1.080
E (falling)
0.810 0.833 0.855
VCC2 Reset Threshold VTH2
D (falling)
0.765 0.788 0.810
V
Reset Threshold Tempco 20
ppm/°C
Reset Threshold Hysteresis
VHYST
Referenced to VTH typical 0.5 %
MAX6715–MAX6729
Dual/Triple Ultra-Low-Voltage SOT23 µP
Supervisory Circuits
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VCC1 = VCC2 = 0.8V to 5.5V, GND = 0, TA= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
VCC to Reset Output Delay tRD V
C C
1 = ( V
TH
1 + 100m V ) to ( V
TH
1 - 100m V ) or
V
C C
2 = ( V
TH
2 + 75m V ) to ( V
TH
2 - 75m V ) 20 µs
D1 1.1
1.65
2.2
D2 8.8
13.2 17.6
D3
140 210 280
D5
280 420 560
D6
560 840 1120
Reset Timeout Period tRP
D4
1120 1680 2240
ms
ADJUSTABLE RESET COMPARATOR INPUT (MAX6719/MAX6720/MAX6723–MAX6727)
RSTIN Input Threshold
VRSTIN 611 626.5 642
mV
RSTIN Input Current
IRSTIN
-25
+25
nA
RSTIN Hysteresis 3mV
RSTIN to Reset Output Delay
tRSTIND
VRSTIN to (VRSTIN - 30mV) 22 µs
POWER-FAIL INPUT (MAX6728/MAX6729)
PFI Input Threshold VPFI
611 626.5 642
mV
PFI Input Current IPFI -25
+25
nA
PFI Hysteresis VPFH 3mV
PFI to PFO Delay tDPF (VPFI + 30mV) to (VPFI - 30mV) 2 µs
MANUAL RESET INPUT (MAX6715–MAX6722/MAX6725–MAX6729)
VIL
0.3 ✕ VCC1
MR Input Voltage VIH
0.7 ✕ VCC1
V
MR Minimum Pulse Width 1µs
MR Glitch Rejection
100
ns
MR to Reset Delay tMR
200
ns
MR Pullup Resistance 25 50 80 kΩ
WATCHDOG INPUT (MAX6721–MAX6729)
First watchdog period after reset timeout
period 35 54 72
Watchdog Timeout Period tWD
Normal mode
1.12 1.68 2.24
s
WDI Pulse Width tWDI (Note 2) 50 ns
VIL
0.3 ✕ VCC1
WDI Input Voltage VIH
0.7 ✕ VCC1
V
WDI Input Current IWDI WDI = 0 or VCC1-1+1µA
MAX6715–MAX6729
Dual/Triple Ultra-Low-Voltage SOT23 µP
Supervisory Circuits
4_______________________________________________________________________________________
Note 1: Devices tested at +25°C. Overtemperature limits are guaranteed by design and not production tested.
Note 2: Parameter guaranteed by design.
ELECTRICAL CHARACTERISTICS (continued)
(VCC1 = VCC2 = 0.8V to 5.5V, GND = 0, TA= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
RESET/POWER-FAIL OUTPUTS
VCC1 or VCC2 ≥ 0.8V, ISINK = 1µA,
output asserted 0.3
VCC1 or VCC2 ≥ 1.0V, ISINK = 50µA,
output asserted 0.3
VCC1 or VCC2 ≥ 1.2V, ISINK = 100µA,
output asserted 0.3
VCC1 or VCC2 ≥ 2.7V, ISINK = 1.2mA,
output asserted 0.3
RST/RST1/RST2/PFO
Output LOW
(Push-Pull or Open-Drain)
VOL
VCC1 or VCC2 ≥ 4.5V, ISINK = 3.2mA,
output asserted 0.4
V
VCC1 ≥ 1.8V, ISOURCE = 200µA, output not
asserted
0.8 ✕ VCC1
VCC1 ≥ 2.7V, ISOURCE = 500µA, output not
asserted
0.8 ✕ VCC1
RST/RST1/PFO
Output HIGH
(Push-Pull Only)
VOH
VCC1 ≥ 4.5V, ISOURCE = 800µA, output not
asserted
0.8 ✕ VCC1
V
VCC2 ≥ 1.8V, ISOURCE = 200µA, output not
asserted
0.8 ✕ VCC2
VCC2 ≥ 2.7V, ISOURCE = 500µA, output not
asserted
0.8 ✕ VCC2
RST2
Output HIGH
(Push-Pull Only)
VOH
VCC2 ≥ 4.5V, ISOURCE = 800µA, output not
asserted
0.8 ✕ VCC2
V
VCC1 ≥ 1.0V, ISOURCE = 1µA, reset asserted 0.8 ✕ VCC1
VCC1 ≥ 1.8V, ISOURCE = 150µA,
reset asserted
0.8 ✕ VCC1
VCC1 ≥ 2.7V, ISOURCE = 500µA,
reset asserted
0.8 ✕ VCC1
RST
Output HIGH
(Push-Pull Only)
VOH
VCC1 ≥ 4.5V, ISOURCE = 800µA,
reset asserted
0.8 ✕ VCC1
V
VCC1 or VCC2 ≥ 1.8V, ISINK = 500µA,
reset not asserted 0.3
VCC1 or VCC2 ≥ 2.7V, ISINK = 1.2mA,
reset not asserted 0.3
RST
Output LOW
(Push-Pull or Open Drain)
VOL
VCC1 or VCC2 ≥ 4.5V, ISINK = 3.2mA,
reset not asserted 0.4
V
RST/RST1/RST2/PFO Output
Open-Drain Leakage Current Output not asserted 0.5 µA
RST Output Open-Drain
Leakage Current Output asserted 0.5 µA
MAX6715–MAX6729
Dual/Triple Ultra-Low-Voltage SOT23 µP
Supervisory Circuits
_______________________________________________________________________________________ 5
0
4
2
10
8
6
16
14
12
18
-40 10-15 35 60 85
SUPPLY CURRENT vs. TEMPERATURE
VCC1 = 5V, VCC2 = 3.3V
MAX6715-29 toc01
TEMPERATURE (°C)
SUPPLY CURRENT (µA)
TOTAL
ICC1
ICC2
0
4
2
10
8
6
16
14
12
18
-40 10-15 35 60 85
SUPPLY CURRENT vs. TEMPERATURE
VCC1 = 3.3V, VCC2 = 2.5V
MAX6715-29 toc02
TEMPERATURE (°C)
SUPPLY CURRENT (µA)
TOTAL
ICC1
ICC2
0
4
2
10
8
6
16
14
12
18
-40 10-15 35 60 85
SUPPLY CURRENT vs. TEMPERATURE
VCC1 = 2.5V, VCC2 = 1.8V
MAX6715-29 toc03
TEMPERATURE (°C)
SUPPLY CURRENT (µA)
TOTAL
ICC1
ICC2
0
4
2
10
8
6
16
14
12
18
-40 10-15 35 60 85
SUPPLY CURRENT vs. TEMPERATURE
VCC1 = 1.8V, VCC2 = 1.2V
MAX6715-29 toc04
TEMPERATURE (°C)
SUPPLY CURRENT (µA)
TOTAL
ICC1
ICC2
0.998
1.000
0.999
1.003
1.002
1.001
1.006
1.005
1.004
1.007
-40 10-15 35 60 85
NORMALIZED RESET/WATCHDOG
TIMEOUT PERIOD vs. TEMPERATURE
MAX6715-29 toc05
TEMPERATURE (°C)
RESET/WATCHDOG PERIOD
0.996
0.997
0.998
0.999
1.000
1.001
1.002
1.003
1.004
-40 -15 10 35 60 85
NORMALIZED VCC RESET THRESHOLD
vs. TEMPERATURE
MAX6715-29 toc07
TEMPERATURE (°C)
RESET THRESHOLD
625
627
626
629
628
630
631
-40 85
RESET INPUT AND POWER-FAIL INPUT
THRESHOLD vs. TEMPERATURE
MAX6715-29 toc08
TEMPERATURE (°C)
THRESHOLD (mV)
10-15 35 60
44
47
46
45
48
49
50
51
52
53
54
-40 10-15 35 60 85
VCC TO RESET DELAY
vs. TEMPERATURE
MAX6715-29 toc09
TEMPERATURE (°C)
VCC TO RESET DELAY (µs)
100mV OVERDRIVE
Typical Operating Characteristics
(VCC1 = 5V, VCC2 = 3.3V, TA= +25°C, unless otherwise noted.)
MAX6715–MAX6729
Dual/Triple Ultra-Low-Voltage SOT23 µP
Supervisory Circuits
6_______________________________________________________________________________________
Pin Description
22.8
23.0
23.2
23.4
23.6
23.8
24.0
24.2
24.4
-40 -15 10 35 60 85
RESET INPUT TO RESET OUTPUT DELAY
vs. TEMPERATURE
MAX6715-29 toc10
TEMPERATURE (°C)
RSTIN TO RESET DELAY (µs)
30mV OVERDRIVE
2.0
2.1
2.2
2.4
2.3
-40 10-15 35 60 85
POWER-FAIL INPUT TO POWER-FAIL
OUTPUT DELAY vs. TEMPERATURE
MAX6715-29 toc11
TEMPERATURE (°C)
RSTIN TO RESET DELAY (µs)
30mV OVERDRIVE
0
0
VRST
2V/div
MAX6715-29 toc12
50ns/div
MR TO RESET OUTPUT DELAY
VMR
2V/div
Typical Operating Characteristics (continued)
(VCC1 = 5V, VCC2 = 3.3V, TA= +25°C, unless otherwise noted.)
PIN
MAX6715/
MAX6716
MAX6717/
MAX6718
MAX6719/
MAX6720
MAX6721/
MAX6722
MAX6723/
MAX6724
MAX6725/
MAX6726 MAX6727
MAX6728/
MAX6729
NAME
FUNCTION
1111111, 41
RST/
RST1
Active-Low Reset Output,
Open-Drain or Push-Pull.
RST/RST1 changes from
high to low when VCC1 or
VCC2 drops below the
selected reset thresholds,
RSTIN is below threshold,
MR is pulled low, or the
watchdog triggers a
reset. RST/RST1 remains
low for the reset timeout
period after VCC1/
VCC2/RSTIN exceed the
device reset thresholds,
MR goes low to high, or
the watchdog triggers a
reset. Open-drain outputs
require an external pullup
resistor. Push-pull
outputs are referenced to
VCC1.
MAX6715–MAX6729
Dual/Triple Ultra-Low-Voltage SOT23 µP
Supervisory Circuits
_______________________________________________________________________________________ 7
Pin Description (continued)
PIN
MAX6715/
MAX6716
MAX6717/
MAX6718
MAX6719/
MAX6720
MAX6721/
MAX6722
MAX6723/
MAX6724
MAX6725/
MAX6726 MAX6727
MAX6728/
MAX6729
NAME
FUNCTION
5———————
RST2
Active-Low Reset Output,
Open-Drain or Push-Pull.
RST2 changes from high
to low when VCC1 or
VCC2 drops below the
selected reset thresholds
or MR is pulled low. RST2
remains low for the reset
timeout period after
VCC1/VCC2 exceed the
device reset thresholds
or MR goes low to high.
Open-drain outputs
require an external pullup
resistor. Push-pull
outputs are referenced to
VCC2.
22222222
GND
Ground
3333—555
MR
Active-Low Manual Reset
Input. Internal 50kΩ
pullup to VCC1. Pull low
to force a reset. Reset
remains active as long as
MR is low and for the
reset timeout period after
MR goes high. Leave
unconnected or connect
to VCC1 if unused.
44444666
VCC2
Secondary Supply
Voltage Input. Powers the
device when it is above
VCC1 and input for
secondary reset
threshold monitor.
65666888
VCC1
Primary Supply Voltage
Input. Powers the device
when it is above VCC2
and input for primary
reset threshold monitor.
MAX6715–MAX6729
Dual/Triple Ultra-Low-Voltage SOT23 µP
Supervisory Circuits
8_______________________________________________________________________________________
Pin Description (continued)
PIN
MAX6715/
MAX6716
MAX6717/
MAX6718
MAX6719/
MAX6720
MAX6721/
MAX6722
MAX6723/
MAX6724
MAX6725/
MAX6726 MAX6727
MAX6728/
MAX6729
NAME
FUNCTION
———5 3333
WDI
Watchdog Input. If WDI
remains high or low for
longer than the watchdog
timeout period, the
internal watchdog timer
runs out and the reset
output asserts for the
reset timeout period. The
internal watchdog timer
clears whenever a reset
is asserted or WDI sees a
rising or falling edge. The
watchdog has a long
timeout period (35s min)
after each reset event
and a short timeout
period (1.12s min) after
the first valid WDI
transition.
—— 5 — 577—
RSTIN
Undervoltage Reset
Comparator Input. High-
impedance input for
adjustable reset monitor.
The reset output is
asserted when RSTIN falls
below the 0.626V internal
reference voltage. Set the
monitored voltage reset
threshold with an external
resistor-divider network.
Connect RSTIN to VCC1 or
VCC2 if not used.
——————— 7
PFI
Power-Fail Voltage
Monitor Input. High-
impedance input for
internal power-fail monitor
comparator. Connect PFI
to an external resistor-
divider network to set the
power-fail threshold
voltage (0.626V typical
internal reference
voltage). Connect to
GND, VCC1, or VCC2 if
not used.
Detailed Description
Supply Voltages
The MAX6715–MAX6729 microprocessor (µP) supervi-
sory circuits maintain system integrity by alerting the µP
to fault conditions. These ICs are optimized for systems
that monitor two or three supply voltages. The output-
reset state is guaranteed to remain valid while either
VCC1 or VCC2 is above 0.8V.
Threshold Levels
Input voltage threshold level combinations are indicat-
ed by a two-letter code in the Reset Voltage Threshold
Suffix Guide (Table 1). Contact factory for availability of
other voltage threshold combinations.
Reset Outputs
The MAX6715–MAX6729 provides an active-low reset
output (RST) and the MAX6725/MAX6726 provides
both an active-high (RST) and an active-low reset out-
put (RST). RST, RST, RST1, and RST2 are asserted
when the voltage at either VCC1 or VCC2 falls below the
voltage threshold level, RSTIN drops below threshold,
or MR is pulled low. Once reset is asserted it stays low
for the reset timeout period (see Table 2). If VCC1,
VCC2, or RSTIN goes below the reset threshold before
the reset timeout period is completed, the internal timer
MAX6715–MAX6729
Dual/Triple Ultra-Low-Voltage SOT23 µP
Supervisory Circuits
_______________________________________________________________________________________ 9
Pin Description (continued)
PIN
MAX6715/
MAX6716
MAX6717/
MAX6718
MAX6719/
MAX6720
MAX6721/
MAX6722
MAX6723/
MAX6724
MAX6725/
MAX6726 MAX6727
MAX6728/
MAX6729
NAME
FUNCTION
——————— 4
PFO
Active-Low Power-Fail
Monitor Output, Open-
Drain or Push-Pull. PFO is
asserted low when PFI is
less than 0.626V. PFO
deasserts without a reset
timeout period. Open-
drain outputs require an
external pullup resistor.
Push-pull outputs are
referenced to VCC1.
————— 4 ——
RST
Active-High Reset
Output, Open-Drain or
Push-Pull. RST changes
from low to high when
VCC1 or VCC2 drops
below selected reset
thresholds, RSTIN is
below threshold, MR is
pulled low, or the
watchdog triggers a
reset. RST remains HIGH
for the reset timeout
period after VCC1/
VCC 2/RSTIN exceed the
device reset thresholds,
MR goes low to high, or
the watchdog triggers a
reset. Open-drain outputs
require an external pullup
resistor. Push-pull
outputs are referenced to
VCC1.
MAX6715–MAX6729
restarts. The MAX6715/MAX6717/MAX6719/MAX6721/
MAX6723/MAX6725/MAX6727/MAX6728 contain open-
drain reset outputs, while the MAX6716/MAX6718/
MAX6720/MAX6722/MAX6724/MAX6726/MAX6729
contain push-pull reset outputs. The MAX6727 provides
two separate open-drain RST outputs driven by the
same internal logic.
Manual Reset Input
Many microprocessor-based products require manual
reset capability, allowing the operator, a test techni-
cian, or external logic circuitry to initiate a reset. A logic
low on MR asserts the reset output. Reset remains
asserted while MR is low and for the reset timeout peri-
od (tRP) after MR returns high. This input has an internal
50kΩpullup resistor to VCC1 and can be left uncon-
nected if not used. MR can be driven with TTL or
CMOS logic levels, or with open-drain/collector outputs.
Connect a normally open momentary switch from MR to
GND to create a manual reset function; external
debounce circuitry is not required. If MR is driven from
long cables or if the device is used in a noisy environ-
ment, connect a 0.1µF capacitor from MR to GND to
provide additional noise immunity.
Adjustable Input Voltage
The MAX6719/MAX6720 and MAX6723–MAX6727 provide
an additional input to monitor a third system voltage. The
threshold voltage at RSTIN is typically 626mV. Connect a
resistor-divider network to the circuit as shown in Figure 1
to establish an externally controlled threshold voltage,
VEXT_TH.
VEXT_TH = 626mV((R1 + R2)/R2)
Low leakage current at RSTIN allows the use of large-
valued resistors resulting in reduced power consump-
tion of the system.
Watchdog Input
The watchdog monitors µP activity through the watch-
dog input (WDI). To use the watchdog function, con-
nect WDI to a bus line or µP I/O line. When WDI
remains high or low for longer than the watchdog time-
out period, the reset output asserts.
The MAX6721–MAX6729 include a dual-mode watch-
dog timer to monitor µP activity. The flexible timeout
architecture provides a long period initial watchdog
mode, allowing complicated systems to complete
lengthy boots, and a short period normal watchdog
mode, allowing the supervisor to provide quick alerts
when processor activity fails. After each reset event
(VCC power-up/brownout, manual reset, or watchdog
reset), there is a long initial watchdog period of 35s
minimum. The long watchdog period mode provides an
extended time for the system to power-up and fully ini-
tialize all µP and system components before assuming
responsibility for routine watchdog updates.
The normal watchdog timeout period (1.12s min)
begins after the first transition on WDI before the con-
clusion of the long initial watchdog period (Figure 2).
During the normal operating mode, the supervisor will
issue a reset pulse for the reset timeout period if the µP
does not update the WDI with a valid transition (high-to-
low or low-to-high) within the standard timeout period
(1.12s min).
Power-Fail Comparator
PFI is the noninverting input to a comparator. If PFI is
less than VPFI (626.5mV), PFO goes low. Common uses
for the power-fail comparator include monitoring prereg-
ulated input of the power supply (such as a battery) or
Dual/Triple Ultra-Low-Voltage SOT23 µP
Supervisory Circuits
10 ______________________________________________________________________________________
MAX6719/
MAX6720/
MAX6723–
MAX6727
VEXT_TH
R1
R2
RSTIN
GND
Figure 1. Monitoring a Third Voltage
1.12s MAX
tWDI-NORMAL
1.12s MAX
tWDI-STARTUP
35s MAX
VTH
VCC
WDI
RESET tRP
Figure 2. Normal Watchdog Startup Sequence
providing an early power-fail warning so software can
conduct an orderly system shutdown. It can also be
used to monitor supplies other than VCC1 or VCC2 by
setting the power-fail threshold with a resistor-divider, as
shown in Figure 3. PFI is the input to the power-fail com-
parator. The typical comparator delay is 2µs from PFI to
PFO. Connect PFI to ground of VCC1 if unused.
Ensuring a Valid Reset Output
Down to VCC = 0
The MAX6715–MAX6729 are guaranteed to operate
properly down to VCC = 0.8V. In applications that
require valid reset levels down to VCC = 0 use a pull-
down resistor at RST to ground. The resistor value used
is not critical, but it must be large enough not to load
the reset output when VCC is above the reset threshold.
For most applications, 100kΩis adequate. This config-
uration does not work for the open-drain outputs of the
MAX6715/MAX6717/MAX6719/MAX6721/MAX6723/
MAX6725/MAX6727/MAX6728. For push-pull, active-
high RST output connect the external resistor as a
pullup from RST to VCC1.
Applications Information
Interfacing to µPs with Bidirectional
Reset Pins
Most microprocessors with bidirectional reset pins can
interface directly to open-drain RST output options.
Systems simultaneously requiring a push-pull RST out-
put and a bidirectional reset interface can be in logic
contention. To prevent contention, connect a 4.7kΩ
resistor between RST and the µP’s reset I/O port as
shown in Figure 4.
Adding Hysteresis to the Power-Fail
Comparator
The power-fail comparator has a typical input hysteresis
of 3mV. This is sufficient for most applications where a
power-supply line is being monitored through an external
voltage-divider (see the Power-Fail Comparator section).
If additional noise margin is desired, connect a resistor
between PFO and PFI as shown in Figure 5. Select the
values of R1, R2, and R3 so PFI sees VPFI (626mV) when
VEXT falls to its power-fail trip point (VFAIL) and when VIN
rises to its power-good trip point (VGOOD). The hysteresis
window extends between the specified VFAIL and VGOOD
thresholds. R3 adds the additional hysteresis by sinking
current from the R1/R2 divider network when PFO is logic
low and sourcing current into the network when PFO is
logic high. R3 is typically an order of magnitude greater
than R1 or R2.
The current through R2 should be at least 2.5µA to
ensure that the 25nA (max) PFI input current does not
significantly shift the trip points. Therefore, R2 <
VPFI/2.5µA < 248kΩfor most applications. R3 will provide
additional hysteresis for PFO push-pull (VOH = VCC1) or
open-drain (VOH = VPULLUP) applications.
MAX6715–MAX6729
Dual/Triple Ultra-Low-Voltage SOT23 µP
Supervisory Circuits
______________________________________________________________________________________ 11
MAX6728/
MAX6729
R1
R2
PFI
GND
VIN
PFO
VTRIP = VPFI R1 + R2
R2
()
MAX6728/
MAX6729
R1
R2
PFI
GND
VCC
VIN
PFO
VTRIP = R2 (VPFI) 1
R1
1
R2
+-
VCC
R1
[]
()
VPFI = 626.5mV
A
B
Figure 3. Using Power-Fail Input to Monitor an Additional
Power-Supply a) VIN is Positive b) VIN is Negative
MAX6715–
MAX6729
GND GND
VCC1V
CC2
VCC2
VCC1
RST
RESET TO OTHER SYSTEM COMPONENTS
RESET
µP
4.7kΩ
Figure 4. Interfacing to µPs with Bidirectional Reset I/O
MAX6715–MAX6729
Monitoring an Additional Power Supply
These µP supervisors can monitor either positive or
negative supplies using a resistor voltage-divider to
PFI. PFO can be used to generate an interrupt to the µP
or cause reset to assert (Figure 3).
Monitoring a Negative Voltage
The power-fail comparator can be used to monitor a
negative supply voltage using the circuit shown in
Figure 3. When the negative supply is valid, PFO is low.
When the negative supply voltage drops, PFO goes
high. The circuit’s accuracy is affected by the PFI
threshold tolerance, VCC, R1, and R2.
Negative-Going VCC Transients
The MAX6715–MAX6729 supervisors are relatively
immune to short-duration negative-going VCC transients
(glitches). It is usually undesirable to reset the µP when
VCC experiences only small glitches. The Typical
Operating Characteristics show Maximum Transient
Duration vs. Reset Threshold Overdrive, for which reset
pulses are not generated. The graph was produced
using negative-going VCC pulses, starting above VTH
and ending below the reset threshold by the magnitude
indicated (reset threshold overdrive). The graph shows
the maximum pulse width that a negative-going VCC
transient may typically have without causing a reset
pulse to be issued. As the amplitude of the transient
increases (i.e., goes farther below the reset threshold),
the maximum allowable pulse width decreases. A 0.1µF
bypass capacitor mounted close to the VCC pin pro-
vides additional transient immunity.
Watchdog Software Considerations
Setting and resetting the watchdog input at different
points in the program, rather than “pulsing” the watch-
dog input high-low-high or low-high-low, helps the
watchdog timer to closely monitor software execution.
This technique avoids a “stuck” loop where the watch-
dog timer continues to be reset within the loop, keeping
the watchdog from timing out. Figure 6 shows an exam-
ple flow diagram where the I/O driving the watchdog
input is set high at the beginning of the program, set low
at the beginning of every subroutine or loop, then set
high again when the program returns to the beginning. If
the program should “hang” in any subroutine, the I/O is
continually set low and the watchdog timer is allowed to
time out, causing a reset or interrupt to be issued.
Chip Information
TRANSISTOR COUNT: 1072
PROCESS: BiCMOS
Dual/Triple Ultra-Low-Voltage SOT23 µP
Supervisory Circuits
12 ______________________________________________________________________________________
MAX6728/
MAX6729
VEXT
R1
R3
R2
PFI
GND
PFO
A
VGOOD = DESIRED VEXT GOOD VOLTAGE THRESHOLD
VFAIL = DESIRED VEXT FAIL VOLTAGE THRESHOLD
VOH = VCC1 (FOR PUSH-PULL PFO)
R2 = 200kΩ (FOR > 2.5µA R2 CURRENT)
R1 = R2 ((VGOOD - VPFI) - (VPFI)(VGOOD - VFAIL) / VOH) / VPFI
R3 = (R1 x VOH) / (VGOOD - VFAIL)
VGOOD
VFAIL
VIN
PFO
Figure 5. Adding Hysteresis to Power-Fail for Push-Pull PFO
START
SET WDI
HIGH
PROGRAM
CODE
SUBROUTINE OR
PROGRAM LOOP
SET WDI LOW
RETURN
SUBROUTINE
COMPLETED
HANG IN
SUBROUTINE
Figure 6. Watchdog Flow Diagram
MAX6715–MAX6729
Dual/Triple Ultra-Low-Voltage SOT23 µP
Supervisory Circuits
______________________________________________________________________________________ 13
Functional Diagram
VCC1
VREF
VCC2
RSTIN/PFI
VREF VCC1
MR
VCC1
VCC1
VCC1
RESET
TIMEOUT
PERIOD
VCC2
RST
RST
PFO
WATCHDOG
TIMER WDI
VCC1
MR
PULLUP
RESET
OUTPUT
DRIVER
VREF/2
MAX6715–MAX6729
Dual/Triple Ultra-Low-Voltage SOT23 µP
Supervisory Circuits
14 ______________________________________________________________________________________
Selector Guide
PART
NUMBER
NUMBER OF
VOLTAGE
MONITORS
OPEN-
DRAIN
RESET
OPEN-
DRAIN
RESET
PUSH-
PULL
RESET
PUSH-
PULL
RESET
MANUAL
RESET
WATCH-
DOG
INPUT
POWER-
FAIL
INPUT/
OUTPUT
MAX6715 2 2 — — — √——
MAX6716 2 — — 2 — √——
MAX6717 2 1 — — — √——
MAX6718 2 — — 1 — √——
MAX6719 3 1 — — — √——
MAX6720 3 — — 1 — √——
MAX6721 2 1 — — — √√—
MAX6722 2 — — 1 — √√—
MAX6723 3 1 — — — — √—
MAX6724 3 — — 1 — — √—
MAX6725 3 1 1 — — √√—
MAX6726 3 — — 1 1 √√—
MAX6727 3 2 — — — √√—
MAX6728 3 1 — — — √√
√ (open drain)
MAX6729 3 — — 1 — √√
√ (push-pull)
Ordering Information (continued)
PART
TEMP RANGE
PIN-PACKAGE
MAX6721UT_ _D_ -T
-40°C to +85°C
6 SOT23-6
MAX6722UT_ _D_ -T
-40°C to +85°C
6 SOT23-6
MAX6723UT_ _D_ -T
-40°C to +85°C
6 SOT23-6
MAX6724UT_ _D_ -T
-40°C to +85°C
6 SOT23-6
MAX6725KA_ _D_ -T
-40°C to +85°C
8 SOT23-8
MAX6726KA_ _D_ -T
-40°C to +85°C
8 SOT23-8
MAX6727KA_ _D_ -T
-40°C to +85°C
8 SOT23-8
MAX6728KA_ _D_ -T
-40°C to +85°C
8 SOT23-8
MAX6729KA_ _D_ -T
-40°C to +85°C
8 SOT23-8
Note: The first “_ _” are placeholders for the threshold voltage
levels of the devices. Desired threshold levels are set by the part
number suffix found in the Reset Voltage Threshold Suffix Guide.
The “_” after the D is a placeholder for the reset timeout delay
time. Desired delay time is set using the timeout period suffix
found in the Reset Timeout Period Suffix Guide. For example the
MAX6716UTLTD3-T is a dual-voltage supervisor VTH1 = 4.625V,
VTH2 = 3.075V, and 210ms (typ) timeout period.
Devices are available in both leaded and lead-free packaging.
Specify lead-free by replacing "-T" with "+T" when ordering.
MAX6715–MAX6729
Dual/Triple Ultra-Low-Voltage SOT23 µP
Supervisory Circuits
______________________________________________________________________________________ 15
Table 1. Reset Voltage Threshold Suffix
Guide**
PART NUMBER
SUFFIX
(_ _)
VCC1 NOMINAL
VOLTAGE
THRESHOLD (V)
VCC2 NOMINAL
VOLTAGE
THRESHOLD (V)
LT 4.625 3.075
MS 4.375 2.925
MR 4.375 2.625
TZ 3.075 2.313
SY 2.925 2.188
RY 2.625 2.188
TW 3.075 1.665
SV 2.925 1.575
RV 2.625 1.575
TI 3.075 1.388
SH 2.925 1.313
RH 2.625 1.313
TG 3.075 1.110
SF 2.925 1.050
RF 2.625 1.050
TE 3.075 0.833
SD 2.925 0.788
RD 2.625 0.788
ZW 2.313 1.665
YV 2.188 1.575
ZI 2.313 1.388
YH 2.188 1.313
ZG 2.313 1.110
YF 2.188 1.050
ZE 2.313 0.833
YD 2.188 0.788
WI 1.665 1.388
VH 1.575 1.313
WG 1.665 1.110
VF 1.575 1.050
WE 1.665 0.833
VD 1.575 0.788
Table 2. Reset Timeout Period Suffix
Guide
ACTIVE TIMEOUT PERIOD
TIMEOUT
PERIOD SUFFIX
MIN [ms] MAX [ms]
D1 1.1 2.2
D2 8.8 17.6
D3 140 280
D5 280 560
D6 560 1120
D4 1120 2240
**Standard versions are shown in bold and are available in a D3
timeout option only. Standard versions require 2,500 piece order
increments and are typically held in sample stock. There is a
10,000 order increment on nonstandard versions. Other thresh-
old voltages may be available, contact factory for availability.
MAX6715–MAX6729
Dual/Triple Ultra-Low-Voltage SOT23 µP
Supervisory Circuits
16 ______________________________________________________________________________________
Pin Configurations
GND
VCC2
16VCC1
5
MAX6715/
MAX6716
SOT23
TOP VIEW
2
34
RST1
MR
RST2
GND
VCC2
16VCC1
5
MAX6721/
MAX6722
SOT23
2
34
RST
MR
WDI GND
VCC2
16VCC1
5
MAX6723/
MAX6724
SOT23
2
34
RST
WDI
RSTIN
5RSTINGND
VCC2
15VCC1
MAX6717/
MAX6718
SOT23
2
34
RST
MR
GND
VCC2
16VCC1
MAX6719/
MAX6720
SOT23
2
34
RST
MR
VCC2
MRRST
1
2
8
7
VCC1
RSTINGND
WDI
RST
SOT23
3
4
6
5
MAX6725/
MAX6726
VCC2
MR
1
2
8
7
VCC1
RSTINGND
WDI
RST
SOT23
3
4
6
5
MAX6727
RST
VCC2
MR
1
2
8
7
VCC1
PFIGND
WDI
RST
SOT23
3
4
6
5
MAX6728/
MAX6729
PFO
MAX6715–MAX6729
Dual/Triple Ultra-Low-Voltage SOT23 µP
Supervisory Circuits
______________________________________________________________________________________ 17
SOT-23 5L .EPS
E
1
1
21-0057
PACKAGE OUTLINE, SOT-23, 5L
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
MAX6715–MAX6729
Dual/Triple Ultra-Low-Voltage SOT23 µP
Supervisory Circuits
18 ______________________________________________________________________________________
6LSOT.EPS
PACKAGE OUTLINE, SOT 6L BODY
21-0058
1
1
G
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
MAX6715–MAX6729
Dual/Triple Ultra-Low-Voltage SOT23 µP
Supervisory Circuits
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 19
©2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.
SOT23, 8L .EPS
REV.DOCUMENT CONTROL NO.APPROVAL
PROPRIETARY INFORMATION
TITLE:
3.002.60E
C
E1
E
BETWEEN 0.08mm AND 0.15mm FROM LEAD TIP.
8. MEETS JEDEC MO178.
8∞
0.60
1.75
0.30
L2
0∞
e1
e
L
1.50E1
0.65 BSC.
1.95 REF.
0.25 BSC.
GAUGE PLANE
SEATING PLANE C
C
L
PIN 1
I.D. DOT
(SEE NOTE 6)
L
C
L
C
A2
e1
D
DETAIL "A"
5. COPLANARITY 4 MILS. MAX.
NOTE:
7. SOLDER THICKNESS MEASURED AT FLAT SECTION OF LEAD
6. PIN 1 I.D. DOT IS 0.3 MM ÿ MIN. LOCATED ABOVE PIN 1.
4. PACKAGE OUTLINE INCLUSIVE OF SOLDER PLATING.
3. PACKAGE OUTLINE EXCLUSIVE OF MOLD FLASH & METAL BURR.
HEEL OF THE LEAD PARALLEL TO SEATING PLANE C.
2. FOOT LENGTH MEASURED FROM LEAD TIP TO UPPER RADIUS OF
1. ALL DIMENSIONS ARE IN MILLIMETERS.
L2
L
A1
A
0.45
1.30
0.15
1.45
MAX
0.28b
0.90A2
0.00A1
0.90
A
MIN
SYMBOL
3.00
0.20
2.80D
0.09
C
SEE DETAIL "A"
L
C
be
D1
21-0078
1
PACKAGE OUTLINE, SOT-23, 8L BODY
0
0
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
Mouser Electronics
Authorized Distributor
Click to View Pricing, Inventory, Delivery & Lifecycle Information:
Maxim Integrated:
MAX6726KALTD3+T MAX6726KALTD6+T MAX6726KARVD3+T MAX6726KASDD3+T MAX6726KASHD3+T
MAX6726KASVD3+T MAX6726KASYD3+T MAX6726KATGD3+T MAX6726KAVDD3+T MAX6726KAVHD3+T
MAX6726KAWGD3+T MAX6726KAYDD3+T MAX6726KAYHD3+T MAX6726KAZGD3+T MAX6726KAZWD3+T
MAX6727KALTD3+T MAX6727KARVD3+T MAX6727KASDD3+T MAX6727KASHD3+T MAX6727KASVD3+T
MAX6727KASYD3+T MAX6727KATGD3+T MAX6727KAVDD3+T MAX6727KAVHD1+T MAX6727KAVHD3+T
MAX6727KAWGD3+T MAX6727KAYDD3+T MAX6727KAYHD3+T MAX6727KAZGD3+T MAX6727KAZWD3+T
MAX6728KATGD3+T MAX6729KALTD3+T MAX6729KARVD3+T MAX6729KASDD3+T MAX6729KASHD3+T
MAX6729KASVD3+T MAX6729KASYD3+T MAX6729KATED3+T MAX6729KATGD3+T MAX6729KAVDD3+T
MAX6729KAVHD3+T MAX6729KAWGD3+T MAX6729KAYDD3+T MAX6729KAYHD3+T MAX6729KAZED3+T
MAX6729KAZGD3+T MAX6729KAZWD3+T MAX6715UTLTD3+T MAX6715UTRVD3+T MAX6715UTSDD3+T
MAX6715UTSHD3+T MAX6715UTSVD3+T MAX6715UTSYD3+T MAX6715UTTGD3+T MAX6715UTVDD3+T
MAX6715UTVHD3+T MAX6715UTWGD3+T MAX6715UTYDD3+T MAX6715UTYHD3+T MAX6715UTZGD3+T
MAX6715UTZWD3+T MAX6716UTLTD3+T MAX6716UTRVD3+T MAX6716UTSDD3+T MAX6716UTSHD3+T
MAX6716UTSVD3+T MAX6716UTSYD3+T MAX6716UTTGD3+T MAX6716UTVDD3+T MAX6716UTVHD3+T
MAX6716UTWGD3+T MAX6716UTYDD3+T MAX6716UTYHD3+T MAX6716UTZGD3+T MAX6716UTZWD3+T
MAX6717UKLTD3+T MAX6717UKRVD3+T MAX6717UKSDD3+T MAX6717UKSFD2+T MAX6717UKSHD3+T
MAX6717UKSVD3+T MAX6717UKSYD3+T MAX6717UKTGD1+T MAX6717UKTGD3+T MAX6717UKTZD6+T
MAX6717UKVHD3+T MAX6717UKWGD3+T MAX6717UKYDD3+T MAX6717UKYHD3+T MAX6717UKZGD3+T
MAX6717UKZWD3+T MAX6718UKLTD3+T MAX6718UKRVD3+T MAX6718UKSDD3+T MAX6718UKSHD3+T
MAX6718UKSVD3+T MAX6718UKSYD3+T MAX6718UKTGD3+T MAX6718UKVDD3+T MAX6718UKVHD3+T