Features
•High-perf ormance, Lo w-p ower AVR® 8-bit Microcontroller
•Advanced RISC Architecture
– 131 Powerful Instructions – Most Single-clock Cycle Execution
– 32 × 8 General Purpose Working Registers
– Fully Static Operation
– Up to 16 MIPS Throughput at 16 MHz
– On-chip 2-cycle Multiplier
•High Endurance Non-volatile Memory segments
– 32 Kbytes of In-System Self-programmable Flash program memory
– 1024 Bytes EEPROM
– 2 Kbytes Internal SRAM
– Write/Erase Cycles: 10,000 Flash/100,000 EEPROM
– Data retention: 20 years at 85°C/100 years at 25°C(1)
– Optional Boot Code Section with Independent Lock Bits
In-System Programmi ng by On-chip Boot Program
True Read-While-Write Operation
– Programming Lock for Software Security
•JTAG (IEEE std. 1149 .1 Compliant) Interface
– Boundary-scan Capabilities According to the JTAG Standard
– Extensive On-chip Debug Support
– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface
•Peripheral Features
– Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes
– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture
Mode
– Real Time Counter with Separate Oscillator
– Four PWM Channels
– 8-channel, 10-bit ADC
8 Single-ended Channels
7 Differential Channels in TQFP Package Only
2 Differential Channels with Programmable Gain at 1x, 10x, or 200x
– Byte-oriented Two-wire Serial Interface
– Programmable Serial USART
– Master/Slave SPI Serial Interface
– Programmable Watchdog Timer with Separ ate On-chip Oscillato r
– On-chip Analog Comparator
•Special Microcontroller Features
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated RC Oscillator
– External and Internal Interru pt Sou rces
– Six Sleep Modes: Idle, ADC Noise Reduction, Power-sa ve, Power-down, Standb y
and Extended Standby
•I/O and Packages
– 32 Programmable I/O Lines
– 40-pin PDIP, 44-lead TQFP, and 44-pad QFN/MLF
•Operating Vo ltag es
– 2.7V - 5.5V for ATmega32L
– 4.5V - 5.5V for ATmega32
•Speed Grades
– 0 - 8 MHz for ATmega32L
– 0 - 16 MHz for ATmega32
•Power Consumption at 1 MHz, 3V, 25°C for ATmega32L
– Active: 1.1 mA
– Idle Mode: 0.35 mA
– Power-down Mode: < 1 µA
8-bit
Microcontroller
with 32K Bytes
In-System
Programmable
Flash
ATmega32
ATmega32L
2503P–AVR–07/10
22503P–AVR–07/10
ATmega32(L)
Pin
Configurations
Figure 1. Pinout ATmega32
(XCK/T0) PB0
(T1) PB1
(INT2/AIN0) PB2
(OC0/AIN1) PB3
(SS) PB4
(MOSI) PB5
(MISO) PB6
(SCK) PB7
RESET
VCC
GND
XTAL2
XTAL1
(RXD) PD0
(TXD) PD1
(INT0) PD2
(INT1) PD3
(OC1B) PD4
(OC1A) PD5
(ICP1) PD6
PA0 (ADC0)
PA1 (ADC1)
PA2 (ADC2)
PA3 (ADC3)
PA4 (ADC4)
PA5 (ADC5)
PA6 (ADC6)
PA7 (ADC7)
AREF
GND
AVCC
PC7 (TOSC2)
PC6 (TOSC1)
PC5 (TDI)
PC4 (TDO)
PC3 (TMS)
PC2 (TCK)
PC1 (SDA)
PC0 (SCL)
PD7 (OC2)
PA4 (ADC4)
PA5 (ADC5)
PA6 (ADC6)
PA7 (ADC7)
AREF
GND
AVCC
PC7 (TOSC2)
PC6 (TOSC1)
PC5 (TDI)
PC4 (TDO)
(MOSI) PB5
(MISO) PB6
(SCK) PB7
RESET
VCC
GND
XTAL2
XTAL1
(RXD) PD0
(TXD) PD1
(INT0) PD2
(INT1) PD3
(OC1B) PD4
(OC1A) PD5
(ICP1) PD6
(OC2) PD7
VCC
GND
(SCL) PC0
(SDA) PC1
(TCK) PC2
(TMS) PC3
PB4 (SS)
PB3 (AIN1/OC0)
PB2 (AIN0/INT2)
PB1 (T1)
PB0 (XCK/T0)
GND
VCC
PA0 (ADC0)
PA1 (ADC1)
PA2 (ADC2)
PA3 (ADC3)
PDIP
TQFP/MLF
Note:
Bottom pad should
be soldered to ground.
3
2503P–AVR–07/10
ATmega32(L)
Overview The ATmega32 is a low-power CMOS 8-bit microcontroller based on the AVR enha nced RISC
architecture. By executing powerful instructions in a single clock cycle, the ATmega32 achieves
throughputs approa ching 1 MIPS per MH z allowing the syste m designe r to optim ize powe r con-
sumption versus processing speed.
Block Diagram Figure 2. Block Diagram
INTERNAL
OSCILLATOR
OSCILLATOR
WATCHDOG
TIMER
MCU CTRL.
& TIMING
OSCILLATOR
TIMERS/
COUNTERS
INTERRUPT
UNIT
STACK
POINTER
EEPROM
SRAM
STATUS
REGISTER
USART
PROGRAM
COUNTER
PROGRAM
FLASH
INSTRUCTION
REGISTER
INSTRUCTION
DECODER
PROGRAMMING
LOGIC
SPI
ADC
INTERFACE
COMP.
INTERFACE
PORTA DRIVERS/BUFFERS
PORTA DIGITAL INTERFACE
GENERAL
PURPOSE
REGISTERS
X
Y
Z
ALU
+
-
PORTC DRIVERS/BUFFERS
PORTC DIGITAL INTERFACE
PORTB DIGITAL INTERFACE
PORTB DRIVERS/BUFFERS
PORTD DIGITAL INTERFACE
PORTD DRIVERS/BUFFERS
XTAL1
XTAL2
RESET
CONTROL
LINES
VCC
GND
MUX &
ADC
AREF
PA0 - PA7 PC0 - PC7
PD0 - PD7PB0 - PB7
AVR CPU
TWI
AVCC
INTERNAL
CALIBRATED
OSCILLATOR
42503P–AVR–07/10
ATmega32(L)
The AVR core combines a rich instruction set with 32 general purpose working registers. All the
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction executed in one clock cycle. The resulting
architecture is more code efficient while achiev ing throughputs up to ten times faster than con-
ventional CISC microcontrollers.
The ATmega3 2 provides the following fea tures: 32 Kbytes of In-System Programmable Flash
Program memory with Read-While-Write capabilities, 1024 bytes EEPROM, 2K byte SRAM, 32
general purpose I/ O lines, 32 general p urpose working r egisters, a JTAG interface fo r Boundary-
scan, On-chip Debugging support and programming, three flexible Timer/Counters with com-
pare mode s, Internal and E xternal Interrup ts, a serial programmable USART, a byte oriented
Two-wire Serial Interface, an 8-channel, 10-bit ADC with optional differential input stage with
programmable gain (TQFP package only), a p rogrammable Watchdog Timer with Internal Oscil-
lator, an SPI serial port, and six software selectable power saving modes. The Idle mode stops
the CPU while allowing the USART, Two-wire interface, A/D Converter, SRAM, Timer/Counters,
SPI port, and inte rrupt system to con tinue functio ning. The Powe r-down mod e saves the register
contents but freezes the Oscillator, disabling all other chip functions until the next External Inter-
rupt or Hardware Reset. In Power-save mode, the Asynchronous Timer continues to run,
allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC
Noise Reduction mode stops the CPU and all I/O modules except Asynchronous Timer and
ADC, to minimize switching noise during ADC conversions. In Standby mode, the crystal/reso-
nator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up
combined with low-power consumption. In Extended Standby mode, both the main Oscillator
and the Asynchronous Timer continue to run.
The device is manufactured u sing Atm el’s high den sity nonvolat ile memory te ch nology. The On-
chip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial
interface, by a conventional nonvolatile memory programm er, or by an On-chip Boot program
running on the AVR core. The boot progra m can use any interface to download the application
program in the App lication Fl ash memory. Sof tware in the Boot Fla sh sect ion wil l continue to run
while the Application Flash section is updated, providing true Rea d-While-Write operation. By
combining an 8-bit RISC CPU with In-System Self-P rogrammable Flash on a monolithic chip,
the Atmel ATmega32 is a powerful microcontroller that provides a highly-fle xible and co st-effec-
tive solution to many embedded control applications.
The ATmega32 AVR is supported with a full suite of program and system development tools
including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators,
and evaluation kits.
Pin Descriptions
VCC Digital supply voltage.
GND Ground.
Port A (PA7..PA0) Port A serves as the analog inputs to the A/D Converter.
Port A also serves as an 8-bit bi-directional I/O port, if the A/D Co nverter is not used. Port pins
can provide inte rnal pull- up r esistors ( selected for each bit) . The Po rt A output buffe rs have sym-
metrical drive characteristics with both high sink and source capability. When pins PA0 to PA7
are used as inputs and are externally pulled low, they will source current if the internal pull-up
resistors are activated. Th e Port A pins are tri-stated when a reset co ndition becomes active,
even if the clock is not running.
5
2503P–AVR–07/10
ATmega32(L)
Port B (PB7..PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port B output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up
resistors are activated. Th e Port B pins are tri-stated when a reset co ndition becomes active,
even if the clock is not running.
Port B also serves the functions of various special features of the ATmega32 as listed on page
57.
Port C (PC7..PC0) Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port C output buffers have symmetrical drive characteristics with both hig h sink and source
capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port C pins are tri-stated when a reset condition becomes active,
even if the clock is not runnin g. If the JTAG interface is enabled , the pull-up resistors on pins
PC5(TDI), PC3(TMS) and PC2(TCK) will be activated even if a reset occurs.
The TD0 pin is tri-stated unless TAP states that shift out data are entered.
Port C also serves the functions of the JTAG interface and other special features of the
ATmega32 as listed on page 60.
Port D (PD7..PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port D output buffers have symmetrical drive characteristics with both hig h sink and source
capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port D pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port D also serves the functions of various special features of the ATmega32 as listed on page
62.
RESET Reset Input. A low level on this pin for longer than the minimum pulse length will generate a
reset, even if the clock is not running. The minimum pulse length is given in Table 15 on page
37. Shorter pulses ar e not guaranteed to generate a reset.
XTAL1 Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.
XTAL2 Output from the inverting Oscillator amplifier.
AVCC AVCC is the supply voltage pin for Port A and the A/D Converter. It should be externally con-
nected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC
through a low-pass filter.
AREF AREF is the analog reference pin for the A/D Converter.
62503P–AVR–07/10
ATmega32(L)
Resources A comprehensive set of development tools, application notes and datasheets are available for
download on http://www.atmel.com/avr.
Note: 1.
Data Retention Reliability Qualification results show that the projected data retention failure rate is much less
than 1 PPM over 20 years at 85°C or 100 years at 25°C.
7
2503P–AVR–07/10
ATmega32(L)
About Code
Examples This documentatio n contains simple co de examples that br iefly sh ow how to u se various parts of
the device. These code examp les assume that the part specific header file is included b efore
compilation. Be aware that no t all C Compiler vendors include bit definitio ns in the header files
and interrupt ha ndling in C is compiler dependent. Plea se confirm with the C Co mpiler documen-
tation for more details.
82503P–AVR–07/10
ATmega32(L)
AVR CPU Core
Introduction This section discusses the AVR core architecture in general. The main function of the CPU core
is to ensure correct program execution. The CPU must therefore be able to access memories,
perform calculations, control peripherals, and handle interrupts.
Architectural
Overview Figure 3. Block Diagram of the AVR MCU Architecture
In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with
separate memories and buses for progr am and data. Instructions in the program memory are
executed with a single level pipelining. While one instruction is being executed, the next instruc-
tion is pre-fetched from the program memory. This concept enables instructions to be executed
in every clock cycle. The program memory is In-System Reprogrammable Flash memory.
The fast-access Register File contains 32 × 8-bit general purpose working registers with a single
clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typ-
ical ALU operation, two operands are output from the Register File, the operation is executed,
and the result is stored back in the Register File – in one clock cycle.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data
Space addressing – enablin g efficient address calculations. On e of the these address pointers
can also be used as an address pointer for look up ta bles in Flash Program memory. These
added function registers are the 16-bit X-, Y-, and Z-register, described later in this section.
The ALU supports arithmetic and logic operations between registers or between a constant and
a register. Single regi ster operation s can also be executed in th e ALU. After an ar ithmetic opera-
tion, the Stat us Register is updated to reflect information about the result of the operation.
Program flow is provided by conditional and unconditional jump and call instructions, able to
directly address the whole address space. Most AVR instructions have a single 16-bit word for-
mat. Every program memory address contains a 16- or 32-bit instruction.
Flash
Program
Memory
Instruction
Register
Instruction
Decoder
Program
Counter
Control Lines
32 x 8
General
Purpose
Registrers
ALU
Status
and Control
I/O Lines
EEPROM
Data Bus 8-bit
Data
SRAM
Direct Addressing
Indirect Addressing
Interrupt
Unit
SPI
Unit
Watchdog
Timer
Analog
Comparator
I/O Module 2
I/O Module1
I/O Module n
9
2503P–AVR–07/10
ATmega32(L)
Program Flash me mory space is divided in two sections, the Boot program se ction and the
Application Program section. Both sections have dedicated Lock bits for write and read/write
protection. The SPM instruction that writes into the Application Flash memory section must
reside in the Boot Program section.
During interrupts an d subroutine calls, the retur n address Program Count er (PC) is stored on the
Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack
size is only limited by the total SRAM size and the usage of the SRAM. All user programs must
initialize the SP in the reset routine (before subroutines or interrupts are executed). The Stack
Pointer SP is read/write accessible in the I/O space. The data SRAM can eas ily be accessed
through the five different addressing modes supported in the AVR architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
A flexible interru pt module has its control register s in the I/O space with an additional global
interrupt enable bit in the Status Register. All interrupts have a separate interrupt vector in the
interrupt vector table. The interrupts have priority in accordance with their interrupt vector posi-
tion. The lower the interrupt vector address, the higher the priority.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control Regis-
ters, SPI, and other I/O fun ctions. The I/O Memory can be access ed directly, or as the Data
Space locations following those of the Register File, $20 - $5F.
ALU – Arithmetic
Logic Unit The high-performance AVR ALU operates in direct connection with all the 32 general purpose
working registers. Within a single clock cycle, arithmetic operations between general purpose
registers or betwee n a re gister an d an immedi ate ar e execut ed . The ALU ope ra tio ns are divided
into three main categories – arithmetic, logical, and bit-functions. Some implementations of the
architecture also provide a powerful multiplier supporting both signed/unsigned multiplication
and fractional format. See the “Instruction Set” section for a detailed description.
10 2503P–AVR–07/10
ATmega32(L)
Status Register The Status Regist er conta ins infor mation a bout the result of th e most recently e xecuted ari thme-
tic instruction. This information can be used for altering program flow in order to perform
conditional operations. Note that the Status Register is updated after all ALU operations, as
specified in the I nstru ction Se t Re ference. This will in many case s re move the n eed f or using t he
dedicated compare instructions, resulting in faster and more compact code.
The Status Register is not automatically stored when entering an interrupt routine and restored
when returning from an inte rr up t. T his mu st be ha nd le d by so ftw ar e.
The AVR Status Register – SREG – is defined as:
• Bit 7 – I: Globa l Interrupt Enable
The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual inter-
rupt enable control is then performed in separate control registers. If the Global Interrupt Enable
Register is cleared, none of the interrupts are enabled independent of the individual interrupt
enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by
the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by
the application with the SEI and CLI instructions, as described in the instruction set reference.
• Bit 6 – T: Bit Copy Storage
The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or desti-
nation for the operated bit. A bit from a register in the Register File can be copied into T by the
BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the
BLD instruction.
• Bit 5 – H: Half Carry Flag
The Half Carry Flag H indicates a half carry in some arithmetic operation s. Half Carry is useful in
BCD arithmetic. See the “Instruction Set Description” fo r detailed information.
• Bit 4 – S: Sign Bit, S = N ⊕ V
The S-bit is always an exclusive or betwee n the Negative Flag N and the Two’s Complement
Overflow Flag V. See the “Instruction Set Description” for detailed information.
• Bit 3 – V: Two’s Complement Overflow Flag
The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the
“Instruction Set Description” for detailed information.
• Bit 2 – N: Negative Flag
The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the
“Instruction Set Description” for detailed information.
• Bit 1 – Z: Zero Flag
The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction
Set Description” for detailed information.
Bit 76543210
I T H S V N Z C SREG
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
11
2503P–AVR–07/10
ATmega32(L)
• Bit 0 – C: Carry Flag
The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set
Description” for detailed information.
General Purpose
Register File The Register File is optimized for the AVR Enhanced RISC instruc tion set. In order t o achieve
the required performance and flexibility, the following input/output schemes are supported by the
Register File:
• One 8-bit output operand and one 8-bit result input
• Two 8-bit output operands and one 8-bit result input
• Two 8-bit output operands and one 16-bit result input
• One 16-bit output operand and one 16-bit result input
Figure 4 shows the structure of the 32 general purpose working registers in the CPU.
Figure 4. AVR CPU General Purpose Work ing Registers
Most of the instructions operating on the Register File have direct access to all registers, and
most of them are single cycle instructions.
As shown in Figure 4, each register is also assigned a data memory address, mapping them
directly into the first 32 locations of the user Data Space. Although not being physically imple-
mented as SRAM locations, this memo ry organization provides great fle xibility in access of the
registers, as the X-, Y-, and Z-pointer Registers can be set to index any register in the file.
7 0 Addr.
R0 $00
R1 $01
R2 $02
…
R13 $0D
General R14 $0E
Purpose R15 $0F
Working R16 $10
Registers R17 $11
…
R26 $1A X-register Low Byte
R27 $1B X-register High Byte
R28 $1C Y-register Low Byte
R29 $1D Y-register High Byte
R30 $1E Z-register Low Byte
R31 $1F Z-register High Byte
12 2503P–AVR–07/10
ATmega32(L)
The X-register, Y-
register and Z-register The registers R26..R31 have some added functions to their general purpose usage. These reg-
isters are 16-bit address pointers for indirect addressing of the Data Space. The three indirect
address registers X, Y, and Z are defined as described in Figure 5.
Figure 5. The X-, Y-, and Z-registers
In the differ ent a ddr essing modes the se ad dr ess regist er s have fun cti ons a s fi xed d isp lacement ,
automatic increment, and automatic decrement (see the Instruction Set Reference for details).
Stack Pointer The Stack is mainly used for storing tem porary data, for storing local variables and for storing
return addresses after interrupts and subroutine calls. The Stack Pointer Register always points
to the top of th e Stack. No te that the Sta ck is implement ed as growing from hig her memor y loca-
tions to lower memor y locat io ns. This im plies t hat a Stack PUSH co mmand decr ease s th e Stack
Pointer.
The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt
Stacks are located. This Stack space in the data SRAM must be defined by the program before
any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to
point above $60. The Stack Pointer is decremented by one when data is pushed onto the Stack
with the PUSH instruction, and it is decremented by two when the return add re ss is pushed on to
the Stack with subroutine call or inte rrupt. The Stack Point er is increme nted by one when data is
popped from the Stack with the POP instruction, an d it is incremented by two when data is
popped from the Stack with return from subroutine RET or return from interrupt RETI.
The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of
bits actually used is implementation dependent. Note that the data space in some implementa-
tions of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register
will not be present.
15 XH XL 0
X - register 707 0
R27 ($1B) R26 ($1A)
15 YH YL 0
Y - register 707 0
R29 ($1D) R28 ($1C)
15 ZH ZL 0
Z - regis t er 70 7 0
R31 ($1F) R30 ($1E)
Bit 151413121110 9 8
SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SPH
SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL
76543210
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
00000000
13
2503P–AVR–07/10
ATmega32(L)
Instruction
Execution Timing This section describes the general access timing concepts for instruction execution. The AVR
CPU is driven by the CPU clock clkCPU, directly genera te d fro m the select ed clo ck source f or the
chip. No internal clock division is used.
Figure 6 shows the parallel instruction fetches and instruction executions enabled by the Har-
vard architecture and the fast-access Register File concept. This is the basic pipelining concept
to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost,
functions per clocks, and functions per power-unit.
Figure 6. The Parallel Instruction Fetches and Instruction Exe cutions
Figure 7 shows the internal timing concept for the Register File. In a single clock cycle an ALU
operation using two register operands is executed, and the result is stored back to the destina-
tion register.
Figure 7. Single Cycle ALU Operation
Reset and
Interrupt Handling The AVR provides several different interrupt sources. These interrupts and the separate reset
vector each have a separate program vector in the program memory space. All interrupts are
assigned individual enable bits which must be wr itten logic one to gether with th e Global Inter rupt
Enable bit in the Status Register in orde r to enable the interrupt. Depending on the Program
Counter value, interrupts ma y be automatically disabled when Boot Lock bits BLB02 or BLB12
are programmed. This feature improves software security. See the section “Memory Program-
ming” on page 256 for details.
The lowest addresses in the progra m memory space are by default defined as the Reset and
Interrupt Vectors. The complete list of vectors is shown in “Interrupts” on page 44. The list also
determines the priority levels of the different interrupts. The lower the address the higher is the
priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request
clk
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
T1 T2 T3 T4
CPU
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
T1 T2 T3 T4
clkCPU
14 2503P–AVR–07/10
ATmega32(L)
0. The Interru pt Vectors can be moved t o the star t of the Bo ot Flash sect ion by setti ng the IVSEL
bit in the General Interrupt Control Register (GICR). Refer to “Interrupts” on page 44 for more
information. The Reset Vector can also be moved to the start of the boot Flash section by pro-
gramming the BOOTRST fuse, see “Boot Loader Support – Read-While-Write Self-
Programming” on page 244.
When an interrupt occurs, th e Global Interrupt Enable I-bit is cleared and all interrup ts are dis-
abled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled
interrupts can then interrupt the current interrupt routine. The I-bit is au tomatically set when a
Return from Interrupt instruction – RETI – is executed.
There are basically two types of interrupts. The first type is triggered by an event that sets the
Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vec-
tor in order to execute the interrupt handling routine, and hardware clears the corresponding
Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s)
to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is
cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is
cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt
Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the
global interrupt enable bit is set, and will the n be executed by order of priority.
The second type of interrupts will trigger as long as the interrupt condition is present. The se
interrupts do not nece ssarily have I nterrupt Fla gs. If t he interr upt condit ion disappear s before the
interrupt is enabled, the interrupt will not be triggered.
When the AVR exits from an interrupt, it will always return to the main program and execute one
more instruction before any pending interrupt is served.
Note that the Status Register is not automatically stored when entering an interrupt routine, nor
restored when returning from an interrupt routine. This must be handled by software.
When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled.
No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the
CLI instruction. The f ollowing e x ample sho ws how this can be used to a void interrupts during the
timed EEPROM write sequence.
Assembly Code Example
in r16, SREG ; store SREG value
cli ; disable interrupts during timed sequence
sbi EECR, EEMWE ; start EEPROM write
sbi EECR, EEWE
out SREG, r16 ; restore SREG value (I-bit)
C Code Example
char cSREG;
cSREG = SREG; /* store SREG value */
/* disable interrupts during timed sequence */
_CLI();
EECR |= (1<<EEMWE); /* start EEPROM write */
EECR |= (1<<EEWE);
SREG = cSREG; /* restore SREG value (I-bit) */
15
2503P–AVR–07/10
ATmega32(L)
When using the SEI instruction to enable interrupts, the instruction following SEI will be exe-
cuted before any pending interrupts, as shown in this example.
Interrupt Response
Time The interrupt execution response for all the enabled AVR interrupts is four clock cycles mini-
mum. After four clo ck cycles t he pr og ram vect or add ress fo r t he actua l interr up t ha nd ling rout ine
is executed. During this four clock cycle period, the Program Counter is pushed onto the Stack.
The vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. If
an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed
before the interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the interrupt
execution response time is in creased by fo ur clock cycles. This incre ase comes in additi on to the
start-up time from the selected sleep mode.
A return from an interrupt handling routine takes four clock cycles. During these four clock
cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is
incremented by two, and t he I-bit in SREG is set.
Assembly Code Example
sei ; set global interrupt enable
sleep ; enter sleep, waiting for interrupt
; note: will enter sleep before any pending
; interrupt(s)
C Code Example
_SEI(); /* set global interrupt enable */
_SLEEP(); /* enter sleep, waiting for interrupt */
/* note: will enter sleep before any pending interrupt(s) */
16 2503P–AVR–07/10
ATmega32(L)
AVR ATmega32
Memories This section describes the different memories in the ATmega32. The AVR architecture has two
main memory spaces, the Data Memory and the Program Memory space. In addition, the
ATmega32 features an EEPROM Memory for data storage. All three memory spaces are linear
and regular.
In-System
Reprogrammable
Flash Program
Memory
The ATmega32 contains 32 Kbytes On-chip In-System Reprogrammable Flash memory for pro-
gram storage. Since all AVR instructions ar e 16 or 32 bits wide, the Flash is organized as 16K ×
16. For software security, the Flash Program memory space is divided into two sections, Boot
Program section and Appli cation Program section.
The Flash memory has an endur ance of at least 10 ,0 00 write/ e rase cycles. The ATmega32 Pro-
gram Counter (PC) is 14 bits wide, thus addressing the 16K program memory locations. The
operation of Boot Program section and associa ted Boot Lock bits for software protection are
described in detail in “Boot Loader Support – Rea d-While-Write Self-Programming” on pag e
244. “Memory Programming” on page 256 contains a detailed description on Flash Program-
ming in SPI, JTAG, or Par allell Programming mode.
Constant tables can be allocated within the entire program memory address space (see the LPM
– Load Program Memory Instruction Description).
Timing diagrams for instruction fetch and execution are presented in “Instruction Execution Tim-
ing” on page 13.
Figure 8. Program Memory Map
$0000
$3FFF
Application Flash Section
Boot Flash Section
17
2503P–AVR–07/10
ATmega32(L)
SRAM Data
Memory Figure 9 shows how the ATmega32 SRAM Memory is organized.
The lower 2144 Data Memory locations ad dress the Registe r File, the I/O Memo ry, and the inter-
nal data SRAM. The firs t 96 locations address the Reg ister File and I/O Memory, and th e next
2048 locations address the internal data SRAM.
The five different addressing modes for the data memory cover: Direct, Indirect with Displace-
ment, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In the Register
File, registers R26 to R31 feature the indirect Addressing Pointer Registers.
The direct addressing reaches the entire data space.
The Indirect with Displacemen t mode reaches 63 add ress locations from the base address given
by the Y- or Z-register.
When using register indirect addressing modes with automatic pre-decrement and post-incre-
ment, the address registers X, Y, and Z are decremented or incremented.
The 32 general purpose working registers, 64 I/O Registers, and the 2048 bytes of internal data
SRAM in the ATmega32 are all accessible through all these addressing modes. The Register
File is described in “General Purpose Register File” on page 11.
Figure 9. Data Memory Map
Register File
R0
R1
R2
R29
R30
R31
I/O Registers
$00
$01
$02
...
$3D
$3E
$3F
...
$0000
$0001
$0002
$001D
$001E
$001F
$0020
$0021
$0022
...
$005D
$005E
$005F
...
Data Address Space
$0060
$0061
$085E
$085F
...
Internal SRAM
18 2503P–AVR–07/10
ATmega32(L)
Data Memory Access
Times This section describes the general access timing concepts for internal memory access. The
internal data SRAM access is performed in two clkCPU cycles as described in Figure 10 .
Figure 10. On-chip Data SRAM Access Cycles
EEPROM Data
Memory The ATmega32 contains 1024 bytes of data EEPROM memory. It is organized as a separate
data space, in which single bytes can be read and written. The EEPROM has an endurance of at
least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described
in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and
the EEPROM Control Register.
“Memory Programmi ng” on pag e 25 6 contains a detailed description on EEPROM Programming
in SPI, JTAG, or Parallell Programming mode.
EEPROM Read/Write
Access The EEPROM Access Registers are accessible in the I/O space.
The write access time for the EEPROM is given in Table 1. A self-timing function, ho wever, lets
the user software detect when the next byt e can be written . If the user code contain s instructio ns
that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, VCC
is likely to rise or fall slowly on Power-up/down. This causes the device for some period of time
to run at a voltage lower than specified as minimum for the clock frequency used. See “Prevent-
ing EEPROM Corruption” on page 22 for details on how to avoid problems in these situations.
In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.
Refer to the description of the EEPROM Control Register for details on this.
When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is
executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next
instruction is executed.
clk
WR
RD
Data
Data
Address Address V alid
T1 T2 T3
Compute Address
Read Write
CPU
Memory Access Instruction Next Instruction
19
2503P–AVR–07/10
ATmega32(L)
The EEPR OM Address
Register – EEARH and
EEARL
• Bits 15..10 – Res: Reserved Bits
These bits are reserved bits in the ATmega32 and will always read as zero.
• Bits 9..0 – EEAR9..0: EEPROM Address
The EEPROM Address Registers – EEARH and EEARL – specify the EEPROM address in the
1024 bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and
1023. The initial value of EEAR is undefined. A proper value must be written before the
EEPROM may be accessed.
The EEPROM Data
Register – EEDR
• Bits 7..0 – EEDR7.0: EEPROM Data
For the EEPROM write oper ation, the EEDR Register contains the data to be written to the
EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the
EEDR contains the data read out from the EEPROM at the address given by EEAR.
The EEPROM Control
Register – EECR
• Bits 7..4 – Res: Reserved Bits
These bits are reserved bits in the ATmega32 and will always read as zero.
• Bit 3 – EERIE: EEPROM Ready Interrupt Enable
Writing EERIE to one enables the EEPROM Ready Interr upt if the I bit in SREG is set. Writing
EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant inter-
rupt when EEWE is cleared.
• Bit 2 – EEMWE: EEPROM Master Write Enable
The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written.
When EEMWE is set, setting EEWE within four clock cycles will write data to the EEPROM at
the selected address If EEMWE is zero, setting EEWE will have no effect. When EEMWE has
been written to one by software, hardware clears the bit to zero after four clock cycles. See the
description of the EEWE bit for an EEPROM write procedure.
Bit 151413121110 9 8
– – – – – – EEAR9 EEAR8 EEARH
EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 EEARL
76543210
Read/WriteRRRRRRR/WR/W
R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value0000000X
XXXXXXXX
Bit 76543210
MSB LSB EEDR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
– – – – EERIE EEMWE EEWE EERE EECR
Read/Write R R R R R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 X 0
20 2503P–AVR–07/10
ATmega32(L)
• Bit 1 – EEWE: EEPROM Write Enable
The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address
and data are c orrectly set up, the EEWE bit must be written to one to write the value in to the
EEPROM. The EEMWE bit must be written to one before a logical one is written to EEWE, oth-
erwise no EEPROM write takes place. The following procedure should be followed when writing
the EEPROM (the order of steps 3 and 4 is not essential):
1. Wait until EEWE becomes zero.
2. Wait until SPMEN in SPMCR becomes zero.
3. Wr ite new EEPROM address to EEAR (optional).
4. Write new EEPROM data to EEDR (optional).
5. Write a logical one to the EEMWE bit while writing a zero to EEWE in EECR.
6. Within four clock cycles after setting EEMWE, write a logical one to EEWE.
The EEPROM can not be programmed during a CPU write to the Flash memory. The software
must check that the Flash programming is completed before initiating a new EEPROM write.
Step 2 is only relevant if the software contains a Boot Loader allowing the CPU to program the
Flash. If t he F l as h is n e ve r b ein g up da te d by the CPU, step 2 ca n b e om itt ed . Se e “Boot Loader
Support – Read-While-Write Self-Programming” on page 244 for details about boot
programming.
Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the
EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is
interrupting another EEPROM Access, the EEAR or EEDR reGister will be modified, causing the
interrupted EEPROM Access t o fail. It is re commend ed to have the Global Int errupt Fla g cleared
during all the steps to avoid these problems.
When the write access time has elapsed , the EEWE bit is cleared by hardware. The user soft-
ware can poll this bit a nd wait f or a zero bef ore wr iting th e next byte. When EEWE has b een set,
the CPU is halted for two cycles before the next instruction is executed.
• Bit 0 – EERE: EEPROM Read Enable
The EEPROM Read Enable Signal – EERE – is the read strobe to the EEPROM. When the cor-
rect address is set up in the EEAR Register, the EERE bit must be written to a logic one to
trigger the EEPROM read. The EEPROM read access takes one instruction, and the requested
data is available immediately. When the EEPROM is read, the CPU is halted for four cycles
before the next instruction is executed.
The user should poll the EEWE bit before starting the read operation. If a write operation is in
progress, it is neither possible to read the EEPROM, nor to change the EEAR Register.
The calibrated Oscillator is used to time the EEPROM accesses. Table 1 lists the typical pro-
gramming time for EEPROM access from the CPU.
Note: 1. Uses 1 MHz clock, independent of CKSEL Fuse setting.
The following code examples show one assembly and one C function for writing to the
EEPROM. The examples assume that interrupts ar e controlled (for example by disabling inter-
rupts globally) so that no interrupts will occur during execution of these functions. The examples
Table 1. EEPROM Programming Time
Symbol Number of Calibrated RC
Oscillator Cycles(1) Typ Programming Time
EEPROM write (from CPU) 8448 8.5 ms
21
2503P–AVR–07/10
ATmega32(L)
also assume that no Flash Boot Loader is present in the software. If such code is present, the
EEPROM write function must also wait for any ongoing SPM command to finish.
Assembly Code Example
EEPROM_write:
; Wait for completion of previous write
sbic EECR,EEWE
rjmp EEPROM_write
; Set up address (r18:r17) in address register
out EEARH, r18
out EEARL, r17
; Write data (r16) to data register
out EEDR,r16
; Write logical one to EEMWE
sbi EECR,EEMWE
; Start eeprom write by setting EEWE
sbi EECR,EEWE
ret
C Code Example
void EEPROM_write(unsigned int uiAddress, unsigned char ucData)
{
/* Wait for completion of previous write */
while(EECR & (1<<EEWE))
;
/* Set up address and data registers */
EEAR = uiAddress;
EEDR = ucData;
/* Write logical one to EEMWE */
EECR |= (1<<EEMWE);
/* Start eeprom write by setting EEWE */
EECR |= (1<<EEWE);
}
22 2503P–AVR–07/10
ATmega32(L)
The next code examples show assembly and C functions for reading the EEPROM. The exam-
ples assume that interrupts are controlled so that no interrupts will occur during execution of
these functio ns.
EEPROM Write During
Power-down Sleep
Mode
When entering Power-down Sleep mode while an EEPROM write operation is active, the
EEPROM write operation will continue, and will complete before the Write Access time has
passed. However, when the write operation is completed, the Oscillator continues running, and
as a consequence, the device does not enter Power-down entirely. It is therefore recommended
to verify that the EEPROM write operation is completed before entering Power-down.
Preventing EEPROM
Corruption During periods of low VCC, the EEPROM data can be co rrupted because the supply voltage is
too low for the CPU and the EEPROM to operate properly. These issues a re the same as for
board level systems using EEPROM, and the same design solutions should be applied.
An EEPROM data corruption can be caused by two situations when the voltage is too low. First,
a regular write seque nce to the EEPROM requires a minimum voltage to operate correctly. Sec-
ondly, the CPU itself can execute instructions incorrectly , if the supply voltage is too low.
Assembly Code Example
EEPROM_read:
; Wait for completion of previous write
sbic EECR,EEWE
rjmp EEPROM_read
; Set up address (r18:r17) in address register
out EEARH, r18
out EEARL, r17
; Start eeprom read by writing EERE
sbi EECR,EERE
; Read data from data register
in r16,EEDR
ret
C Code Example
unsigned char EEPROM_read(unsigned int uiAddress)
{
/* Wait for completion of previous write */
while(EECR & (1<<EEWE))
;
/* Set up address register */
EEAR = uiAddress;
/* Start eeprom read by writing EERE */
EECR |= (1<<EERE);
/* Return data from data register */
return EEDR;
}
23
2503P–AVR–07/10
ATmega32(L)
EEPROM data corruption can easily be avoided by following this design recommendation:
Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This
can be done by enabling the internal Brown-out Detector (BOD). If the detection level of the
internal BOD does not match the needed detection level, an external low VCC Reset Protec-
tion circuit can be used. If a reset occurs while a write operation is in prog ress, the write
operation will be completed provided that the power supply voltag e is sufficient.
I/O Memory The I/O space definition of the ATmega32 is shown in “Register Summary” on page 327.
All ATmega32 I/Os and peripherals are placed in the I/O space. The I/O locations are accessed
by the IN and O UT instru ctions, tran sferri ng data be tween th e 32 gener al purpose wo rking regis-
ters and the I/O space. I/O Registers within the address range $00 - $1F are directly bit-
accessible using the SBI and CBI instructions. In these registers, the value of single bits can be
checked by using the SBIS and SBIC instructions. Refer to the Instruction Set section for more
details. When using the I/O specific commands IN and OUT, the I/O addresses $00 - $3F must
be used. When addressing I/O Registers as data space using LD and ST instructions, $20 must
be added to these addresses.
For compatibility with future devices, reserved bits should be written to zero if accessed.
Reserved I/O memory addresses should never be written.
Some of the Status Flag s are cleared b y writing a lo gical one to t hem. Note th at the CBI a nd SBI
instructions will operate on all bits in the I/O Register, writing a one back into any flag read as
set, thus clearing the flag. The CBI and SBI instructions work with registers $00 to $1F only.
The I/O and Peripherals Control Registers are explained in later sections.
24 2503P–AVR–07/10
ATmega32(L)
System Clock
and Cloc k
Options
Clock Systems
and their
Distribution
Figure 11 presents the principal clock systems in the AVR and their distribution. All of the clocks
need not be active at a given time . In order to red uce power co nsumption, the clo cks to modu les
not being used can be halted by using different sleep modes, as described in “Power Manage-
ment and Sleep Modes” on page 32. The clock systems are detailed Figure 11.
Figure 11. Clock Distribution
CPU Clock – clkCPU The CPU clock is routed to parts of the system concerned with operation of the AVR core.
Examples of such modules are the General Purpose Register File, the Status Register and the
data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from performing
general operations and calculations.
I/O Clock – clkI/O The I/O clock is used by the majority of the I/O modules, like Timer/Counters, SPI, and USART.
The I/O clock is also used by the External Interrupt module, but note that some external inter-
rupts are detecte d by asynchronous logic, allowing such interr upts to be detected even if the I/O
clock is halted. Also note that address recognition in the TWI module is carried out asynchro-
nously when clkI/O is halted, enabling TWI address reception in all sleep modes.
Flash Clock – clkFLASH The Fla sh clock controls o peration of t he Flash in terface. Th e Flash clock is usually active simul-
taneously with the CPU clock.
Asynchronous Timer
Clock – clkASY
The Asynchronous Timer clock allows the Asynchronous Timer/Counter to be clocked directly
from an external 32 kHz clock crystal. The dedicated clock domain allows using this
Timer/Counter as a real-time counter even when the device is in sleep mode.
25
2503P–AVR–07/10
ATmega32(L)
ADC Clock – clkADC The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks
in order to re duce noise ge ner ated by digital cir cuit ry. Th is gives mo re accurat e ADC conversion
results.
Clock Sources The device has the follo wing clock source options, selectable by Flash Fuse bits as shown
below. The cloc k fr om t he se lected so ur ce is i npu t t o th e AVR clo c k gene ra to r, an d rou te d t o the
appropriate modules.
Note: 1. For all fuses “1” means unprogrammed while “0” means programmed.
The various choices for each clocking option is given in the following sections. When the CPU
wakes up from Power-down or Power-save, the selected clock source is used to time the start-
up, ensuring stable Oscillator operation before instruction execution starts. When the CPU starts
from Reset, there is as an additional delay allowing the power to re ach a stable level before
commencing normal operation. The Watchdog Oscillator is used for timing this real-time part of
the start-up time. The number of WDT Oscillator cycles used for each time-out is shown in Table
3. The frequency of the Watchdog Oscillator is voltage depend ent as shown in “Register Sum-
mary” on page 327.
Default Clock
Source The device is shipped with CKSEL = “0001” and SUT = “10”. The default clock source setting is
therefore the 1 MHz Internal RC Oscillator with longest startup time. This default setting ensures
that all users can make their desired clock source setting using an In-System or Parallel
Programmer.
Table 2. Device Clocking Options Select(1)
Device Clocking Option CKSEL3..0
External Cr ystal/Ceramic Resonator 1111 - 1010
External Low-frequency Crystal 1001
Exter nal RC Oscillator 1000 - 0101
Calibrated Internal RC Oscillator 0100 - 0001
Exter nal Clock 0000
Table 3. Number of Watchdog Oscillator Cycles
Typ Time-out (VCC = 5.0V) Typ Time-out (VCC = 3.0V) Number of Cycles
4.1 ms 4.3 ms 4K (4,096)
65 ms 69 ms 64K (65,536)
26 2503P–AVR–07/10
ATmega32(L)
Crystal Oscillator XTAL1 and XTAL2 are input and output , respectively, of an inver ting amplifier which ca n be con-
figured for use as an On-chip Oscillator, as shown in Figure 12. Either a quartz crystal or a
ceramic resonator may be used. The CKOPT Fuse selects between two different Oscillator
amplifier modes. When CKOPT is programmed, the Oscillator output will oscillate will a full rail-
to-rail swing on the output. This mode is suitable when operating in a very noisy environment or
when the output from XTAL2 drives a second clock buffer. This mode has a wide frequency
range. When CKOPT is unprogrammed, the Oscillator has a smaller output swing. This reduces
power consumption considerably. This mode has a limited frequency range and it can not be
used to drive other clock buffers.
For resonators, th e maximum f re quency is 8 MHz with CKOPT un pr ogramm ed an d 16 MHz with
CKOPT programmed. C1 and C2 should always be equal for both crystals and resonators. The
optimal value of the capacitors depends on the crystal or resonator in use, the amount of stray
capacitance, and the electromagnetic noise of the environment. Some initial guidelines for
choosing capacitors for use with crystals are given in Table 4. For ceramic resonators, the
capacitor values given by the manufacturer should be used.
Figure 12. Crystal Oscillator Connections
The Oscillator can operate in three different modes, each optimized for a specific frequency
range. The operating mode is selected by the fuses CKSEL3..1 as shown in Table 4.
Note: 1. This option should not be used with crystals, only with ceramic resonators.
Table 4. Crystal Oscillator Operating Modes
CKOPT CKSEL3..1 Frequency Range
(MHz) Recommended Range for Capacitors
C1 and C2 for Use with Crystals (pF)
1 101(1) 0.4 - 0.9 –
1 110 0.9 - 3.0 12 - 22
1 111 3.0 - 8.0 12 - 22
0 101, 110 , 111 1.0 ≤12 - 22
XTAL2
XTAL1
GND
C2
C1
27
2503P–AVR–07/10
ATmega32(L)
The CKSEL0 Fuse together with the SUT1..0 fuses select the start-up times as shown in Table
5.
Notes: 1. These options should only be used when not operating close to the maximum frequency of the
device, and only if frequency stability at start-up is not important for the application. These
options are not suitable for crystals.
2. These options are intended for use with ceramic resonators and will ensure frequency stability
at start-up. They can also be used with crystals when not operating close to the maximum fre-
quency of the device, and if frequency stability at start-up is not important for the application.
Table 5. Start-up Times for the Crystal Oscillator Clock Selection
CKSEL0 SUT1..0
Start-up Time from
Power-down and
Power-save
Additional Delay
from Reset
(VCC = 5.0V) Recommended Usage
0 00 258 CK(1) 4.1 ms Ceramic resonator, fast
rising power
0 01 258 CK(1) 65 ms Cer amic resonator, slowly
rising power
010 1K CK
(2) –Ceramic resonator, BOD
enabled
011 1K CK
(2) 4.1 ms Ceramic resonator, fast
rising power
100 1K CK
(2) 65 ms Ceramic resonator, slowly
rising power
101 16K CK – Cr ystal Oscillator, BOD
enabled
1 10 16K CK 4.1 ms Crystal Oscillator, fast
rising power
1 11 16K CK 65 ms Crystal Oscillator, slowly
rising power
28 2503P–AVR–07/10
ATmega32(L)
Low-frequency
Crystal Oscillator To use a 32.7 68 kHz watch crystal a s the clock sour ce for the device, t he Lo w-fre quency Crysta l
Oscillator must be selected b y setting the CKSEL fuses to “10 01”. The crystal should be con-
nected as shown in Figure 12. By programming the CKOPT Fuse, the user can enable internal
capacitors on XTAL1 and XTAL2, thereby removing the need for external capacitors. The inter-
nal capacitors have a nominal value of 36 pF.
When this Oscillator is selected, start-up times are deter mined by the SUT fuses as shown in
Table 6.
Note: 1. These options should only be used if frequency stability at start-up is not important for the
application.
External RC
Oscillator For timing insensitive applications, the exte rnal RC configuration shown in Figure 13 can be
used. The frequency is roughly estimated by the equation f = 1/(3RC). C should be at least 22
pF. By progr amm ing t he CKOP T Fu se, t he user can en able a n inte rn al 3 6 pF capacitor b etw een
XTAL1 and GND, thereby removing the need for an external capacitor. For more information on
Oscillator operation and details on how to choose R and C, refer to the External RC Oscillator
application note.
Figure 13. External RC Configuration
The Oscillator can operate in four different modes, each optimized for a specific frequency
range. The operating mode is selected by the fuses CKSEL3..0 as shown in Table 7.
Table 6. Start-up Times for the Low-frequency Crystal Oscillator Clock Selection
SUT1..0
Start-up Time from
Power-down and
Power-save
Additional Delay
from Reset
(VCC = 5.0V) Recommended Usage
00 1K CK(1) 4.1 ms Fast rising power or BOD enabled
01 1K CK(1) 65 ms Slowly rising power
10 32K CK 65 ms Stable frequency at start-up
11 Reserved
XTAL2
XTAL1
GND
C
R
V
CC
NC
29
2503P–AVR–07/10
ATmega32(L)
When this Oscillator is selected, start-up times are deter mined by the SUT fuses as shown in
Table 8.
Note: 1. This option should not be used when operating close to the maximum frequency of the de vice .
Calibrated Internal
RC Oscillator The Calibrated Internal RC Oscillator provides a fixed 1.0 MHz, 2.0 MHz, 4.0 MHz, or 8.0 MHz
clock. All frequencies are nominal values at 5V and 25°C. This clock may be selected as the
system clock by programming the CKSEL fuses as shown in Table 9. If selected, it will operate
with no external comp onents. The CKOPT Fuse shou ld always be unprogrammed when using
this clock option . During Reset, hard ware loads the calibr ation byte for the 1 M Hz into the OS C-
CAL Register and thereby automatically calibrates the RC Oscillator. At 5V, 25°C and 1.0 MHz
Oscillator frequency selected, this calibration gives a frequency within ±3% of the nominal fre-
quency. Using calibration methods as described in application notes available at
www.atmel.com/avr it is possible to achieve ±1% accuracy at any given VCC and Temperature.
When this Oscillator is used as the Chip Clock, the Watchdog Oscillator will still be used for the
Watchdog Timer and for the reset time-out. For more infor mation on the pre-programmed cali-
bration value, see the section “Calibration Byte” on page 258.
Note: 1. The device is shipped with this option selected.
Table 7. External RC Oscillator Operating Modes
CKSEL3..0 Frequency Range (MHz)
0101 0.1 - 0.9
0110 0.9 - 3.0
0111 3.0 - 8.0
1000 8.0 - 12.0
Table 8. Start-up Times for the External RC Oscillator Clock Selection
SUT1..0
Start-up Time from
Power-down and
Power-save
Additional Delay
from Reset
(VCC = 5.0V) Recommended Usage
00 18 CK – BOD enabled
01 18 CK 4.1 ms Fast rising power
10 18 CK 65 ms Slowly rising power
11 6 CK(1) 4.1 ms Fast rising power or BOD enabled
Table 9. Internal Calibrated RC Oscillator Operating Modes
CKSEL3..0 Nominal Frequency (MHz)
0001(1) 1.0
0010 2.0
0011 4.0
0100 8.0
30 2503P–AVR–07/10
ATmega32(L)
When this Oscillator is selected, start-up times are deter mined by the SUT fuses as shown in
Table 10. XTAL1 and XTAL2 should be left unconnected (NC).
Note: 1. The device is shipped with this option selected.
Oscillator Calibration
Register – OSCCAL
• Bits 7..0 – CAL7..0: Oscillator Calibration Value
Writing the calibration byte to this address will trim the Internal Oscillator to remove process vari-
ations from the Oscillator frequency. During Res et, the 1 MHz calibration value which is located
in the signature row High Byte (address 0x00) is automatically loaded into the OSCCAL Regis-
ter. If the internal RC is used at other frequencies, the calibration values must be loaded
manually. This can be done by first reading the signature row by a programmer, and then store
the calibration values in the Flash or EEPROM. Then the value can be read by software and
loaded into the OSCCAL Register. When OSCCAL is zero, the lowest available frequency is
chosen. Writing non-zero values to this register will increase the frequency of the Internal Oscil-
lator. Writing $FF to the register gives the highest available frequency. The calibrated Oscillator
is used to time EEPROM and Flash access. If EEPROM or Flash is written, do not calibrate to
more than 10% above the nominal frequency. Otherwise, the EEPROM or Flash write may fail.
Note that the Oscillator is intended for calibration to 1.0 MHz, 2.0 MHz, 4.0 MHz, or 8.0 MHz.
Tuning to other values is no t guaranteed, as indicated in Table 11.
Table 10. Start-up Times for the Internal Calibrated RC Oscillator Clock Selection
SUT1..0
Start-up Time from
Power-down and
Power-save
Additional Dela y
from Reset
(VCC = 5.0V) Recommended Usage
00 6 CK – BOD enabled
01 6 CK 4.1 ms Fast rising power
10(1) 6 CK 65 ms Slowly rising power
11 Reserved
Bit 76543210
CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 OSCCAL
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value Device Specific Calibration Value
Table 11. Internal RC Oscillator Frequency Range.
OSCCAL Value Min Frequency in Percentage of
Nominal Frequency (%) Max Frequency in Percentage of
Nominal Frequency (%)
$00 50 100
$7F 75 150
$FF 100 200
31
2503P–AVR–07/10
ATmega32(L)
External Clock To drive the device from an external clock source, XTAL1 should be driven as shown in Figure
14. To run the device on an external clock, the CKSEL fuses mu st be programmed to “0000”. By
programming the CKOPT Fuse, the user can enab le an int ernal 36 pF capacitor between XTAL1
and GND.
Figure 14. External Clock Drive Configuration
When this clock source i s select ed, st ar t-u p time s ar e dete rmin ed by the SUT fuses as shown in
Table 12.
When applying an external clock, it is required t o avoid sudden changes in the applied clock fre-
quency to ensure stable operation of the MCU. A variation in frequency of more than 2% from
one clock cycle to the next can lead to unpredictable behavior. It is required to ensure that the
MCU is kept in reset during such changes in the clock frequency.
Timer/Counter
Oscillator For AVR microcontrollers with Timer/Counter Oscillator pins (TOSC1 and TOSC2), the crystal is
connected directly between the pins. No externa l capacitors are needed. The Oscillator is opti-
mized for use with a 32 .768 kHz watc h crystal. Applying an external clock source to TOSC1 is
not recommended.
Note: The Timer/Counter Oscillator uses the same type of crystal oscillator as Low-Frequency Oscillator
and the internal capacitors have the same nominal value of 36 pF.
Table 12. Start-up Times for the External Clock Selection
SUT1..0
Start-up Time from
Power-down and
Power-save
Additional Delay
from Reset
(VCC = 5.0V) Recommended Usage
00 6 CK – BOD enabled
01 6 CK 4.1 ms Fast rising po wer
10 6 CK 65 ms Slowly rising power
11 Reserved
EXTERNAL
CLOCK
SIGNAL
32 2503P–AVR–07/10
ATmega32(L)
Power
Management
and Sleep
Modes
Sleep modes enable the application to shut down unused modules in the MCU, thereby saving
power. The AVR provides vario us sleep modes allowing the user to tailor the power consump-
tion to the application’s requirements.
To enter any of the six sleep modes, the SE bit in MCUCR must be written to logic one and a
SLEEP instruction must be executed. The SM2, SM1, and SM0 bits in the MCUCR Register
select which sleep mode (Idle, ADC Noise Reduction, Power-d own, Power-save, Standb y, or
Extended Standby) will be activated by the SLEEP instruction. See Table 13 for a summary. If
an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU is
then halted for four cycles in addition to the start-up time, it executes the interrupt routine, and
resumes execution from the instruction following SLEEP. The contents of the Register File and
SRAM are unaltered when the device wakes up from sleep. If a Reset occurs during sleep
mode, the MCU wakes up and executes from the Reset Vector.
Figure 11 on page 24 presents the different clock systems in the ATmega32, and their distribu-
tion. The figure is helpful in selecting an appropriate sleep mode.
MCU Control Register
– MCUCR The MCU Control Register contains control bits for power management.
• Bit 7 – SE: Sleep Enable
The SE bit must be written to lo gic one to make the MCU enter the sle ep mode when the SLEEP
instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmers
purpose, it is recomm ended to write the Sle ep Enable ( SE) bit to o ne just bef ore the e xecution of
the SLEEP instruction and to clear it immediately after waking up.
• Bits 6...4 – SM2..0: Sleep Mode Select Bits 2, 1, and 0
These bits select between the six available sleep modes as shown in Table 13.
Note: 1. Standby mode and Extended Standby mode are only available with external crystals or
resonators.
Bit 76543210
SE SM2 SM1 SM0 ISC11 ISC10 ISC01 ISC00 MCUCR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Table 13. Sleep Mode Select
SM2 SM1 SM0 Sleep Mode
000Idle
0 0 1 ADC Noise Reduction
010Power-down
011Power-save
100Reserved
101Reserved
110Standby
(1)
1 1 1 Extended Standby(1)
33
2503P–AVR–07/10
ATmega32(L)
Idle Mode When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle
mode, stopping the CPU but allowing SPI, USART, Analog Comparator, ADC, Two-wire Serial
Interface, Timer /Co unte rs, Wa tchdog, a nd the int erru pt syste m to con tinue o pe ratin g. This sleep
mode basically halts clkCPU and clkFLASH, while allowing the other clocks to run.
Idle mode enables the M CU to wake up from external triggered interrupts as well a s internal
ones like the Timer O verflow and USART Transmit Complete interru pts. If wake-up from the
Analog Comparato r interrupt is not required , the Analog Comparator can b e powered down by
setting the ACD bit in the Analog Comparator Control and Status Register – ACSR. This will
reduce power consumption in Idle mode. If the ADC is enabled, a conversion starts automati-
cally when this mode is entered.
ADC Noise
Reduction Mode When the SM2..0 bits are written to 001, the SLEEP instruction makes the MCU enter ADC
Noise Reduction mod e, stopping the CPU but allowing the ADC, the External Interrup ts, the
Two-wire Serial Interface address watch, Timer/Counter2 and the Watchdog to continue operat-
ing (if enabled). This sleep m ode basically halts clkI/O, clkCPU, and clkFLASH, while allowing the
other clocks to run.
This improves the noise environment for the ADC, enabling higher resolution measurements. If
the ADC is enabled, a conve rsion star ts automa tically when this mode is enter ed. Apart form the
ADC Conversion Complete interrupt, only an External Reset, a Watchdog Reset, a Brown-out
Reset, a Two-wire Serial Interface Address Match Interrupt, a Timer/Counter2 inte rrupt, an
SPM/EEPROM ready interrupt, an External level interrupt on INT0 or INT1, or an external inter-
rupt on INT2 can wake up the MCU from ADC Noise Reduction mode.
Power-down Mode When the SM2..0 bits are written to 010, the SLEEP instruction makes the MCU enter Power-
down mode. In this mode, the External Oscillator is stopped, while the External interrupts, the
Two-wire Serial Interface a ddress watch, and the Watchdog continu e operating (if enabled).
Only an External Reset, a Watchdog Reset, a Brown-out Reset, a Two-wire Serial Interface
address match interrupt, an External level interrupt on INT0 or INT1, or an External interrupt on
INT2 can wake up the MCU. This sleep mo de basically halts a ll gene rated clo cks, allowin g oper-
ation of asynchronous modules only.
Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed
level must be held for some time to wake up the MCU. Refer to “External Interrupts” on page 66
for details.
When waking up from Power-down mode, there is a delay from the wake-up condition occurs
until the wake-up becomes effective. This allows the clock to restart and become stable after
having been stopped. The wake-up period is defined by the same CKSEL fuses that define the
reset time-out period, as described in “Clock Sources” on page 25.
Power-save Mode When the SM2..0 bits are written to 011, the SLEEP instruction makes the MCU enter Power-
save mode. This mode is identical to Power-down, with one exception:
If Timer/Counter2 is clocked asynchronously, that is, the AS2 bit in ASSR is set, Timer/Counter2
will run during sleep. The device can wake u p from either Timer Overflow or Output Compare
event from Timer/Counter2 if the corresponding T imer/Counter2 interrupt enable bits are set in
TIMSK, and the Global Interrupt Enable bit in SREG is set.
If the Asynch ronous Tim er is NOT clocked asynchronously, Power-down mode is r ecommended
instead of Power-save mode because the contents of the registers in the Asynchronous Time r
should be considered undefined after wake-up in Power-save mode if AS2 is 0.
This sleep mode basically halts all clocks except clkASY, allowing opera tion only of asynchronous
modules, includin g T ime r/ Co un te r2 if clocke d as yn ch ro no us ly.
34 2503P–AVR–07/10
ATmega32(L)
Standb y Mode When the SM2..0 bits are 110 and an external crystal/resonator clock o ption is selected, the
SLEEP instruction makes the MCU enter Standby mode. This mode is identical to Power-down
with the exception that the Oscillator is kept running. From Standby mode, the device wakes up
in six clock cycles.
Extended Standb y
Mode When the SM2..0 bits are 111 and an external crystal/resonator clock option is selected, the
SLEEP instruction makes the MCU enter Extended Standby mode. This mode is identical to
Power-save mode with the exception that the Oscillator is kept running. From Extended Standby
mode, the device wakes up in six clock cycles..
Notes: 1. Exter nal Cr ystal or resonator selected as clock source.
2. If AS2 bit in ASSR is set.
3. Only INT2 or level interrupt INT1 and INT0.
Minimizing Po wer
Consumption There are several issues to consider when trying to minimize the power consumption in an AVR
controlled system. In general, sleep modes should be used as much as possible, and the sleep
mode should be selected so that as few as possi ble of the device’s functions are operating. All
functions not needed should be disabled. In particular, the following modules may need special
consideration when trying to achieve the lowest possible power consumption.
Analog to Digital
Converter If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should be dis-
abled before entering any sleep mode. When the ADC is turned off and on again, the next
conversion will be an extended conversion. Refer to “Analog to Digital Converter” on page 201
for details on ADC operation.
Table 14. Active Clock Domains and Wake Up Sources in the Different Sleep Modes
Active Clock domains Oscillators W a ke-up Sources
Sleep Mode
clkCPU
clkFLASH
clkIO
clkADC
clkASY
Main Clock
Source Enabled
Timer Oscillator
Enabled
INT2
INT1
INT0
TWI Address
Match
Timer
2
SPM / EEPROM
Ready
ADC
Other
I/O
Idle X X X X X(2) X X X XXX
ADC Noise
Reduction XX XX
(2) X(3) XXXX
Power-down X(3) X
Power-save X(2) X(2) X(3) XX
(2)
Standby(1) XX
(3) X
Extended
Standby(1) X(2) XX
(2) X(3) XX
(2)
35
2503P–AVR–07/10
ATmega32(L)
Analog Comparator When entering Idle mode, the Analog Comparator should be disabled if not used. When entering
ADC Noise Reduction mode, the Analog Comparator should be disabled. In the other sleep
modes, the Analog Comparator is automatically disabled. However , if th e Ana log C omp arat or is
set up to use the Internal Voltage Reference as input, the Analog Comparator should be dis-
abled in all sleep modes. Otherwise, the Internal Voltage Reference will be enabled,
independent of sleep mode. Refer to “Analog Comparator” on page 198 for details on how to
configure the Analo g Comparator.
Brown-out Detector If the Br own-out Detector is not needed in th e application, this module should be turne d off. If the
Brown-out Detector is enabled by the BODEN Fuse, it will be enabled in all sleep modes, and
hence, always consume power. In the deeper sleep modes, this will contribute significantly to
the total current consumption. Refer to “Brown-out Detection” on page 39 for details on ho w to
configure the Brown-out Detector.
Internal Voltage
Reference The Internal Voltage Reference will be enabled when needed by the Brown-out Detector, the
Analog Comparator or the ADC. If these modules are disable d as described in the sections
above, the internal voltage reference will be disabled and it will not be consuming power. When
turned on again, the user must allow the reference to start up before the output is used. If the
reference is kept on in sleep mode, the output can be used immediately. Refer to “Internal Volt-
age Reference” on page 41 for details on the start-up time.
Watchdog Timer If the Watchdog Timer is not needed in the app lication, this module should be turned off. If the
Watchdog Timer is enabled, it will be enabled in all sleep modes, and hence, always consume
power. In the deeper sleep modes, this will contribute significantly to the total current consump-
tion. Refer to “Watchdog Timer” on pa ge 41 for d et ails on ho w to configu re the Wa tchd og Time r.
Port Pins When entering a sleep mode, all port pins should be configured to use m inimum power. The
most important thing is then to ensure that no pins drive resistive loads. In sleep modes whe re
the both the I/O clock (clkI/O) and the ADC clock (clkADC) are stopped, the input buffers of the
device will be disabled. This ensures that no power is consumed by the input logic when not
needed. In some cases, the input logic is needed for detecting wake-u p conditions, and it will
then be ena bled. Refer to the section “Digital Input Enable and Sleep Modes” on page 53 for
details on which pins are enabled. If the input buffer is enabled and the input signal is left floating
or have an analog signal level close to VCC/2, the input buffer will use excessive power.
JTAG Interface and
On-chip Debug
System
If the On-chip debug system is enabled by the OCDEN Fuse and the chip enter Power down or
Power save sleep mode, the main clock source remains enabled. In these sleep modes, this will
contribute significantly to the total current consumption. There are three alternative ways to
avoid this:
• Disable OCDEN Fuse.
• Disable JTAGEN Fuse.
• Write one to the JTD bit in MCUCSR.
The TDO pin is left floating wh en the JTAG interf ace is enabled while th e JTAG TAP controller is
not shifting data. If the hardware connected to the TDO pin does not pull up the logic le vel,
power consumption will increase. Note that the TDI pin for the next device in the scan chain con-
tains a pull-up that avoids this problem. Writing the JTD bit in the MCUCSR register to one or
leaving the JTAG fuse unprogrammed disables the JTAG interface.
36 2503P–AVR–07/10
ATmega32(L)
System Control
and Reset
Resetting the AVR During Reset, all I/O Registers are set to their initial values, and the program starts execution
from the Reset Vector. The instruction placed at the Reset Vector must be a JMP – absolute
jump – instruction to the reset handling routine. If the program never enables an interrupt
source, the Interrupt Vectors are not used, and regular program code can be placed at these
locations. This is also the case if the Reset Vector is in the Application section while the Interrupt
Vectors are in the Boot section or vice versa. The circuit diagram in Figure 15 shows the reset
logic. Table 15 defines the electrical parameters of the reset circuitry.
The I/O ports of the AVR are im mediately reset to their initial state when a reset source goes
active. This does not require any clock source to be running.
After all reset sources have gone inactive, a delay counter is invoked, stretching the Internal
Reset. This allows the power to re ach a stable level befor e normal operat ion starts. The time-out
period of the delay counter is defined by the user through the CKSEL Fuses. The different selec-
tions for the delay period are presented in “Clock Sources” on page 25.
Reset Sources The ATmega32 has five sources of reset:
• Power-on Reset. The MCU is reset when the supply voltage is below the Po wer-on Reset
threshold (VPOT).
• External Reset. The MCU is reset when a low level is present on the RESET pin for longer
than the minimum pulse length.
• Watchdog Reset. The MCU is reset when the Watchdog Timer period expires and the
Watchdog is enabled.
• Brown-out Reset. The MCU is reset when the supply voltage VCC is below the Brown-out
Reset threshold (VBOT) and the Brown-out Detector is enabled.
• JTAG AVR Reset. The MCU is reset as long as there is a logic one in the Reset Register,
one of the scan chains of the JTAG system. Refer to the section “IEEE 1149.1 (JTAG)
Boundary-scan” on page 225 for details.
37
2503P–AVR–07/10
ATmega32(L)
Figure 15. Reset Logic
Notes: 1. The Power-on Reset will no t work unless the supply voltage has been below VPOT (falling).
2. VBOT may be below nominal minimum operating voltage for some devices. For devices where
this is the ca se, the device is tested down to VCC = VBOT during the prod uction te st. This gua r-
antees that a Brown-out Reset will occur before VCC drops to a voltage where correct
operation of the microcontroller is no longer guaranteed. The test is performed using
BODLEVEL = 1 for ATmega32L and BODLEVEL = 0 for ATmega32. BODLEVEL = 1 is not
applicable for ATmega32.
Table 15. Reset Characteristics
Symbol Parameter Condition Min Typ Max Units
VPOT
Po wer-on Reset
Threshold Voltage (rising) 1.4 2.3 V
Po wer-on Reset
Threshold Voltage
(falling)(1) 1.3 2.3 V
VRST RESET Pin Threshold
Voltage 0.2VCC 0.9VCC V
tRST Minimum pulse width on
RESET Pin 1.5 µs
VBOT Brown-out Reset
Threshold Voltage(2) BODLEVEL = 1 2.5 2.7 2.9 V
BODLEVEL = 0 3.6 4.0 4.2
tBOD
Minimum low voltage
period for Brown-out
Detection
BODLEVEL = 1 2 µs
BODLEVEL = 0 2 µs
VHYST Brown-out Detector
hysteresis 50 mV
MCU Control and Status
Register (MCUCSR)
BODEN
BODLEVEL
Delay Counters
CKSEL[3:0]
CK TIMEOUT
WDRF
BORF
EXTRF
PORF
DATA BUS
Clock
Generator
SPIKE
FILTER
Pull-up Resistor
JTRF
JTAG Reset
Register
Watchdog
Oscillator
SUT[1:0]
Watchdog
Timer
Reset Circuit
Brown-out
Reset Circuit
Power-on
Reset Circuit
INTERNAL RESET
COUNTER RESET
38 2503P–AVR–07/10
ATmega32(L)
Power-on Rese t A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level
is defined in Table 15. The POR is activated whenever VCC is below the detection level. The
POR circuit can be used to trigger the Start-up Reset, as well as to detect a failure in supply
voltage.
A Power-on Reset (POR) cir cuit ensures that the device is reset from Power-on . Reaching the
Power-on Reset threshold voltage invokes the delay counter, which determines how long the
device is kept in RESET after VCC rise. The RESET signal is activated again, without any delay,
when VCC decreases below the detection level.
Figure 16. MCU Start-up, RESET Tied to VCC.
Figure 17. MCU Start-up, RESET Extended Externally
V
RESET
TIME-OUT
I
NTERNAL
RESET
tTOUT
VPOT
VRST
CC
RESET
TIME-OUT
I
NTERNAL
RESET
tTOUT
VPOT
VRST
V
CC
39
2503P–AVR–07/10
ATmega32(L)
External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the
minimum pulse width (see Table 15) will generate a reset, even if the clock is not running.
Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the
Reset Threshold Voltage – VRST – on its positive edge, t he delay counter st arts the MCU after
the Time-out period tTOUT has expired.
Figure 18. External Reset During Operation
Brown-out Detection ATmega32 has an On-chip Brown-out Detection (BOD) circuit for monitoring the VCC level dur-
ing operation by comparing it to a fixed trigger level. The trigger level for the BOD can be
selected by the fuse BODLEVEL to be 2.7V (BODLEVEL unprogrammed), or 4.0V (BODLEVEL
programmed). The trigger level has a hysteresis to ensure spike free Brown-out Detection. The
hysteresis on the detection level should be interpreted as VBOT+ = VBOT + VHYST/2 and VBOT- =
VBOT - VHYST/2.
The BOD circuit can be enabled/disabled by the fuse BODEN. When the BOD is enabled
(BODEN programmed ), and VCC decreases to a valu e below the trigger level (VBOT- in Figure
19), the Brown-out Reset is immediately activated. When VCC increases above the trigger level
(VBOT+ in Figure 19), the delay counter starts the MCU after the Time-out period tTOUT has
expired.
The BOD circuit will only detect a drop in VCC if the voltage stays below the trigger level for lon-
ger than tBOD given in Table 15.
Figure 19. Brown-out Reset During Operation
CC
V
CC
RESET
TIME-OUT
INTERNAL
RESET
V
BOT-
V
BOT+
tTOUT
40 2503P–AVR–07/10
ATmega32(L)
Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On
the falling edge of this pulse, the delay timer starts counting the Time-out period tTOUT. Refer to
page 41 fo r details on operation of the Watchdog Timer.
Figure 20. Watchdog Reset During Operation
MCU Control and
Status Register –
MCUCSR
The MCU Control and Sta tus Register provides information on which reset source caused an
MCU Reset.
• Bit 4 – JTRF: JTAG Reset Flag
This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by
the JTAG instruction AVR_RESET. This bit is reset by a Power-on Reset, or by writing a logic
zero to the flag.
• Bit 3 – WDRF: Watchdog Reset Flag
This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a
logic zero to the flag.
• Bit 2 – BORF: Brown-out Reset Flag
This bit is set if a Brown-out Reset occurs. The bit is reset by a Powe r-on Reset, or by writing a
logic zero to the flag.
• Bit 1 – EXTRF: External Reset Flag
This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a
logic zero to the flag.
• Bit 0 – PORF: Power-on Reset Flag
This bit is set if a Power-on Reset occu rs. The bit is reset only by writing a logic zero to the fl ag.
To make use of the Reset Flags t o identify a reset condition, the user shou ld read and t hen reset
the MCUCSR as early as possible in the program. If the register is cleared before another reset
occurs, the source of th e reset can be found by examining the Reset Flags.
CK
CC
Bit 76543210
JTD ISC2 – JTRF WDRF BORF EXTRF PORF MCUCSR
Read/Write R/W R/W R R/W R/W R/W R/W R/W
Initial Value 0 0 0 See Bit Description
41
2503P–AVR–07/10
ATmega32(L)
Internal Voltage
Reference ATmega32 features an internal bandgap reference. This reference is used for Brown-out Detec-
tion, and it can be used as an input to the Analog Comparator or the ADC. The 2.56V reference
to the ADC is generated from the internal bandgap reference.
Voltage Reference
Enable Signals and
Start-up Time
The voltage reference has a start-up time tha t may influence the way it should be used. T he
start-up time is give n in Tab le 16. To save power, the reference is not always turned on. The ref-
erence is on during the following situations:
1. When the BOD is enabled (by programming the BODEN Fuse).
2. When the bandgap reference is connected to the Analog Comparator (by setting the
ACBG bit in ACSR).
3. When the ADC is enabled.
Thus, when the BOD is not enabled, after setting the ACBG bit or enabling the ADC, the user
must always allow the reference to start up before the output from the Analog Comparator or
ADC is used. To reduce power consumption in Power-down mode, the user can avoid the three
conditions above to ensure that the reference is turned off before entering Power-down mode.
Watchdog Timer The Watchdog Timer is clocked from a separate On-chip Oscillator which runs at 1 MHz. This is
the typical value at VCC = 5V. See character iza tio n data f or typ ica l values at othe r VCC levels. By
controlling the Watchdog Timer prescaler, the Watchd og Reset interval can be adjusted as
shown in Table 17 on page 42. The WDR – Watchdog Reset – instruction resets the Watchdog
Timer. The Watchdog Timer is also reset when it is disabled and when a Chip Reset occurs.
Eight different clock cycle periods can be selected to determine the reset period. If the reset
period expires without another Watchdog Reset, the ATmega32 resets and executes from the
Reset Vector. For timing details on the Watchdog Reset, refer to page 40.
To prevent unintentional disabling o f the Watchdog, a special turn-off sequence must be fol-
lowed when the Watchdog is disable d. Refer to the description of the Watchdog Timer Control
Register for details.
Figure 21. Watchdog Timer
Table 16. Internal Voltage Reference Characteristics
Symbol Parameter Min Typ Max Units
VBG Bandgap reference voltage 1.15 1.23 1.35 V
tBG Bandgap reference start-up time 40 70 µs
IBG Bandgap reference current consumption 10 µA
WATCHDOG
OSCILLATOR
42 2503P–AVR–07/10
ATmega32(L)
Watchdog Timer
Control Register –
WDTCR
• Bits 7..5 – Res: Reserved Bits
These bits are reserved bits in the ATmega32 and will always read as zero.
• Bit 4 – WDTOE: Watchdog Turn-off Enable
This bit must be set when the W DE bit is written to logic z ero. Otherwise, the Watchdog will not
be disabled. Once written to one, hardware will clear this bit after four clock cycles. Refer to the
description of t he WDE bit for a Watchdog disable procedure.
• Bit 3 – WDE: Watchdog Enable
When the WDE is written to logic one, the Watchdog Timer is enabled, and if the WDE is written
to logic zero, the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE
bit has logic level one. To disable an enabled Watchdog Timer, the following procedure must be
followed:
1. In the same operation, write a logic on e to WDTOE and WDE. A logic one must be writ-
ten to WDE even though it is set to one before the disable operation starts.
2. Within the next four clock cycles, write a logic 0 to WDE. This disables the Watchdog.
• Bits 2..0 – WDP2, WDP1, WDP0: Watchdog Timer Prescaler 2, 1, and 0
The WDP2, WDP1, and WDP0 bits determine the Watchdog Timer prescaling when the Watch-
dog Timer is enabled. The different prescaling values and their corresponding Timeout Periods
are shown in Table 17.
Bit 76543210
– – – WDTOE WDE WDP2 WDP1 WDP0 WDTCR
Read/Write R R R R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Table 17. Watchdog Timer Prescale Select
WDP2 WDP1 WDP0 Number of WDT
Oscillator Cycles Typical Time-out
at VCC = 3.0V T ypical Time-out
at VCC = 5.0V
0 0 0 16K (16,384) 17.1 ms 16.3 ms
0 0 1 32K (32,768) 34.3 ms 32.5 ms
0 1 0 64K (65,536) 68.5 ms 65 ms
0 1 1 128K (131,072) 0.14 s 0.13 s
1 0 0 256K (262,144) 0.27 s 0.26 s
1 0 1 512K (524,288) 0.55 s 0.52 s
1 1 0 1,024K (1,048,576) 1.1 s 1.0 s
1 1 1 2,048K (2,097,152) 2.2 s 2.1 s
43
2503P–AVR–07/10
ATmega32(L)
The following code example shows one assembly and one C function for turning off the WDT.
The example assumes that interrupts are co ntrolled (f or example by disabling inte rrupts globally)
so that no interrupts will occur during execution of these functions.
Assembly Code Example
WDT_off:
; reset WDT
wdr
; Write logical one to WDTOE and WDE
in r16, WDTCR
ori r16, (1<<WDTOE)|(1<<WDE)
out WDTCR, r16
; Turn off WDT
ldi r16, (0<<WDE)
out WDTCR, r16
ret
C Code Example
void WDT_off(void)
{
/* reset WDT */
_WDR();
/* Write logical one to WDTOE and WDE */
WDTCR |= (1<<WDTOE) | (1<<WDE);
/* Turn off WDT */
WDTCR = 0x00;
}
44 2503P–AVR–07/10
ATmega32(L)
Interrupts This section describes the specifics of the interrupt handling as performed in ATmega32. For a
general explanation of the AVR interrupt handling, refer to “Reset and Interrupt Handling” on
page 13.
Interrupt Vectors
in ATmega32
Notes: 1. When the BOOTRST fuse is programmed, the device will jump to the Boot Load er address at
reset, see “Boot Loader Support – Read-While-Write Self-Programming” on page 244 .
2. When the IVSEL bit in GICR is set, interrupt vectors will be moved to the start of the Boot
Flash section. The address of each Interrupt Vector will then be the address in this table added
to the start address of the Boot Flash section.
Table 19 shows Reset and Interrupt Vectors placement for the various combinations of
BOOTRST and IVSEL settings. If the program never enables an interrupt source, the Interrupt
Vectors are not used , and regular progra m code can be placed at th ese locations. This is als o
the case if the Reset Vector is in the Application section while the Interrupt Vectors are in the
Boot section or vice versa.
Table 18. Reset and Interrupt Vectors
Vector No. Program
Address(2) Source Interrupt Definition
1$000
(1) RESET External Pin, Powe r-on Reset, Bro w n-out
Reset, Watchdog Reset, and JTAG AVR
Reset
2 $002 INT0 External Interrupt Request 0
3 $004 INT1 External Interrupt Request 1
4 $006 INT2 External Interrupt Request 2
5 $008 TIMER2 COMP Timer/Counter2 Compare Match
6 $00A TIMER2 OVF Timer/Counter2 Overflow
7 $00C TIMER1 CAPT Timer/Cou nter1 Capture Event
8 $00E TIMER1 COMPA Timer/Counter1 Compare Match A
9 $010 TIMER1 COMPB Timer/Counter1 Compare Match B
10 $012 TIMER1 OVF Timer/Counter1 Overflow
11 $014 TIMER0 COMP Timer/Counter0 Compare Match
12 $016 TIMER0 OVF Timer/Counter0 Overflow
13 $018 SPI, STC Serial Transfer Complete
14 $01A USART, RXC USART, Rx Complete
15 $01C USART, UDRE USART Data Register Empty
16 $01E USART, TXC USART, Tx Complete
17 $020 ADC ADC Conversion Complete
18 $022 EE_RDY EEPROM Ready
19 $024 ANA_COMP Analog Comparator
20 $026 TWI Two-wire Serial Interface
21 $028 SPM_RDY Store Program Memory Ready
45
2503P–AVR–07/10
ATmega32(L)
Note: 1. The Boot Reset Address is shown in Table 99 on page 255. For the BOOTRST Fuse “1”
means unprogrammed while “0” means programmed.
The most typical and general program setup for the Reset and Interrupt Vector Addresses in
ATmega32 is:
Address Labels Code Comments
$000 jmp RESET ; Reset Handler
$002 jmp EXT_INT0 ; IRQ0 Handler
$004 jmp EXT_INT1 ; IRQ1 Handler
$006 jmp EXT_INT2 ; IRQ2 Handler
$008 jmp TIM2_COMP ; Timer2 Compare Handler
$00A jmp TIM2_OVF ; Timer2 Overflow Handler
$00C jmp TIM1_CAPT ; Timer1 Capture Handler
$00E jmp TIM1_COMPA ; Timer1 CompareA Handler
$010 jmp TIM1_COMPB ; Timer1 CompareB Handler
$012 jmp TIM1_OVF ; Timer1 Overflow Handler
$014 jmp TIM0_COMP ; Timer0 Compare Handler
$016 jmp TIM0_OVF ; Timer0 Overflow Handler
$018 jmp SPI_STC ; SPI Transfer Complete Handler
$01A jmp USART_RXC ; USART RX Complete Handler
$01C jmp USART_UDRE ; UDR Empty Handler
$01E jmp USART_TXC ; USART TX Complete Handler
$020 jmp ADC ; ADC Conversion Complete Handler
$022 jmp EE_RDY ; EEPROM Ready Handler
$024 jmp ANA_COMP ; Analog Comparator Handler
$026 jmp TWI ; Two-wire Serial Interface Handler
$028 jmp SPM_RDY ; Store Program Memory Ready Handler
;
$02A RESET: ldi r16,high(RAMEND) ; Main program start
$02B out SPH,r16 ; Set Stack Pointer to top of RAM
$02C ldi r16,low(RAMEND)
$02D out SPL,r16
$02E sei ; Enable interrupts
$02F <instr> xxx
... ... ...
Table 19. Reset and Interrupt Vectors Placement(1)
BOOTRST IVSEL Reset address Interrupt Vectors Start Address
1 0 $0000 $0002
1 1 $0000 Boot Reset Address + $0002
0 0 Boot Reset Address $0002
0 1 Boot Reset Address Boot Reset Address + $0002
46 2503P–AVR–07/10
ATmega32(L)
When the BOOTRST Fuse is unprogrammed, the Boot section size set to 4 Kbytes and the
IVSEL bit in the GICR Register is set before any interrupts are enabled, the most typical and
general program setup for the Reset and In terrupt Vector Addresses is:
Address Labels Code Comments
$000 RESET: ldi r16,high(RAMEND) ; Main program start
$001 out SPH,r16 ; Set Stack Pointer to top of RAM
$002 ldi r16,low(RAMEND)
$003 out SPL,r16
$004 sei ; Enable interrupts
$005 <instr> xxx
;
.org $3802
$3802 jmp EXT_INT0 ; IRQ0 Handler
$3804 jmp EXT_INT1 ; IRQ1 Handler
... .... .. ;
$3828 jmp SPM_RDY ; Store Program Memory Ready Handler
When the BOOTRST Fuse is programmed and the Boot section size set to 4 Kbytes, the most
typical and general program setup for the Reset and Interrupt Vector Addresses is:
Address Labels Code Comments
.org $002
$002 jmp EXT_INT0 ; IRQ0 Handler
$004 jmp EXT_INT1 ; IRQ1 Handler
... .... .. ;
$028 jmp SPM_RDY ; Store Program Memory Ready Handler
;
.org $3800
$3800 RESET: ldi r16,high(RAMEND) ; Main program start
$3801 out SPH,r16 ; Set Stack Pointer to top of RAM
$3802 ldi r16,low(RAMEND)
$3803 out SPL,r16
$3804 sei ; Enable interrupts
$3805 <instr> xxx
When the BOOTRST Fuse is programmed, the Boot section size set to 4 Kbytes and the IVSEL
bit in the GICR Register is set before any interrupts are enabled, the most typical and general
program setup for the Reset and Interrupt Vector Addresses is:
Address Labels Code Comments
.org $3800
$3800 jmp RESET ; Reset handler
$3802 jmp EXT_INT0 ; IRQ0 Handler
$3804 jmp EXT_INT1 ; IRQ1 Handler
... .... .. ;
$3828 jmp SPM_RDY ; Store Program Memory Ready Handler
;
$382A RESET: ldi r16,high(RAMEND) ; Main program start
$382B out SPH,r16 ; Set Stack Pointer to top of RAM
$382C ldi r16,low(RAMEND)
$382D out SPL,r16
$382E sei ; Enable interrupts
$382F <instr> xxx
47
2503P–AVR–07/10
ATmega32(L)
Moving Interrupts
Between Application
and Boot Space
The General Interrupt Control Register controls the placement of the Interrupt Vector table.
General Interrupt
Control Register –
GICR
• Bit 1 – IVSEL: Interrupt Vector Select
When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the Flash
memory. When this bit is set (one), the interrupt vectors are moved to the beginning of the Boot
Loader sect ion of the Flash. The actual addres s of the start of the Boot Flash sec tion is deter-
mined by the BOOTSZ fuses. Refer to the section “Boot Loader Support – Read-While-Write
Self-Programming” on page 244 for details. To av oid unintentional chan ges of Interrupt Vector
tables, a special write procedure must be followed to change the IVSEL bit:
1. Write the Interrupt Vector Change Enable (IVCE) bit to one.
2. Within four cycles, write the desired v alu e to IVSEL while writing a zero to IVCE.
Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled
in the cycle IVCE is set, and they remain disabled until after the instruction following the write to
IVSEL. If IVSEL is not written, interrupts remain disa bled for four cycles. The I-bit in the Status
Register is unaffected by the automatic disabling.
Note: If Interrupt Vectors are placed in the Boot Loader section and Boot Lock bit BLB02 is programmed,
interrupts are disabled while e xecuting from the Application section. If Interrupt Vectors are placed
in the Application section and Boot Lock bit BLB12 is programed, interrupts are disabled while
e xecuting from the Boot Loader section. Refer to the section “Boot Loader Support – Rea d-While-
Write Self-Programming” on page 244 for details on Boot Lock bits.
Bit 76543210
INT1 INT0 INT2 – – – IVSEL IVCE GICR
Read/Write R/W R/W R/W R R R R/W R/W
Initial Value 0 0 0 0 0 0 0 0
48 2503P–AVR–07/10
ATmega32(L)
• Bit 0 – IVCE: Interrupt Vector Change Enable
The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by
hardware four cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable
interrupts, as explai ned in the IVSEL description above. See Code Example below.
Assembly Code Example
Move_interrupts:
; Enable change of interrupt vectors
ldi r16, (1<<IVCE)
out GICR, r16
; Move interrupts to boot Flash section
ldi r16, (1<<IVSEL)
out GICR, r16
ret
C Code Example
void Move_interrupts(void)
{
/* Enable change of interrupt vectors */
GICR = (1<<IVCE);
/* Move interrupts to boot Flash section */
GICR = (1<<IVSEL);
}
49
2503P–AVR–07/10
ATmega32(L)
I/O Ports
Introduction All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports.
This means that the direction of one port pin can be changed without unintentionally changing
the direction of any other pin with the SBI and CBI instructions. The same applies when chang-
ing drive value (if conf igured a s output) or enablin g/disabling o f pull-up resistors (if con figured as
input). Each output buffer has symmetrical drive characteristics with both hig h sink and source
capability. The pin driver is strong enough to drive LED displays directly. All port pins have indi-
vidually selectable pull-up resistors with a supply-voltage invariant resistance. All I/O pins have
protection diodes to both VCC and Ground as indicated in Figure 22. Refer to “Electrical Charac-
teristics” on page 287 for a complete list of parameters.
Figure 22. I/O Pin Equivalent Schematic
All registers and bit references in this section are written in general form. A lower case “x” repre-
sents the numbering letter for the p ort, and a lower case “n” represe nts the bit numb er. However,
when using the reg ister or bit defines in a program, the precise for m must be used. that is,
PORTB3 for bit no. 3 in Port B, her e docume nt ed ge ner ally as PO RT xn. The physical I /O Regis-
ters and bit locations are listed in “Register Description for I/O Ports” on page 64.
Three I/O memory address locations are allocated for each port, one each for the Data Register
– PORTx, Data Direction Register – DDRx, and the Port Input Pins – PINx. The Port Input Pins
I/O location is read only, while the Data Register and the Data Direction Register are read/write.
In addition, the Pull-up Disable – PUD bit in SFIOR disables the pull-up function for all pins in all
ports when set.
Using the I/O port as G eneral Digital I/O is described in “Ports as General Digital I/O” on page
49. Most port pins are m ultiplexed with alternate function s for the peripheral features o n the
device. How each alternate function interferes with the port pin is described in “Alternate Port
Functions” on page 54. Refer to the individual module sections for a full description of the alter-
nate functions.
Note that enabling the alternate function of some of the port pins does not affect the use of the
other pins in the por t as general digital I/O.
Ports as General
Digital I/O The ports are bi-direct iona l I/ O ports with o pti onal in tern al pull-up s. F igur e 23 shows a functiona l
description of one I/O-port pin, here generically called Pxn.
C
pin
Logic
R
pu
See Figure 23
"General Digital I/O" for
Details
Pxn
50 2503P–AVR–07/10
ATmega32(L)
Figure 23. General Digital I/O(1)
Note: 1. WPx, WDx, RRx, RPx, and RDx are common to all pins within the same por t. clkI/O, SLEEP,
and PUD are common to all ports.
Configuring the Pin Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in “Register
Description for I/O Ports” on pa ge 64 , the DDxn bits are accessed at the DDRx I/O address, the
PORTxn bits at the PORTx I/O address, and the PINxn bits at the PINx I/O address.
The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written logic one,
Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is configured as an input
pin.
If PORTxn is written logic one when the pin is configured as an input pin, the pull-up resistor is
activated. To switch t he pull-up resist or off, PORTxn h as to be written logic zero or the pi n has to
be configured as an output pin. The port pins are tri-stated when a reset condition becomes
active, even if no clocks are running.
If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven
high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port
pin is driven low (zero).
When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn}
= 0b11), an intermediate state with either pull-up enabled ({DDxn, PORTxn} = 0b01) or output
low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up enabled state is fully accept-
able, as a high-impedant environment will not notice the differenc e between a strong high driver
and a pull-up. If this is not the case, the PUD bit in the SFIOR Register can be set to disable all
pull-ups in all ports.
clk
RPx
RRx
WPx
RDx
WDx
PUD
SYNCHRONIZER
WDx: WRITE DDRx
WPx: WRITE PORTx
RRx: READ PORTx REGISTER
RPx: READ PORTx PIN
PUD: PULLUP DISABLE
clk
I/O
: I/O CLOCK
RDx: READ DDRx
D
L
Q
Q
RESET
RESET
Q
Q
D
Q
QD
CLR
PORTxn
Q
QD
CLR
DDxn
PINxn
DATA BU S
SLEEP
SLEEP: SLEEP CONTROL
Pxn
I/O
51
2503P–AVR–07/10
ATmega32(L)
Switching between input with pull-up and output low generates the same problem. The user
must use e ither the tri-st ate ({DDxn, PORTxn} = 0b00) or th e output high state ({DDxn, PORTxn}
= 0b11) as an intermediate step.
Table 20 summarizes the control signals for the pi n value.
Reading the Pin Value Independent of the setting of Data Direction bit DDxn, the port pin can be read through the
PINxn Register bit. As shown in Fi gure 23, the PINxn Registe r bit and the preceding lat ch consti-
tute a synchronizer. This is needed to avoid metastability if the physical pin changes value near
the edge of the internal clock, but it also int roduces a dela y. Figur e 24 shows a timin g diagram of
the synchronization when reading an externally applied pin value. The maximum and minimum
propagation delays are denoted tpd,max and tpd,min respectively.
Figure 24. Synchronization when Reading an Externally Applied Pin Value
Consider the clock period st arting shortly after the first falling edge of the system clock. The latch
is closed when the clock is low, and goes transpa rent when the clock is high, as indicated by the
shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock
goes low. It is clocked into the PINxn Register at the succeeding positive clock edge. As
indicated by the two arrows tpd,max and tpd,min, a single signal transition on the pin will be delayed
between ½ and 1½ system clock pe riod depending upon the time of assertion.
Table 20. Port Pin Configurations
DDxn PORTxn PUD
(in SFIOR) I/O Pull-up Comment
0 0 X Input No Tri-state (Hi-Z)
0 1 0 Input Yes Pxn will source current if ext. pulled
low.
0 1 1 Input No Tri-state (Hi-Z)
1 0 X Output No Output Low (Sink)
1 1 X Output No Output High (Source)
SYSTEM CLK
INSTRUCTIONS
SYNC LATCH
PINxn
r17
in r17, PINx
0xFF
0x00
t
pd, max
XXXXXX
t
pd, min
52 2503P–AVR–07/10
ATmega32(L)
When reading back a software assigned pin value, a nop instruction must be inserted as indi-
cated in Figure 25. The out instru ction set s th e “ SYNC LAT CH” sig nal at th e positive edg e o f the
clock. In this case, the delay tpd through the synchronizer is one system clock period.
Figure 25. Synchronization when Reading a Software Assigned Pin Value
nop in r17, PINx
0xFF
0x00 0xFF
tpd
out PORTx, r16
SYSTEM CLK
r16
INSTRUCTIONS
SYNC LATCH
PINxn
r17
53
2503P–AVR–07/10
ATmega32(L)
The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define
the port pins from 4 to 7 as input with pull-ups assigned to port pins 6 and 7. The resulting pin
values are read back again, but as previously discussed, a nop instruction is included to be able
to read back the value recently assigned to some of the pins.
Note: 1. For the assembly program, two temporary registers are used to minimize the time from pull-
ups are set on pins 0, 1, 6, and 7, until the direction bits are correctly set, defining bit 2 and 3
as low and redefining bits 0 and 1 as strong high drivers.
Digital Input Enable
and Sleep Modes As shown in Figure 23, the digital input signal can be clamped to ground at the input of the
schmitt-trigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep Controller in
Power-down mode, Power-save mode, Standby mode, and Extended Sta ndby mode to avoid
high power consumption if some input signals are left floating, or have an analog signal level
close to VCC/2.
SLEEP is overridden for port pins enabled as External Interrupt pins. If the External Interrupt
Request is not enabled, SLEEP is active also for these pins. SLEEP is also overridden by vari-
ous other alternate functions as described in “Alternate Port Functions” on page 54.
If a logic high level (“one”) is present on an Asynchronous External Interrupt pin configured as
“Interrupt on Rising Edge, Falling Edge, or Any Logic Change on Pin” while the External Inter-
rupt is not enabled, the corresponding External Interrupt Flag will be set when resuming from the
above mentioned sleep modes, as the clamping in these sleep modes produces the requested
logic change.
Assembly Code Example(1)
...
; Define pull-ups and set outputs high
; Define directions for port pins
ldi r16,(1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0)
ldi r17,(1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0)
out PORTB,r16
out DDRB,r17
; Insert nop for synchronization
nop
; Read port pins
in r16,PINB
...
C Code Example(1)
unsigned char i;
...
/* Define pull-ups and set outputs high */
/* Define directions for port pins */
PORTB = (1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0);
DDRB = (1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0);
/* Insert nop for synchronization*/
_NOP();
/* Read port pins */
i = PINB;
...
54 2503P–AVR–07/10
ATmega32(L)
Unconnected pins If some pins are unused, it is recommended to ensur e that these pins have a def ined level. Even
though most of t he digital inputs are d isabled in the deep sleep modes as descr ibed above, fl oat-
ing inputs should be avoided to reduce current consumption in all other modes where the digital
inputs are enabled (Reset, Active mode and Idle mode).
The simplest method to ensure a defined level of an unused pin, is to enable the internal pullup.
In this case, the pullup will be disabled during reset. If low power consumption during r eset is
important, it is recommended to use an external pullup or pulldown. Connecting unused pins
directly to VCC or GND is not recommended, sin ce this may ca use excess ive curr ents if the pin is
accidentally configured as an output.
Alternate Port
Functions Most port pins have alternate functions in addition to being General Digital I/Os. Figure 26
shows how the port pin control signals from the simplified Figure 23 can be ov erridden by alter-
nate functions. The overriding sig nals may not be present in all port pins, but the figure serves
as a generic description applica ble to all port pins in the AVR microcontroller family.
Figure 26. Alternate Port Functions(1)
Note: 1. WPx, WDx, RRx, RPx, and RDx are common to all pins within the same por t. clkI/O, SLEEP,
and PUD are common to all ports. All other signals are unique for each pin.
clk
RPx
RRx
WPx
RDx
WDx
PUD
SYNCHRONIZER
WDx: WRITE DDRx
WPx: WRITE PORTx
RRx: READ PORTx REGISTER
RPx: READ PORTx PIN
PUD: PULLUP DISABLE
clk
I/O
: I/O CLOCK
RDx: READ DDRx
D
L
Q
Q
SET
CLR
0
1
0
1
0
1
DIxn
AIOxn
DIEOExn
PVOVxn
PVOExn
DDOVxn
DDOExn
PUOExn
PUOVxn
PUOExn: Pxn PULL-UP OVERRIDE ENABLE
PUOVxn: Pxn PULL-UP OVERRIDE VALUE
DDOExn: Pxn DATA DIRECTION OVERRIDE ENABLE
DDOVxn: Pxn DATA DIRECTION OVERRIDE VALUE
PVOExn: Pxn PORT VALUE OVERRIDE ENABLE
PVOVxn: Pxn PORT VALUE OVERRIDE VALUE
DIxn: DIGITAL INPUT PIN n ON PORTx
AIOxn: ANALOG INPUT/OUTPUT PIN n ON PORTx
RESET
RESET
Q
QD
CLR
Q
QD
CLR
Q
Q
D
CLR
PINxn
PORTxn
DDxn
DATA BU S
0
1
DIEOVxn
SLEEP
DIEOExn: Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE
DIEOVxn: Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE
SLEEP: SLEEP CONTROL
Pxn
I/O
55
2503P–AVR–07/10
ATmega32(L)
Table 21 summarizes the function of the overriding signals. The pin and port indexes from Fig-
ure 26 are not shown in the su cceeding ta bles. The overrid ing sign als are ge nerated inte rnally in
the modules having the alternate function.
The following subsections shortly describe the alternate functions for each port, and relate the
overriding signals to the alternate function. Refer to the alternate function description for further
details.
Table 21. Generic Descript ion of Overriding Signals for Alternate Functions
Signal Name Full Name Description
PUOE Pull-up Override
Enable If this signal is set, the pull-up enable is controlled by
the PUOV signal. If this signal is cleared, the pull-up is
enabled when {DDxn, PORTxn, PUD} = 0b010.
PUOV Pull-up Override
Value If PUOE is set, the pull-up is enabled/disabled when
PUOV is set/cleared, regardless of the setting of the
DDxn, PORTxn, and PUD Register bits.
DDOE Data Direc tion
Override Enable If this signal is set, the Output Driver Enable is
controlled by the DDO V signal. If this signal is cleared,
the Output driver is enabled b y the DDxn Register bit.
DDOV Data Direction
Override Value If DDOE is set, the Output Driver is enabled/disabled
when DDO V is set/cleared, regardless of the setting of
the DDxn Register bit.
PVOE Port Value Override
Enable If this signal is set and the Output Driver is enabled,
the port value is controlled by the PVOV signal. If
PV OE is cleared, and the Output Driver is enabled, the
port Value is controlled by the PORTxn Register bit.
PVOV Port Value Override
Value If PVOE is set, the port value is set to PVOV,
regardless of the setting of the PORTxn Register bit.
DIEOE Digital Input Enable
Override Enable If this bit is set, the Digital Input Enable is controlled by
the DIEOV signal. If this signal is cleared, the Digital
Input Enable is determined by MCU-state (Normal
Mode, sleep modes).
DIEOV Digital Input Enable
Override Value If DIEOE is set, the Digital Input is enabled/disabled
when DIEOV is set/cleared, regardless of the MCU
state (Nor mal Mode, sleep modes).
DI Digital Input This is the Digital Input to alternate functions. In the
figure, the signal is connected to the output of the
schmitt trigger but bef ore the synchroniz er. Unless the
Digital Input is used as a clock source, the module with
the alternate function will use its own synchronizer.
AIO Analog Inpu t/ output This is the Analog Input/output to/from alternate
functions. The signal is connected directly to the pad,
and can be used bi-directionally.
56 2503P–AVR–07/10
ATmega32(L)
Special Function I/O
Register – SFIOR
• Bit 2 – PUD: Pull-up disable
When this bit is written to one, the pull-ups in the I/O ports are disab led even if the DDxn and
PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). See “Con-
figuring the Pin” on page 50 for more details about this feature.
Alternate Functions of
Port A Port A has an alternate function as analog input for the ADC as shown in Table 22. If some Por t
A pins are configured as outputs, it is essential that these do not switch when a conversion is in
progress. This might corrupt the result of the conversion.
Table 23 and Table 24 relate the alternate functions of Port A to the overriding signals shown in
Figure 26 on page 54.
Bit 7 6 5 4 3 2 1 0
ADTS2 ADTS1 ADTS0 –ACME PUD PSR2 PSR10 SFIOR
Read/Write R/W R/W R/W R R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Table 22. Port A Pins Alternate Functions
Port Pin Alternate Function
PA7 ADC7 (ADC input channel 7)
PA6 ADC6 (ADC input channel 6)
PA5 ADC5 (ADC input channel 5)
PA4 ADC4 (ADC input channel 4)
PA3 ADC3 (ADC input channel 3)
PA2 ADC2 (ADC input channel 2)
PA1 ADC1 (ADC input channel 1)
PA0 ADC0 (ADC input channel 0)
Table 23. Overriding Signals for Alt ernate Functions in PA7..PA4
Signal Name PA7/ADC7 PA6/ADC6 PA5/ADC5 PA4/ADC4
PUOE 0000
PUOV 0000
DDOE 0 0 0 0
DDOV 0 0 0 0
PVOE 0000
PVOV 0000
DIEOE 0000
DIEOV 0000
DI ––––
AIO ADC7 INPUT ADC6 INPUT ADC5 INPUT ADC4 INPUT
57
2503P–AVR–07/10
ATmega32(L)
Alternate Functions of
Port B The Port B pins with al ternate functions are shown in Table 25.
The alternate pin configuration is as follows:
• SCK – Port B, Bit 7
SCK: Master Clock output, Slave Clock input pin for SPI. When the SPI is enabled as a Slave,
this pin is configured as an input regardless of the setting of DDB7. When the SPI is enabled as
a Master, the data direction of this pin is controlled by DDB7. When the pin is forced by the SPI
to be an input, the pull-up can still be controlled by the PORTB7 bit.
• MISO – Port B, Bit 6
MISO: Master Data input, Slave Data output pin for SPI. When the SPI is enabled as a Master,
this pin is configured as an input regardless of the setting of DDB6. When the SPI is enabled as
a Slave, the data dir ection of this p in is co ntrolled by DDB6. When the pin is for ced by the SPI to
be an input, the pull-up can still be controlled by the PORTB6 bit.
Table 24. Overriding Signals for Alt ernate Functions in PA3..PA0
Signal Name PA3/ADC3 PA2/ADC2 PA1/ADC1 PA0/ADC0
PUOE 0000
PUOV 0000
DDOE 0 0 0 0
DDOV 0 0 0 0
PVOE 0000
PVOV 0000
DIEOE 0000
DIEOV 0000
DI ––––
AIO ADC3 INPUT ADC2 INPUT ADC1 INPUT ADC0 INPUT
Table 25. Port B Pins Alternate Functions
Port Pin Alternate Functions
PB7 SCK (SPI Bus Serial Clock)
PB6 MISO (SPI Bus Master Input/Slave Output)
PB5 MOSI (SPI Bus Master Output/Slave Input)
PB4 SS (SPI Slave Select Input)
PB3 AIN1 (Analog Comparator Negative Input)
OC0 (Timer/Counter0 Output Compare Match Output)
PB2 AIN0 (Analog Comparator Positive Input)
INT2 (Exter nal Interrupt 2 Input)
PB1 T1 (Timer/Counter1 External Counter Input)
PB0 T0 (Timer/Counter0 Exter nal Counter Input)
XCK (USART External Clock Input/Output)
58 2503P–AVR–07/10
ATmega32(L)
• MOSI – Port B, Bit 5
MOSI: SPI Master Data output, Slave Data input for SPI. Whe n the SPI is enabled as a Slave,
this pin is configured as an input regardless of the setting of DDB5. When the SPI is enabled as
a Master, the data direction of this pin is controlled by DDB5. When the pin is forced by the SPI
to be an input, the pull-up can still be controlled by the PORTB5 bit.
•SS
– Port B, Bit 4
SS: Slave Select input. When the SPI is enabled as a Slave, this pin is configured as an input
regardless of the sett ing of DDB4. As a Slave, the SPI is activated when this p in is driven low.
When the SPI is ena bled as a Master, the data direction of this pin is controlled by DDB4. When
the pin is forced by the SPI to be an input, the pull-up can still be controlled by the PORTB4 bit.
• AIN1/OC 0 – Port B, Bit 3
AIN1, Analog Compara tor Negative Inp ut. Configure the port pin as input wit h the internal pull-up
switched off to avoid the digital port function from interfering with the function of the analog
comparator.
OC0, Output Compare Match output: The PB3 pin can serve as an external output for the
Timer/Counter0 Compare Match. The PB3 pin has to be configured as an output (DDB3 set
(one)) to serve this function. The OC0 pin is also the output pin for the PWM mode timer
function.
• AIN0/INT2 – Port B, Bit 2
AIN0, Analog Comparator Positive input. Configure the port pin as input with the internal pull-up
switched off to avoid the digital port function from interfering with the function of the Analog
Comparator.
INT2, External Interrupt Source 2: The PB2 pin can serve as an external interrupt source to the
MCU.
• T1 – Port B, Bit 1
T1, Timer/Counter1 Counter Source.
• T0/XCK – Port B, Bit 0
T0, Timer/Counter0 Counter Source.
XCK, USART External Clock. The Data Direction Register (DDB0) controls whether the clock is
output (DDB0 set) or input (DDB0 cleared). The XCK pin is active only when the USART oper-
ates in Synchronous mode.
Table 26 and Table 27 relate the alternate functions of Port B to the overriding signals shown in
Figure 26 on page 54 . SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the MISO signal,
while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT.
59
2503P–AVR–07/10
ATmega32(L)
Table 26. Overriding Signals for Alt ernate Functions in PB7..PB4
Signal
Name PB7/SCK PB6/MISO PB5/MOSI PB4/SS
PUOE SPE • MSTR SPE • MSTR SPE • MSTR SPE • MSTR
PUOV PORTB7 • PUD PORTB6 • PUD PORTB5 • PUD PORTB4 • PUD
DDOE SPE • MSTR SPE • MSTR SPE • MSTR SPE • MSTR
DDOV 0 0 0 0
PVOE SPE • MSTR SPE • MSTR SPE • MSTR 0
PVOV SCK OUTPUT SPI SLAVE OUTPUT SPI MSTR OUTPUT 0
DIEOE 0 0 0 0
DIEOV 0 0 0 0
DI SCK INPUT SPI MSTR INPUT SPI SLAVE INPUT SPI SS
AIO – – – –
Table 27. Overriding Signals for Alt ernate Functions in PB3..PB0
Signal
Name PB3/OC0/AIN1 PB2/INT2/AIN0 PB1/T1 PB0/T0/XCK
PUOE 0 0 0 0
PUOV 0 0 0 0
DDOE 0 0 0 0
DDOV 0 0 0 0
PVOE OC0 ENABLE 0 0 UMSEL
PVOV OC0 0 0 XCK OUTPUT
DIEOE 0 INT2 ENABLE 0 0
DIEOV 0 1 0 0
DI – INT2 INPUT T1 INPUT XCK INPUT/T0 INPUT
AIO AIN1 INPUT AIN0 INPUT – –
60 2503P–AVR–07/10
ATmega32(L)
Alternate Functions of
Port C The Port C pins with alternate functions are shown in Table 28. If the JTAG interface is enabled,
the pull-up resistors on pins PC5(TDI), PC3(TMS) and PC2(TCK) will be activated even if a reset
occurs.
The alternate pin configuration is as follows:
• TOSC2 – Port C, Bit 7
TOSC2, Timer Oscillator pin 2: When the AS2 bit in ASSR is set (one) to enable asynchronous
clocking of Timer/Co unter2, pin PC7 is discon nected from the port, an d becomes the invertin g
output of the Oscillator amplifier. In this mode, a Crystal Oscillator is connected to this pin, and
the pin can not be used as an I/O pin.
• TOSC1 – Port C, Bit 6
TOSC1, Timer Oscillator pin 1: When the AS2 bit in ASSR is set (one) to enable asynchronous
clocking of Timer/Coun ter2, pi n PC6 is disconnect ed fr om the p ort, and b ecomes th e input of the
inverting Oscillator amplifier. In this mode, a Crystal Oscillator is connected to this pin, and the
pin can not be used as an I/O pin.
• TDI – Port C, Bit 5
TDI, JTAG Te st Data I n: Serial input d ata to be shifted in t o the I nstruction Register or Data Re g-
ister (scan chains). When the JTAG interface is enabled, this pin can not be used as an I/O pin.
• TDO – Port C, Bit 4
TDO, JTAG Test Data Out: Serial output data from Instruction Register or Data Register. When
the JTAG interface is enabled, this pin can not be used as an I/O pin.
The TD0 pin is tri-stated unless TAP states th at shifts out data are entered.
• TMS – Port C, Bit 3
TMS, JTAG Test Mode Select: This pin is used for navigating through the TAP-controller state
machine. When the JTAG interface is enabled, this pin can not be used as an I/O pin.
• TCK – Port C, Bit 2
TCK, JTAG Test Clock: JTAG operation is synchronous to TCK. When the JTAG interface is
enabled, this pin can not be used as an I/O pin.
Table 28. Port C Pins Alternate Functions
Port Pin Alternate Function
PC7 TOSC2 (Timer Oscillator Pin 2)
PC6 TOSC1 (Timer Oscillator Pin 1)
PC5 TDI (JTAG Test Data In)
PC4 TDO (JTAG Test Data Out)
PC3 TMS (JTAG Test Mode Select)
PC2 TCK (JTAG Test Clock)
PC1 SDA (Two-wire Serial Bus Data Input/Output Li ne)
PC0 SCL (Two-wire Serial Bus Clock Line)
61
2503P–AVR–07/10
ATmega32(L)
• SDA – Port C, Bit 1
SDA, Two-wire Serial Interface Data: When the TWEN bit in T WCR is set (one) to enable the
Two-wire Serial Inter face, pin PC1 is disconnected from the port and becomes the Se rial Data
I/O pin for the Two -wire Serial Interface. In this mode, ther e is a spike filter on the pin to sup-
press spikes shorter than 50 ns on the input signal, and the pin is driven by an open drain driver
with slew-rate limitation. When this pin is used by the Two-wire Serial Interface, the pull-up can
still be controlled by the PORTC1 bit.
• SCL – Port C, Bit 0
SCL, Two-wire Serial Interface Clock: When the TWEN bi t in TWCR is set (one) to ena ble the
Two-wire Serial Interface, pin PC0 is disconnected from the port and becomes the Serial Clock
I/O pin for the Two -wire Serial Interface. In this mode, ther e is a spike filter on the pin to sup-
press spikes shorter than 50 ns on the input signal, and the pin is driven by an open drain driver
with slew-rate limitation. When this pin is used by the Two-wire Serial Interface, the pull-up can
still be controlled by the PORTC0 bit.
Table 29 and Table 30 relate the alternate functions of Port C to the overriding signals shown in
Figure 26 on page 54.
Table 29. Overriding Signals for Alternate Functions in PC7..PC4
Signal
Name PC7/TOSC2 PC6/TOSC1 PC5/TDI PC4/TDO
PUOE AS2 AS2 JTAGEN JTAGEN
PUOV 0 0 1 0
DDOE AS2 AS2 JTAGEN JTAGEN
DDOV 0 0 0 SHIFT_IR + SHIFT_DR
PVOE 0 0 0 JTAGEN
PVOV 0 0 0 TDO
DIEOE AS2 AS2 JTAGEN JTAGEN
DIEOV 0 0 0 0
DI – – – –
AIO T/C2 OSC OUTPUT T/C2 OSC INPUT TDI –
62 2503P–AVR–07/10
ATmega32(L)
Note: 1. When enabled, the Two-wire Serial Interface enables slew-rate controls on the output pins
PC0 and PC1. This is not shown in the figure. In additio n, spi ke filters are conne cted between
the AIO outputs shown in the port figure and the digital logic of the TWI module.
Alternate Functions of
Port D The Port D pins with alternate functions are shown in Table 31.
The alternate pin configuration is as follows:
• OC2 – Port D, Bit 7
OC2, Timer/Counter2 Output Compar e Match outp ut: The PD7 pin can serve as an exte rnal out-
put for the Timer/Counter2 Output Compare. The pin has to be configured as an output (DDD7
set (one)) to serve this function. The OC2 pin is also the output pin for the PWM mode timer
function.