SE97TP/S900,547 - NXP Semiconductors

1. General description

The NXP Semiconductors SE97 measures temperature from −40 °C to +125 °C with

JEDEC Grade B ±1°C accuracy between +75 °C and +95 °C and al so pro vi de 25 6 bytes

of EEPROM memory communicating via the I2C-bus/SMBus. It is typically mounted on a

Dual In-line Memory Module (DIMM) measuring the DRAM temperature in accordance

with the new JEDEC (JC-42.4) Mobile Platform Memory Module Temperature Sensor

Component specifica tion and also replacing the Serial Presence Detect (SPD) which is

used to store memory module and vendor information.

The SE97 thermal sensor operates over the VDD range of 3.0 V to 3.6 V and the EEPROM

over the range of 3.0 V to 3.6 V write and 1.7 V to 3.6 V read.

Placing the Temp Sensor ( TS) on a DIMM allows accurate monitoring of the DIMM module

temperature to better estimate the DRAM case temperature (Tcase) to prevent it from

exceeding the maximum operating temperature of 85 °C. The chip set throttles the

memory traffic based on the actual temperatures instead of the calculated worst-case

temperature or the amb ient temperature using a temp sensor mounted on the

motherboard . There is up to 30 % improvement in thin and light notebooks that are using

one or two 1 GB SO-DIMM modules. The TS is required on DDR3 RDIMM and RDIMM

ECC. Future uses of the TS will include more dynamic control over thermal throttling, the

ability to use the Alarm Window to create multiple temperature zones for dynamic

throttling and to save processor time by scaling the memory refresh rate.

The TS consists of a ΔΣ Analog-to-Digital Converter (ADC) that monitors and updates its

own temperature reading s 10 times per second, converts the reading to a digit al data, and

latches them into the da ta temperature register. User-programmable registers, the

specification of upper/lower alarm an d critical temperature trip points, EVENT output

control, and temperature shutdown, provide flexibility for DIMM temperature-sensing

applications.

When the temperature changes beyond the specified boundary limits, the SE97 outputs

an EVENT signal using an open-drain output that can be pulled up between 0.9 V and

3.6 V. The user has the option of setting the EVENT output signal polarity as either an

active LOW or active HIGH comparator output for thermostat oper ation, or as a

temperature event interrupt output for microprocessor-based systems. The EVENT output

can even be configured as a critical temperature output.

The EEPROM is designed specifically for DRAM DIMMs SPD. The lower 128 bytes

(address 00h to 7Fh) can be Permanent Write Protected (PWP) or Reversible Write

Protected (RWP) by software. This allows DRAM vendor and product information to be

stored and write protected. The upper 128 bytes (address 80h to FFh) are not write

protected and can be used for general purpose data storage.

SE97

DDR memory module temp sensor with integrated SPD, 3.3 V

Rev. 07 — 29 January 2010 Product data sheet

Product data sheet Rev. 07 — 29 January 2010 2 of 55

NXP Semiconductors SE97

DDR memory module temp sensor with integrated SPD, 3.3 V

The SE97 has a single die for both the temp sensor and EEPROM for higher reliability and

supports the industry-standard 2-wire I2C-bus/SMBus serial interface. The SMBus

TIMEOUT function is supported to prevent system lock-ups. Manufacturer and Device ID

registers provide the ability to confirm the identity of the device. Three address pins allow

up to eight devices to be controlled on a single bus.

2. Features

2.1 General features

JEDEC (JC-42.4) TSE 2002B3 DIMM ±0.5 °C (typ.) between 75 °C and 95 °C

temperature sensor plus 256-byte serial EEPROM for Serial Presence Detect (SPD)

Optimized for voltage range: 3.0 V to 3.6 V, but SPD can be read down to 1.7 V

Shutdown current: 0.1 μA (typ.) and 5.0 μA (max.)

2-wire interfa ce: I2C-bus/SMBus compatible, 0 Hz to 400 kHz

SMBus ALERT Response Address and TIMEOUT (programmable)

ESD protection exceeds 2500 V HBM per JESD22-A114, 250 V MM per

JESD22-A115, and 1000 V CDM per JESD22-C101

Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA

Availa ble packages: TSSOP8, HVSON8, HXSON8, HWSON8 (JEDEC PSON8

VCED-3)

2.2 Temperature sensor features

11-bit ADC Temperature-to-Digital converter with 0.125 °C resolution

Operating current: 250 μA (typ.) and 400 μA (max.)

Programmable hysteresis threshold: off, 0 °C, 1.5 °C, 3 °C, 6 °C

Over/under/critical temperature EVENT output

B grade accuracy:

±0.5 °C/±1°C (typ./max.) →+75 °C to +95 °C

±1.0 °C/±2°C (typ./max.) →+40 °C to +125 °C

±2.0 °C/±3°C (typ./max.) →−40 °C to +125 °C

2.3 Serial EEPROM features

Operating current:

Write →0.6 mA (typ.) for 3.5 ms (typ.)

Read →100 μA (typ.)

Organized as 1 block of 256 bytes [(256 ×8) bits]

100,000 write/erase cycles and 10 years of data retention

Permanent and Reversible Software Write Protect

Software Write Protection for the lower 128 bytes

Product data sheet Rev. 07 — 29 January 2010 3 of 55

NXP Semiconductors SE97

DDR memory module temp sensor with integrated SPD, 3.3 V

3. Applications

DDR2 and DDR3 mem or y mo du le s

Laptops, personal computers and servers

Enterprise networking

Hard disk drives and other PC peripherals

4. Ordering information

[1] SE97TL and SE97TP offer improved VPOR/EVENT IOL.

[2] Industry standard 2 mm ×3mm×0.8 mm package to JEDEC VCED-3 PSON8 in 8 mm ×4 mm pitch tape 4 k quantity reels.

[3] SOT1069-1 is manufactured in APHK Hong Kong and SOT1069-2 is manufactured in APB Bangkok. The third line of the topside

marking will start with ‘P’ for SPHK and ‘n’ for APB.

Table 1. Ordering information

Type number Topside

mark Package

Name Description Version

SE97PW SE97 TSSOP8 plastic thin shrink small outline package; 8 leads;

body width 4.4 mm SOT530-1

SE97TK SE97 HVSON8 plastic thermal enhanced very thin small outline package;

no leads; 8 terminals; body 3 ×3×0.85 mm SOT908-1

SE97TL[1] 97L HXSON8 plastic thermal enhanced extremely thin small outline package;

no leads; 8 terminals; body 2 ×3×0.5 mm SOT1052-1

SE97TP[1][2][3] S97 HWSON8 plastic thermal enhanced very very thin small outline package;

no leads; 8 terminals; body 2 ×3×0.8 mm SOT1069-1

SE97TP/S900[1][2][3] S97 HWSON8 plastic thermal enhanced very very thin small outline package;

no leads; 8 terminals; body 2 ×3×0.8 mm SOT1069-2

Product data sheet Rev. 07 — 29 January 2010 4 of 55

NXP Semiconductors SE97

DDR memory module temp sensor with integrated SPD, 3.3 V

5. Block diagram

Fig 1. Block diagram of SE97

002aab349

SCL

SDA

EVENT

2-kbit EEPROM

WRITE PROTECT

SOFTWARE

WRITE PROTECT

SE97

VSS

SMBus/I2C-BUS

INTERFACE

VDD

FFh

7Fh

00h

TEMPERATURE REGISTER

CRITICAL ALARM TRIP

UPPER ALARM TRIP

LOWER ALARM TRIP

CAPABILITY

MANUFACTURING ID

DEVICE/REV ID

SMBus TIMEOUT/ALERT

CONFIGURATION

• HYSTERESIS

• SHUT DOWN TEMP SENSOR

• LOCK PROTECTION

• EVENT OUTPUT ON/OFF

• EVENT OUTPUT POLARITY

• EVENT OUTPUT STATUS

• CLEAR EVENT OUTPUT STATUS

POINTER REGISTER

BAND GAP

TEMPERATURE

SENSOR

11-BIT ΔΣ ADC

POR

10 V

OVERVOLTAGE

FILTER

30 kΩ to 800 kΩ

80h

Product data sheet Rev. 07 — 29 January 2010 5 of 55

NXP Semiconductors SE97

DDR memory module temp sensor with integrated SPD, 3.3 V

6. Pinning information

6.1 Pinning

Fig 2. Pin configuration for TSSOP8 Fig 3. Pin configuration for HXSON8

Fig 4. Pin configuration for HVSON8 Fig 5. Pin configuration for HWSON8

(SOT1069-1)

Fig 6. Pin conf iguration for HWSON8 (SOT1069-2)

SE97PW

A0 VDD

A1 EVENT

A2 SCL

VSS SDA

002aab805

terminal 1

index area

1A0

SE97TL

002aad548

Transparent top view

2A1

3A2

EVENT

SCL

SDA

002aab803

SE97TK

SDA

VSS

SCL

A1 EVENT

A0 VDD

Transparent top view

3 6

2 7

1 8

terminal 1

index area

terminal 1

index area

1A0

SE97TP

002aad768

Transparent top view

2A1

3A2

EVENT

SCL

SDA

VSS

VDD

EVENT

SCL

SDA

terminal 1

index area

SE97TP/S900

002aaf007

Transparent top view

Product data sheet Rev. 07 — 29 January 2010 6 of 55

NXP Semiconductors SE97

DDR memory module temp sensor with integrated SPD, 3.3 V

6.2 Pin description

Table 2. Pin description

Symbol Pin Type Description

A0 1 I I2C-bus/SMBus slave address bit 0 with internal pull-down. This

input is overvoltage tolerant to support software write protection.

A1 2 I I2C-bus/SMBus slave address bit 1 with internal pull-down

A2 3 I I2C-bus/SMBus slave address bit 2 with internal pull-down

VSS 4 ground device ground

SDA 5 I/O SMBus/I2C-bus serial data input/output (open-drain). Must have

external pul l - up resi st or.

SCL 6 I SMBus/I2C-bus serial clock input/o utput (open-drain). Must have

external pul l - up resi st or.

EVENT 7 O Thermal alarm output for high/low and critical temperature limit

(open-drain). Must have external pull-up resistor.

VDD 8 power device power supply (3.0 V to 3.6 V); supports 1.7 V for

EEPROM read only.

Product data sheet Rev. 07 — 29 January 2010 7 of 55

NXP Semiconductors SE97

DDR memory module temp sensor with integrated SPD, 3.3 V

7. Functional description

7.1 Serial bus interface

The SE97 communicates with a host controller by means of the 2-wire serial bus

(I2C-bus/SMBus) that consists of a serial clock (SCL) and serial data (SDA) signals. The

device supports SMBus, I2C-bus Standard-mode and Fast-mode. The I2C-bus standard

speed is defined to have bus speeds from 0 Hz to 100 kHz, I2C-bus fast speed from 0 Hz

to 400 kHz, and the SMBus is from 10 kHz to 100 kHz. The host or bus master g enerates

the SCL signal, and the SE97 uses the SCL signal to receive or send data on the SDA

line. Data transfer is serial, bidirectional, and is one byte at a time with the Most Significant

Bit (MSB) is transferred first. Since SCL and SDA are open-drain, pull-up resistors must

be installed on these pins.

7.2 Slave address

The SE97 uses a 4-bit fixed and 3-bit programmable (A0, A1 and A2) 7-bit slave addr ess

that allows a tot al of eight devices to coexist on the same bus. The A0, A1 and A2 pins are

pulled LOW internally. The A0 pin is also overvoltage tolerant supporting 10 V software

write protect. When it is driven hig her than 7.8 V, writing a special command would put the

EEPROM in reversible write protect mode (see Section 7.10.2 “Memory p rotection”). Each

pin is sampled at the st art of each I2C-bus/SMBus access. The temperature sensor’s fixed

address is ‘0011b’. The EEPROM’s fixed address for the normal EEPROM read/write is

‘1010b’, and for EEPROM software protection command is ‘0110b’. Refer to Figure 7.

a. Temperature sensor b. EEPROM (normal read/write) c. EEPROM (software

protection command)

Fig 7. Slave address

R/W

002aab30

0 0 1 1 A2 A1 A0

fixed hardware

selectable

slave address

MSB LSB

R/W

002aab35

1 0 1 0 A2 A1 A0

fixed hardware

selectable

slave address

MSB LSB

R/W

002aab35

0 1 1 0 A2 A1 A0

fixed hardware

selectable

slave address

MSB LSB

Product data sheet Rev. 07 — 29 January 2010 8 of 55

NXP Semiconductors SE97

DDR memory module temp sensor with integrated SPD, 3.3 V

7.3 EVENT output condition

The EVENT output indicates conditions such as the temperature crossing a predefined

boundary. The EVENT modes are very configurable and selected using the configuration

using either TCRIT/UPPER/LOWER or TCRIT only temperature bands (CONFIG[2]) as

modified by hysteresis (CONFIG[10:9]). The UPPER/LOWER (CONFIG[6]) and TCRIT

(CONFIG[7]) bands can be locked. Figure 8 shows an example of the me asured

temperature versus time, with the corresp onding behavio r of the EVENT ou tput in each of

these modes.

Upon device power-up, the default condition for the EVENT output is high-impedance to

prevent spurious or unwanted alarms, but can be later enabled (CONFIG[3]). EVENT

output polarity can be set to active HIGH or active LOW (CONFIG[1]). EVENT status can

be read (CONFIG[4]) and cleared (CONFIG[5]).

•Advisory note:

–NXP device: After po wer-up, bit 3 (1) and bit 2 or bit 0 (leave as 0 or 1) can be set

at the sam e time (e .g., in same byte ) but o nce bit 3 is set (1) then changing bit 2 or

bit 0 has no effect on the device operation.

–Competitor device: Does not require that bit 3 be cleared (e.g., set back to (0))

before changing bit 2 or bit 0.

–Wo rk-around: In or der to change bit 2 or bit 0 once bit 3 (1) is set, bit 3 (0) must be

cleared in one byte and then change bit 2 or bit 0 and reset bit 3 (1) in the next

byte.

–SE97B will allow bit 2 or bit 0 to be changed even if bit 3 is set.

If the device enters Shutdown mode (CONFIG[8]) with asserted EVENT output, the output

remains asserted during shutdown.

7.3.1 EVENT pin output voltage levels and resistor sizing

The EVENT open-drain output is typically pu lled up to a voltage level fr om 0.9 V to 3.6 V

with an external pull-up resistor, but there is no real lower limit on the pull-up voltage for

the EVENT pin since it is simply an open-drain output. It could be pulled up to 0.1 V and

would not affect the output. From the system perspective, there will be a practical limit.

That limit will be the voltage necessary for the device monitori ng the interrupt pin to detect

a HIGH on its input. A possible practical limit for a CMOS input would be 0.4 V. Another

thing to consider is the value of the pull- up resistor. When a low supply voltage is applied

to the drain (through the pull-up resistor) it is important to use a higher value pull-up

resistor, to allow a larger maximum signal swing on the EVENT pin.

Product data sheet Rev. 07 — 29 January 2010 9 of 55

NXP Semiconductors SE97

DDR memory module temp sensor with integrated SPD, 3.3 V

When Tamb ≥ Tth(crit) and Tamb < Tth(crit) − Thys the EVENT output is in Comparator mode

and bit 0 of CONFIG (EVENT output mode) is igno re d .

Refer to Table 3 for figure note information.

Fig 8. EVENT output condition

002aae324

time

temperature (°C)

critical

EVENT in Interrupt mode

EVENT in Comparator mode

software interrupt clear

Lower Boundary Alarm

Upper Boundary Alarm

EVENT in ‘Critical Temp only’ mode

(1) (2) (1) (3) (4) (3)(5) * (6) (4) (2)

Tamb

Ttrip(l) − Thys

Ttrip(u) − Thys

Tth(crit) − Thys

Ttrip(u) − Thys

Ttrip(l) − Thys

Table 3. EVENT output condition

Figure

note EVENT output boundary

conditions EVENT outpu t Temperature Register Status bits

Comparator

mode Interrupt

mode Critical Temp

only mode Bit 15

Above

Critical

Trip

Bit 14

Above

Alarm

Window

Bit 13

Below

Alarm

Window

(1) Tamb ≥Ttrip(l) HLH000

(2) Tamb < Ttrip(l) − Thys LLH001

(3) Tamb > Ttrip(u) LLH010

(4) Tamb ≤ Ttrip(u) − Thys HLH000

(5) Tamb ≥Tth(crit) LLL110

(6) Tamb < Tth(crit) − Thys LHH010

Product data sheet Rev. 07 — 29 January 2010 10 of 55

NXP Semiconductors SE97

DDR memory module temp sensor with integrated SPD, 3.3 V

7.3.2 EVENT thresholds

7.3.2.1 Alarm window

The device provides a comparison window with an UPPER trip point and a LOWER trip

point, programmed through the Upper Boundary Alarm Trip register (02h), and Lower

Boundary Alarm Trip register (03h). The Upper Boundary Alarm Trip register holds the

upper temperature tr ip point, while the Lower Boundary Alarm T rip register holds the lower

temperature trip point as modified by hysteresis as programmed in the Configuration

above or below) the alarm window.

•Advisory note:

–NXP Device: The EVENT output can be cleared through the Clear EVENT bit

(CEVNT) or SMBus ALERT.

–Competitor Device: The EVENT output can be cleared only through the

Clear EVENT bit (CEVNT).

–Work-around: Only clear EVENT output using the Clear EVENT bit (CEVNT).

–There will be no change to NXP devices.

The Upper Boundary Alarm Trip should always be set above the Lower Boundary Alarm

Trip.

•Advisory note:

–NXP device: Requires one conversion cycle (125 ms) after setting the alarm

window before comparing the alarm limit with temperature register to ensure that

there is correct data in the temperature register before comparing with the Alarm

Window and operating EVENT output.

–Competitor devices: Compares the alarm limit with temperature register at any

time, so they get the EVENT output immediately when new UPPER or LOWER

Alarm Windows and the EVENT output are set at the same time.

–Work-around: Wait at least 125 ms before enabling EVENT output (EOCTL = 1).

–SE97B will compare alarm window and temperature register immediately.

7.3.2.2 Critical trip

The Tth(crit) temperature setting is programmed in the Cr itical Alarm Trip register (04h) as

modified by hysteresis as programmed in the Configuration register. When the

temperature reaches the critical temperature value in this register (and EVENT is

enabled), the EVENT output asserts and canno t be de-asserted until the temperature

drops below the critical temperature threshold. The Event cannot be cleared through the

Clear EVENT bit (CEVNT) or SMBus ALERT.

The Critical Alarm Trip should always be set above the Upper Boundary Alarm Trip.

•Advisory note:

–NXP device: Requires one conversion cycle (125 ms) after setting the Alarm

Window before comparing the alarm limit wi th temperature register to ensure that

there is correct data in the temperature register before comparing with the Alarm

Window and operating EVENT output.

Product data sheet Rev. 07 — 29 January 2010 11 of 55

NXP Semiconductors SE97

DDR memory module temp sensor with integrated SPD, 3.3 V

–Competitor devices: Compares the Alarm Window with temperature register at any

time, so they get the EVENT output immediately when new Tth(crit) and EVENT

output are set at the same time.

–Work-around: Wait at least 125 ms before enabling EVENT output (EOCTL = 1).

Intel will change Nehalem BIOS so that Tth(crit) is set for more than 125 ms before

EVENT output is enabled and Event value is checked.

1. Set Tth(crit).

2. Doing something else (make sure that exceeds 125 ms).

3. Enable the EVENT output (EOCTL = 1).

4. Wait 20 μs.

5. Read Event value.

–SE97B will compare alarm window and temperature register immediately.

7.3.3 EVENT operation modes

7.3.3.1 Co m parator mode

In comparator mode, the EVENT output behaves like a window-comparator output that

asserts when the temperature is out side the window (e.g., above the value programmed in

the Upper Boundary Alarm Trip register or below the value programmed in the Lower

Boundary Alarm Trip register or above the Critical Alarm Trip resister if Tth(crit) only is

selected). Reads/writes on the registers do not affect the EVENT output in comparator

mode. The EVENT signal rem ains asserted until the temperature goes insid e the alarm

window or the window thresholds are repr ogrammed so that the current temperature is

within the alarm window.

The comparator mode is useful for thermostat-type applications, such as turning on a

cooling fan or triggering a system shutdown when the temperature exceeds a safe

operating range.

7.3.3.2 Interrupt mode

In interrupt mode, EVENT asserts whenever the tempe rature crosses an alarm window

threshold. After such an event occurs, writing a 1 to the Clear EVENT bit (CEVNT) in the

configuration register de-asserts the EVENT output until the next trigger condition occurs.

In interrupt mode, EVENT asserts when the temperature crosses the alarm upper

boundary. If the EVENT output is cleared and the temperature continues to increase until

it crosses the critical temperature threshold, EVENT asserts again. Because the

temperature is greater than the critical temperature threshold, a Clear EVENT command

does not clear the EVENT output. Once the temperature drops below the critical

temperature, EVENT de-asserts immediately.

•Advisory note:

–NXP device: If the EVENT output is not cleared before the temper ature goes

above the critical temperature threshold EVENT de-asserts immediately when

temperature drops below the critical temperature.

–Competitor devices: If the EVENT output is not cleared before or when the

temperature is in the critical temperature threshold, EVENT will remain asserted

after the temperature drop s below the critical temperature until a Clear EVENT

command.

Product data sheet Rev. 07 — 29 January 2010 12 of 55

NXP Semiconductors SE97

DDR memory module temp sensor with integrated SPD, 3.3 V

–Work-around: Always clear the EVENT output befor e tem p er a tur e exce ed s the

critical temperature.

–SE97B will keep EVENT asserted after the temperature drops below the critical

temperature until a Clear EVENT command de-asserts EVENT.

7.4 Conversion rate

The conversion time is the amount of time required for the ADC to complete a

temperature measurement for the local temperature sensor. The conversion rate is the

inverse of the conversion period which describes the number of cycles the temperature

measurement completes in one second—the faster the conversion rate, the faster the

temperature reading is updated. The SE97’s conversion rate is at least 8 Hz or 125 ms.

7.4.1 What temperature is read when conversion is in progress

The SE97 has been designed to ensure a valid temperature is always available. When a

read to the temperature register is initia ted through the SMBus, the device checks to see if

the temperature con version process (Analog-to-Digit al conversion) is complete and a new

temperature is available:

•If the temperature conversion process is complete, then th e new temperature value is

sent out on the SMBus.

•If the temperature conversion process in not complete, then the previous temperature

value is sent out on the SMBus.

It is possible that while SMBus Master is reading th e tem p er a tur e reg iste r, a new

temperature conversion completes. However, this will not affect the dat a (MSB or LSB)

that is being shifted out. On the next read of the temperature register, the new

temperature value will be shifted out.

7.5 Power-up default condition

After power-on, the SE97 is initialized to the following default condition:

•Starts monitoring local sensor

•EVENT register is cleared; EVENT output is pulled HIGH by external pull-ups

•EVENT hysteresis is defaulted to 0 °C

•Command pointer is defaulte d to ‘00h’

•Critical Temp, Alarm Temperature Upper and Lower Boundary Trip register are

defaulted to 0 °C

•Capability register is defaulted to ‘0017h’ for the B grade

•Operational mode: comparator

•SMBus register is defaulted to ‘00h’

7.6 Device initialization

SE97 temperature sensors have programmable registers, which, upon power-up, default

to zero. The open-drain EVENT output is default to being disabled, comp arator mode and

active LOW. The alarm trigge r re gis te rs de fa ul t to being unprotected. The configuration

registers, upper and lower alarm boundary registers and critical temperature window are

defaulted to zero and need to be programmed to the desired values. SMBus TIMEOUT

Product data sheet Rev. 07 — 29 January 2010 13 of 55

NXP Semiconductors SE97

DDR memory module temp sensor with integrated SPD, 3.3 V

feature default s to being enable d and ca n be pr ogramme d to disa ble. These registe rs are

required to be initialized before the device can properly function. Except for the SPD,

which does not have any programmable register s, and does not need to be initialized.

Table 4 shows the default values and the example value to be programmed to these

registers.

7.7 SMBus time-out

The SE97 supports SMBus time-out feature. If the host holds SCL LOW between 25 ms

and 35 ms, the SE97 would reset its internal state machine to the bus IDLE state to

prevent the system bus hang-up. This feature is turned on by default. The SMBus time-out

is disabled by writing a ‘1’ to bit 7 of register 22h.

Remark: When SMBus time -out is enab led, the I2C- bus m inimum bu s speed is limited by

the SMBus time-out specification limit of 10 kHz.

The SE97 has no SCL driver, so it cannot hold the SCL line LOW.

Remark: SMBus time-out works over the entire supply range of 1.7 V to 3.6 V unless the

shutdown bit (SHMD) is set and turns off the oscillator.

7.8 SMBus ALERT Response Address (ARA)

The SE97 supports SMBus ALERT when it is programmed for the Interrupt mode and

when the EVENT polarity bit is set to ‘0’. The EVENT pin can be ANDed with other

EVENT or interrupt signals from other slave devices to signal their intention to

communicate with the host controller. When the host detects EVENT or other interrupt

signal LOW, it issues an ARA to which a slave device would respon d with its address.

When there are multiple slave devices generating an ALERT the SE97 performs bus

arbitration with the other slaves. If it wins the bus, it responds to the ARA and then clears

the EVENT pin.

Remark: Either in comparator mode or when the SE97 crosses the critical temperature,

the host must also read the EVENT status bit and provide remedy to the situation by

bringing the temperature to within the alarm window or below the critical temperature if

that bit is set. Otherwise, the EVENT pin will not get de-asserted.

Remark: In the SE97 the ARA is set to default ON. However, in the SE97B the ARA will

be set to default OFF since ARA is not anticipated to be used in DDR3 DIMM applications.

Table 4. Registers to be initialized

01h 0000h 0209h Configuration register

•hysteres is = 1. 5 °C

•EVENT output = Interrupt mode

•EVENT output is enabled

02h 0000h 0550h Upper Boundary Alarm Trip register = 85 °C

03h 0000h 1F40h Lower Boundary Alarm Trip register = −20 °C

04h 0000h 05F0h Critical Alarm Trip register = 95 °C

22h 0000h 0000h SMBus register = no change

Product data sheet Rev. 07 — 29 January 2010 14 of 55

NXP Semiconductors SE97

DDR memory module temp sensor with integrated SPD, 3.3 V

7.9 SMBus/I2C-bus interface

The data registers in this device are selected by th e Pointer register. At power-up, the

Pointer register is set to ‘00h’, the location for the Capability register. The Pointer register

latches the last location to which it was set. Each data register falls into one of three types

of user accessibility:

•Read only

•Write only

•Write/Read same address

A ‘write’ to this device will always include the address byte and the pointer byte. A write to

any register other than the Pointer reg ister requires two data bytes.

Reading this dev ice ca n take place eithe r of two ways:

•If the location latched in the Pointer register is correct (most of the time it is expected

that the Pointer register will point to one of the Temperature register (as it will be the

data mo st frequently read), then the read can simply consist of an address byte,

followed by retrieving the two data bytes.

•If the Pointer register needs to be set, then an address byte, pointer byte,

repeat START, and another address byte will accomplish a read.

The data byte has th e most significant bit first. At the end of a re ad, th is device can accept

either Acknowledg e (ACK) or No Acknowledge (NACK) fro m the Master (No Acknowledge

is typically used as a signal for the slave that the Master has read its last byte). It takes

this device 125 ms to measure the temperature. Refer to timing diagrams Figure 10 to

Figure 13 for how to program the devic e.

Fig 9. How SE97 responds to SMBus ALERT Response Address

0 0 0 1 1 A2

Alert Response Address

1 1 0 0S 0 0 0

START bit read acknowledge

002aac685

A1 A0 0 1 P

device address

no acknowledge STOP bit

host NACK and

sends a STOP bit

Slave acknowledges and

sends its slave address.

The last bit of slave address

is hard coded '0'.

master sends a START bit,

ARA and a read command

host detects

SMBus ALERT

A = ACK = Acknowledge bit. W = Write bit = 0. R = Read bit = 1.

Fig 10. SMBus/I2C-bus write to the Pointer register

123456789123456789

SCL

A6 A5 A4 A3 A2 A1 A0

SDA D7 D6 D5 D4 D3 D2 D1 D0

device address and write register address

WAS

START ACK

by device

STOP

ACK

by device

002aab30

Product data sheet Rev. 07 — 29 January 2010 15 of 55

NXP Semiconductors SE97

DDR memory module temp sensor with integrated SPD, 3.3 V

A = ACK = Acknowledge bit. W = Write bit = 0. R = Read bit = 1.

Fig 11. SMBus/I2C-bus write to the Pointer register followed by a write data word

123456789123456789

SCL

A6 A5 A4 A3 A2 A1 A0

SDA D7 D6 D5 D4 D3 D2 D1 D0

device address and write write register address

WAS

START

by host

ACK

by device

ACK

by device

(cont.)

002aab412

123456789123456789

SCL

D15 D14 D13 D12 D11 D10 D9

SDA D7 D6 D5 D4 D3 D2 D1 D0

most significant byte data least significant byte data

by host ACK

by device

STOP

by host

ACK

by device

A = ACK = Acknowledge bit. A = NACK = No Acknowledge bit. W = Write bit = 0. R = Read bit = 1.

Fig 12. SMBus/I2C-bus write to Pointer register followed by a repeated START and an immediate data word read

123456789123456789

SCL

A6 A5 A4 A3 A2 A1 A0

SDA D7 D6 D5 D4 D3 D2 D1 D0

device address and write read register address

WAS

START

by host

ACK

by device

ACK

by device

(cont.)

123456789

D15 D14 D13 D12 D11 D10 D9 D8

returned most significant byte data

ACK

by host

SCL

SDA

123456789

SCL

A6 A5 A4 A3 A2 A1 A0

SDA

device address and read

RASR

repeated

START

by host

ACK

by device

(cont.)

002aac686

123456789

D7 D6 D5 D4 D3 D2 D1 D0

returned least significant byte data

STOP

by host

NACK

by host

Product data sheet Rev. 07 — 29 January 2010 16 of 55

NXP Semiconductors SE97

DDR memory module temp sensor with integrated SPD, 3.3 V

A = ACK = Acknowledge bit. A = NACK = No Acknowledge bit. W = Write bit = 0. R = Read bit = 1.

Fig 13. SMBus/I2C-bus word read from register with a pre-set pointer

123456789

D15 D14 D13 D12 D11 D10 D9 D8

returned most significant byte data

ACK

by host

SCL

SDA

123456789

SCL

A6 A5 A4 A3 A2 A1 A0

SDA

device address and read

ACK

by device

(cont.)

002aac68

123456789

D7 D6 D5 D4 D3 D2 D1 D0

returned least significant byte data

STOPNACK

by host

START

by host

Product data sheet Rev. 07 — 29 January 2010 17 of 55

NXP Semiconductors SE97

DDR memory module temp sensor with integrated SPD, 3.3 V

7.10 EEPROM operation

The 2-kbit EEPROM is organized as either 256 bytes of 8 bits each (byte mode), or

16 pages of 16 bytes each (page mode). Accessing the EEPROM in byte mode or page

mode is automatic; partial page write of 2 bytes, 4 bytes, or 8 bytes is also supported.

Communication with the EEPROM is via the 2-wire serial I2C-bus or SMBus. Figure 14

provides an overview of the EEPROM partitioning.

The EEPROM can be read over voltage range 1.7 V to 3.6 V, but all write operations must

be done 3.0 V to 3.6 V.

7.10.1 Write operations

7.10.1.1 Byte Write

In Byte Write mode the master creates a START condition and then br oadcasts the slave

address, byte address, and data to be written. The slave acknowledges all 3 bytes by

pulling down the SDA line during the ninth clock cycle following each byte. The master

creates a STOP condition after the last ACK from the slave, which then starts the internal

write operation (see Figure 15). During internal write, the slave will ignore any read/write

request from the master.

Fig 14. EEPROM partitioning

FFh

80h

7Fh

0Fh

00h

00h 01h 07h

…

1 page

or 16 bytes

8 pages or

128 bytes

16 pages or

256 bytes

no write protect

write protect

by software

002aac81

Fig 15. Byte Write timing

002aab246

0 1 0 A2 A1 A0 0 AS 1 A P

slave address (memory)

START condition R/W acknowledge

from slave

acknowledge

from slave

word address

SDA

STOP condition;

write to the memory is performed

data

DATA A

acknowledge

from slave

Product data sheet Rev. 07 — 29 January 2010 18 of 55

NXP Semiconductors SE97

DDR memory module temp sensor with integrated SPD, 3.3 V

7.10.1.2 Page Write

The SE97 cont ains 256 bytes of dat a, arranged in 1 6 pages of 16 bytes each. The page is

selected by the four Most Significant Bits (MSB) of the address byte presented to the

device after the slave address, while the four Least Significant Bit s (LSB) point to the byte

within the page. By loading more than one data byte into the device, up to an entire page

can be written in one write cycle (see Figure 16). The internal byte address counter will

increment automatically after each data byte. If the master transmits more than

16 data bytes, then earlier bytes will be overwritten by later bytes in a wrap-around

fashion within the selected page. The internal write cycle is started following the STOP

condition created by the master.

7.10.1.3 Acknowledge polling

Acknowledge polling can be used to determine if the SE97 is busy writing or is ready to

accept commands. Polling is implemented by se nding a ‘Selectiv e Read’ command

(described in Section 7.10.3 “Read operations”) to the device. The SE97 will not

acknowledge the slave address as long as internal write is in progress.

7.10.2 Memory protection

The lower half (the first 128 bytes) of the memory can be write protected by special

EEPROM commands without an external control pin. The SE97 features three types of

memory write pr ot ec tion inst ru ctio n s, and three respective read Protection instructions.

The level of write-protection (set or clear) that has been defined using these instructions

remained defined even after power cycle.

The memory protection commands are:

•Permanent Write Protection (PWP)

•Reversible Write Protection (RWP)

•Clear Write Protection (CWP)

•Read Permanent Write Protection (RPWP)

•Read Reversible Write Protection (RRWP)

•Read Clear Write Protection (RCWP)

Fig 16. Page Wr ite timing

0 1 0 A2 A1 A0 0 AS 1 A

slave address (memory)

START condition R/W acknowledge

from slave

acknowledge

from slave

word address

SDA

data to memory

DATA n A

acknowledge

from slave

002aab247

STOP condition;

write to the memory is performed

data to memory

DATA n + 15 A

acknowledge

from slave

Product data sheet Rev. 07 — 29 January 2010 19 of 55

NXP Semiconductors SE97

DDR memory module temp sensor with integrated SPD, 3.3 V

Table 5 is the summary for normal and memory protection instructions.

[1] The most significant bit, bit 7, is sent first.

[2] A0, A1, and A2 are compared against the respective external pins on the SE97.

[3] VI(ov) ranges from 7.8 V to 10 V.

This special EEPROM command consists of a unique 4-bit fixed a ddr ess (0110b) and the

voltage level applied on the 3-bit hardware address. Normally, to address the memory

array, the 4-bit fixed address is ‘1010b’. To access the memory protection settings, the

4-bit fixed address is ‘0110b’. Figure 17 and Figure 18 show the write and rea d protectio n

sequence, respectively.

Up to eight memory devices can be connected on a single I2C-bus. Each one is given a

3-bit on the hardware selectable address (A2, A1, A0) inputs. The device only responds

when the 4-bit fixed and hardware selectable bits are matched. The 8th bit is the

read/write bit. This bit is set to 1 or 0 for read and write protection, re spectively.

The corresponding de vice acknowledges during the ninth bit time when there is a match

on the 7-bit address.

The device does not acknowledge when there is no match on the 7-bit address or whe n

the device is already in permanent write protection mode and is programmed with any

write protection instructions (i.e., PWP, RWP, CWP).

Table 5. EEPROM commands summary

Command Fixed address Hardware selectable

address R/W

Bit 7[1] Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Normal EEPROM read/write 1010A2A1A0R/W

Reversible Write Protection (RWP) 0110V

SS VSS VI(ov)[3] 0

Clear Reversible Write Protection (CRWP)0110V

SS VDD VI(ov)[3] 0

Permanent Write Protection (PWP)[2] 0110A2A1A00

Read RWP 0110V

SS VSS VI(ov)[3] 1

Read CRWP 0110V

SS VDD VI(ov)[3] 1

Read PWP 0110A2A1A01

X = Don’t Care

(1) Refer to Table 6 regarding the exact state of the acknowledge bit.

Fig 17. Software Write Protect (write)

1 1 0 A2 A1 A0 0 AS 0 A

slave address (memory)

START condition R/W acknowledge(1)

from slave

acknowledge(1)

from slave

dummy byte address

SDA

dummy data

acknowledge(1)

from slave

002aab356

STOP condition

XXXXXXXX XXXXXXXX

Product data sheet Rev. 07 — 29 January 2010 20 of 55

NXP Semiconductors SE97

DDR memory module temp sensor with integrated SPD, 3.3 V

7.10.2.1 Permanent Write Protection (PWP)

If the software write-protection has been set with the PWP instruction, the first 128 bytes

of the memory ar e pe r ma n en tly writ e- pr otected. This write-protection cannot be cleared

by any instruction, or by pow er-cycling the device. Also , onc e the PWP inst ru ctio n ha s

been successfully executed, the device no longer acknowledges any instruction (with 4-bit

fixed address of 0110b) to access the write-protection settings.

7.10.2.2 Re ve rsi bl e Write Protec ti on (RWP) and Clea r Reversi b le Write Prot ec ti on (CRWP)

If the software write-protection has been set with the RWP instruction, it can be cleared

again with a CRWP instruction.

The two instructions, RWP and CRWP have the same format as a Byte Write instruction,

but with a different setting for the hardware address pins (as shown in Table 5). Like the

Byte Write instruction, it is followed by an address byte and a data byte, but in this case

the contents are all ‘Don’t Care’ (Figure 17). Another difference is that the voltage, VI(ov),

must be applied on the A0 pin, and specific logical levels must be applie d on the other two

(A1 and A2), as shown in Table 5.

X = Don’t Care

(1) Refer to Table 7 regarding the exact state of the acknowledge bit.

Fig 18. Software Write Protect (r ea d)

1 1 0 A2 A1 A0 1 AS 0 A

slave address (memory)

START condition R/W acknowledge(1)

from slave

no acknowledge(1)

from slave

dummy byte address

SDA

dummy data

no acknowledge(1)

from slave

002aac644

STOP condition

XXXXXXXX XXXXXXXX

Table 6. Acknowledge whe n writing data or defining write protection

Instructions with R/W bit = 0.

Status Instruction ACK Address ACK Data byte ACK Write cycle

(Tcy(W))

Permanently

protected PWP, RWP or CRWP NACK not significant NACK not significant NACK no

page or byte write in

lower 128 bytes ACK address ACK data NACK no

Protected wit h

RWP RWP NACK not significant NACK not significant NACK no

CRWP ACK not significant ACK not significant ACK yes

PWP ACK not significant ACK not significant ACK yes

page or byte write in

lower 128 bytes ACK address ACK data NACK no

Not protected PWP or RWP ACK not significant ACK not significant ACK yes

CRWP ACK not significant ACK not significant ACK no

page or byte write ACK address ACK data ACK yes

Product data sheet Rev. 07 — 29 January 2010 21 of 55

NXP Semiconductors SE97

DDR memory module temp sensor with integrated SPD, 3.3 V

7.10.2.3 Read Permanent Write Protection (RPWP), Read Reversible Write Protection

(RRWP), and Read Clear Reversible Write Protection (RCRWP)

Read PWP, RWP, and CRWP allow the SE97 to be read in write protection mode. The

instruction format is the same as that of the write protection except that the 8th bit, R/W, is

set to 1. Figure 18 shows th e instruction format, wh ile Table 7 shows the responses when

the instructions are issued.

7.10.3 Read operations

7.10.3.1 Current address read

In Standby mode, the SE97 internal address counter points to the data byte immediately

following the last byte accessed by a previous operation. If the ‘previous’ byte was the last

byte in memory, then the address counter will point to the first memory byte, and so on. If

the SE97 decodes a slave address with a ‘1’ in the R/W bit position (Figure 19), it will

issue an Acknowledge in the ninth clock cycle and will then transmit the data byte being

pointed at by the address counter. The master can then stop further transmission by

issuing a No Acknowledg e on the nint h bit th en follo we d by a STOP condition.

7.10.3.2 Selective read

The read operation can also be started at an address different from the one stored in the

address counter. The address counter can be ‘initialized’ by performing a ‘dummy’ write

operation (Figure 20). The START condition is followed by th e slave address (with the

R/W bit set to ‘0’) and the desired byte address. Instead of following-up with data, the

master then issues a second START, followed by the ‘Current Address Read’ sequence,

as described in Section 7.10.3.1.

Table 7. Acknowledge when reading the write protection

Instructions with R/W bit = 1.

Status Instruction ACK Address ACK Data byte ACK

Permanently

protected RPWP, RRWP or

RCRWP NACK not significant NACK not significant NACK

Protected wit h

RWP RRWP NACK not significant NACK not significa nt NACK

RCRWP ACK not significant NACK not significant NACK

RPWP ACK not significant NACK not significant NACK

Not protected RPWP, RRWP or

RCRWP ACK not significant NACK not significant NACK

Fig 19. Current address read timing

0 1 0 A2 A1 A0 1 AS 1

slave address (memory)

START condition R/W acknowledge

from slave

data from memory

SDA

002aab251

STOP condition

no acknowledge

from master

Product data sheet Rev. 07 — 29 January 2010 22 of 55

NXP Semiconductors SE97

DDR memory module temp sensor with integrated SPD, 3.3 V

7.10.3.3 Sequential read

If the master acknowledges the first data byte transmitted by the SE97, then the device

will continue transmitting as long as each data byte is acknowledged by the master

(Figure 21). If the end of memory is reached during seq uential Read, the address coun ter

will ‘wrap around’ to the beginning of memory, and so on. Sequential Read works with

either ‘Immediate Address Read’ or ‘Selective Read’, the only difference bein g the starting

byte address.

Fig 20. Selective read timin g

0 1 0 A2 A1 A0 0 AS 1 A

slave address (memory)

START condition R/W acknowledge

from slave

acknowledge

from slave

word address

SDA

002aac901

STOP condition

data from memory

no acknowledge

from master

0 1 0 A2 A1 A0S 1

slave address (memory)

START condition

1 A

R/W acknowledge

from slave

Fig 21. Sequential read timing

0 1 0 A2 A1 A0 1 AS 1 A

slave address (memory)

START condition R/W acknowledge

from slave

acknowledge

from master

data from memory

SDA

data from memory

DATA n + 1 A

acknowledge

from master

002aab253

STOP condition

data from memory

DATA n + X A

no acknowledge

from master

DATA n

Product data sheet Rev. 07 — 29 January 2010 23 of 55

NXP Semiconductors SE97

DDR memory module temp sensor with integrated SPD, 3.3 V

7.11 Hot plugging

The SE97 can be used in ho t plugg i ng ap plications. Inte rn al circ uit ry pr ev en ts damag ing

current backflow through the device when it is powered down, but with the I2C-bus,

EVENT or address pins still connected. The open-drain SDA and EVENT pins (SCL and

address pins are input only) effectively places the outputs in a high-impedance state

during power-up and power-down, which prevents driver conflict an d bus contention. The

50 ns noise filter will filter out any insertion glitches from the state machine, which is very

robust and not prone to false operation.

The device needs a proper power-up sequence to reset itself, not only for the device

I2C-bus and I/O initial states, but also to load specific pre-defined data or calibration data

into its op erational registers. The power-up sequence should occur correctly with a fast

ramp rate and the I2C- bus active. The SE97 might not respond immediately after

power-up, but it should not damage the part if the power-up sequence is abnormal. If the

SCL line is held LOW, the part will not exit the power-on reset mode since the part is held

in reset until SCL is released.

8. Register descriptions

8.1 Register overview

This section describes all the registers used in the SE97. The registers are used for

latching the temperature reading, storing the low and high temperature limit s, configuring,

the hysteresis threshold and the ADC, as well as reporting status. The device uses the

pointer register to access these registers. Read registers, as the name implies, are used

for read only, and the write registers are for write only. Any attempt to read from a

write-only register will result in reading ‘0’s. Writing to a read-only register will have no

effect on the read even though the write command is acknowledged. The Pointer register

is an 8-bit register. All other registers are 16-bit.

A write to reserved registers my cause une xpected results which may result in requiring a

reset by removing and re-applying its power.

Table 8. Regis t er summary

Address (hex) Default state (hex) Register name

n/a n/a Pointer register

00h 0017h Capability register (B grade = 0017h)

01h 0000h Configuration register

02h 0000h Upper Boundary Alarm Trip register

03h 0000h Lower Boundary Alarm Trip register

04h 0000h Critical Alarm Trip register

05h n/a Temperature register

06h 1131h Manufacturer ID register

07h A200h Device ID/Revision register for SE97PW, SE97TK

A201h Device ID/Revision register for SE97TP, SE97TL

08h to 21h 0000h reserved registers

22h 0000h SMBus register

23h to FFh 0000h reserved registers

Product data sheet Rev. 07 — 29 January 2010 24 of 55

NXP Semiconductors SE97

DDR memory module temp sensor with integrated SPD, 3.3 V

8.2 Capability register (00h, 16-bit read-only)

[1] The SE97 A0 pin can support up to 10 V, but the final die was already taped out before the JC42.4 ballot 1435.00 register change could

be implemented. Bit 5 is changed from ‘0’ to ‘1’ on the future 1.7 V to 3.6 V SE97B.

Table 9. Capability register (address 00h) bit allocatio n

Bit 15 14 13 12 11 10 9 8

Symbol RFU

Default 00000000

Access RRRRRRRR

Bit 7 6 5 4 3 2 1 0

Symbol RFU VHV TRES WRNG HACC BCAP

Default 000

[1] 10111

Access RRRRRRRR

Table 10. Capability register (address 00h) bit description

Bit Symbol Description

15:6 RFU Reserved for future use; must be zero.

5 VHV High voltage standoff for pin A0.

0 — default

1 — This part can support a voltage up to 10 V on the A0 pin to

support JC42.4 ballot 1435.00.

4:3 TRES Temperature resol ution.

10 — 0.125 °C LSB (11-bit)

2 WRNG Wider range.

1 — can read temperatures below 0 °C and set sign bit accordingly

1 HACC Higher accuracy (set during manufacture).

1 — B grade accuracy

0 BCAP Basic capability.

1 — has Alarm and Critical Trips interrupt capability

Product data sheet Rev. 07 — 29 January 2010 25 of 55

NXP Semiconductors SE97

DDR memory module temp sensor with integrated SPD, 3.3 V

8.3 Configuration register (01h, 16-bit read/write)

Table 11. Configuration register (address 01h) bit allocation

Bit 15 14 13 12 11 10 9 8

Symbol RFU HEN SHMD

Default 00000000

Access RRRRRR/WR/WR/W

Bit 7 6 5 4 3 2 1 0

Symbol CTLB AWLB CEVNT ESTAT EOCTL CVO EP EMD

Default 00000000

Access R/W R/W R/W R/W R/W R/W R/W R/W

Table 12. Configuration register (address 01h) bit descriptio n

Bit Symbol Description

15:11 RFU reserved for future use; must be ‘0’.

10:9 HEN Hysteresis Enable.

00 — disable hysteresis (default)

01 — enable hysteresis at 1.5 °C

10 — enable hysteresis at 3 °C

11 — enable hysteresis at 6 °C

When enabled, hysteresis is applied to temperature movement around trigger

points. For example, consider the behavior of the ‘Above Alarm Window’ bit

(bit 14 of the Temperature register) when the hysteresis is set to 3 °C. As the

temperature rises, bit 14 will be set to ‘1’ (temperature is above the alarm

window) when the Temperature register contains a value that is greater than the

value in the Alarm Temperature Upper Boundary register. If the temperature

decreases, bit 14 will remain set unti l the measured temperature is less than or

equal to the value in the Alarm Temperature Upper Bounda ry register minus

3°C. (Refer to Figure 8 and Table 13).

Similarly, the ‘Below Alarm Window’ bit (bit 13 of the Temperature register) will

be set to ‘0’ (temperature is equal to or above the Alarm Window Lower

Boundary Trip register) when the value in the Temperature register is equal to or

greater than the value in the Alarm Tempe r ature Lower Boundary register. As

the temperature decreases, bit 13 will be set to ‘1’ when the value in the

Temperature register is equal to or less than the value in the Alarm Temperature

Lower Boundary register minus 3 °C. Note that hysteresis is also applied to

EVENT pin functionality.

When either of the Critical Trip or Alarm Window lock bits is set, these bits

cannot be altered until unlocked.

Product data sheet Rev. 07 — 29 January 2010 26 of 55

NXP Semiconductors SE97

DDR memory module temp sensor with integrated SPD, 3.3 V

8 SHMD Shutdown Mode.

0 — enabled Temperature Sensor (default)

1 — disabled Temperature Sensor

When shut down, the thermal sensor diode and ADC are disa bled to save

power, no events will be generated. Wh en either of the Critical Trip or Alarm

Window lock bits is set, this bit cannot be set until unlocked. However, it can be

cleared at any time.

Remark: SMBus Time-out works over the entire supply range of 1.7 V to 3.6 V

unless the shutdown bit (SHMD) is set and turns off the oscillator.

•The EEPROM read works over the entire supply range of 1.7 V to 3.6 V

whether or not SHMD is set because it does not need oscillator to function.

There is no undervoltage lockout, the device no longer responds at some

voltage below 1.7 V.

•EEPROM write works over the supply range of 3.0 V to 3.6 V, but not if

SHMD is set since the oscillator is needed to write to EEPROM. There is an

undervoltage lockout around 2.7 V that disables the RRPROM write

operation.

•Thermal sensor is operational over the supply range of 3.0 V to 3.6 V, but

not if SHMD is set since the oscillator is needed. There is an undervoltage

lockout around 2.7 V that disables the temp sensor.

Thermal sensor auto turn-off feature:

It was determined during testing of the SE97TP on 5 May 2008 that the Thermal

Sensor auto turn-off feature was not compatible with the JEDEC power supply

maximum ramp rate of 70 ms to 100 ms (slowest ramp rate) and this feature was

disabled for all SE97 samples/production devices tested after 6 May (wk 0818

date code is when the devices were assembled).

If there is a slow ramp rate on the supply voltage to 3.3 V the SE97 would be EE

read only and not Thermal Sensor. This is due to a feature integrated into the

device to automatically turn off the oscillator and place the thermal sensor in

shutdown if the SE97 was being used in SO-DIMM in notebook applications at

1.8 V to reduce the power consumption on the battery. The feature count s for

30 ms (±5 ms) after the oscillator starts working (around 1.2 V to 1.7 V) and if at

30 ms the voltage is greater than 2.4 V, the oscillator is left on and the Thermal

Sensor functions as normal. But if the voltage is less than 2.4 V at 30 ms, the

oscillator is turned off and the SE97 will think the part is in SPD only mode

defaulting to the oscillator and Thermal Sensor disabled (SHMD Shutdown

Mode bit 8 = 1). The oscillator and Thermal Sensor can be re-enabled by writing

a logic 0 to SHMD. It is important in RDIMM/server applications that the Thermal

Sensor is working as the default condition since the Thermal Sensor needs to be

compatible with the JEDEC power supply ramp rate (maximum ramp rate is

70 ms to 100 ms) so the Thermal Sensor auto turn-off feature was disabled

starting on 6 May 2008 by changing a programmable bit on the device during

final test. There is no change in performance of the SE97 with this feature turned

off and was verified during characterization. There is no way to read the SE97

registers via the I2C-bus to determine if the Thermal Sensor auto turn-off feature

is enabled or disabled. This is set in a factory only register. You need to check

the date code or do an operational test (e.g., run up to < 2.4 V, hold, then go to

3.3 V, th en read SHMD bit 8 in the Configuration register to see if it is set to

logic 0 (e.g., oscillator running = feature disabled ) or logic 1 (e.g., oscillator

turned off = feature enabled)). The Thermal Sensor auto turn-off feature is active

in all package options prior to wk 0818. The SE97TP and SE97 TL were not yet

released to production so there is a clear line at release/orderable devices

versus samples with this feature disabled in all production devices.

Table 12. Configuration register (address 01h) bit descriptio n …continued

Bit Symbol Description

Product data sheet Rev. 07 — 29 January 2010 27 of 55

NXP Semiconductors SE97

DDR memory module temp sensor with integrated SPD, 3.3 V

7 CTLB Critical Trip Lock bit.

0 — Critical Alarm Trip register is not locked and can be altered (default)

1 — Critical Alarm Trip register settings cannot be altered

This bit is initially cleared. When set, this bit will return a ‘1’, and remains locked

until cleared by internal Power-on reset. This bit can be written with a single

write and do not require double writes.

6 AWLB Alarm Window Lock bit.

0 — Upper and Lower Alarm Trip registers are not locked and can be altered

(default)

1 — Upper and Lower Alarm Trip registers setting cannot be altered

This bit is initially cleared. When set, this bit will return a ‘1’ and remains locked

until cleared by internal power-on reset. This bit can be written with a single write

and does not require double writes.

5 CEVNT Clear EVENT (write only).

0 — no effect (default)

1 — clears active EVENT in Interrupt mode. Writing to this register has no

effect in Comparator mode.

When read, this register always returns zero.

4 ESTAT EVENT Status (read only).

0 — EVENT output condition is not being asserted by this device (default)

1 — EVENT output pin is being asserted by this device due to Alarm Window

or Critical Trip condition

The actual event causing the EVENT can be determined from the Read

Temperature register. Interrupt Events can be cleared by writing to the ‘Clear

EVENT’ bit (CEVNT). Writing to this bit will have no effect.

3 EOCTL EVENT Output Control.

0 — EVENT output disabled (default)

1 — EVENT output enabled

When either of the Critical Trip or Alarm Window lock bits is set, this bit cannot

be altered until unlocked.

2 CVO Critical Event Only.

0 — EVENT output on Alarm or Critical temperature event (d efault)

1 — EVENT only if temperature is above the value in the critical temperature

When the Critical Trip or Alarm Window lock bit is set, this bit cannot be altered

until unlocked.

•Advisory note:

–JEDEC specification requires only the Alarm Window lock bit to be set.

–Work-around: Clear both Critical Trip and Alarm Window lock bits.

–Future 1.7 V to 3.6 V SE97B will require only the Alarm Window lock bit

to be set.

1 EP EVENT Polarity.

0 — active LOW (default)

1 — active HIGH. When either of the Critical Trip or Alarm Window lock bit s is

set, this bit cannot be altered until unlocked.

Table 12. Configuration register (address 01h) bit descriptio n …continued

Bit Symbol Description

Product data sheet Rev. 07 — 29 January 2010 28 of 55

NXP Semiconductors SE97

DDR memory module temp sensor with integrated SPD, 3.3 V

0 EMD EVENT Mode.

0 — comparator output mode (default)

1 — interrupt mode

When either of the Critical Trip or Alarm Window lock bits is set, this bit cannot

be altered until unlocked.

Table 12. Configuration register (address 01h) bit descriptio n …continued

Bit Symbol Description

Table 13. Hysteresis enable

Action Below Alarm Window bit (bit 13) Above Alarm Window bit (bit 14) Above Critical Trip bit (bit 15)

Temperature

slope Threshold

temperature Temperature

slope Threshold

temperature Temperature

slope Threshold

temperature

sets falling Ttrip(l) −Thys rising Ttrip(u) rising Tth(crit)

clears rising Ttrip(l) falling Ttrip(u) −Thys falling Tth(crit) −Thys

Fig 22. Hysteresis: how it works

002aac799

current temperature

time

temperature

set clear

clear set clear

Below Alarm Window

(register 05h;

bit 13 = BAW bit)

Above Alarm Window

(register 05h;

bit 14 = AAW bit)

Above Critical Trip

(register 05h;

bit 15 = ACT bit)

lower alarm

threshold

upper alarm

threshold

critical alarm

threshold

hysteresis

Product data sheet Rev. 07 — 29 January 2010 29 of 55

NXP Semiconductors SE97

DDR memory module temp sensor with integrated SPD, 3.3 V

8.4 Temperature format

The temperature da ta from the temperature rea d back register is an 11-bit 2’s complement

word with the least significant bit (LSB) equal to 0.125 °C (resolution).

•A value of 019Ch will represent 25.75 °C

•A value of 07C0h will represent 124 °C

•A value of 1E64h will represent −25.75 °C.

The unused LSB (bit 0) is set to ‘0’. Bit 11 will have a resolution of 128 °C.

The upper 3 bits of the temperature register indicate Trip Status based on the current

temperature, and are not affected by the status of the EVENT output.

Table 14 lists the examples of the content of the temperatur e data register fo r positive and

negative temperature for two scenarios of status bits: status bits = 000b and

status bits = 111b.

Table 14. Degree Celsius and Temperature Data register

Temperature Content of Temperature Data register

Status bits = 000b Status bits = 111b

Binary Hex Binary Hex

+125 °C

000 0 01111101 000 0

07D0h

111 0 01111101 000 0

E7D0h

+25 °C

000 0 00011001 000 0

0190h

111 0 00011001 000 0

E190h

+1 °C

000 0 00000001 000 0

0010h

111 0 00000001 000 0

E010h

+0.25 °C

000 0 00000000 010 0

0004h

111 0 00000000 010 0

E004h

+0.125 °C

000 0 00000000 001 0

0002h

111 0 00000000 001 0

E002h

0°C

000 0 00000000 000 0

0000h

111 0 00000000 000 0

E000h

−0.125 °C

000 1 11111111 111 0

1FFEh

111 1 11111111 111 0

FFFEh

−0.25 °C

000 1 11111111 110 0

1FFCh

111 1 11111111 110 0

FFFCh

−1°C

000 1 11111111 000 0

1FF0h

111 1 11111111 000 0

FFF0h

−20 °C

000 1 11110100 000 0

1F40h

111 1 11110100 000 0

FF40h

−25 °C

000 1 11100111 000 0

1E70h

111 1 11100111 000 0

FE70h

−55 °C

000 1 11001001 000 0

1C90h

111 1 11001001 000 0

FC90h

Product data sheet Rev. 07 — 29 January 2010 30 of 55

NXP Semiconductors SE97

DDR memory module temp sensor with integrated SPD, 3.3 V

8.5 Temperature Trip Point registers

8.5.1 Upper Boundary Alarm Trip register (16-bit read/write)

The value is the upper threshold temperature value for Alarm mode. The data format is

2’s complement with bit 2 = 0.25 °C. ‘RFU’ bits will always report zero. Interrupts will

respond to the presently programmed boundary values. If boundary va lues are being

altered in-system, it is advised to turn off interrupts until a known st ate can be obtained to

avoid superfluous interrupt activity.

Table 15. Upper Boundary Alarm Trip register bit all ocation

Bit 15 14 13 12 11 10 9 8

Symbol RFU SIGN UBT

Default 00000000

Access R R R R/W R/W R/W R/W R/W

Bit 7 6 5 4 3 2 1 0

Symbol UBT RFU

Default 00000000

Access R/W R/W R/W R/W R/W R/W R R

Table 16. Upper Boundary Alarm Trip register bit description

Bit Symbol Description

15:13 RFU reserved; always ‘0’

12 SIGN Sign (MSB)

11:2 UBT Upper Boundary Alarm Trip Temperature (LSB = 0.25 °C)

1:0 RFU reserved; always ‘0’

Product data sheet Rev. 07 — 29 January 2010 31 of 55

NXP Semiconductors SE97

DDR memory module temp sensor with integrated SPD, 3.3 V

8.5.2 Lower Boundary Alarm Trip register (16-bit read/write)

The value is the lower threshold temperature value for Alarm mode. The data format is

2’s complement with bit 2 = 0.25 °C. RFU bits will always report zero. Interrupts will

respond to the presently programmed boundary values. If boundary va lues are being

altered in-system, it is advised to turn off interrupts until a known st ate can be obtained to

avoid superfluous interrupt activity.

8.5.3 Critical Alarm Trip register (16-bit read/write)

The value is the critical temperature. The data format is 2’s complement with

bit 2 = 0.25 °C. RFU bits will always report zero.

Table 17. Lower Boundary Alarm Trip register bit allocation

Bit 15 14 13 12 11 10 9 8

Symbol RFU SIGN LBT

Default 00000000

Access R R R R/W R/W R/W R/W R/W

Bit 7 6 5 4 3 2 1 0

Symbol LBT RFU

Default 00000000

Access R/W R/W R/W R/W R/W R/W R R

Table 18. Lower Boundary Alarm Trip register bit description

Bit Symbol Description

15:13 RFU reserved; always ‘0’

12 SIGN Sign (MSB)

11:2 LBT Lower Boundary Alarm Trip Temperature (LSB = 0.25 °C)

1:0 RFU reserved; always ‘0’

Table 19. Lower Boundary Alarm Trip register bit allocation

Bit 15 14 13 12 11 10 9 8

Symbol RFU SIGN CT

Default 00000000

Access R R R R/W R/W R/W R/W R/W

Bit 7 6 5 4 3 2 1 0

Symbol CT RFU

Default 00000000

Access R/W R/W R/W R/W R/W R/W R R

Table 20. Critical Alarm Trip reg ister bit description

Bit Symbol Description

15:13 RFU reserved; always ‘0’

12 SIGN Sign (MSB)

11:2 CT Critical Alarm Trip Temperature (LSB = 0.25 °C)

1:0 RFU reserved; always ‘0’

Product data sheet Rev. 07 — 29 January 2010 32 of 55

NXP Semiconductors SE97

DDR memory module temp sensor with integrated SPD, 3.3 V

8.6 Temperature register (16-bit read-only)

Table 21. Temperature register bit allocation

Bit 15 14 13 12 11 10 9 8

Symbol ACT AAW BAW SIGN TEMP

Default 00000000

Access RRRRRRRR

Bit 7 6 5 4 3 2 1 0

Symbol TEMP RFU

Default 00000000

Access RRRRRRRR

Table 22. Temperature register bit description

Bit Symbol Description

15 ACT Above Critical Trip.

Increasing Tamb:

0 — Tamb <T

th(crit)

1 — Tamb ≥Tth(crit)

Decreasing Tamb:

0 — Tamb <T

th(crit) −Thys

1 — Tamb ≥Tth(crit) −Thys

14 AAW Above Alarm Window.

Increasing Tamb:

0 — Tamb ≤Ttrip(u)

1 — Tamb >T

trip(u)

Decreasing Tamb:

0 — Tamb ≤Ttrip(u) −Thys

1 — Tamb >T

trip(u) −Thys

13 BAW Below Alarm Window.

Increasing Tamb:

0 — Tamb ≥Ttrip(l)

1 — Tamb <T

trip(l)

Decreasing Tamb:

0 — Tamb ≥Ttrip(l) −Thys

1 — Tamb <T

trip(l) −Thys

12 SIGN Sign bit.

0 — positive temperature value

1 — negative temperature value

11:1 TEMP Temperature Value (2’s complement). (LSB = 0.125 °C)

0 RFU reserved; always ‘0’

Product data sheet Rev. 07 — 29 January 2010 33 of 55

NXP Semiconductors SE97

DDR memory module temp sensor with integrated SPD, 3.3 V

8.7 Manufacturer’ s ID register (16-bit read-only)

The SE97 Manufacturer’s ID register is intended to match NXP Semiconductors PCI SIG

(1131h).

8.8 Device ID register

The SE97 device ID is A2h. The device revision varies by device.

[1] 00 for SE97PW, SE97TK (original) is 00h.

01 for SE97TL, SE97TP (improved VPOR and EVENT IOL) is 01h.

Table 23. Manufacturer’s ID register bit allocation

Bit 15 14 13 12 11 10 9 8

Symbol Manufacturer ID

Default 00010001

Access RRRRRRRR

Bit 7 6 5 4 3 2 1 0

Symbol (continued)

Default 00110001

Access RRRRRRRR

Table 24. Device ID register bit allocation

Bit 15 14 13 12 11 10 9 8

Symbol Device ID

Default 10100010

Access RRRRRRRR

Bit 7 6 5 4 3 2 1 0

Symbol Device revision

Default 000000[1] [1]

Access RRRRRRRR

Product data sheet Rev. 07 — 29 January 2010 34 of 55

NXP Semiconductors SE97

DDR memory module temp sensor with integrated SPD, 3.3 V

8.9 SMBus register

Table 25. SMBus Time-out register bit allocation

Bit 15 14 13 12 11 10 9 8

Symbol RFU

Default 0 0000000

Access R RRRRRRR

Bit 7 6543210

Symbol STMOUT RFU SALRT

Default 0 0000000

Access R/WRRRRRRR/W

Table 26. SMBus Time-out register bit description

Bit Symbol Description

15:8 RFU reserved; always ‘0’

7 STMOUT SMBus time-out.

0 — SMBus time-out is enabled (default)

1 — disable SMBus time-out

When eith er of the Crit i c al Trip or Alarm Window lock bits is set, this bit

cannot be alte red until unlocked.

6:1 RFU reserved; always ‘0’

0 SALRT SMBus ALERT Response Address (ARA).

0 — SMBus ARA is enabled (default)

1 — disable SMBus ARA

When eith er of the Crit i c al Trip or Alarm Window lock bits is set, this bit

cannot be alte red until unlocked.

Product data sheet Rev. 07 — 29 January 2010 35 of 55

NXP Semiconductors SE97

DDR memory module temp sensor with integrated SPD, 3.3 V

9. Application design-in information

In a typical application, the SE97 behaves as a slave device and interfaces to a bus

master (or host) via the SCL and SDA lines. The EVENT output is monitored by the host,

and asserts when the temperature reading exceeds the programmed values in the alarm

registers. The A0, A1 and A2 pins ar e directly connected to VDD or VSS without any pull-up

resistors. The SDA and SCL serial interface pins are open-drain I/Os that require pull-up

resistors, and are able to sink a maximum of 3 mA with a voltage drop less than 0.4 V.

T ypi cal pull-up values for SCL and SDA are 10 kΩ, but the resistor value s can be changed

in order to meet the rise time requirement if the capacitance load is too large due to

routing, connectors, or multiple components sharing the same bus.

Fig 23. Typical appl ication showing SE97 interfacing with 3.3 V host

002aab35

HOST

CONTROLLER

SE97

SCL

SDA

EVENT

VDD

10 kΩ

(3×)

VSS

slave master

3.3 V

Fig 24. SE97 interfac ing with 1.1 V host controller

002aad26

HOST

CONTROLLER

SE97

SCL

SDA

EVENT

VDD 10 kΩ

VSS

3.3 V

0.1 μF

10 kΩ

PCA9509

mother board

0.1 μF

VCC(B)

VCC(A)

10 kΩ10 kΩ

SCL

SDA

EVENT

0.1 μF

1.1 V

Product data sheet Rev. 07 — 29 January 2010 36 of 55

NXP Semiconductors SE97

DDR memory module temp sensor with integrated SPD, 3.3 V

9.1 SE97 in memory module application

Figure 25 shows the SE97 being placed in the memory module application. The SE97 is

centered in the memory module to monitor the temperature of the DRAM and also to

provide a 2-kbit EEPROM as the Serial Presence Detect (SPD). In the event of

overheating, the SE97 triggers the EVENT output and the memory controller throttles the

memory bus to slow the DRAM. The memory con troller can also read the SE97 and watch

the DRAM thermal behavior, taking p reventive measures when necessary.

9.2 Layout consideration

The SE97 does not require any additional components other than the host controller to

read its temperature. It is recommended that a 0.1 μF bypass capacitor between the VDD

and VSS pins is located as close as possible to the power and ground pins for noise

protection.

9.3 Thermal considerations

In general, self-heating is the result of power consumption and not a concern, especially

with the SE97, which consumes very low power. In the event the SDA and EVENT pins

are heavily loaded with small pull- up resistor values, self-heating affects temperature

accuracy by approximately 0.5 °C.

Equation 1 is the formula to calculate the effect of self-heating:

(1)

where:

ΔT = Tj−Tamb

Tj = junction temperature

Tamb = ambient temperature

Rth(j-a) = package thermal resistance

VDD = supply voltage

IDD(AV) = average supply current

Fig 25. System application

002aac80

SE97

EVENT

DIMM

DRAM DRAM DRAM DRAM

MEMORY CONTROLLER

SMBus

CPU

ΔTR

th j-a()

VDD IDD AV()

×()VOL SDA()

IOL ksin()SDA()

×()VOL EVENT()

IOL ksin()EVENT

×()++[ ]

×=

Product data sheet Rev. 07 — 29 January 2010 37 of 55

NXP Semiconductors SE97

DDR memory module temp sensor with integrated SPD, 3.3 V

VOL(SDA) = LOW-level output voltage on pin SDA

VOL(EVENT) = LOW-level output voltage on pin EVENT

IOL(sink)(SDA) = SDA output current LO W

IOL(sink)EVENT = EVENT output current LOW

Calculation example:

Tamb (typical temperature inside the notebook) = 50 °C

IDD(AV) = 400 μA

VDD = 3.6 V

Maximum VOL(SDA) = 0.4 V

IOL(sink)(SDA) = 1 mA

VOL(EVENT) = 0.4 V

IOL(sink)EVENT = 3 mA

Rth(j-a) of HVSON8 = 56 °C/W

Rth(j-a) of TSSOP8 = 160 °C/W

Self heating due to power dissipation for HVSON8 is:

(2)

Self heating due to power dissipa tion for TSSOP8 is:

(3)

10. Limiting values

ΔT 56 3.6 0.4×()0.4 3×()0.4 1×()++[]×56 °C W 3.04 mW 0.17 °C=×⁄==

ΔT 160 3.6 0.4×()0.4 3×()0.4 1×()++[]160 °C W 3.04 mV×⁄ 0.49 °C==×=

Table 27. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

VDD supply voltage −0.3 +4.2 V

Vnvoltage on any other pin SDA, SCL, EVENT pins −0.3 +4.2 V

VA0 voltage on pin A0 overvoltage input; A0 pin −0.3 +12.5 V

Isink sink current at SDA, SCL, EVENT pins −1+50.0mA

Tj(max) maximum junction temperature - 150 °C

Tstg storage temperature −65 +165 °C

Product data sheet Rev. 07 — 29 January 2010 38 of 55

NXP Semiconductors SE97

DDR memory module temp sensor with integrated SPD, 3.3 V

11. Characteristics

Table 28. SE97 thermal sensor characteristics

VDD = 3.0 V to 3.6 V; Tamb =

−

C to +125

C; unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

Tlim(acc) temperature limit accuracy B grade; VDD =3.3V±10 %

Tamb =75°Cto95°C−1.0 < ±0.5 +1.0 °C

Tamb =40°Cto125°C−2.0 < ±1.0 +2.0 °C

Tamb =−40 °Cto+125°C−3.0 < ±2+3.0°C

Tres temperature resolution - 0.125 - °C

Tconv conversion period conversion time from STOP bit

to conversion complete -100120ms

Ef(conv) conversion rate error percentage error in

programmed data −30 - +30 %

Product data sheet Rev. 07 — 29 January 2010 39 of 55

NXP Semiconductors SE97

DDR memory module temp sensor with integrated SPD, 3.3 V

[1] High-voltage input voltage applied to pin A0 during RWP and CR WP operations. The JEDEC specification is 7 V (min.) and 10 V (max.),

but since the SE97 EEPROM write works only down to 3.0 V, the condition of VI(ov) >4.8V+V

DD or > 4.8 V + 3.0 V was applied and the

minimum voltage changed to 7.8 V. If VDD is 3.6 V then the minimum voltage is 8.4 V.

Table 29. DC characteristics

VDD = 1.7 V to 3.6 V; Tamb =

−

C to +125

C; unless otherwise specified. These specifications are gua ranteed by design.

Symbol Parameter Conditions Min Typ Max Unit

IDD(AV) average supply current SMBus inactive - 250 400 μA

Isd(VDD) supply voltage shutdown mode

current SMBus inactive - 0.1 5.0 μA

VIH HIGH-level input voltage SCL, SDA;

VDD = 3.0 V to 3.6 V 0.7 ×VDD -V

DD +1 V

VIL LOW-level input voltage SCL, SDA;

VDD = 3.0 V to 3.6 V --0.3×VDD V

VOL1 LOW-level output voltage 1 VDD =3.0V; I

OL =3mA - - 0.4 V

VOL2 LOW-level output voltage 2 VDD =1.7V; I

OL =1.5mA - - 0.5 V

VI(ov) overvoltage input voltage pin A0; VI(ov) −VDD >4.8V [1] 7.8 - 10 V

VPOR power-on reset voltage power supply rising - - 1.7 V

power supply falling

SE97PW, SE97TK 0.1 - - V

SE97TL, SE97TP 0.6 - - V

IOL(sink)EVENT LOW-level output sink current on

pin EVENT VOL1 =0.4V

SE97PW, SE9 7TK 2 - - mA

SE97TL, SE97TP 6 - - mA

IOL(sink)(SDA) LOW-level output sink current on

pin SDA VOL2 =0.5V 3 - - mA

ILOH HIGH-level output leakage current EVENT; VOH =V

DD −1.0 - +1.0 μA

ILIH HIGH-level input leakage current SDA, SCL; VI=V

DD −1.0 - +1.0 μA

ILIL LOW-level input leakage current SDA, SCL; VI=V

SS −1.0 - +1.0 μA

A0, A1, A2; VI=V

SS −1.0 - +1.0 μA

Ci(SCL/SDA) SCL and SDA input capacitance - 5 10 pF

ILleakage current on A0, A1, A2 - 1 - μA

Ipd pull-down current internal; A0, A1, A2 pins;

VI=0.3V

DD to VDD

--4.0μA

ZIL LOW-level input impedance pins A0, A1, A2; VI<0.3V

DD 30 - - kΩ

ZIH HIGH-level input impedance pins A0, A1, A2 800 - - kΩ

Product data sheet Rev. 07 — 29 January 2010 40 of 55

NXP Semiconductors SE97

DDR memory module temp sensor with integrated SPD, 3.3 V

I2C-bus and EEPROM inactive. I2C-bus, temp sensor and EEPROM inactive.

Fig 26. Average supply current Fig 27. Sh utdown supply current

Temp sensor and EEPROM active. VDD = 3.0 V to 3.6 V.

Fig 28. Average supply current during EEPROM write Fig 29. Typical temperature accuracy

VOL1 =0.4V. V

OL1 =0.4V.

Fig 30. EVENT output current SE97PW, SE97TK Fig 31. EVENT output current SE97TL, SE97TP

200

300

100

400

500

IDD(AV)

(μA)

Tamb (°C)

−40 12080040

002aac910

VDD = 3.6 V

3.0 V

Isd(VDD)

(μA)

−1

Tamb (°C)

−40 12080040

002aac911

VDD = 3.6 V

3.0 V

200

500

400

300

600

IDD(AV)

(μA)

002aac912

Tamb (°C)

−40 12080040

VDD = 3.6 V

3.0 V

−2.0

3.5

−3.5

Tamb (°C)

−50 125

002aad769

1007550250−25

2.0

Tlim(acc)

(°C)

−1.0

1.0

2.0

8.0

IOL

(mA)

Tamb (°C)

−50 125

002aad258

1007550250−25

6.0

4.0

VDD = 3.0 V to 3.6 V

VDD = 1.7 V

Tamb (°C)

−50 125

002aad767

1007550250−25

VDD = 3.7 V

3.3 V

2.9 V

1.7 V

IOL(sink)EVENT

(mA)

Product data sheet Rev. 07 — 29 January 2010 41 of 55

NXP Semiconductors SE97

DDR memory module temp sensor with integrated SPD, 3.3 V

VOL2 =0.6V. V

DD = 3.0 V to 3.6 V.

Fig 32. SDA output current Fig 33. Conversion rate

VDD = 3.0 V to 3.6 V. VDD = 3.0 V to 3.6 V.

Fig 34. Conversion period Fig 35. EEPROM write cycle time

For temp sensor conversion.

VDD = 3.0 V to 3.6 V. For EEPROM read operation.

VDD = 1.7 V to 3.6 V.

Fig 36. Average power-on threshold voltage Fig 37. Average power-on threshold voltage

Tamb (°C)

−40 12080040

002aac907

VDD = 3.6 V

3.0 V

IOL(sink)(SDA)

(mA)

Tamb (°C)

−40 12080040

002aac908

conversion rate

(conv/s)

120

100

140

Tconv

(ms)

002aac909

Tamb (°C)

−40 12080040

Tcy(W)

(ms)

Tamb (°C)

−40 12080040

002aac902

2.4

2.6

2.2

2.8

3.0

Vth

(V)

2.0

Tamb (°C)

−40 12080040

002aac903

1.2

1.4

1.6

Vth

(V)

1.0

Tamb (°C)

−40 12080040

002aac904

Product data sheet Rev. 07 — 29 January 2010 42 of 55

NXP Semiconductors SE97

DDR memory module temp sensor with integrated SPD, 3.3 V

VDD = 3.0 V to 3.6 V.

From 25 °C (air) to 120 °C (oil bath).

(1) TSSOP8

(2) HVSON8, HWSON8, HXSON8

VDD = 3.3 V + 150 mV (p-p); 0.1 μF AC coupling

capacitor; no decoupling capacitor; Tamb =25°C.

Fig 38. Package thermal response Fig 39. Temperature error versus power supply noise

frequency

120

thermal

response

(%)

time (s)

054231

002aac905

(1)

(2)

noise frequency (Hz)

002aac914

temp error

(°C)

−1

Product data sheet Rev. 07 — 29 January 2010 43 of 55

NXP Semiconductors SE97

DDR memory module temp sensor with integrated SPD, 3.3 V

[1] Minimum clock frequency is 0 kHz if SMBus Time-out is disabled.

[2] Delay from SDA STOP to SDA START.

[3] A device must internally provide a hold time of at least 200 ns for SDA signal (referenced to the VIH(min) of the SCL signal) to bridge the

undefined region of the falling edge of SCL.

[4] Delay from SCL HIGH-to-LOW transition to SDA edges.

[5] Delay from SCL LOW-to-HIGH transition to restart SDA.

[6] Delay from SDA START to first SCL HIGH-to-LOW transition.

[7] These parameters tested initially and after a design or process change that affects the parameter.

[8] tpu(R) and tpu(W) are the delays required from the time VDD is stable until the specified operation can be initiated.

Table 30. SMBus AC ch ar a c t er istics

VDD = 1.7 V to 3.6 V; Tamb =

−

C to +125

C; unless otherwise specified. These specifications are gua ranteed by design.

The AC specifications fully meet or exceed SMBus 2.0 specifications, but allow the bus to interface with the I2C-bus from DC

to 400 kHz.

Symbol Parameter Conditions Standard mode Fast mode Unit

Min Max Min Max

fSCL SCL clock frequency 10[1] 100 10[1] 400 kHz

tHIGH HIGH period of the SCL clock 70 % to 70 % 4000 - 600 - ns

tLOW LOW period of the SCL clock 30 % to 30 % 4700 - 1300 - ns

tto(SMBus) SMBus time-out time LOW period to reset

SMBus 25 35 25 35 ms

trrise time of both SDA and

SCL signals - 1000 20 300 ns

tffall time of both SDA and SCL

signals - 300 - 300 ns

tSU;DAT data set-up time 250 - 100 - ns

th(i)(D) data input hold time [2][3] 0-0-ns

tHD;DAT data hold time [4] 200 3450 200 900 ns

tSU;STA set-up time for a repeated

START condition [5] 4700 - 600 - ns

tHD;STA hold time (repeated) START

condition 30 % of SDA to

70 % of SCL [6] 4000 - 600 - ns

tSU;STO set-up time for STOP

condition 4000 - 600 - ns

tBUF bus free time between a

STOP and START condition [2] 4700 - 1300 - ns

tSP pulse width of spikes that

must be suppressed by the

input filter

-50-50ns

tVD;DAT data valid time from clock 200 - 200 - ns

tf(o) output fall time - - - 250 ns

tPOR power-on reset pulse time power supply falling 0.5 - 0.5 - μs

EEPROM power-up timing[7]

tpu(R) read power-up time [8] -1-1ms

tpu(W) write powe r-u p ti me [8] -1-1ms

Write cycle limits

Tcy(W) write cycle time [9] -10-10ms

Product data sheet Rev. 07 — 29 January 2010 44 of 55

NXP Semiconductors SE97

DDR memory module temp sensor with integrated SPD, 3.3 V

[9] The write cycle time is the time elapsed between the STOP command (following the write instruction) and the completion of the internal

write cycle. During the internal write cycle, SDA is released by the slave and the device does not acknowledge external commands.

S = START condition

P = STOP condition

Fig 40. AC waveforms

002aae750

tLOW

SDA

P S

tBUF tHD;STA

tHD;DAT

tHIGH

tSU;DAT

tSU;STA

tHD;DAT

S P

tSU;STO

VIH

VIL

VIH

VIL

SCL

SDA

SCL

tSU;STO

VIH

VIL

VIH

VIL

STOP

condition

START

condition

tSU;STA

write cycle

Product data sheet Rev. 07 — 29 January 2010 45 of 55

NXP Semiconductors SE97

DDR memory module temp sensor with integrated SPD, 3.3 V

12. Package outline

Fig 41. Package outline SOT530-1 (TSSOP8)

UNIT A1

max. A2A3bpLHELpwyv

ceD(1) E(2) Z(1) θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.15

0.05

0.95

0.85

0.30

0.19

0.20

0.13

3.1

2.9

4.5

4.3 0.65 6.5

6.3

0.70

0.35

8°

0°

0.1 0.10.10.94

DIMENSIONS (mm are the original dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

0.7

0.5

SOT530-1 MO-153 00-02-24

03-02-18

0.25

(A3)

detail X

vMA

2.5 5 mm0

scale

SSOP8: plastic thin shrink small outline package; 8 leads; body width 4.4 mm SOT530-

1.1

pin 1 index

Product data sheet Rev. 07 — 29 January 2010 46 of 55

NXP Semiconductors SE97

DDR memory module temp sensor with integrated SPD, 3.3 V

Fig 42. Package outline SOT908-1 (HVSON8)

0.50.21 0.05

0.00

A1Eh

UNIT D(1) ye

1.5

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 3.1

2.9

1.65

1.35

3.1

2.9

2.25

1.95

0.3

0.2 0.05 0.1

DIMENSIONS (mm are the original dimensions)

SOT908-1 MO-229

E(1)

0.5

0.3

0.1

0.05

SOT908-1

VSON8: plastic thermal enhanced very thin small outline package; no leads;

terminals; body 3 x 3 x 0.85 mm

A(1)

max.

05-09-26

05-10-05

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

terminal 1

index area

B A

detail X

exposed tie bar (4×)

terminal 1

index area

eAC B

C wM

0 1 2 mm

scale

Product data sheet Rev. 07 — 29 January 2010 47 of 55

NXP Semiconductors SE97

DDR memory module temp sensor with integrated SPD, 3.3 V

Fig 43. Package outline SOT1052-1 (HXSON8)

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

SOT1052-1 MO-229

SOT1052-

Note

1. Dimension A is including plating thickness. The package footprint is compatible with JEDEC MO229

DIMENSIONS (mm are the original dimensions)

XSON8: plastic thermal enhanced extremely thin small outline package; no leads;

terminals; body 2 x 3 x 0.5 mm

UNIT

max

nom

min

0.5 0.04 2.1

2.0

1.9

1.6

1.4

0.5

3.1

3.0

2.9

1.6

1.4

0.45

0.35

0.3

0.2

0.1 0.05 0.05

A(1) A1b D D1E E1e L v y y1

0 1 2 mm

scale

terminal 1

index area

1/2 e

terminal 1

index area

XBAb v M

detail X

AA1

(8×)

08-01-11

08-03-11

Product data sheet Rev. 07 — 29 January 2010 48 of 55

NXP Semiconductors SE97

DDR memory module temp sensor with integrated SPD, 3.3 V

Fig 44. Package outline SOT1069-1 (HWSON8)

References

Outline

version

European

projection Issue date

IEC JEDEC JEITA

SOT1069-1 MO-229

sot1069-1_po

08-07-10

09-08-10

Unit

max

nom

min

0.80

0.75

0.70

0.05

0.02

0.2

0.30

0.25

0.20

2.1

2.0

1.9

1.6

1.4

1.6

1.4

0.5

0.45

0.35

A(1)

Dimensions

Note

1. Dimension A is including plating thickness. The package footprint is compatible with JEDEC MO229

WSON8: plastic thermal enhanced very very thin small outline package; no leads;

terminals; body 2 x 3 x 0.8 mm SOT1069-

A1A2

0.65

0.55

0.45

A3bDD

3.1

3.0

2.9

E2eK

0.2

0.1

0.05

0 1 2 mm

scale

terminal 1

index area

XBAb v

(8×)

detail X

terminal 1

index area

1/2 e

Product data sheet Rev. 07 — 29 January 2010 49 of 55

NXP Semiconductors SE97

DDR memory module temp sensor with integrated SPD, 3.3 V

Fig 45. Package outline SOT1069-2 (HWSON8)

References

Outline

version

European

projection Issue date

IEC JEDEC JEITA

SOT1069-2 - - -

MO-229

- - -

sot1069-2_po

09-10-22

09-11-18

Unit

max

nom

min

0.80

0.75

0.70

0.05

0.02

0.00

2.1

2.0

1.9

1.6

1.5

1.4

3.1

3.0

2.9

0.5 1.5

0.45

0.40

0.35

0.05

A(1)

Dimensions

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

WSON8: plastic thermal enhanced very very thin small outline package; no leads;

terminals; body 2 x 3 x 0.8 mm SOT1069-

0.65

0.55

0.45

0.2

A3b

0.30

0.25

0.18

D(1) D2E(1) E2

1.6

1.5

1.4

0.40

0.35

0.30

0.1

0.05

0 1 2 mm

scale

terminal 1

index area

detail X

terminal 1

index area b

eAC B

1 4

Product data sheet Rev. 07 — 29 January 2010 50 of 55

NXP Semiconductors SE97

DDR memory module temp sensor with integrated SPD, 3.3 V

13. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reflow

soldering description”.

13.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on on e printed wiring board; however, it is not

suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

13.2 Wave and reflow soldering

W ave soldering is a joining te chnology in which the joints are m ade by solder coming from

a standing wave of liquid solder. The wave solder ing process is suitable for the following:

•Through-hole components

•Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solde r lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads ha ving a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reflow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature profile. Leaded pa ckages,

packages with solder balls, and leadless packages are all reflow soldera ble.

Key characteristics in both wave and reflow soldering are:

•Board specifications, including the board finish, solder masks and vias

•Package footprints, including solder thieves and orientation

•The moisture sensitivity level of the packages

•Package placement

•Inspection and repair

•Lead-free soldering ve rsus SnPb soldering

13.3 Wave soldering

Key characteristics in wave soldering are:

•Process issues, such as application of adhesive and flux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

•Solder bath specifications, including temperature and impurities

Product data sheet Rev. 07 — 29 January 2010 51 of 55

NXP Semiconductors SE97

DDR memory module temp sensor with integrated SPD, 3.3 V

13.4 Reflow soldering

Key characteristics in reflow soldering are :

•Lead-free ve rsus SnPb soldering; note th at a lead-free reflow process usua lly leads to

higher minimum peak temperatures (see Figure 46) than a SnPb process, thus

reducing the process window

•Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

•Reflow temperature profile; this profile includes preheat, reflow (in which the board is

heated to the peak temperature) an d cooling down. It is imperative that the peak

temperature is high enoug h for the solder to make reliable solder joint s (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on p ackage thickness and volume and is classified in accordance with

Table 31 and 32

Moisture sensitivity precautions, as indicated on the packing, must be respe cted at all

times.

Studies have shown that small packages reach higher temp eratures during reflow

soldering, see Figure 46.

Table 31. SnPb eutectic process (from J-STD-0 20C)

Package thickness (mm) Package reflow temperature (°C)

Volume (mm3)

< 350 ≥ 350

< 2.5 235 220

≥ 2.5 220 220

Table 32. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reflow temperature (°C)

Volume (mm3)

< 350 350 to 2000 > 2000

< 1.6 260 260 260

1.6 to 2.5 260 250 245

> 2.5 250 245 245

Product data sheet Rev. 07 — 29 January 2010 52 of 55

NXP Semiconductors SE97

DDR memory module temp sensor with integrated SPD, 3.3 V

For further informa tion on temperature profiles, refer to Application Note AN10365

“Surface mount reflow soldering description”.

14. Abbreviations

MSL: Moisture Sensitivity Level

Fig 46. Temperature profiles for large and small components

001aac84

temperature

time

minimum peak temperature

= minimum soldering temperature

maximum peak temperature

= MSL limit, damage level

peak

temperature

Table 33. Abbreviations

Acronym Description

ADC Analog-to-Digital Converter

ARA Alert Response Address

CDM Charged-Device Model

CMOS Complementary Metal-Oxide Semiconductor

CPU Central Processing Unit

DDR Double Data Rate

DIMM Dual In-line Memory Module

DRAM Dynamic Random Access Memory

ECC Error-Correcting Code

EEPROM Electrically Erasable Programmable Read-Only Memory

ESD ElectroStatic Discharge

HBM Human Body Model

I2C-bus Inter-Integrated Circuit bus

LSB Least Significant Bit

MM Machine Model

MSB Most Significant Bit

PC Personal Computer

PCB Printed-Circuit Board

POR Power-On Reset

Product data sheet Rev. 07 — 29 January 2010 53 of 55

NXP Semiconductors SE97

DDR memory module temp sensor with integrated SPD, 3.3 V

15. Revision history

RDIMM Registered Dual In-line Memory Module

SMBus System Management Bus

SO-DIMM Small Outline Dual In-line Memory Module

SPD Serial Presence Detect

Table 33. Abbreviations …continued

Acronym Description

Table 34. Revision history

Document ID Release date Data sheet st atus Change notice Supersedes

SE97_7 20100129 Product data sheet - SE97_6

Modifications: •Table 1 “Ordering information”:

–added Type number SE97TP/S900

–added Table note [3]

•Added (new) Figure 6 “Pin configuration for HWSON8 (SOT1069-2)”

•Section 7.7 “SMBus time-out”, 1st paragraph, second sentence: changed from “between 25 ns and

35 ms” to “between 25 ms and 35 ms”

•Table 8 “Register summary”, address 07h (Device ID/Revision register):

–Default state is split: A200h for SE97PW, SE97TK; A201h for SE97TP, SE97TL

•Section 8.8 “Device ID register”:

–1st paragraph, 1st sentence: changed from “The SE97 device ID is A1h.” to “The SE97 device ID

is A2h.”

–Table note [1] modified

•Added (new) Figure 45 “Package outline SOT1069-2 (HWSON8)”

SE97_6 20090817 Product data sheet - SE97_5

SE97_5 20090806 Product data sheet - SE97_4

SE97_4 20090130 Product data sheet - SE97_3

SE97_3 20080715 Product data sheet - SE97_2

SE97_2 20071012 Product data sheet - SE97_1

SE97_1 20070524 Objective data sheet - -

Product data sheet Rev. 07 — 29 January 2010 54 of 55

NXP Semiconductors SE97

DDR memory module temp sensor with integrated SPD, 3.3 V

16. Legal information

16.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of de vice(s) descr ibed in th is document m ay have cha nged since thi s document w as publish ed and may di ffe r in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

16.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liab ility for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and tit le. A short data sh eet is intended

for quick reference only and shou ld not b e relied u pon to cont ain det ailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semicond uctors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall pre va il.

16.3 Disclaimers

General — In formation in this document is believed to be accurate and

reliable. However, NXP Semiconductors d oes not give an y represent ations or

warranties, expressed or impli ed, as to the accuracy or completeness of such

information and shall have no liability for th e co nsequences of use of such

information.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all informa tion supplied prior

to the publication hereof .

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, milit ary, aircraft,

space or life support equipment, nor in app lications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liab ility for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ra tings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other co nditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may af fect device reliability.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/profile/terms, including those pertaining to warrant y,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conflict between inf ormation in this document and such

terms and conditions, the latter will prevail.

No offer to sell or license — Nothing i n this document may be interpreted or

construed as an of fer t o sell product s that is open for accept ance or the gr ant,

conveyance or implication of any license under any copyrights, patents or

other industrial or inte llectual property rights.

Export control — This document as well as the item(s) described herein

may be subject to export control regulatio ns. Export might require a prior

authorization from national authorities.

16.4 Trademarks

Notice: All referenced b rands, produc t names, service names and trademarks

are the property of their respective ow ners.

I2C-bus — logo is a trademark of NXP B.V.

17. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contains data from the objective specification for product development.

Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.

Product [short] data sheet Production This document contains the product specification.

NXP Semiconductors SE97

DDR memory module temp sensor with integrated SPD, 3.3 V

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 29 January 2010

Document identifier: SE97_7

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

18. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2.1 General features. . . . . . . . . . . . . . . . . . . . . . . . 2

2.2 Temperature sensor features . . . . . . . . . . . . . . 2

2.3 Serial EEPROM features . . . . . . . . . . . . . . . . . 2

3 Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

4 Ordering information. . . . . . . . . . . . . . . . . . . . . 3

5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4

6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 5

6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6

7 Functional description . . . . . . . . . . . . . . . . . . . 7

7.1 Serial bus interface. . . . . . . . . . . . . . . . . . . . . . 7

7.2 Slave address. . . . . . . . . . . . . . . . . . . . . . . . . . 7

7.3 EVENT output condition. . . . . . . . . . . . . . . . . . 8

7.3.1 EVENT pin output voltage levels and

resistor sizing . . . . . . . . . . . . . . . . . . . . . . . . . . 8

7.3.2 EVENT thresholds . . . . . . . . . . . . . . . . . . . . . 10

7.3.2.1 Alarm window. . . . . . . . . . . . . . . . . . . . . . . . . 10

7.3.2.2 Critical trip. . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

7.3.3 EVENT operation modes . . . . . . . . . . . . . . . . 11

7.3.3.1 Comparator mode. . . . . . . . . . . . . . . . . . . . . . 11

7.3.3.2 Interrupt mode . . . . . . . . . . . . . . . . . . . . . . . . 11

7.4 Conversion rate . . . . . . . . . . . . . . . . . . . . . . . 12

7.4.1 What temperature is read when

conversion is in progress . . . . . . . . . . . . . . . . 12

7.5 Power-up default condition. . . . . . . . . . . . . . . 12

7.6 Device initialization. . . . . . . . . . . . . . . . . . . . . 12

7.7 SMBus time-out . . . . . . . . . . . . . . . . . . . . . . . 13

7.8 SMBus ALERT Response Address

(ARA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

7.9 SMBus/I2C-bus interface . . . . . . . . . . . . . . . . 14

7.10 EEPROM operation . . . . . . . . . . . . . . . . . . . . 17

7.10.1 Write operations . . . . . . . . . . . . . . . . . . . . . . . 17

7.10.1.1 Byte Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

7.10.1.2 Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

7.10.1.3 Acknowledge polling. . . . . . . . . . . . . . . . . . . . 18

7.10.2 Memory protection . . . . . . . . . . . . . . . . . . . . . 18

7.10.2.1 Permanent Write Protection (PWP) . . . . . . . . 20

7.10.2.2 Reversible Write Protection (RWP) and

Clear Reversible Write Protection (CRWP) . . 20

7.10.2.3 Read Permanent Write Protection (RPWP),

Read Reversible Write Protection (RRWP),

and Read Clear Reversible Write Protection

(RCRWP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

7.10.3 Read operations. . . . . . . . . . . . . . . . . . . . . . . 21

7.10.3.1 Current address read . . . . . . . . . . . . . . . . . . . 21

7.10.3.2 Selective read . . . . . . . . . . . . . . . . . . . . . . . . 21

7.10.3.3 Sequential read . . . . . . . . . . . . . . . . . . . . . . . 22

7.11 Hot plugging. . . . . . . . . . . . . . . . . . . . . . . . . . 23

8 Register descriptions . . . . . . . . . . . . . . . . . . . 23

8.1 Register overview . . . . . . . . . . . . . . . . . . . . . 23

8.2 Capability register

(00h, 16-bit read-only) . . . . . . . . . . . . . . . . . . 24

8.3 Configura tion register

(01h, 16-bit read/write). . . . . . . . . . . . . . . . . . 25

8.4 Temperature format . . . . . . . . . . . . . . . . . . . . 29

8.5 Temperature Trip Point registers . . . . . . . . . . 30

8.5.1 Upper Boundary Alarm Trip register

(16-bit read/write). . . . . . . . . . . . . . . . . . . . . . 30

8.5.2 Lower Boundary Alarm Trip register

(16-bit read/write). . . . . . . . . . . . . . . . . . . . . . 31

8.5.3 Critical Alarm Trip register

(16-bit read/write). . . . . . . . . . . . . . . . . . . . . . 31

8.6 Temperature register

(16-bit read-only) . . . . . . . . . . . . . . . . . . . . . . 32

8.7 Manufacturer’s ID register

(16-bit read-only) . . . . . . . . . . . . . . . . . . . . . . 33

8.8 Device ID register . . . . . . . . . . . . . . . . . . . . . 33

8.9 SMBus register . . . . . . . . . . . . . . . . . . . . . . . 34

9 Application design-in information. . . . . . . . . 35

9.1 SE97 in memory module application . . . . . . . 36

9.2 Layout consideration . . . . . . . . . . . . . . . . . . . 36

9.3 Thermal considerations . . . . . . . . . . . . . . . . . 36

10 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 37

11 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 38

12 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 45

13 Soldering of SMD pa ckages. . . . . . . . . . . . . . 50

13.1 Introduction to soldering. . . . . . . . . . . . . . . . . 50

13.2 Wave and reflow soldering. . . . . . . . . . . . . . . 50

13.3 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . 50

13.4 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . 51

14 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 52

15 Revision history . . . . . . . . . . . . . . . . . . . . . . . 53

16 Legal information . . . . . . . . . . . . . . . . . . . . . . 54

16.1 Data sheet status. . . . . . . . . . . . . . . . . . . . . . 54

16.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

16.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 54

16.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 54

17 Contact information . . . . . . . . . . . . . . . . . . . . 54

18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55